1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Implement the AER root port service driver. The driver registers an IRQ 4 * handler. When a root port triggers an AER interrupt, the IRQ handler 5 * collects root port status and schedules work. 6 * 7 * Copyright (C) 2006 Intel Corp. 8 * Tom Long Nguyen (tom.l.nguyen@intel.com) 9 * Zhang Yanmin (yanmin.zhang@intel.com) 10 * 11 * (C) Copyright 2009 Hewlett-Packard Development Company, L.P. 12 * Andrew Patterson <andrew.patterson@hp.com> 13 */ 14 15 #define pr_fmt(fmt) "AER: " fmt 16 #define dev_fmt pr_fmt 17 18 #include <linux/bitops.h> 19 #include <linux/cper.h> 20 #include <linux/pci.h> 21 #include <linux/pci-acpi.h> 22 #include <linux/sched.h> 23 #include <linux/kernel.h> 24 #include <linux/errno.h> 25 #include <linux/pm.h> 26 #include <linux/init.h> 27 #include <linux/interrupt.h> 28 #include <linux/delay.h> 29 #include <linux/kfifo.h> 30 #include <linux/slab.h> 31 #include <acpi/apei.h> 32 #include <ras/ras_event.h> 33 34 #include "../pci.h" 35 #include "portdrv.h" 36 37 #define AER_ERROR_SOURCES_MAX 128 38 39 #define AER_MAX_TYPEOF_COR_ERRS 16 /* as per PCI_ERR_COR_STATUS */ 40 #define AER_MAX_TYPEOF_UNCOR_ERRS 27 /* as per PCI_ERR_UNCOR_STATUS*/ 41 42 struct aer_err_source { 43 unsigned int status; 44 unsigned int id; 45 }; 46 47 struct aer_rpc { 48 struct pci_dev *rpd; /* Root Port device */ 49 DECLARE_KFIFO(aer_fifo, struct aer_err_source, AER_ERROR_SOURCES_MAX); 50 }; 51 52 /* AER stats for the device */ 53 struct aer_stats { 54 55 /* 56 * Fields for all AER capable devices. They indicate the errors 57 * "as seen by this device". Note that this may mean that if an 58 * end point is causing problems, the AER counters may increment 59 * at its link partner (e.g. root port) because the errors will be 60 * "seen" by the link partner and not the problematic end point 61 * itself (which may report all counters as 0 as it never saw any 62 * problems). 63 */ 64 /* Counters for different type of correctable errors */ 65 u64 dev_cor_errs[AER_MAX_TYPEOF_COR_ERRS]; 66 /* Counters for different type of fatal uncorrectable errors */ 67 u64 dev_fatal_errs[AER_MAX_TYPEOF_UNCOR_ERRS]; 68 /* Counters for different type of nonfatal uncorrectable errors */ 69 u64 dev_nonfatal_errs[AER_MAX_TYPEOF_UNCOR_ERRS]; 70 /* Total number of ERR_COR sent by this device */ 71 u64 dev_total_cor_errs; 72 /* Total number of ERR_FATAL sent by this device */ 73 u64 dev_total_fatal_errs; 74 /* Total number of ERR_NONFATAL sent by this device */ 75 u64 dev_total_nonfatal_errs; 76 77 /* 78 * Fields for Root ports & root complex event collectors only, these 79 * indicate the total number of ERR_COR, ERR_FATAL, and ERR_NONFATAL 80 * messages received by the root port / event collector, INCLUDING the 81 * ones that are generated internally (by the rootport itself) 82 */ 83 u64 rootport_total_cor_errs; 84 u64 rootport_total_fatal_errs; 85 u64 rootport_total_nonfatal_errs; 86 }; 87 88 #define AER_LOG_TLP_MASKS (PCI_ERR_UNC_POISON_TLP| \ 89 PCI_ERR_UNC_ECRC| \ 90 PCI_ERR_UNC_UNSUP| \ 91 PCI_ERR_UNC_COMP_ABORT| \ 92 PCI_ERR_UNC_UNX_COMP| \ 93 PCI_ERR_UNC_MALF_TLP) 94 95 #define SYSTEM_ERROR_INTR_ON_MESG_MASK (PCI_EXP_RTCTL_SECEE| \ 96 PCI_EXP_RTCTL_SENFEE| \ 97 PCI_EXP_RTCTL_SEFEE) 98 #define ROOT_PORT_INTR_ON_MESG_MASK (PCI_ERR_ROOT_CMD_COR_EN| \ 99 PCI_ERR_ROOT_CMD_NONFATAL_EN| \ 100 PCI_ERR_ROOT_CMD_FATAL_EN) 101 #define ERR_COR_ID(d) (d & 0xffff) 102 #define ERR_UNCOR_ID(d) (d >> 16) 103 104 #define AER_ERR_STATUS_MASK (PCI_ERR_ROOT_UNCOR_RCV | \ 105 PCI_ERR_ROOT_COR_RCV | \ 106 PCI_ERR_ROOT_MULTI_COR_RCV | \ 107 PCI_ERR_ROOT_MULTI_UNCOR_RCV) 108 109 static int pcie_aer_disable; 110 static pci_ers_result_t aer_root_reset(struct pci_dev *dev); 111 112 void pci_no_aer(void) 113 { 114 pcie_aer_disable = 1; 115 } 116 117 bool pci_aer_available(void) 118 { 119 return !pcie_aer_disable && pci_msi_enabled(); 120 } 121 122 #ifdef CONFIG_PCIE_ECRC 123 124 #define ECRC_POLICY_DEFAULT 0 /* ECRC set by BIOS */ 125 #define ECRC_POLICY_OFF 1 /* ECRC off for performance */ 126 #define ECRC_POLICY_ON 2 /* ECRC on for data integrity */ 127 128 static int ecrc_policy = ECRC_POLICY_DEFAULT; 129 130 static const char * const ecrc_policy_str[] = { 131 [ECRC_POLICY_DEFAULT] = "bios", 132 [ECRC_POLICY_OFF] = "off", 133 [ECRC_POLICY_ON] = "on" 134 }; 135 136 /** 137 * enable_ecrc_checking - enable PCIe ECRC checking for a device 138 * @dev: the PCI device 139 * 140 * Returns 0 on success, or negative on failure. 141 */ 142 static int enable_ecrc_checking(struct pci_dev *dev) 143 { 144 int aer = dev->aer_cap; 145 u32 reg32; 146 147 if (!aer) 148 return -ENODEV; 149 150 pci_read_config_dword(dev, aer + PCI_ERR_CAP, ®32); 151 if (reg32 & PCI_ERR_CAP_ECRC_GENC) 152 reg32 |= PCI_ERR_CAP_ECRC_GENE; 153 if (reg32 & PCI_ERR_CAP_ECRC_CHKC) 154 reg32 |= PCI_ERR_CAP_ECRC_CHKE; 155 pci_write_config_dword(dev, aer + PCI_ERR_CAP, reg32); 156 157 return 0; 158 } 159 160 /** 161 * disable_ecrc_checking - disables PCIe ECRC checking for a device 162 * @dev: the PCI device 163 * 164 * Returns 0 on success, or negative on failure. 165 */ 166 static int disable_ecrc_checking(struct pci_dev *dev) 167 { 168 int aer = dev->aer_cap; 169 u32 reg32; 170 171 if (!aer) 172 return -ENODEV; 173 174 pci_read_config_dword(dev, aer + PCI_ERR_CAP, ®32); 175 reg32 &= ~(PCI_ERR_CAP_ECRC_GENE | PCI_ERR_CAP_ECRC_CHKE); 176 pci_write_config_dword(dev, aer + PCI_ERR_CAP, reg32); 177 178 return 0; 179 } 180 181 /** 182 * pcie_set_ecrc_checking - set/unset PCIe ECRC checking for a device based on global policy 183 * @dev: the PCI device 184 */ 185 void pcie_set_ecrc_checking(struct pci_dev *dev) 186 { 187 switch (ecrc_policy) { 188 case ECRC_POLICY_DEFAULT: 189 return; 190 case ECRC_POLICY_OFF: 191 disable_ecrc_checking(dev); 192 break; 193 case ECRC_POLICY_ON: 194 enable_ecrc_checking(dev); 195 break; 196 default: 197 return; 198 } 199 } 200 201 /** 202 * pcie_ecrc_get_policy - parse kernel command-line ecrc option 203 * @str: ECRC policy from kernel command line to use 204 */ 205 void pcie_ecrc_get_policy(char *str) 206 { 207 int i; 208 209 i = match_string(ecrc_policy_str, ARRAY_SIZE(ecrc_policy_str), str); 210 if (i < 0) 211 return; 212 213 ecrc_policy = i; 214 } 215 #endif /* CONFIG_PCIE_ECRC */ 216 217 #define PCI_EXP_AER_FLAGS (PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE | \ 218 PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE) 219 220 int pcie_aer_is_native(struct pci_dev *dev) 221 { 222 struct pci_host_bridge *host = pci_find_host_bridge(dev->bus); 223 224 if (!dev->aer_cap) 225 return 0; 226 227 return pcie_ports_native || host->native_aer; 228 } 229 230 int pci_enable_pcie_error_reporting(struct pci_dev *dev) 231 { 232 int rc; 233 234 if (!pcie_aer_is_native(dev)) 235 return -EIO; 236 237 rc = pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_AER_FLAGS); 238 return pcibios_err_to_errno(rc); 239 } 240 EXPORT_SYMBOL_GPL(pci_enable_pcie_error_reporting); 241 242 int pci_disable_pcie_error_reporting(struct pci_dev *dev) 243 { 244 int rc; 245 246 if (!pcie_aer_is_native(dev)) 247 return -EIO; 248 249 rc = pcie_capability_clear_word(dev, PCI_EXP_DEVCTL, PCI_EXP_AER_FLAGS); 250 return pcibios_err_to_errno(rc); 251 } 252 EXPORT_SYMBOL_GPL(pci_disable_pcie_error_reporting); 253 254 int pci_aer_clear_nonfatal_status(struct pci_dev *dev) 255 { 256 int aer = dev->aer_cap; 257 u32 status, sev; 258 259 if (!pcie_aer_is_native(dev)) 260 return -EIO; 261 262 /* Clear status bits for ERR_NONFATAL errors only */ 263 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status); 264 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, &sev); 265 status &= ~sev; 266 if (status) 267 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, status); 268 269 return 0; 270 } 271 EXPORT_SYMBOL_GPL(pci_aer_clear_nonfatal_status); 272 273 void pci_aer_clear_fatal_status(struct pci_dev *dev) 274 { 275 int aer = dev->aer_cap; 276 u32 status, sev; 277 278 if (!pcie_aer_is_native(dev)) 279 return; 280 281 /* Clear status bits for ERR_FATAL errors only */ 282 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status); 283 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, &sev); 284 status &= sev; 285 if (status) 286 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, status); 287 } 288 289 /** 290 * pci_aer_raw_clear_status - Clear AER error registers. 291 * @dev: the PCI device 292 * 293 * Clearing AER error status registers unconditionally, regardless of 294 * whether they're owned by firmware or the OS. 295 * 296 * Returns 0 on success, or negative on failure. 297 */ 298 int pci_aer_raw_clear_status(struct pci_dev *dev) 299 { 300 int aer = dev->aer_cap; 301 u32 status; 302 int port_type; 303 304 if (!aer) 305 return -EIO; 306 307 port_type = pci_pcie_type(dev); 308 if (port_type == PCI_EXP_TYPE_ROOT_PORT || 309 port_type == PCI_EXP_TYPE_RC_EC) { 310 pci_read_config_dword(dev, aer + PCI_ERR_ROOT_STATUS, &status); 311 pci_write_config_dword(dev, aer + PCI_ERR_ROOT_STATUS, status); 312 } 313 314 pci_read_config_dword(dev, aer + PCI_ERR_COR_STATUS, &status); 315 pci_write_config_dword(dev, aer + PCI_ERR_COR_STATUS, status); 316 317 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status); 318 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, status); 319 320 return 0; 321 } 322 323 int pci_aer_clear_status(struct pci_dev *dev) 324 { 325 if (!pcie_aer_is_native(dev)) 326 return -EIO; 327 328 return pci_aer_raw_clear_status(dev); 329 } 330 331 void pci_save_aer_state(struct pci_dev *dev) 332 { 333 int aer = dev->aer_cap; 334 struct pci_cap_saved_state *save_state; 335 u32 *cap; 336 337 if (!aer) 338 return; 339 340 save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_ERR); 341 if (!save_state) 342 return; 343 344 cap = &save_state->cap.data[0]; 345 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, cap++); 346 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, cap++); 347 pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK, cap++); 348 pci_read_config_dword(dev, aer + PCI_ERR_CAP, cap++); 349 if (pcie_cap_has_rtctl(dev)) 350 pci_read_config_dword(dev, aer + PCI_ERR_ROOT_COMMAND, cap++); 351 } 352 353 void pci_restore_aer_state(struct pci_dev *dev) 354 { 355 int aer = dev->aer_cap; 356 struct pci_cap_saved_state *save_state; 357 u32 *cap; 358 359 if (!aer) 360 return; 361 362 save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_ERR); 363 if (!save_state) 364 return; 365 366 cap = &save_state->cap.data[0]; 367 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, *cap++); 368 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, *cap++); 369 pci_write_config_dword(dev, aer + PCI_ERR_COR_MASK, *cap++); 370 pci_write_config_dword(dev, aer + PCI_ERR_CAP, *cap++); 371 if (pcie_cap_has_rtctl(dev)) 372 pci_write_config_dword(dev, aer + PCI_ERR_ROOT_COMMAND, *cap++); 373 } 374 375 void pci_aer_init(struct pci_dev *dev) 376 { 377 int n; 378 379 dev->aer_cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); 380 if (!dev->aer_cap) 381 return; 382 383 dev->aer_stats = kzalloc(sizeof(struct aer_stats), GFP_KERNEL); 384 385 /* 386 * We save/restore PCI_ERR_UNCOR_MASK, PCI_ERR_UNCOR_SEVER, 387 * PCI_ERR_COR_MASK, and PCI_ERR_CAP. Root and Root Complex Event 388 * Collectors also implement PCI_ERR_ROOT_COMMAND (PCIe r5.0, sec 389 * 7.8.4). 390 */ 391 n = pcie_cap_has_rtctl(dev) ? 5 : 4; 392 pci_add_ext_cap_save_buffer(dev, PCI_EXT_CAP_ID_ERR, sizeof(u32) * n); 393 394 pci_aer_clear_status(dev); 395 396 if (pci_aer_available()) 397 pci_enable_pcie_error_reporting(dev); 398 399 pcie_set_ecrc_checking(dev); 400 } 401 402 void pci_aer_exit(struct pci_dev *dev) 403 { 404 kfree(dev->aer_stats); 405 dev->aer_stats = NULL; 406 } 407 408 #define AER_AGENT_RECEIVER 0 409 #define AER_AGENT_REQUESTER 1 410 #define AER_AGENT_COMPLETER 2 411 #define AER_AGENT_TRANSMITTER 3 412 413 #define AER_AGENT_REQUESTER_MASK(t) ((t == AER_CORRECTABLE) ? \ 414 0 : (PCI_ERR_UNC_COMP_TIME|PCI_ERR_UNC_UNSUP)) 415 #define AER_AGENT_COMPLETER_MASK(t) ((t == AER_CORRECTABLE) ? \ 416 0 : PCI_ERR_UNC_COMP_ABORT) 417 #define AER_AGENT_TRANSMITTER_MASK(t) ((t == AER_CORRECTABLE) ? \ 418 (PCI_ERR_COR_REP_ROLL|PCI_ERR_COR_REP_TIMER) : 0) 419 420 #define AER_GET_AGENT(t, e) \ 421 ((e & AER_AGENT_COMPLETER_MASK(t)) ? AER_AGENT_COMPLETER : \ 422 (e & AER_AGENT_REQUESTER_MASK(t)) ? AER_AGENT_REQUESTER : \ 423 (e & AER_AGENT_TRANSMITTER_MASK(t)) ? AER_AGENT_TRANSMITTER : \ 424 AER_AGENT_RECEIVER) 425 426 #define AER_PHYSICAL_LAYER_ERROR 0 427 #define AER_DATA_LINK_LAYER_ERROR 1 428 #define AER_TRANSACTION_LAYER_ERROR 2 429 430 #define AER_PHYSICAL_LAYER_ERROR_MASK(t) ((t == AER_CORRECTABLE) ? \ 431 PCI_ERR_COR_RCVR : 0) 432 #define AER_DATA_LINK_LAYER_ERROR_MASK(t) ((t == AER_CORRECTABLE) ? \ 433 (PCI_ERR_COR_BAD_TLP| \ 434 PCI_ERR_COR_BAD_DLLP| \ 435 PCI_ERR_COR_REP_ROLL| \ 436 PCI_ERR_COR_REP_TIMER) : PCI_ERR_UNC_DLP) 437 438 #define AER_GET_LAYER_ERROR(t, e) \ 439 ((e & AER_PHYSICAL_LAYER_ERROR_MASK(t)) ? AER_PHYSICAL_LAYER_ERROR : \ 440 (e & AER_DATA_LINK_LAYER_ERROR_MASK(t)) ? AER_DATA_LINK_LAYER_ERROR : \ 441 AER_TRANSACTION_LAYER_ERROR) 442 443 /* 444 * AER error strings 445 */ 446 static const char *aer_error_severity_string[] = { 447 "Uncorrected (Non-Fatal)", 448 "Uncorrected (Fatal)", 449 "Corrected" 450 }; 451 452 static const char *aer_error_layer[] = { 453 "Physical Layer", 454 "Data Link Layer", 455 "Transaction Layer" 456 }; 457 458 static const char *aer_correctable_error_string[] = { 459 "RxErr", /* Bit Position 0 */ 460 NULL, 461 NULL, 462 NULL, 463 NULL, 464 NULL, 465 "BadTLP", /* Bit Position 6 */ 466 "BadDLLP", /* Bit Position 7 */ 467 "Rollover", /* Bit Position 8 */ 468 NULL, 469 NULL, 470 NULL, 471 "Timeout", /* Bit Position 12 */ 472 "NonFatalErr", /* Bit Position 13 */ 473 "CorrIntErr", /* Bit Position 14 */ 474 "HeaderOF", /* Bit Position 15 */ 475 NULL, /* Bit Position 16 */ 476 NULL, /* Bit Position 17 */ 477 NULL, /* Bit Position 18 */ 478 NULL, /* Bit Position 19 */ 479 NULL, /* Bit Position 20 */ 480 NULL, /* Bit Position 21 */ 481 NULL, /* Bit Position 22 */ 482 NULL, /* Bit Position 23 */ 483 NULL, /* Bit Position 24 */ 484 NULL, /* Bit Position 25 */ 485 NULL, /* Bit Position 26 */ 486 NULL, /* Bit Position 27 */ 487 NULL, /* Bit Position 28 */ 488 NULL, /* Bit Position 29 */ 489 NULL, /* Bit Position 30 */ 490 NULL, /* Bit Position 31 */ 491 }; 492 493 static const char *aer_uncorrectable_error_string[] = { 494 "Undefined", /* Bit Position 0 */ 495 NULL, 496 NULL, 497 NULL, 498 "DLP", /* Bit Position 4 */ 499 "SDES", /* Bit Position 5 */ 500 NULL, 501 NULL, 502 NULL, 503 NULL, 504 NULL, 505 NULL, 506 "TLP", /* Bit Position 12 */ 507 "FCP", /* Bit Position 13 */ 508 "CmpltTO", /* Bit Position 14 */ 509 "CmpltAbrt", /* Bit Position 15 */ 510 "UnxCmplt", /* Bit Position 16 */ 511 "RxOF", /* Bit Position 17 */ 512 "MalfTLP", /* Bit Position 18 */ 513 "ECRC", /* Bit Position 19 */ 514 "UnsupReq", /* Bit Position 20 */ 515 "ACSViol", /* Bit Position 21 */ 516 "UncorrIntErr", /* Bit Position 22 */ 517 "BlockedTLP", /* Bit Position 23 */ 518 "AtomicOpBlocked", /* Bit Position 24 */ 519 "TLPBlockedErr", /* Bit Position 25 */ 520 "PoisonTLPBlocked", /* Bit Position 26 */ 521 NULL, /* Bit Position 27 */ 522 NULL, /* Bit Position 28 */ 523 NULL, /* Bit Position 29 */ 524 NULL, /* Bit Position 30 */ 525 NULL, /* Bit Position 31 */ 526 }; 527 528 static const char *aer_agent_string[] = { 529 "Receiver ID", 530 "Requester ID", 531 "Completer ID", 532 "Transmitter ID" 533 }; 534 535 #define aer_stats_dev_attr(name, stats_array, strings_array, \ 536 total_string, total_field) \ 537 static ssize_t \ 538 name##_show(struct device *dev, struct device_attribute *attr, \ 539 char *buf) \ 540 { \ 541 unsigned int i; \ 542 struct pci_dev *pdev = to_pci_dev(dev); \ 543 u64 *stats = pdev->aer_stats->stats_array; \ 544 size_t len = 0; \ 545 \ 546 for (i = 0; i < ARRAY_SIZE(pdev->aer_stats->stats_array); i++) {\ 547 if (strings_array[i]) \ 548 len += sysfs_emit_at(buf, len, "%s %llu\n", \ 549 strings_array[i], \ 550 stats[i]); \ 551 else if (stats[i]) \ 552 len += sysfs_emit_at(buf, len, \ 553 #stats_array "_bit[%d] %llu\n",\ 554 i, stats[i]); \ 555 } \ 556 len += sysfs_emit_at(buf, len, "TOTAL_%s %llu\n", total_string, \ 557 pdev->aer_stats->total_field); \ 558 return len; \ 559 } \ 560 static DEVICE_ATTR_RO(name) 561 562 aer_stats_dev_attr(aer_dev_correctable, dev_cor_errs, 563 aer_correctable_error_string, "ERR_COR", 564 dev_total_cor_errs); 565 aer_stats_dev_attr(aer_dev_fatal, dev_fatal_errs, 566 aer_uncorrectable_error_string, "ERR_FATAL", 567 dev_total_fatal_errs); 568 aer_stats_dev_attr(aer_dev_nonfatal, dev_nonfatal_errs, 569 aer_uncorrectable_error_string, "ERR_NONFATAL", 570 dev_total_nonfatal_errs); 571 572 #define aer_stats_rootport_attr(name, field) \ 573 static ssize_t \ 574 name##_show(struct device *dev, struct device_attribute *attr, \ 575 char *buf) \ 576 { \ 577 struct pci_dev *pdev = to_pci_dev(dev); \ 578 return sysfs_emit(buf, "%llu\n", pdev->aer_stats->field); \ 579 } \ 580 static DEVICE_ATTR_RO(name) 581 582 aer_stats_rootport_attr(aer_rootport_total_err_cor, 583 rootport_total_cor_errs); 584 aer_stats_rootport_attr(aer_rootport_total_err_fatal, 585 rootport_total_fatal_errs); 586 aer_stats_rootport_attr(aer_rootport_total_err_nonfatal, 587 rootport_total_nonfatal_errs); 588 589 static struct attribute *aer_stats_attrs[] __ro_after_init = { 590 &dev_attr_aer_dev_correctable.attr, 591 &dev_attr_aer_dev_fatal.attr, 592 &dev_attr_aer_dev_nonfatal.attr, 593 &dev_attr_aer_rootport_total_err_cor.attr, 594 &dev_attr_aer_rootport_total_err_fatal.attr, 595 &dev_attr_aer_rootport_total_err_nonfatal.attr, 596 NULL 597 }; 598 599 static umode_t aer_stats_attrs_are_visible(struct kobject *kobj, 600 struct attribute *a, int n) 601 { 602 struct device *dev = kobj_to_dev(kobj); 603 struct pci_dev *pdev = to_pci_dev(dev); 604 605 if (!pdev->aer_stats) 606 return 0; 607 608 if ((a == &dev_attr_aer_rootport_total_err_cor.attr || 609 a == &dev_attr_aer_rootport_total_err_fatal.attr || 610 a == &dev_attr_aer_rootport_total_err_nonfatal.attr) && 611 ((pci_pcie_type(pdev) != PCI_EXP_TYPE_ROOT_PORT) && 612 (pci_pcie_type(pdev) != PCI_EXP_TYPE_RC_EC))) 613 return 0; 614 615 return a->mode; 616 } 617 618 const struct attribute_group aer_stats_attr_group = { 619 .attrs = aer_stats_attrs, 620 .is_visible = aer_stats_attrs_are_visible, 621 }; 622 623 static void pci_dev_aer_stats_incr(struct pci_dev *pdev, 624 struct aer_err_info *info) 625 { 626 unsigned long status = info->status & ~info->mask; 627 int i, max = -1; 628 u64 *counter = NULL; 629 struct aer_stats *aer_stats = pdev->aer_stats; 630 631 if (!aer_stats) 632 return; 633 634 switch (info->severity) { 635 case AER_CORRECTABLE: 636 aer_stats->dev_total_cor_errs++; 637 counter = &aer_stats->dev_cor_errs[0]; 638 max = AER_MAX_TYPEOF_COR_ERRS; 639 break; 640 case AER_NONFATAL: 641 aer_stats->dev_total_nonfatal_errs++; 642 counter = &aer_stats->dev_nonfatal_errs[0]; 643 max = AER_MAX_TYPEOF_UNCOR_ERRS; 644 break; 645 case AER_FATAL: 646 aer_stats->dev_total_fatal_errs++; 647 counter = &aer_stats->dev_fatal_errs[0]; 648 max = AER_MAX_TYPEOF_UNCOR_ERRS; 649 break; 650 } 651 652 for_each_set_bit(i, &status, max) 653 counter[i]++; 654 } 655 656 static void pci_rootport_aer_stats_incr(struct pci_dev *pdev, 657 struct aer_err_source *e_src) 658 { 659 struct aer_stats *aer_stats = pdev->aer_stats; 660 661 if (!aer_stats) 662 return; 663 664 if (e_src->status & PCI_ERR_ROOT_COR_RCV) 665 aer_stats->rootport_total_cor_errs++; 666 667 if (e_src->status & PCI_ERR_ROOT_UNCOR_RCV) { 668 if (e_src->status & PCI_ERR_ROOT_FATAL_RCV) 669 aer_stats->rootport_total_fatal_errs++; 670 else 671 aer_stats->rootport_total_nonfatal_errs++; 672 } 673 } 674 675 static void __print_tlp_header(struct pci_dev *dev, 676 struct aer_header_log_regs *t) 677 { 678 pci_err(dev, " TLP Header: %08x %08x %08x %08x\n", 679 t->dw0, t->dw1, t->dw2, t->dw3); 680 } 681 682 static void __aer_print_error(struct pci_dev *dev, 683 struct aer_err_info *info) 684 { 685 const char **strings; 686 unsigned long status = info->status & ~info->mask; 687 const char *level, *errmsg; 688 int i; 689 690 if (info->severity == AER_CORRECTABLE) { 691 strings = aer_correctable_error_string; 692 level = KERN_WARNING; 693 } else { 694 strings = aer_uncorrectable_error_string; 695 level = KERN_ERR; 696 } 697 698 for_each_set_bit(i, &status, 32) { 699 errmsg = strings[i]; 700 if (!errmsg) 701 errmsg = "Unknown Error Bit"; 702 703 pci_printk(level, dev, " [%2d] %-22s%s\n", i, errmsg, 704 info->first_error == i ? " (First)" : ""); 705 } 706 pci_dev_aer_stats_incr(dev, info); 707 } 708 709 void aer_print_error(struct pci_dev *dev, struct aer_err_info *info) 710 { 711 int layer, agent; 712 int id = ((dev->bus->number << 8) | dev->devfn); 713 const char *level; 714 715 if (!info->status) { 716 pci_err(dev, "PCIe Bus Error: severity=%s, type=Inaccessible, (Unregistered Agent ID)\n", 717 aer_error_severity_string[info->severity]); 718 goto out; 719 } 720 721 layer = AER_GET_LAYER_ERROR(info->severity, info->status); 722 agent = AER_GET_AGENT(info->severity, info->status); 723 724 level = (info->severity == AER_CORRECTABLE) ? KERN_WARNING : KERN_ERR; 725 726 pci_printk(level, dev, "PCIe Bus Error: severity=%s, type=%s, (%s)\n", 727 aer_error_severity_string[info->severity], 728 aer_error_layer[layer], aer_agent_string[agent]); 729 730 pci_printk(level, dev, " device [%04x:%04x] error status/mask=%08x/%08x\n", 731 dev->vendor, dev->device, info->status, info->mask); 732 733 __aer_print_error(dev, info); 734 735 if (info->tlp_header_valid) 736 __print_tlp_header(dev, &info->tlp); 737 738 out: 739 if (info->id && info->error_dev_num > 1 && info->id == id) 740 pci_err(dev, " Error of this Agent is reported first\n"); 741 742 trace_aer_event(dev_name(&dev->dev), (info->status & ~info->mask), 743 info->severity, info->tlp_header_valid, &info->tlp); 744 } 745 746 static void aer_print_port_info(struct pci_dev *dev, struct aer_err_info *info) 747 { 748 u8 bus = info->id >> 8; 749 u8 devfn = info->id & 0xff; 750 751 pci_info(dev, "%s%s error received: %04x:%02x:%02x.%d\n", 752 info->multi_error_valid ? "Multiple " : "", 753 aer_error_severity_string[info->severity], 754 pci_domain_nr(dev->bus), bus, PCI_SLOT(devfn), 755 PCI_FUNC(devfn)); 756 } 757 758 #ifdef CONFIG_ACPI_APEI_PCIEAER 759 int cper_severity_to_aer(int cper_severity) 760 { 761 switch (cper_severity) { 762 case CPER_SEV_RECOVERABLE: 763 return AER_NONFATAL; 764 case CPER_SEV_FATAL: 765 return AER_FATAL; 766 default: 767 return AER_CORRECTABLE; 768 } 769 } 770 EXPORT_SYMBOL_GPL(cper_severity_to_aer); 771 772 void cper_print_aer(struct pci_dev *dev, int aer_severity, 773 struct aer_capability_regs *aer) 774 { 775 int layer, agent, tlp_header_valid = 0; 776 u32 status, mask; 777 struct aer_err_info info; 778 779 if (aer_severity == AER_CORRECTABLE) { 780 status = aer->cor_status; 781 mask = aer->cor_mask; 782 } else { 783 status = aer->uncor_status; 784 mask = aer->uncor_mask; 785 tlp_header_valid = status & AER_LOG_TLP_MASKS; 786 } 787 788 layer = AER_GET_LAYER_ERROR(aer_severity, status); 789 agent = AER_GET_AGENT(aer_severity, status); 790 791 memset(&info, 0, sizeof(info)); 792 info.severity = aer_severity; 793 info.status = status; 794 info.mask = mask; 795 info.first_error = PCI_ERR_CAP_FEP(aer->cap_control); 796 797 pci_err(dev, "aer_status: 0x%08x, aer_mask: 0x%08x\n", status, mask); 798 __aer_print_error(dev, &info); 799 pci_err(dev, "aer_layer=%s, aer_agent=%s\n", 800 aer_error_layer[layer], aer_agent_string[agent]); 801 802 if (aer_severity != AER_CORRECTABLE) 803 pci_err(dev, "aer_uncor_severity: 0x%08x\n", 804 aer->uncor_severity); 805 806 if (tlp_header_valid) 807 __print_tlp_header(dev, &aer->header_log); 808 809 trace_aer_event(dev_name(&dev->dev), (status & ~mask), 810 aer_severity, tlp_header_valid, &aer->header_log); 811 } 812 #endif 813 814 /** 815 * add_error_device - list device to be handled 816 * @e_info: pointer to error info 817 * @dev: pointer to pci_dev to be added 818 */ 819 static int add_error_device(struct aer_err_info *e_info, struct pci_dev *dev) 820 { 821 if (e_info->error_dev_num < AER_MAX_MULTI_ERR_DEVICES) { 822 e_info->dev[e_info->error_dev_num] = pci_dev_get(dev); 823 e_info->error_dev_num++; 824 return 0; 825 } 826 return -ENOSPC; 827 } 828 829 /** 830 * is_error_source - check whether the device is source of reported error 831 * @dev: pointer to pci_dev to be checked 832 * @e_info: pointer to reported error info 833 */ 834 static bool is_error_source(struct pci_dev *dev, struct aer_err_info *e_info) 835 { 836 int aer = dev->aer_cap; 837 u32 status, mask; 838 u16 reg16; 839 840 /* 841 * When bus id is equal to 0, it might be a bad id 842 * reported by root port. 843 */ 844 if ((PCI_BUS_NUM(e_info->id) != 0) && 845 !(dev->bus->bus_flags & PCI_BUS_FLAGS_NO_AERSID)) { 846 /* Device ID match? */ 847 if (e_info->id == ((dev->bus->number << 8) | dev->devfn)) 848 return true; 849 850 /* Continue id comparing if there is no multiple error */ 851 if (!e_info->multi_error_valid) 852 return false; 853 } 854 855 /* 856 * When either 857 * 1) bus id is equal to 0. Some ports might lose the bus 858 * id of error source id; 859 * 2) bus flag PCI_BUS_FLAGS_NO_AERSID is set 860 * 3) There are multiple errors and prior ID comparing fails; 861 * We check AER status registers to find possible reporter. 862 */ 863 if (atomic_read(&dev->enable_cnt) == 0) 864 return false; 865 866 /* Check if AER is enabled */ 867 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, ®16); 868 if (!(reg16 & PCI_EXP_AER_FLAGS)) 869 return false; 870 871 if (!aer) 872 return false; 873 874 /* Check if error is recorded */ 875 if (e_info->severity == AER_CORRECTABLE) { 876 pci_read_config_dword(dev, aer + PCI_ERR_COR_STATUS, &status); 877 pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK, &mask); 878 } else { 879 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status); 880 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, &mask); 881 } 882 if (status & ~mask) 883 return true; 884 885 return false; 886 } 887 888 static int find_device_iter(struct pci_dev *dev, void *data) 889 { 890 struct aer_err_info *e_info = (struct aer_err_info *)data; 891 892 if (is_error_source(dev, e_info)) { 893 /* List this device */ 894 if (add_error_device(e_info, dev)) { 895 /* We cannot handle more... Stop iteration */ 896 /* TODO: Should print error message here? */ 897 return 1; 898 } 899 900 /* If there is only a single error, stop iteration */ 901 if (!e_info->multi_error_valid) 902 return 1; 903 } 904 return 0; 905 } 906 907 /** 908 * find_source_device - search through device hierarchy for source device 909 * @parent: pointer to Root Port pci_dev data structure 910 * @e_info: including detailed error information such like id 911 * 912 * Return true if found. 913 * 914 * Invoked by DPC when error is detected at the Root Port. 915 * Caller of this function must set id, severity, and multi_error_valid of 916 * struct aer_err_info pointed by @e_info properly. This function must fill 917 * e_info->error_dev_num and e_info->dev[], based on the given information. 918 */ 919 static bool find_source_device(struct pci_dev *parent, 920 struct aer_err_info *e_info) 921 { 922 struct pci_dev *dev = parent; 923 int result; 924 925 /* Must reset in this function */ 926 e_info->error_dev_num = 0; 927 928 /* Is Root Port an agent that sends error message? */ 929 result = find_device_iter(dev, e_info); 930 if (result) 931 return true; 932 933 if (pci_pcie_type(parent) == PCI_EXP_TYPE_RC_EC) 934 pcie_walk_rcec(parent, find_device_iter, e_info); 935 else 936 pci_walk_bus(parent->subordinate, find_device_iter, e_info); 937 938 if (!e_info->error_dev_num) { 939 pci_info(parent, "can't find device of ID%04x\n", e_info->id); 940 return false; 941 } 942 return true; 943 } 944 945 /** 946 * handle_error_source - handle logging error into an event log 947 * @dev: pointer to pci_dev data structure of error source device 948 * @info: comprehensive error information 949 * 950 * Invoked when an error being detected by Root Port. 951 */ 952 static void handle_error_source(struct pci_dev *dev, struct aer_err_info *info) 953 { 954 int aer = dev->aer_cap; 955 956 if (info->severity == AER_CORRECTABLE) { 957 /* 958 * Correctable error does not need software intervention. 959 * No need to go through error recovery process. 960 */ 961 if (aer) 962 pci_write_config_dword(dev, aer + PCI_ERR_COR_STATUS, 963 info->status); 964 if (pcie_aer_is_native(dev)) 965 pcie_clear_device_status(dev); 966 } else if (info->severity == AER_NONFATAL) 967 pcie_do_recovery(dev, pci_channel_io_normal, aer_root_reset); 968 else if (info->severity == AER_FATAL) 969 pcie_do_recovery(dev, pci_channel_io_frozen, aer_root_reset); 970 pci_dev_put(dev); 971 } 972 973 #ifdef CONFIG_ACPI_APEI_PCIEAER 974 975 #define AER_RECOVER_RING_ORDER 4 976 #define AER_RECOVER_RING_SIZE (1 << AER_RECOVER_RING_ORDER) 977 978 struct aer_recover_entry { 979 u8 bus; 980 u8 devfn; 981 u16 domain; 982 int severity; 983 struct aer_capability_regs *regs; 984 }; 985 986 static DEFINE_KFIFO(aer_recover_ring, struct aer_recover_entry, 987 AER_RECOVER_RING_SIZE); 988 989 static void aer_recover_work_func(struct work_struct *work) 990 { 991 struct aer_recover_entry entry; 992 struct pci_dev *pdev; 993 994 while (kfifo_get(&aer_recover_ring, &entry)) { 995 pdev = pci_get_domain_bus_and_slot(entry.domain, entry.bus, 996 entry.devfn); 997 if (!pdev) { 998 pr_err("no pci_dev for %04x:%02x:%02x.%x\n", 999 entry.domain, entry.bus, 1000 PCI_SLOT(entry.devfn), PCI_FUNC(entry.devfn)); 1001 continue; 1002 } 1003 cper_print_aer(pdev, entry.severity, entry.regs); 1004 if (entry.severity == AER_NONFATAL) 1005 pcie_do_recovery(pdev, pci_channel_io_normal, 1006 aer_root_reset); 1007 else if (entry.severity == AER_FATAL) 1008 pcie_do_recovery(pdev, pci_channel_io_frozen, 1009 aer_root_reset); 1010 pci_dev_put(pdev); 1011 } 1012 } 1013 1014 /* 1015 * Mutual exclusion for writers of aer_recover_ring, reader side don't 1016 * need lock, because there is only one reader and lock is not needed 1017 * between reader and writer. 1018 */ 1019 static DEFINE_SPINLOCK(aer_recover_ring_lock); 1020 static DECLARE_WORK(aer_recover_work, aer_recover_work_func); 1021 1022 void aer_recover_queue(int domain, unsigned int bus, unsigned int devfn, 1023 int severity, struct aer_capability_regs *aer_regs) 1024 { 1025 struct aer_recover_entry entry = { 1026 .bus = bus, 1027 .devfn = devfn, 1028 .domain = domain, 1029 .severity = severity, 1030 .regs = aer_regs, 1031 }; 1032 1033 if (kfifo_in_spinlocked(&aer_recover_ring, &entry, 1, 1034 &aer_recover_ring_lock)) 1035 schedule_work(&aer_recover_work); 1036 else 1037 pr_err("buffer overflow in recovery for %04x:%02x:%02x.%x\n", 1038 domain, bus, PCI_SLOT(devfn), PCI_FUNC(devfn)); 1039 } 1040 EXPORT_SYMBOL_GPL(aer_recover_queue); 1041 #endif 1042 1043 /** 1044 * aer_get_device_error_info - read error status from dev and store it to info 1045 * @dev: pointer to the device expected to have a error record 1046 * @info: pointer to structure to store the error record 1047 * 1048 * Return 1 on success, 0 on error. 1049 * 1050 * Note that @info is reused among all error devices. Clear fields properly. 1051 */ 1052 int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info) 1053 { 1054 int type = pci_pcie_type(dev); 1055 int aer = dev->aer_cap; 1056 int temp; 1057 1058 /* Must reset in this function */ 1059 info->status = 0; 1060 info->tlp_header_valid = 0; 1061 1062 /* The device might not support AER */ 1063 if (!aer) 1064 return 0; 1065 1066 if (info->severity == AER_CORRECTABLE) { 1067 pci_read_config_dword(dev, aer + PCI_ERR_COR_STATUS, 1068 &info->status); 1069 pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK, 1070 &info->mask); 1071 if (!(info->status & ~info->mask)) 1072 return 0; 1073 } else if (type == PCI_EXP_TYPE_ROOT_PORT || 1074 type == PCI_EXP_TYPE_RC_EC || 1075 type == PCI_EXP_TYPE_DOWNSTREAM || 1076 info->severity == AER_NONFATAL) { 1077 1078 /* Link is still healthy for IO reads */ 1079 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, 1080 &info->status); 1081 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, 1082 &info->mask); 1083 if (!(info->status & ~info->mask)) 1084 return 0; 1085 1086 /* Get First Error Pointer */ 1087 pci_read_config_dword(dev, aer + PCI_ERR_CAP, &temp); 1088 info->first_error = PCI_ERR_CAP_FEP(temp); 1089 1090 if (info->status & AER_LOG_TLP_MASKS) { 1091 info->tlp_header_valid = 1; 1092 pci_read_config_dword(dev, 1093 aer + PCI_ERR_HEADER_LOG, &info->tlp.dw0); 1094 pci_read_config_dword(dev, 1095 aer + PCI_ERR_HEADER_LOG + 4, &info->tlp.dw1); 1096 pci_read_config_dword(dev, 1097 aer + PCI_ERR_HEADER_LOG + 8, &info->tlp.dw2); 1098 pci_read_config_dword(dev, 1099 aer + PCI_ERR_HEADER_LOG + 12, &info->tlp.dw3); 1100 } 1101 } 1102 1103 return 1; 1104 } 1105 1106 static inline void aer_process_err_devices(struct aer_err_info *e_info) 1107 { 1108 int i; 1109 1110 /* Report all before handle them, not to lost records by reset etc. */ 1111 for (i = 0; i < e_info->error_dev_num && e_info->dev[i]; i++) { 1112 if (aer_get_device_error_info(e_info->dev[i], e_info)) 1113 aer_print_error(e_info->dev[i], e_info); 1114 } 1115 for (i = 0; i < e_info->error_dev_num && e_info->dev[i]; i++) { 1116 if (aer_get_device_error_info(e_info->dev[i], e_info)) 1117 handle_error_source(e_info->dev[i], e_info); 1118 } 1119 } 1120 1121 /** 1122 * aer_isr_one_error - consume an error detected by root port 1123 * @rpc: pointer to the root port which holds an error 1124 * @e_src: pointer to an error source 1125 */ 1126 static void aer_isr_one_error(struct aer_rpc *rpc, 1127 struct aer_err_source *e_src) 1128 { 1129 struct pci_dev *pdev = rpc->rpd; 1130 struct aer_err_info e_info; 1131 1132 pci_rootport_aer_stats_incr(pdev, e_src); 1133 1134 /* 1135 * There is a possibility that both correctable error and 1136 * uncorrectable error being logged. Report correctable error first. 1137 */ 1138 if (e_src->status & PCI_ERR_ROOT_COR_RCV) { 1139 e_info.id = ERR_COR_ID(e_src->id); 1140 e_info.severity = AER_CORRECTABLE; 1141 1142 if (e_src->status & PCI_ERR_ROOT_MULTI_COR_RCV) 1143 e_info.multi_error_valid = 1; 1144 else 1145 e_info.multi_error_valid = 0; 1146 aer_print_port_info(pdev, &e_info); 1147 1148 if (find_source_device(pdev, &e_info)) 1149 aer_process_err_devices(&e_info); 1150 } 1151 1152 if (e_src->status & PCI_ERR_ROOT_UNCOR_RCV) { 1153 e_info.id = ERR_UNCOR_ID(e_src->id); 1154 1155 if (e_src->status & PCI_ERR_ROOT_FATAL_RCV) 1156 e_info.severity = AER_FATAL; 1157 else 1158 e_info.severity = AER_NONFATAL; 1159 1160 if (e_src->status & PCI_ERR_ROOT_MULTI_UNCOR_RCV) 1161 e_info.multi_error_valid = 1; 1162 else 1163 e_info.multi_error_valid = 0; 1164 1165 aer_print_port_info(pdev, &e_info); 1166 1167 if (find_source_device(pdev, &e_info)) 1168 aer_process_err_devices(&e_info); 1169 } 1170 } 1171 1172 /** 1173 * aer_isr - consume errors detected by root port 1174 * @irq: IRQ assigned to Root Port 1175 * @context: pointer to Root Port data structure 1176 * 1177 * Invoked, as DPC, when root port records new detected error 1178 */ 1179 static irqreturn_t aer_isr(int irq, void *context) 1180 { 1181 struct pcie_device *dev = (struct pcie_device *)context; 1182 struct aer_rpc *rpc = get_service_data(dev); 1183 struct aer_err_source e_src; 1184 1185 if (kfifo_is_empty(&rpc->aer_fifo)) 1186 return IRQ_NONE; 1187 1188 while (kfifo_get(&rpc->aer_fifo, &e_src)) 1189 aer_isr_one_error(rpc, &e_src); 1190 return IRQ_HANDLED; 1191 } 1192 1193 /** 1194 * aer_irq - Root Port's ISR 1195 * @irq: IRQ assigned to Root Port 1196 * @context: pointer to Root Port data structure 1197 * 1198 * Invoked when Root Port detects AER messages. 1199 */ 1200 static irqreturn_t aer_irq(int irq, void *context) 1201 { 1202 struct pcie_device *pdev = (struct pcie_device *)context; 1203 struct aer_rpc *rpc = get_service_data(pdev); 1204 struct pci_dev *rp = rpc->rpd; 1205 int aer = rp->aer_cap; 1206 struct aer_err_source e_src = {}; 1207 1208 pci_read_config_dword(rp, aer + PCI_ERR_ROOT_STATUS, &e_src.status); 1209 if (!(e_src.status & AER_ERR_STATUS_MASK)) 1210 return IRQ_NONE; 1211 1212 pci_read_config_dword(rp, aer + PCI_ERR_ROOT_ERR_SRC, &e_src.id); 1213 pci_write_config_dword(rp, aer + PCI_ERR_ROOT_STATUS, e_src.status); 1214 1215 if (!kfifo_put(&rpc->aer_fifo, e_src)) 1216 return IRQ_HANDLED; 1217 1218 return IRQ_WAKE_THREAD; 1219 } 1220 1221 static int set_device_error_reporting(struct pci_dev *dev, void *data) 1222 { 1223 bool enable = *((bool *)data); 1224 int type = pci_pcie_type(dev); 1225 1226 if ((type == PCI_EXP_TYPE_ROOT_PORT) || 1227 (type == PCI_EXP_TYPE_RC_EC) || 1228 (type == PCI_EXP_TYPE_UPSTREAM) || 1229 (type == PCI_EXP_TYPE_DOWNSTREAM)) { 1230 if (enable) 1231 pci_enable_pcie_error_reporting(dev); 1232 else 1233 pci_disable_pcie_error_reporting(dev); 1234 } 1235 1236 return 0; 1237 } 1238 1239 /** 1240 * set_downstream_devices_error_reporting - enable/disable the error reporting bits on the root port and its downstream ports. 1241 * @dev: pointer to root port's pci_dev data structure 1242 * @enable: true = enable error reporting, false = disable error reporting. 1243 */ 1244 static void set_downstream_devices_error_reporting(struct pci_dev *dev, 1245 bool enable) 1246 { 1247 set_device_error_reporting(dev, &enable); 1248 1249 if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_EC) 1250 pcie_walk_rcec(dev, set_device_error_reporting, &enable); 1251 else if (dev->subordinate) 1252 pci_walk_bus(dev->subordinate, set_device_error_reporting, 1253 &enable); 1254 1255 } 1256 1257 /** 1258 * aer_enable_rootport - enable Root Port's interrupts when receiving messages 1259 * @rpc: pointer to a Root Port data structure 1260 * 1261 * Invoked when PCIe bus loads AER service driver. 1262 */ 1263 static void aer_enable_rootport(struct aer_rpc *rpc) 1264 { 1265 struct pci_dev *pdev = rpc->rpd; 1266 int aer = pdev->aer_cap; 1267 u16 reg16; 1268 u32 reg32; 1269 1270 /* Clear PCIe Capability's Device Status */ 1271 pcie_capability_read_word(pdev, PCI_EXP_DEVSTA, ®16); 1272 pcie_capability_write_word(pdev, PCI_EXP_DEVSTA, reg16); 1273 1274 /* Disable system error generation in response to error messages */ 1275 pcie_capability_clear_word(pdev, PCI_EXP_RTCTL, 1276 SYSTEM_ERROR_INTR_ON_MESG_MASK); 1277 1278 /* Clear error status */ 1279 pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_STATUS, ®32); 1280 pci_write_config_dword(pdev, aer + PCI_ERR_ROOT_STATUS, reg32); 1281 pci_read_config_dword(pdev, aer + PCI_ERR_COR_STATUS, ®32); 1282 pci_write_config_dword(pdev, aer + PCI_ERR_COR_STATUS, reg32); 1283 pci_read_config_dword(pdev, aer + PCI_ERR_UNCOR_STATUS, ®32); 1284 pci_write_config_dword(pdev, aer + PCI_ERR_UNCOR_STATUS, reg32); 1285 1286 /* 1287 * Enable error reporting for the root port device and downstream port 1288 * devices. 1289 */ 1290 set_downstream_devices_error_reporting(pdev, true); 1291 1292 /* Enable Root Port's interrupt in response to error messages */ 1293 pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, ®32); 1294 reg32 |= ROOT_PORT_INTR_ON_MESG_MASK; 1295 pci_write_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, reg32); 1296 } 1297 1298 /** 1299 * aer_disable_rootport - disable Root Port's interrupts when receiving messages 1300 * @rpc: pointer to a Root Port data structure 1301 * 1302 * Invoked when PCIe bus unloads AER service driver. 1303 */ 1304 static void aer_disable_rootport(struct aer_rpc *rpc) 1305 { 1306 struct pci_dev *pdev = rpc->rpd; 1307 int aer = pdev->aer_cap; 1308 u32 reg32; 1309 1310 /* 1311 * Disable error reporting for the root port device and downstream port 1312 * devices. 1313 */ 1314 set_downstream_devices_error_reporting(pdev, false); 1315 1316 /* Disable Root's interrupt in response to error messages */ 1317 pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, ®32); 1318 reg32 &= ~ROOT_PORT_INTR_ON_MESG_MASK; 1319 pci_write_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, reg32); 1320 1321 /* Clear Root's error status reg */ 1322 pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_STATUS, ®32); 1323 pci_write_config_dword(pdev, aer + PCI_ERR_ROOT_STATUS, reg32); 1324 } 1325 1326 /** 1327 * aer_remove - clean up resources 1328 * @dev: pointer to the pcie_dev data structure 1329 * 1330 * Invoked when PCI Express bus unloads or AER probe fails. 1331 */ 1332 static void aer_remove(struct pcie_device *dev) 1333 { 1334 struct aer_rpc *rpc = get_service_data(dev); 1335 1336 aer_disable_rootport(rpc); 1337 } 1338 1339 /** 1340 * aer_probe - initialize resources 1341 * @dev: pointer to the pcie_dev data structure 1342 * 1343 * Invoked when PCI Express bus loads AER service driver. 1344 */ 1345 static int aer_probe(struct pcie_device *dev) 1346 { 1347 int status; 1348 struct aer_rpc *rpc; 1349 struct device *device = &dev->device; 1350 struct pci_dev *port = dev->port; 1351 1352 BUILD_BUG_ON(ARRAY_SIZE(aer_correctable_error_string) < 1353 AER_MAX_TYPEOF_COR_ERRS); 1354 BUILD_BUG_ON(ARRAY_SIZE(aer_uncorrectable_error_string) < 1355 AER_MAX_TYPEOF_UNCOR_ERRS); 1356 1357 /* Limit to Root Ports or Root Complex Event Collectors */ 1358 if ((pci_pcie_type(port) != PCI_EXP_TYPE_RC_EC) && 1359 (pci_pcie_type(port) != PCI_EXP_TYPE_ROOT_PORT)) 1360 return -ENODEV; 1361 1362 rpc = devm_kzalloc(device, sizeof(struct aer_rpc), GFP_KERNEL); 1363 if (!rpc) 1364 return -ENOMEM; 1365 1366 rpc->rpd = port; 1367 INIT_KFIFO(rpc->aer_fifo); 1368 set_service_data(dev, rpc); 1369 1370 status = devm_request_threaded_irq(device, dev->irq, aer_irq, aer_isr, 1371 IRQF_SHARED, "aerdrv", dev); 1372 if (status) { 1373 pci_err(port, "request AER IRQ %d failed\n", dev->irq); 1374 return status; 1375 } 1376 1377 aer_enable_rootport(rpc); 1378 pci_info(port, "enabled with IRQ %d\n", dev->irq); 1379 return 0; 1380 } 1381 1382 /** 1383 * aer_root_reset - reset Root Port hierarchy, RCEC, or RCiEP 1384 * @dev: pointer to Root Port, RCEC, or RCiEP 1385 * 1386 * Invoked by Port Bus driver when performing reset. 1387 */ 1388 static pci_ers_result_t aer_root_reset(struct pci_dev *dev) 1389 { 1390 int type = pci_pcie_type(dev); 1391 struct pci_dev *root; 1392 int aer; 1393 struct pci_host_bridge *host = pci_find_host_bridge(dev->bus); 1394 u32 reg32; 1395 int rc; 1396 1397 /* 1398 * Only Root Ports and RCECs have AER Root Command and Root Status 1399 * registers. If "dev" is an RCiEP, the relevant registers are in 1400 * the RCEC. 1401 */ 1402 if (type == PCI_EXP_TYPE_RC_END) 1403 root = dev->rcec; 1404 else 1405 root = pcie_find_root_port(dev); 1406 1407 /* 1408 * If the platform retained control of AER, an RCiEP may not have 1409 * an RCEC visible to us, so dev->rcec ("root") may be NULL. In 1410 * that case, firmware is responsible for these registers. 1411 */ 1412 aer = root ? root->aer_cap : 0; 1413 1414 if ((host->native_aer || pcie_ports_native) && aer) { 1415 /* Disable Root's interrupt in response to error messages */ 1416 pci_read_config_dword(root, aer + PCI_ERR_ROOT_COMMAND, ®32); 1417 reg32 &= ~ROOT_PORT_INTR_ON_MESG_MASK; 1418 pci_write_config_dword(root, aer + PCI_ERR_ROOT_COMMAND, reg32); 1419 } 1420 1421 if (type == PCI_EXP_TYPE_RC_EC || type == PCI_EXP_TYPE_RC_END) { 1422 rc = pcie_reset_flr(dev, PCI_RESET_DO_RESET); 1423 if (!rc) 1424 pci_info(dev, "has been reset\n"); 1425 else 1426 pci_info(dev, "not reset (no FLR support: %d)\n", rc); 1427 } else { 1428 rc = pci_bus_error_reset(dev); 1429 pci_info(dev, "%s Port link has been reset (%d)\n", 1430 pci_is_root_bus(dev->bus) ? "Root" : "Downstream", rc); 1431 } 1432 1433 if ((host->native_aer || pcie_ports_native) && aer) { 1434 /* Clear Root Error Status */ 1435 pci_read_config_dword(root, aer + PCI_ERR_ROOT_STATUS, ®32); 1436 pci_write_config_dword(root, aer + PCI_ERR_ROOT_STATUS, reg32); 1437 1438 /* Enable Root Port's interrupt in response to error messages */ 1439 pci_read_config_dword(root, aer + PCI_ERR_ROOT_COMMAND, ®32); 1440 reg32 |= ROOT_PORT_INTR_ON_MESG_MASK; 1441 pci_write_config_dword(root, aer + PCI_ERR_ROOT_COMMAND, reg32); 1442 } 1443 1444 return rc ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED; 1445 } 1446 1447 static struct pcie_port_service_driver aerdriver = { 1448 .name = "aer", 1449 .port_type = PCIE_ANY_PORT, 1450 .service = PCIE_PORT_SERVICE_AER, 1451 1452 .probe = aer_probe, 1453 .remove = aer_remove, 1454 }; 1455 1456 /** 1457 * pcie_aer_init - register AER root service driver 1458 * 1459 * Invoked when AER root service driver is loaded. 1460 */ 1461 int __init pcie_aer_init(void) 1462 { 1463 if (!pci_aer_available()) 1464 return -ENXIO; 1465 return pcie_port_service_register(&aerdriver); 1466 } 1467