1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Implement the AER root port service driver. The driver registers an IRQ 4 * handler. When a root port triggers an AER interrupt, the IRQ handler 5 * collects root port status and schedules work. 6 * 7 * Copyright (C) 2006 Intel Corp. 8 * Tom Long Nguyen (tom.l.nguyen@intel.com) 9 * Zhang Yanmin (yanmin.zhang@intel.com) 10 * 11 * (C) Copyright 2009 Hewlett-Packard Development Company, L.P. 12 * Andrew Patterson <andrew.patterson@hp.com> 13 */ 14 15 #define pr_fmt(fmt) "AER: " fmt 16 #define dev_fmt pr_fmt 17 18 #include <linux/bitops.h> 19 #include <linux/cper.h> 20 #include <linux/pci.h> 21 #include <linux/pci-acpi.h> 22 #include <linux/sched.h> 23 #include <linux/kernel.h> 24 #include <linux/errno.h> 25 #include <linux/pm.h> 26 #include <linux/init.h> 27 #include <linux/interrupt.h> 28 #include <linux/delay.h> 29 #include <linux/kfifo.h> 30 #include <linux/slab.h> 31 #include <acpi/apei.h> 32 #include <acpi/ghes.h> 33 #include <ras/ras_event.h> 34 35 #include "../pci.h" 36 #include "portdrv.h" 37 38 #define AER_ERROR_SOURCES_MAX 128 39 40 #define AER_MAX_TYPEOF_COR_ERRS 16 /* as per PCI_ERR_COR_STATUS */ 41 #define AER_MAX_TYPEOF_UNCOR_ERRS 27 /* as per PCI_ERR_UNCOR_STATUS*/ 42 43 struct aer_err_source { 44 u32 status; /* PCI_ERR_ROOT_STATUS */ 45 u32 id; /* PCI_ERR_ROOT_ERR_SRC */ 46 }; 47 48 struct aer_rpc { 49 struct pci_dev *rpd; /* Root Port device */ 50 DECLARE_KFIFO(aer_fifo, struct aer_err_source, AER_ERROR_SOURCES_MAX); 51 }; 52 53 /* AER stats for the device */ 54 struct aer_stats { 55 56 /* 57 * Fields for all AER capable devices. They indicate the errors 58 * "as seen by this device". Note that this may mean that if an 59 * end point is causing problems, the AER counters may increment 60 * at its link partner (e.g. root port) because the errors will be 61 * "seen" by the link partner and not the problematic end point 62 * itself (which may report all counters as 0 as it never saw any 63 * problems). 64 */ 65 /* Counters for different type of correctable errors */ 66 u64 dev_cor_errs[AER_MAX_TYPEOF_COR_ERRS]; 67 /* Counters for different type of fatal uncorrectable errors */ 68 u64 dev_fatal_errs[AER_MAX_TYPEOF_UNCOR_ERRS]; 69 /* Counters for different type of nonfatal uncorrectable errors */ 70 u64 dev_nonfatal_errs[AER_MAX_TYPEOF_UNCOR_ERRS]; 71 /* Total number of ERR_COR sent by this device */ 72 u64 dev_total_cor_errs; 73 /* Total number of ERR_FATAL sent by this device */ 74 u64 dev_total_fatal_errs; 75 /* Total number of ERR_NONFATAL sent by this device */ 76 u64 dev_total_nonfatal_errs; 77 78 /* 79 * Fields for Root ports & root complex event collectors only, these 80 * indicate the total number of ERR_COR, ERR_FATAL, and ERR_NONFATAL 81 * messages received by the root port / event collector, INCLUDING the 82 * ones that are generated internally (by the rootport itself) 83 */ 84 u64 rootport_total_cor_errs; 85 u64 rootport_total_fatal_errs; 86 u64 rootport_total_nonfatal_errs; 87 }; 88 89 #define AER_LOG_TLP_MASKS (PCI_ERR_UNC_POISON_TLP| \ 90 PCI_ERR_UNC_ECRC| \ 91 PCI_ERR_UNC_UNSUP| \ 92 PCI_ERR_UNC_COMP_ABORT| \ 93 PCI_ERR_UNC_UNX_COMP| \ 94 PCI_ERR_UNC_MALF_TLP) 95 96 #define SYSTEM_ERROR_INTR_ON_MESG_MASK (PCI_EXP_RTCTL_SECEE| \ 97 PCI_EXP_RTCTL_SENFEE| \ 98 PCI_EXP_RTCTL_SEFEE) 99 #define ROOT_PORT_INTR_ON_MESG_MASK (PCI_ERR_ROOT_CMD_COR_EN| \ 100 PCI_ERR_ROOT_CMD_NONFATAL_EN| \ 101 PCI_ERR_ROOT_CMD_FATAL_EN) 102 #define ERR_COR_ID(d) (d & 0xffff) 103 #define ERR_UNCOR_ID(d) (d >> 16) 104 105 #define AER_ERR_STATUS_MASK (PCI_ERR_ROOT_UNCOR_RCV | \ 106 PCI_ERR_ROOT_COR_RCV | \ 107 PCI_ERR_ROOT_MULTI_COR_RCV | \ 108 PCI_ERR_ROOT_MULTI_UNCOR_RCV) 109 110 static int pcie_aer_disable; 111 static pci_ers_result_t aer_root_reset(struct pci_dev *dev); 112 113 void pci_no_aer(void) 114 { 115 pcie_aer_disable = 1; 116 } 117 118 bool pci_aer_available(void) 119 { 120 return !pcie_aer_disable && pci_msi_enabled(); 121 } 122 123 #ifdef CONFIG_PCIE_ECRC 124 125 #define ECRC_POLICY_DEFAULT 0 /* ECRC set by BIOS */ 126 #define ECRC_POLICY_OFF 1 /* ECRC off for performance */ 127 #define ECRC_POLICY_ON 2 /* ECRC on for data integrity */ 128 129 static int ecrc_policy = ECRC_POLICY_DEFAULT; 130 131 static const char * const ecrc_policy_str[] = { 132 [ECRC_POLICY_DEFAULT] = "bios", 133 [ECRC_POLICY_OFF] = "off", 134 [ECRC_POLICY_ON] = "on" 135 }; 136 137 /** 138 * enable_ecrc_checking - enable PCIe ECRC checking for a device 139 * @dev: the PCI device 140 * 141 * Returns 0 on success, or negative on failure. 142 */ 143 static int enable_ecrc_checking(struct pci_dev *dev) 144 { 145 int aer = dev->aer_cap; 146 u32 reg32; 147 148 if (!aer) 149 return -ENODEV; 150 151 pci_read_config_dword(dev, aer + PCI_ERR_CAP, ®32); 152 if (reg32 & PCI_ERR_CAP_ECRC_GENC) 153 reg32 |= PCI_ERR_CAP_ECRC_GENE; 154 if (reg32 & PCI_ERR_CAP_ECRC_CHKC) 155 reg32 |= PCI_ERR_CAP_ECRC_CHKE; 156 pci_write_config_dword(dev, aer + PCI_ERR_CAP, reg32); 157 158 return 0; 159 } 160 161 /** 162 * disable_ecrc_checking - disables PCIe ECRC checking for a device 163 * @dev: the PCI device 164 * 165 * Returns 0 on success, or negative on failure. 166 */ 167 static int disable_ecrc_checking(struct pci_dev *dev) 168 { 169 int aer = dev->aer_cap; 170 u32 reg32; 171 172 if (!aer) 173 return -ENODEV; 174 175 pci_read_config_dword(dev, aer + PCI_ERR_CAP, ®32); 176 reg32 &= ~(PCI_ERR_CAP_ECRC_GENE | PCI_ERR_CAP_ECRC_CHKE); 177 pci_write_config_dword(dev, aer + PCI_ERR_CAP, reg32); 178 179 return 0; 180 } 181 182 /** 183 * pcie_set_ecrc_checking - set/unset PCIe ECRC checking for a device based 184 * on global policy 185 * @dev: the PCI device 186 */ 187 void pcie_set_ecrc_checking(struct pci_dev *dev) 188 { 189 if (!pcie_aer_is_native(dev)) 190 return; 191 192 switch (ecrc_policy) { 193 case ECRC_POLICY_DEFAULT: 194 return; 195 case ECRC_POLICY_OFF: 196 disable_ecrc_checking(dev); 197 break; 198 case ECRC_POLICY_ON: 199 enable_ecrc_checking(dev); 200 break; 201 default: 202 return; 203 } 204 } 205 206 /** 207 * pcie_ecrc_get_policy - parse kernel command-line ecrc option 208 * @str: ECRC policy from kernel command line to use 209 */ 210 void pcie_ecrc_get_policy(char *str) 211 { 212 int i; 213 214 i = match_string(ecrc_policy_str, ARRAY_SIZE(ecrc_policy_str), str); 215 if (i < 0) 216 return; 217 218 ecrc_policy = i; 219 } 220 #endif /* CONFIG_PCIE_ECRC */ 221 222 #define PCI_EXP_AER_FLAGS (PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE | \ 223 PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE) 224 225 int pcie_aer_is_native(struct pci_dev *dev) 226 { 227 struct pci_host_bridge *host = pci_find_host_bridge(dev->bus); 228 229 if (!dev->aer_cap) 230 return 0; 231 232 return pcie_ports_native || host->native_aer; 233 } 234 EXPORT_SYMBOL_NS_GPL(pcie_aer_is_native, "CXL"); 235 236 static int pci_enable_pcie_error_reporting(struct pci_dev *dev) 237 { 238 int rc; 239 240 if (!pcie_aer_is_native(dev)) 241 return -EIO; 242 243 rc = pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_AER_FLAGS); 244 return pcibios_err_to_errno(rc); 245 } 246 247 int pci_aer_clear_nonfatal_status(struct pci_dev *dev) 248 { 249 int aer = dev->aer_cap; 250 u32 status, sev; 251 252 if (!pcie_aer_is_native(dev)) 253 return -EIO; 254 255 /* Clear status bits for ERR_NONFATAL errors only */ 256 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status); 257 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, &sev); 258 status &= ~sev; 259 if (status) 260 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, status); 261 262 return 0; 263 } 264 EXPORT_SYMBOL_GPL(pci_aer_clear_nonfatal_status); 265 266 void pci_aer_clear_fatal_status(struct pci_dev *dev) 267 { 268 int aer = dev->aer_cap; 269 u32 status, sev; 270 271 if (!pcie_aer_is_native(dev)) 272 return; 273 274 /* Clear status bits for ERR_FATAL errors only */ 275 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status); 276 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, &sev); 277 status &= sev; 278 if (status) 279 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, status); 280 } 281 282 /** 283 * pci_aer_raw_clear_status - Clear AER error registers. 284 * @dev: the PCI device 285 * 286 * Clearing AER error status registers unconditionally, regardless of 287 * whether they're owned by firmware or the OS. 288 * 289 * Returns 0 on success, or negative on failure. 290 */ 291 int pci_aer_raw_clear_status(struct pci_dev *dev) 292 { 293 int aer = dev->aer_cap; 294 u32 status; 295 int port_type; 296 297 if (!aer) 298 return -EIO; 299 300 port_type = pci_pcie_type(dev); 301 if (port_type == PCI_EXP_TYPE_ROOT_PORT || 302 port_type == PCI_EXP_TYPE_RC_EC) { 303 pci_read_config_dword(dev, aer + PCI_ERR_ROOT_STATUS, &status); 304 pci_write_config_dword(dev, aer + PCI_ERR_ROOT_STATUS, status); 305 } 306 307 pci_read_config_dword(dev, aer + PCI_ERR_COR_STATUS, &status); 308 pci_write_config_dword(dev, aer + PCI_ERR_COR_STATUS, status); 309 310 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status); 311 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, status); 312 313 return 0; 314 } 315 316 int pci_aer_clear_status(struct pci_dev *dev) 317 { 318 if (!pcie_aer_is_native(dev)) 319 return -EIO; 320 321 return pci_aer_raw_clear_status(dev); 322 } 323 324 void pci_save_aer_state(struct pci_dev *dev) 325 { 326 int aer = dev->aer_cap; 327 struct pci_cap_saved_state *save_state; 328 u32 *cap; 329 330 if (!aer) 331 return; 332 333 save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_ERR); 334 if (!save_state) 335 return; 336 337 cap = &save_state->cap.data[0]; 338 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, cap++); 339 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, cap++); 340 pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK, cap++); 341 pci_read_config_dword(dev, aer + PCI_ERR_CAP, cap++); 342 if (pcie_cap_has_rtctl(dev)) 343 pci_read_config_dword(dev, aer + PCI_ERR_ROOT_COMMAND, cap++); 344 } 345 346 void pci_restore_aer_state(struct pci_dev *dev) 347 { 348 int aer = dev->aer_cap; 349 struct pci_cap_saved_state *save_state; 350 u32 *cap; 351 352 if (!aer) 353 return; 354 355 save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_ERR); 356 if (!save_state) 357 return; 358 359 cap = &save_state->cap.data[0]; 360 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, *cap++); 361 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, *cap++); 362 pci_write_config_dword(dev, aer + PCI_ERR_COR_MASK, *cap++); 363 pci_write_config_dword(dev, aer + PCI_ERR_CAP, *cap++); 364 if (pcie_cap_has_rtctl(dev)) 365 pci_write_config_dword(dev, aer + PCI_ERR_ROOT_COMMAND, *cap++); 366 } 367 368 void pci_aer_init(struct pci_dev *dev) 369 { 370 int n; 371 372 dev->aer_cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); 373 if (!dev->aer_cap) 374 return; 375 376 dev->aer_stats = kzalloc(sizeof(struct aer_stats), GFP_KERNEL); 377 378 /* 379 * We save/restore PCI_ERR_UNCOR_MASK, PCI_ERR_UNCOR_SEVER, 380 * PCI_ERR_COR_MASK, and PCI_ERR_CAP. Root and Root Complex Event 381 * Collectors also implement PCI_ERR_ROOT_COMMAND (PCIe r5.0, sec 382 * 7.8.4). 383 */ 384 n = pcie_cap_has_rtctl(dev) ? 5 : 4; 385 pci_add_ext_cap_save_buffer(dev, PCI_EXT_CAP_ID_ERR, sizeof(u32) * n); 386 387 pci_aer_clear_status(dev); 388 389 if (pci_aer_available()) 390 pci_enable_pcie_error_reporting(dev); 391 392 pcie_set_ecrc_checking(dev); 393 } 394 395 void pci_aer_exit(struct pci_dev *dev) 396 { 397 kfree(dev->aer_stats); 398 dev->aer_stats = NULL; 399 } 400 401 #define AER_AGENT_RECEIVER 0 402 #define AER_AGENT_REQUESTER 1 403 #define AER_AGENT_COMPLETER 2 404 #define AER_AGENT_TRANSMITTER 3 405 406 #define AER_AGENT_REQUESTER_MASK(t) ((t == AER_CORRECTABLE) ? \ 407 0 : (PCI_ERR_UNC_COMP_TIME|PCI_ERR_UNC_UNSUP)) 408 #define AER_AGENT_COMPLETER_MASK(t) ((t == AER_CORRECTABLE) ? \ 409 0 : PCI_ERR_UNC_COMP_ABORT) 410 #define AER_AGENT_TRANSMITTER_MASK(t) ((t == AER_CORRECTABLE) ? \ 411 (PCI_ERR_COR_REP_ROLL|PCI_ERR_COR_REP_TIMER) : 0) 412 413 #define AER_GET_AGENT(t, e) \ 414 ((e & AER_AGENT_COMPLETER_MASK(t)) ? AER_AGENT_COMPLETER : \ 415 (e & AER_AGENT_REQUESTER_MASK(t)) ? AER_AGENT_REQUESTER : \ 416 (e & AER_AGENT_TRANSMITTER_MASK(t)) ? AER_AGENT_TRANSMITTER : \ 417 AER_AGENT_RECEIVER) 418 419 #define AER_PHYSICAL_LAYER_ERROR 0 420 #define AER_DATA_LINK_LAYER_ERROR 1 421 #define AER_TRANSACTION_LAYER_ERROR 2 422 423 #define AER_PHYSICAL_LAYER_ERROR_MASK(t) ((t == AER_CORRECTABLE) ? \ 424 PCI_ERR_COR_RCVR : 0) 425 #define AER_DATA_LINK_LAYER_ERROR_MASK(t) ((t == AER_CORRECTABLE) ? \ 426 (PCI_ERR_COR_BAD_TLP| \ 427 PCI_ERR_COR_BAD_DLLP| \ 428 PCI_ERR_COR_REP_ROLL| \ 429 PCI_ERR_COR_REP_TIMER) : PCI_ERR_UNC_DLP) 430 431 #define AER_GET_LAYER_ERROR(t, e) \ 432 ((e & AER_PHYSICAL_LAYER_ERROR_MASK(t)) ? AER_PHYSICAL_LAYER_ERROR : \ 433 (e & AER_DATA_LINK_LAYER_ERROR_MASK(t)) ? AER_DATA_LINK_LAYER_ERROR : \ 434 AER_TRANSACTION_LAYER_ERROR) 435 436 /* 437 * AER error strings 438 */ 439 static const char * const aer_error_severity_string[] = { 440 "Uncorrectable (Non-Fatal)", 441 "Uncorrectable (Fatal)", 442 "Correctable" 443 }; 444 445 static const char *aer_error_layer[] = { 446 "Physical Layer", 447 "Data Link Layer", 448 "Transaction Layer" 449 }; 450 451 static const char *aer_correctable_error_string[] = { 452 "RxErr", /* Bit Position 0 */ 453 NULL, 454 NULL, 455 NULL, 456 NULL, 457 NULL, 458 "BadTLP", /* Bit Position 6 */ 459 "BadDLLP", /* Bit Position 7 */ 460 "Rollover", /* Bit Position 8 */ 461 NULL, 462 NULL, 463 NULL, 464 "Timeout", /* Bit Position 12 */ 465 "NonFatalErr", /* Bit Position 13 */ 466 "CorrIntErr", /* Bit Position 14 */ 467 "HeaderOF", /* Bit Position 15 */ 468 NULL, /* Bit Position 16 */ 469 NULL, /* Bit Position 17 */ 470 NULL, /* Bit Position 18 */ 471 NULL, /* Bit Position 19 */ 472 NULL, /* Bit Position 20 */ 473 NULL, /* Bit Position 21 */ 474 NULL, /* Bit Position 22 */ 475 NULL, /* Bit Position 23 */ 476 NULL, /* Bit Position 24 */ 477 NULL, /* Bit Position 25 */ 478 NULL, /* Bit Position 26 */ 479 NULL, /* Bit Position 27 */ 480 NULL, /* Bit Position 28 */ 481 NULL, /* Bit Position 29 */ 482 NULL, /* Bit Position 30 */ 483 NULL, /* Bit Position 31 */ 484 }; 485 486 static const char *aer_uncorrectable_error_string[] = { 487 "Undefined", /* Bit Position 0 */ 488 NULL, 489 NULL, 490 NULL, 491 "DLP", /* Bit Position 4 */ 492 "SDES", /* Bit Position 5 */ 493 NULL, 494 NULL, 495 NULL, 496 NULL, 497 NULL, 498 NULL, 499 "TLP", /* Bit Position 12 */ 500 "FCP", /* Bit Position 13 */ 501 "CmpltTO", /* Bit Position 14 */ 502 "CmpltAbrt", /* Bit Position 15 */ 503 "UnxCmplt", /* Bit Position 16 */ 504 "RxOF", /* Bit Position 17 */ 505 "MalfTLP", /* Bit Position 18 */ 506 "ECRC", /* Bit Position 19 */ 507 "UnsupReq", /* Bit Position 20 */ 508 "ACSViol", /* Bit Position 21 */ 509 "UncorrIntErr", /* Bit Position 22 */ 510 "BlockedTLP", /* Bit Position 23 */ 511 "AtomicOpBlocked", /* Bit Position 24 */ 512 "TLPBlockedErr", /* Bit Position 25 */ 513 "PoisonTLPBlocked", /* Bit Position 26 */ 514 NULL, /* Bit Position 27 */ 515 NULL, /* Bit Position 28 */ 516 NULL, /* Bit Position 29 */ 517 NULL, /* Bit Position 30 */ 518 NULL, /* Bit Position 31 */ 519 }; 520 521 static const char *aer_agent_string[] = { 522 "Receiver ID", 523 "Requester ID", 524 "Completer ID", 525 "Transmitter ID" 526 }; 527 528 #define aer_stats_dev_attr(name, stats_array, strings_array, \ 529 total_string, total_field) \ 530 static ssize_t \ 531 name##_show(struct device *dev, struct device_attribute *attr, \ 532 char *buf) \ 533 { \ 534 unsigned int i; \ 535 struct pci_dev *pdev = to_pci_dev(dev); \ 536 u64 *stats = pdev->aer_stats->stats_array; \ 537 size_t len = 0; \ 538 \ 539 for (i = 0; i < ARRAY_SIZE(pdev->aer_stats->stats_array); i++) {\ 540 if (strings_array[i]) \ 541 len += sysfs_emit_at(buf, len, "%s %llu\n", \ 542 strings_array[i], \ 543 stats[i]); \ 544 else if (stats[i]) \ 545 len += sysfs_emit_at(buf, len, \ 546 #stats_array "_bit[%d] %llu\n",\ 547 i, stats[i]); \ 548 } \ 549 len += sysfs_emit_at(buf, len, "TOTAL_%s %llu\n", total_string, \ 550 pdev->aer_stats->total_field); \ 551 return len; \ 552 } \ 553 static DEVICE_ATTR_RO(name) 554 555 aer_stats_dev_attr(aer_dev_correctable, dev_cor_errs, 556 aer_correctable_error_string, "ERR_COR", 557 dev_total_cor_errs); 558 aer_stats_dev_attr(aer_dev_fatal, dev_fatal_errs, 559 aer_uncorrectable_error_string, "ERR_FATAL", 560 dev_total_fatal_errs); 561 aer_stats_dev_attr(aer_dev_nonfatal, dev_nonfatal_errs, 562 aer_uncorrectable_error_string, "ERR_NONFATAL", 563 dev_total_nonfatal_errs); 564 565 #define aer_stats_rootport_attr(name, field) \ 566 static ssize_t \ 567 name##_show(struct device *dev, struct device_attribute *attr, \ 568 char *buf) \ 569 { \ 570 struct pci_dev *pdev = to_pci_dev(dev); \ 571 return sysfs_emit(buf, "%llu\n", pdev->aer_stats->field); \ 572 } \ 573 static DEVICE_ATTR_RO(name) 574 575 aer_stats_rootport_attr(aer_rootport_total_err_cor, 576 rootport_total_cor_errs); 577 aer_stats_rootport_attr(aer_rootport_total_err_fatal, 578 rootport_total_fatal_errs); 579 aer_stats_rootport_attr(aer_rootport_total_err_nonfatal, 580 rootport_total_nonfatal_errs); 581 582 static struct attribute *aer_stats_attrs[] __ro_after_init = { 583 &dev_attr_aer_dev_correctable.attr, 584 &dev_attr_aer_dev_fatal.attr, 585 &dev_attr_aer_dev_nonfatal.attr, 586 &dev_attr_aer_rootport_total_err_cor.attr, 587 &dev_attr_aer_rootport_total_err_fatal.attr, 588 &dev_attr_aer_rootport_total_err_nonfatal.attr, 589 NULL 590 }; 591 592 static umode_t aer_stats_attrs_are_visible(struct kobject *kobj, 593 struct attribute *a, int n) 594 { 595 struct device *dev = kobj_to_dev(kobj); 596 struct pci_dev *pdev = to_pci_dev(dev); 597 598 if (!pdev->aer_stats) 599 return 0; 600 601 if ((a == &dev_attr_aer_rootport_total_err_cor.attr || 602 a == &dev_attr_aer_rootport_total_err_fatal.attr || 603 a == &dev_attr_aer_rootport_total_err_nonfatal.attr) && 604 ((pci_pcie_type(pdev) != PCI_EXP_TYPE_ROOT_PORT) && 605 (pci_pcie_type(pdev) != PCI_EXP_TYPE_RC_EC))) 606 return 0; 607 608 return a->mode; 609 } 610 611 const struct attribute_group aer_stats_attr_group = { 612 .attrs = aer_stats_attrs, 613 .is_visible = aer_stats_attrs_are_visible, 614 }; 615 616 static void pci_dev_aer_stats_incr(struct pci_dev *pdev, 617 struct aer_err_info *info) 618 { 619 unsigned long status = info->status & ~info->mask; 620 int i, max = -1; 621 u64 *counter = NULL; 622 struct aer_stats *aer_stats = pdev->aer_stats; 623 624 if (!aer_stats) 625 return; 626 627 switch (info->severity) { 628 case AER_CORRECTABLE: 629 aer_stats->dev_total_cor_errs++; 630 counter = &aer_stats->dev_cor_errs[0]; 631 max = AER_MAX_TYPEOF_COR_ERRS; 632 break; 633 case AER_NONFATAL: 634 aer_stats->dev_total_nonfatal_errs++; 635 counter = &aer_stats->dev_nonfatal_errs[0]; 636 max = AER_MAX_TYPEOF_UNCOR_ERRS; 637 break; 638 case AER_FATAL: 639 aer_stats->dev_total_fatal_errs++; 640 counter = &aer_stats->dev_fatal_errs[0]; 641 max = AER_MAX_TYPEOF_UNCOR_ERRS; 642 break; 643 } 644 645 for_each_set_bit(i, &status, max) 646 counter[i]++; 647 } 648 649 static void pci_rootport_aer_stats_incr(struct pci_dev *pdev, 650 struct aer_err_source *e_src) 651 { 652 struct aer_stats *aer_stats = pdev->aer_stats; 653 654 if (!aer_stats) 655 return; 656 657 if (e_src->status & PCI_ERR_ROOT_COR_RCV) 658 aer_stats->rootport_total_cor_errs++; 659 660 if (e_src->status & PCI_ERR_ROOT_UNCOR_RCV) { 661 if (e_src->status & PCI_ERR_ROOT_FATAL_RCV) 662 aer_stats->rootport_total_fatal_errs++; 663 else 664 aer_stats->rootport_total_nonfatal_errs++; 665 } 666 } 667 668 static void __aer_print_error(struct pci_dev *dev, 669 struct aer_err_info *info) 670 { 671 const char **strings; 672 unsigned long status = info->status & ~info->mask; 673 const char *level, *errmsg; 674 int i; 675 676 if (info->severity == AER_CORRECTABLE) { 677 strings = aer_correctable_error_string; 678 level = KERN_WARNING; 679 } else { 680 strings = aer_uncorrectable_error_string; 681 level = KERN_ERR; 682 } 683 684 for_each_set_bit(i, &status, 32) { 685 errmsg = strings[i]; 686 if (!errmsg) 687 errmsg = "Unknown Error Bit"; 688 689 pci_printk(level, dev, " [%2d] %-22s%s\n", i, errmsg, 690 info->first_error == i ? " (First)" : ""); 691 } 692 pci_dev_aer_stats_incr(dev, info); 693 } 694 695 void aer_print_error(struct pci_dev *dev, struct aer_err_info *info) 696 { 697 int layer, agent; 698 int id = pci_dev_id(dev); 699 const char *level; 700 701 if (!info->status) { 702 pci_err(dev, "PCIe Bus Error: severity=%s, type=Inaccessible, (Unregistered Agent ID)\n", 703 aer_error_severity_string[info->severity]); 704 goto out; 705 } 706 707 layer = AER_GET_LAYER_ERROR(info->severity, info->status); 708 agent = AER_GET_AGENT(info->severity, info->status); 709 710 level = (info->severity == AER_CORRECTABLE) ? KERN_WARNING : KERN_ERR; 711 712 pci_printk(level, dev, "PCIe Bus Error: severity=%s, type=%s, (%s)\n", 713 aer_error_severity_string[info->severity], 714 aer_error_layer[layer], aer_agent_string[agent]); 715 716 pci_printk(level, dev, " device [%04x:%04x] error status/mask=%08x/%08x\n", 717 dev->vendor, dev->device, info->status, info->mask); 718 719 __aer_print_error(dev, info); 720 721 if (info->tlp_header_valid) 722 pcie_print_tlp_log(dev, &info->tlp, dev_fmt(" ")); 723 724 out: 725 if (info->id && info->error_dev_num > 1 && info->id == id) 726 pci_err(dev, " Error of this Agent is reported first\n"); 727 728 trace_aer_event(dev_name(&dev->dev), (info->status & ~info->mask), 729 info->severity, info->tlp_header_valid, &info->tlp); 730 } 731 732 static void aer_print_port_info(struct pci_dev *dev, struct aer_err_info *info) 733 { 734 u8 bus = info->id >> 8; 735 u8 devfn = info->id & 0xff; 736 737 pci_info(dev, "%s%s error message received from %04x:%02x:%02x.%d\n", 738 info->multi_error_valid ? "Multiple " : "", 739 aer_error_severity_string[info->severity], 740 pci_domain_nr(dev->bus), bus, PCI_SLOT(devfn), 741 PCI_FUNC(devfn)); 742 } 743 744 #ifdef CONFIG_ACPI_APEI_PCIEAER 745 int cper_severity_to_aer(int cper_severity) 746 { 747 switch (cper_severity) { 748 case CPER_SEV_RECOVERABLE: 749 return AER_NONFATAL; 750 case CPER_SEV_FATAL: 751 return AER_FATAL; 752 default: 753 return AER_CORRECTABLE; 754 } 755 } 756 EXPORT_SYMBOL_GPL(cper_severity_to_aer); 757 #endif 758 759 void pci_print_aer(struct pci_dev *dev, int aer_severity, 760 struct aer_capability_regs *aer) 761 { 762 int layer, agent, tlp_header_valid = 0; 763 u32 status, mask; 764 struct aer_err_info info; 765 766 if (aer_severity == AER_CORRECTABLE) { 767 status = aer->cor_status; 768 mask = aer->cor_mask; 769 } else { 770 status = aer->uncor_status; 771 mask = aer->uncor_mask; 772 tlp_header_valid = status & AER_LOG_TLP_MASKS; 773 } 774 775 layer = AER_GET_LAYER_ERROR(aer_severity, status); 776 agent = AER_GET_AGENT(aer_severity, status); 777 778 memset(&info, 0, sizeof(info)); 779 info.severity = aer_severity; 780 info.status = status; 781 info.mask = mask; 782 info.first_error = PCI_ERR_CAP_FEP(aer->cap_control); 783 784 pci_err(dev, "aer_status: 0x%08x, aer_mask: 0x%08x\n", status, mask); 785 __aer_print_error(dev, &info); 786 pci_err(dev, "aer_layer=%s, aer_agent=%s\n", 787 aer_error_layer[layer], aer_agent_string[agent]); 788 789 if (aer_severity != AER_CORRECTABLE) 790 pci_err(dev, "aer_uncor_severity: 0x%08x\n", 791 aer->uncor_severity); 792 793 if (tlp_header_valid) 794 pcie_print_tlp_log(dev, &aer->header_log, dev_fmt(" ")); 795 796 trace_aer_event(dev_name(&dev->dev), (status & ~mask), 797 aer_severity, tlp_header_valid, &aer->header_log); 798 } 799 EXPORT_SYMBOL_NS_GPL(pci_print_aer, "CXL"); 800 801 /** 802 * add_error_device - list device to be handled 803 * @e_info: pointer to error info 804 * @dev: pointer to pci_dev to be added 805 */ 806 static int add_error_device(struct aer_err_info *e_info, struct pci_dev *dev) 807 { 808 if (e_info->error_dev_num < AER_MAX_MULTI_ERR_DEVICES) { 809 e_info->dev[e_info->error_dev_num] = pci_dev_get(dev); 810 e_info->error_dev_num++; 811 return 0; 812 } 813 return -ENOSPC; 814 } 815 816 /** 817 * is_error_source - check whether the device is source of reported error 818 * @dev: pointer to pci_dev to be checked 819 * @e_info: pointer to reported error info 820 */ 821 static bool is_error_source(struct pci_dev *dev, struct aer_err_info *e_info) 822 { 823 int aer = dev->aer_cap; 824 u32 status, mask; 825 u16 reg16; 826 827 /* 828 * When bus id is equal to 0, it might be a bad id 829 * reported by root port. 830 */ 831 if ((PCI_BUS_NUM(e_info->id) != 0) && 832 !(dev->bus->bus_flags & PCI_BUS_FLAGS_NO_AERSID)) { 833 /* Device ID match? */ 834 if (e_info->id == pci_dev_id(dev)) 835 return true; 836 837 /* Continue id comparing if there is no multiple error */ 838 if (!e_info->multi_error_valid) 839 return false; 840 } 841 842 /* 843 * When either 844 * 1) bus id is equal to 0. Some ports might lose the bus 845 * id of error source id; 846 * 2) bus flag PCI_BUS_FLAGS_NO_AERSID is set 847 * 3) There are multiple errors and prior ID comparing fails; 848 * We check AER status registers to find possible reporter. 849 */ 850 if (atomic_read(&dev->enable_cnt) == 0) 851 return false; 852 853 /* Check if AER is enabled */ 854 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, ®16); 855 if (!(reg16 & PCI_EXP_AER_FLAGS)) 856 return false; 857 858 if (!aer) 859 return false; 860 861 /* Check if error is recorded */ 862 if (e_info->severity == AER_CORRECTABLE) { 863 pci_read_config_dword(dev, aer + PCI_ERR_COR_STATUS, &status); 864 pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK, &mask); 865 } else { 866 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status); 867 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, &mask); 868 } 869 if (status & ~mask) 870 return true; 871 872 return false; 873 } 874 875 static int find_device_iter(struct pci_dev *dev, void *data) 876 { 877 struct aer_err_info *e_info = (struct aer_err_info *)data; 878 879 if (is_error_source(dev, e_info)) { 880 /* List this device */ 881 if (add_error_device(e_info, dev)) { 882 /* We cannot handle more... Stop iteration */ 883 /* TODO: Should print error message here? */ 884 return 1; 885 } 886 887 /* If there is only a single error, stop iteration */ 888 if (!e_info->multi_error_valid) 889 return 1; 890 } 891 return 0; 892 } 893 894 /** 895 * find_source_device - search through device hierarchy for source device 896 * @parent: pointer to Root Port pci_dev data structure 897 * @e_info: including detailed error information such like id 898 * 899 * Return true if found. 900 * 901 * Invoked by DPC when error is detected at the Root Port. 902 * Caller of this function must set id, severity, and multi_error_valid of 903 * struct aer_err_info pointed by @e_info properly. This function must fill 904 * e_info->error_dev_num and e_info->dev[], based on the given information. 905 */ 906 static bool find_source_device(struct pci_dev *parent, 907 struct aer_err_info *e_info) 908 { 909 struct pci_dev *dev = parent; 910 int result; 911 912 /* Must reset in this function */ 913 e_info->error_dev_num = 0; 914 915 /* Is Root Port an agent that sends error message? */ 916 result = find_device_iter(dev, e_info); 917 if (result) 918 return true; 919 920 if (pci_pcie_type(parent) == PCI_EXP_TYPE_RC_EC) 921 pcie_walk_rcec(parent, find_device_iter, e_info); 922 else 923 pci_walk_bus(parent->subordinate, find_device_iter, e_info); 924 925 if (!e_info->error_dev_num) { 926 u8 bus = e_info->id >> 8; 927 u8 devfn = e_info->id & 0xff; 928 929 pci_info(parent, "found no error details for %04x:%02x:%02x.%d\n", 930 pci_domain_nr(parent->bus), bus, PCI_SLOT(devfn), 931 PCI_FUNC(devfn)); 932 return false; 933 } 934 return true; 935 } 936 937 #ifdef CONFIG_PCIEAER_CXL 938 939 /** 940 * pci_aer_unmask_internal_errors - unmask internal errors 941 * @dev: pointer to the pcie_dev data structure 942 * 943 * Unmasks internal errors in the Uncorrectable and Correctable Error 944 * Mask registers. 945 * 946 * Note: AER must be enabled and supported by the device which must be 947 * checked in advance, e.g. with pcie_aer_is_native(). 948 */ 949 static void pci_aer_unmask_internal_errors(struct pci_dev *dev) 950 { 951 int aer = dev->aer_cap; 952 u32 mask; 953 954 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, &mask); 955 mask &= ~PCI_ERR_UNC_INTN; 956 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, mask); 957 958 pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK, &mask); 959 mask &= ~PCI_ERR_COR_INTERNAL; 960 pci_write_config_dword(dev, aer + PCI_ERR_COR_MASK, mask); 961 } 962 963 static bool is_cxl_mem_dev(struct pci_dev *dev) 964 { 965 /* 966 * The capability, status, and control fields in Device 0, 967 * Function 0 DVSEC control the CXL functionality of the 968 * entire device (CXL 3.0, 8.1.3). 969 */ 970 if (dev->devfn != PCI_DEVFN(0, 0)) 971 return false; 972 973 /* 974 * CXL Memory Devices must have the 502h class code set (CXL 975 * 3.0, 8.1.12.1). 976 */ 977 if ((dev->class >> 8) != PCI_CLASS_MEMORY_CXL) 978 return false; 979 980 return true; 981 } 982 983 static bool cxl_error_is_native(struct pci_dev *dev) 984 { 985 struct pci_host_bridge *host = pci_find_host_bridge(dev->bus); 986 987 return (pcie_ports_native || host->native_aer); 988 } 989 990 static bool is_internal_error(struct aer_err_info *info) 991 { 992 if (info->severity == AER_CORRECTABLE) 993 return info->status & PCI_ERR_COR_INTERNAL; 994 995 return info->status & PCI_ERR_UNC_INTN; 996 } 997 998 static int cxl_rch_handle_error_iter(struct pci_dev *dev, void *data) 999 { 1000 struct aer_err_info *info = (struct aer_err_info *)data; 1001 const struct pci_error_handlers *err_handler; 1002 1003 if (!is_cxl_mem_dev(dev) || !cxl_error_is_native(dev)) 1004 return 0; 1005 1006 /* protect dev->driver */ 1007 device_lock(&dev->dev); 1008 1009 err_handler = dev->driver ? dev->driver->err_handler : NULL; 1010 if (!err_handler) 1011 goto out; 1012 1013 if (info->severity == AER_CORRECTABLE) { 1014 if (err_handler->cor_error_detected) 1015 err_handler->cor_error_detected(dev); 1016 } else if (err_handler->error_detected) { 1017 if (info->severity == AER_NONFATAL) 1018 err_handler->error_detected(dev, pci_channel_io_normal); 1019 else if (info->severity == AER_FATAL) 1020 err_handler->error_detected(dev, pci_channel_io_frozen); 1021 } 1022 out: 1023 device_unlock(&dev->dev); 1024 return 0; 1025 } 1026 1027 static void cxl_rch_handle_error(struct pci_dev *dev, struct aer_err_info *info) 1028 { 1029 /* 1030 * Internal errors of an RCEC indicate an AER error in an 1031 * RCH's downstream port. Check and handle them in the CXL.mem 1032 * device driver. 1033 */ 1034 if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_EC && 1035 is_internal_error(info)) 1036 pcie_walk_rcec(dev, cxl_rch_handle_error_iter, info); 1037 } 1038 1039 static int handles_cxl_error_iter(struct pci_dev *dev, void *data) 1040 { 1041 bool *handles_cxl = data; 1042 1043 if (!*handles_cxl) 1044 *handles_cxl = is_cxl_mem_dev(dev) && cxl_error_is_native(dev); 1045 1046 /* Non-zero terminates iteration */ 1047 return *handles_cxl; 1048 } 1049 1050 static bool handles_cxl_errors(struct pci_dev *rcec) 1051 { 1052 bool handles_cxl = false; 1053 1054 if (pci_pcie_type(rcec) == PCI_EXP_TYPE_RC_EC && 1055 pcie_aer_is_native(rcec)) 1056 pcie_walk_rcec(rcec, handles_cxl_error_iter, &handles_cxl); 1057 1058 return handles_cxl; 1059 } 1060 1061 static void cxl_rch_enable_rcec(struct pci_dev *rcec) 1062 { 1063 if (!handles_cxl_errors(rcec)) 1064 return; 1065 1066 pci_aer_unmask_internal_errors(rcec); 1067 pci_info(rcec, "CXL: Internal errors unmasked"); 1068 } 1069 1070 #else 1071 static inline void cxl_rch_enable_rcec(struct pci_dev *dev) { } 1072 static inline void cxl_rch_handle_error(struct pci_dev *dev, 1073 struct aer_err_info *info) { } 1074 #endif 1075 1076 /** 1077 * pci_aer_handle_error - handle logging error into an event log 1078 * @dev: pointer to pci_dev data structure of error source device 1079 * @info: comprehensive error information 1080 * 1081 * Invoked when an error being detected by Root Port. 1082 */ 1083 static void pci_aer_handle_error(struct pci_dev *dev, struct aer_err_info *info) 1084 { 1085 int aer = dev->aer_cap; 1086 1087 if (info->severity == AER_CORRECTABLE) { 1088 /* 1089 * Correctable error does not need software intervention. 1090 * No need to go through error recovery process. 1091 */ 1092 if (aer) 1093 pci_write_config_dword(dev, aer + PCI_ERR_COR_STATUS, 1094 info->status); 1095 if (pcie_aer_is_native(dev)) { 1096 struct pci_driver *pdrv = dev->driver; 1097 1098 if (pdrv && pdrv->err_handler && 1099 pdrv->err_handler->cor_error_detected) 1100 pdrv->err_handler->cor_error_detected(dev); 1101 pcie_clear_device_status(dev); 1102 } 1103 } else if (info->severity == AER_NONFATAL) 1104 pcie_do_recovery(dev, pci_channel_io_normal, aer_root_reset); 1105 else if (info->severity == AER_FATAL) 1106 pcie_do_recovery(dev, pci_channel_io_frozen, aer_root_reset); 1107 } 1108 1109 static void handle_error_source(struct pci_dev *dev, struct aer_err_info *info) 1110 { 1111 cxl_rch_handle_error(dev, info); 1112 pci_aer_handle_error(dev, info); 1113 pci_dev_put(dev); 1114 } 1115 1116 #ifdef CONFIG_ACPI_APEI_PCIEAER 1117 1118 #define AER_RECOVER_RING_SIZE 16 1119 1120 struct aer_recover_entry { 1121 u8 bus; 1122 u8 devfn; 1123 u16 domain; 1124 int severity; 1125 struct aer_capability_regs *regs; 1126 }; 1127 1128 static DEFINE_KFIFO(aer_recover_ring, struct aer_recover_entry, 1129 AER_RECOVER_RING_SIZE); 1130 1131 static void aer_recover_work_func(struct work_struct *work) 1132 { 1133 struct aer_recover_entry entry; 1134 struct pci_dev *pdev; 1135 1136 while (kfifo_get(&aer_recover_ring, &entry)) { 1137 pdev = pci_get_domain_bus_and_slot(entry.domain, entry.bus, 1138 entry.devfn); 1139 if (!pdev) { 1140 pr_err("no pci_dev for %04x:%02x:%02x.%x\n", 1141 entry.domain, entry.bus, 1142 PCI_SLOT(entry.devfn), PCI_FUNC(entry.devfn)); 1143 continue; 1144 } 1145 pci_print_aer(pdev, entry.severity, entry.regs); 1146 1147 /* 1148 * Memory for aer_capability_regs(entry.regs) is being 1149 * allocated from the ghes_estatus_pool to protect it from 1150 * overwriting when multiple sections are present in the 1151 * error status. Thus free the same after processing the 1152 * data. 1153 */ 1154 ghes_estatus_pool_region_free((unsigned long)entry.regs, 1155 sizeof(struct aer_capability_regs)); 1156 1157 if (entry.severity == AER_NONFATAL) 1158 pcie_do_recovery(pdev, pci_channel_io_normal, 1159 aer_root_reset); 1160 else if (entry.severity == AER_FATAL) 1161 pcie_do_recovery(pdev, pci_channel_io_frozen, 1162 aer_root_reset); 1163 pci_dev_put(pdev); 1164 } 1165 } 1166 1167 /* 1168 * Mutual exclusion for writers of aer_recover_ring, reader side don't 1169 * need lock, because there is only one reader and lock is not needed 1170 * between reader and writer. 1171 */ 1172 static DEFINE_SPINLOCK(aer_recover_ring_lock); 1173 static DECLARE_WORK(aer_recover_work, aer_recover_work_func); 1174 1175 void aer_recover_queue(int domain, unsigned int bus, unsigned int devfn, 1176 int severity, struct aer_capability_regs *aer_regs) 1177 { 1178 struct aer_recover_entry entry = { 1179 .bus = bus, 1180 .devfn = devfn, 1181 .domain = domain, 1182 .severity = severity, 1183 .regs = aer_regs, 1184 }; 1185 1186 if (kfifo_in_spinlocked(&aer_recover_ring, &entry, 1, 1187 &aer_recover_ring_lock)) 1188 schedule_work(&aer_recover_work); 1189 else 1190 pr_err("buffer overflow in recovery for %04x:%02x:%02x.%x\n", 1191 domain, bus, PCI_SLOT(devfn), PCI_FUNC(devfn)); 1192 } 1193 EXPORT_SYMBOL_GPL(aer_recover_queue); 1194 #endif 1195 1196 /** 1197 * aer_get_device_error_info - read error status from dev and store it to info 1198 * @dev: pointer to the device expected to have a error record 1199 * @info: pointer to structure to store the error record 1200 * 1201 * Return 1 on success, 0 on error. 1202 * 1203 * Note that @info is reused among all error devices. Clear fields properly. 1204 */ 1205 int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info) 1206 { 1207 int type = pci_pcie_type(dev); 1208 int aer = dev->aer_cap; 1209 u32 aercc; 1210 1211 /* Must reset in this function */ 1212 info->status = 0; 1213 info->tlp_header_valid = 0; 1214 1215 /* The device might not support AER */ 1216 if (!aer) 1217 return 0; 1218 1219 if (info->severity == AER_CORRECTABLE) { 1220 pci_read_config_dword(dev, aer + PCI_ERR_COR_STATUS, 1221 &info->status); 1222 pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK, 1223 &info->mask); 1224 if (!(info->status & ~info->mask)) 1225 return 0; 1226 } else if (type == PCI_EXP_TYPE_ROOT_PORT || 1227 type == PCI_EXP_TYPE_RC_EC || 1228 type == PCI_EXP_TYPE_DOWNSTREAM || 1229 info->severity == AER_NONFATAL) { 1230 1231 /* Link is still healthy for IO reads */ 1232 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, 1233 &info->status); 1234 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, 1235 &info->mask); 1236 if (!(info->status & ~info->mask)) 1237 return 0; 1238 1239 /* Get First Error Pointer */ 1240 pci_read_config_dword(dev, aer + PCI_ERR_CAP, &aercc); 1241 info->first_error = PCI_ERR_CAP_FEP(aercc); 1242 1243 if (info->status & AER_LOG_TLP_MASKS) { 1244 info->tlp_header_valid = 1; 1245 pcie_read_tlp_log(dev, aer + PCI_ERR_HEADER_LOG, 1246 aer + PCI_ERR_PREFIX_LOG, 1247 aer_tlp_log_len(dev, aercc), 1248 &info->tlp); 1249 } 1250 } 1251 1252 return 1; 1253 } 1254 1255 static inline void aer_process_err_devices(struct aer_err_info *e_info) 1256 { 1257 int i; 1258 1259 /* Report all before handle them, not to lost records by reset etc. */ 1260 for (i = 0; i < e_info->error_dev_num && e_info->dev[i]; i++) { 1261 if (aer_get_device_error_info(e_info->dev[i], e_info)) 1262 aer_print_error(e_info->dev[i], e_info); 1263 } 1264 for (i = 0; i < e_info->error_dev_num && e_info->dev[i]; i++) { 1265 if (aer_get_device_error_info(e_info->dev[i], e_info)) 1266 handle_error_source(e_info->dev[i], e_info); 1267 } 1268 } 1269 1270 /** 1271 * aer_isr_one_error - consume an error detected by root port 1272 * @rpc: pointer to the root port which holds an error 1273 * @e_src: pointer to an error source 1274 */ 1275 static void aer_isr_one_error(struct aer_rpc *rpc, 1276 struct aer_err_source *e_src) 1277 { 1278 struct pci_dev *pdev = rpc->rpd; 1279 struct aer_err_info e_info; 1280 1281 pci_rootport_aer_stats_incr(pdev, e_src); 1282 1283 /* 1284 * There is a possibility that both correctable error and 1285 * uncorrectable error being logged. Report correctable error first. 1286 */ 1287 if (e_src->status & PCI_ERR_ROOT_COR_RCV) { 1288 e_info.id = ERR_COR_ID(e_src->id); 1289 e_info.severity = AER_CORRECTABLE; 1290 1291 if (e_src->status & PCI_ERR_ROOT_MULTI_COR_RCV) 1292 e_info.multi_error_valid = 1; 1293 else 1294 e_info.multi_error_valid = 0; 1295 aer_print_port_info(pdev, &e_info); 1296 1297 if (find_source_device(pdev, &e_info)) 1298 aer_process_err_devices(&e_info); 1299 } 1300 1301 if (e_src->status & PCI_ERR_ROOT_UNCOR_RCV) { 1302 e_info.id = ERR_UNCOR_ID(e_src->id); 1303 1304 if (e_src->status & PCI_ERR_ROOT_FATAL_RCV) 1305 e_info.severity = AER_FATAL; 1306 else 1307 e_info.severity = AER_NONFATAL; 1308 1309 if (e_src->status & PCI_ERR_ROOT_MULTI_UNCOR_RCV) 1310 e_info.multi_error_valid = 1; 1311 else 1312 e_info.multi_error_valid = 0; 1313 1314 aer_print_port_info(pdev, &e_info); 1315 1316 if (find_source_device(pdev, &e_info)) 1317 aer_process_err_devices(&e_info); 1318 } 1319 } 1320 1321 /** 1322 * aer_isr - consume errors detected by root port 1323 * @irq: IRQ assigned to Root Port 1324 * @context: pointer to Root Port data structure 1325 * 1326 * Invoked, as DPC, when root port records new detected error 1327 */ 1328 static irqreturn_t aer_isr(int irq, void *context) 1329 { 1330 struct pcie_device *dev = (struct pcie_device *)context; 1331 struct aer_rpc *rpc = get_service_data(dev); 1332 struct aer_err_source e_src; 1333 1334 if (kfifo_is_empty(&rpc->aer_fifo)) 1335 return IRQ_NONE; 1336 1337 while (kfifo_get(&rpc->aer_fifo, &e_src)) 1338 aer_isr_one_error(rpc, &e_src); 1339 return IRQ_HANDLED; 1340 } 1341 1342 /** 1343 * aer_irq - Root Port's ISR 1344 * @irq: IRQ assigned to Root Port 1345 * @context: pointer to Root Port data structure 1346 * 1347 * Invoked when Root Port detects AER messages. 1348 */ 1349 static irqreturn_t aer_irq(int irq, void *context) 1350 { 1351 struct pcie_device *pdev = (struct pcie_device *)context; 1352 struct aer_rpc *rpc = get_service_data(pdev); 1353 struct pci_dev *rp = rpc->rpd; 1354 int aer = rp->aer_cap; 1355 struct aer_err_source e_src = {}; 1356 1357 pci_read_config_dword(rp, aer + PCI_ERR_ROOT_STATUS, &e_src.status); 1358 if (!(e_src.status & AER_ERR_STATUS_MASK)) 1359 return IRQ_NONE; 1360 1361 pci_read_config_dword(rp, aer + PCI_ERR_ROOT_ERR_SRC, &e_src.id); 1362 pci_write_config_dword(rp, aer + PCI_ERR_ROOT_STATUS, e_src.status); 1363 1364 if (!kfifo_put(&rpc->aer_fifo, e_src)) 1365 return IRQ_HANDLED; 1366 1367 return IRQ_WAKE_THREAD; 1368 } 1369 1370 static void aer_enable_irq(struct pci_dev *pdev) 1371 { 1372 int aer = pdev->aer_cap; 1373 u32 reg32; 1374 1375 /* Enable Root Port's interrupt in response to error messages */ 1376 pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, ®32); 1377 reg32 |= ROOT_PORT_INTR_ON_MESG_MASK; 1378 pci_write_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, reg32); 1379 } 1380 1381 static void aer_disable_irq(struct pci_dev *pdev) 1382 { 1383 int aer = pdev->aer_cap; 1384 u32 reg32; 1385 1386 /* Disable Root's interrupt in response to error messages */ 1387 pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, ®32); 1388 reg32 &= ~ROOT_PORT_INTR_ON_MESG_MASK; 1389 pci_write_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, reg32); 1390 } 1391 1392 /** 1393 * aer_enable_rootport - enable Root Port's interrupts when receiving messages 1394 * @rpc: pointer to a Root Port data structure 1395 * 1396 * Invoked when PCIe bus loads AER service driver. 1397 */ 1398 static void aer_enable_rootport(struct aer_rpc *rpc) 1399 { 1400 struct pci_dev *pdev = rpc->rpd; 1401 int aer = pdev->aer_cap; 1402 u16 reg16; 1403 u32 reg32; 1404 1405 /* Clear PCIe Capability's Device Status */ 1406 pcie_capability_read_word(pdev, PCI_EXP_DEVSTA, ®16); 1407 pcie_capability_write_word(pdev, PCI_EXP_DEVSTA, reg16); 1408 1409 /* Disable system error generation in response to error messages */ 1410 pcie_capability_clear_word(pdev, PCI_EXP_RTCTL, 1411 SYSTEM_ERROR_INTR_ON_MESG_MASK); 1412 1413 /* Clear error status */ 1414 pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_STATUS, ®32); 1415 pci_write_config_dword(pdev, aer + PCI_ERR_ROOT_STATUS, reg32); 1416 pci_read_config_dword(pdev, aer + PCI_ERR_COR_STATUS, ®32); 1417 pci_write_config_dword(pdev, aer + PCI_ERR_COR_STATUS, reg32); 1418 pci_read_config_dword(pdev, aer + PCI_ERR_UNCOR_STATUS, ®32); 1419 pci_write_config_dword(pdev, aer + PCI_ERR_UNCOR_STATUS, reg32); 1420 1421 aer_enable_irq(pdev); 1422 } 1423 1424 /** 1425 * aer_disable_rootport - disable Root Port's interrupts when receiving messages 1426 * @rpc: pointer to a Root Port data structure 1427 * 1428 * Invoked when PCIe bus unloads AER service driver. 1429 */ 1430 static void aer_disable_rootport(struct aer_rpc *rpc) 1431 { 1432 struct pci_dev *pdev = rpc->rpd; 1433 int aer = pdev->aer_cap; 1434 u32 reg32; 1435 1436 aer_disable_irq(pdev); 1437 1438 /* Clear Root's error status reg */ 1439 pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_STATUS, ®32); 1440 pci_write_config_dword(pdev, aer + PCI_ERR_ROOT_STATUS, reg32); 1441 } 1442 1443 /** 1444 * aer_remove - clean up resources 1445 * @dev: pointer to the pcie_dev data structure 1446 * 1447 * Invoked when PCI Express bus unloads or AER probe fails. 1448 */ 1449 static void aer_remove(struct pcie_device *dev) 1450 { 1451 struct aer_rpc *rpc = get_service_data(dev); 1452 1453 aer_disable_rootport(rpc); 1454 } 1455 1456 /** 1457 * aer_probe - initialize resources 1458 * @dev: pointer to the pcie_dev data structure 1459 * 1460 * Invoked when PCI Express bus loads AER service driver. 1461 */ 1462 static int aer_probe(struct pcie_device *dev) 1463 { 1464 int status; 1465 struct aer_rpc *rpc; 1466 struct device *device = &dev->device; 1467 struct pci_dev *port = dev->port; 1468 1469 BUILD_BUG_ON(ARRAY_SIZE(aer_correctable_error_string) < 1470 AER_MAX_TYPEOF_COR_ERRS); 1471 BUILD_BUG_ON(ARRAY_SIZE(aer_uncorrectable_error_string) < 1472 AER_MAX_TYPEOF_UNCOR_ERRS); 1473 1474 /* Limit to Root Ports or Root Complex Event Collectors */ 1475 if ((pci_pcie_type(port) != PCI_EXP_TYPE_RC_EC) && 1476 (pci_pcie_type(port) != PCI_EXP_TYPE_ROOT_PORT)) 1477 return -ENODEV; 1478 1479 rpc = devm_kzalloc(device, sizeof(struct aer_rpc), GFP_KERNEL); 1480 if (!rpc) 1481 return -ENOMEM; 1482 1483 rpc->rpd = port; 1484 INIT_KFIFO(rpc->aer_fifo); 1485 set_service_data(dev, rpc); 1486 1487 status = devm_request_threaded_irq(device, dev->irq, aer_irq, aer_isr, 1488 IRQF_SHARED, "aerdrv", dev); 1489 if (status) { 1490 pci_err(port, "request AER IRQ %d failed\n", dev->irq); 1491 return status; 1492 } 1493 1494 cxl_rch_enable_rcec(port); 1495 aer_enable_rootport(rpc); 1496 pci_info(port, "enabled with IRQ %d\n", dev->irq); 1497 return 0; 1498 } 1499 1500 static int aer_suspend(struct pcie_device *dev) 1501 { 1502 struct aer_rpc *rpc = get_service_data(dev); 1503 1504 aer_disable_rootport(rpc); 1505 return 0; 1506 } 1507 1508 static int aer_resume(struct pcie_device *dev) 1509 { 1510 struct aer_rpc *rpc = get_service_data(dev); 1511 1512 aer_enable_rootport(rpc); 1513 return 0; 1514 } 1515 1516 /** 1517 * aer_root_reset - reset Root Port hierarchy, RCEC, or RCiEP 1518 * @dev: pointer to Root Port, RCEC, or RCiEP 1519 * 1520 * Invoked by Port Bus driver when performing reset. 1521 */ 1522 static pci_ers_result_t aer_root_reset(struct pci_dev *dev) 1523 { 1524 int type = pci_pcie_type(dev); 1525 struct pci_dev *root; 1526 int aer; 1527 struct pci_host_bridge *host = pci_find_host_bridge(dev->bus); 1528 u32 reg32; 1529 int rc; 1530 1531 /* 1532 * Only Root Ports and RCECs have AER Root Command and Root Status 1533 * registers. If "dev" is an RCiEP, the relevant registers are in 1534 * the RCEC. 1535 */ 1536 if (type == PCI_EXP_TYPE_RC_END) 1537 root = dev->rcec; 1538 else 1539 root = pcie_find_root_port(dev); 1540 1541 /* 1542 * If the platform retained control of AER, an RCiEP may not have 1543 * an RCEC visible to us, so dev->rcec ("root") may be NULL. In 1544 * that case, firmware is responsible for these registers. 1545 */ 1546 aer = root ? root->aer_cap : 0; 1547 1548 if ((host->native_aer || pcie_ports_native) && aer) 1549 aer_disable_irq(root); 1550 1551 if (type == PCI_EXP_TYPE_RC_EC || type == PCI_EXP_TYPE_RC_END) { 1552 rc = pcie_reset_flr(dev, PCI_RESET_DO_RESET); 1553 if (!rc) 1554 pci_info(dev, "has been reset\n"); 1555 else 1556 pci_info(dev, "not reset (no FLR support: %d)\n", rc); 1557 } else { 1558 rc = pci_bus_error_reset(dev); 1559 pci_info(dev, "%s Port link has been reset (%d)\n", 1560 pci_is_root_bus(dev->bus) ? "Root" : "Downstream", rc); 1561 } 1562 1563 if ((host->native_aer || pcie_ports_native) && aer) { 1564 /* Clear Root Error Status */ 1565 pci_read_config_dword(root, aer + PCI_ERR_ROOT_STATUS, ®32); 1566 pci_write_config_dword(root, aer + PCI_ERR_ROOT_STATUS, reg32); 1567 1568 aer_enable_irq(root); 1569 } 1570 1571 return rc ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED; 1572 } 1573 1574 static struct pcie_port_service_driver aerdriver = { 1575 .name = "aer", 1576 .port_type = PCIE_ANY_PORT, 1577 .service = PCIE_PORT_SERVICE_AER, 1578 1579 .probe = aer_probe, 1580 .suspend = aer_suspend, 1581 .resume = aer_resume, 1582 .remove = aer_remove, 1583 }; 1584 1585 /** 1586 * pcie_aer_init - register AER root service driver 1587 * 1588 * Invoked when AER root service driver is loaded. 1589 */ 1590 int __init pcie_aer_init(void) 1591 { 1592 if (!pci_aer_available()) 1593 return -ENXIO; 1594 return pcie_port_service_register(&aerdriver); 1595 } 1596