1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Implement the AER root port service driver. The driver registers an IRQ 4 * handler. When a root port triggers an AER interrupt, the IRQ handler 5 * collects root port status and schedules work. 6 * 7 * Copyright (C) 2006 Intel Corp. 8 * Tom Long Nguyen (tom.l.nguyen@intel.com) 9 * Zhang Yanmin (yanmin.zhang@intel.com) 10 * 11 * (C) Copyright 2009 Hewlett-Packard Development Company, L.P. 12 * Andrew Patterson <andrew.patterson@hp.com> 13 */ 14 15 #define pr_fmt(fmt) "AER: " fmt 16 #define dev_fmt pr_fmt 17 18 #include <linux/bitops.h> 19 #include <linux/cper.h> 20 #include <linux/pci.h> 21 #include <linux/pci-acpi.h> 22 #include <linux/sched.h> 23 #include <linux/kernel.h> 24 #include <linux/errno.h> 25 #include <linux/pm.h> 26 #include <linux/init.h> 27 #include <linux/interrupt.h> 28 #include <linux/delay.h> 29 #include <linux/kfifo.h> 30 #include <linux/slab.h> 31 #include <acpi/apei.h> 32 #include <acpi/ghes.h> 33 #include <ras/ras_event.h> 34 35 #include "../pci.h" 36 #include "portdrv.h" 37 38 #define AER_ERROR_SOURCES_MAX 128 39 40 #define AER_MAX_TYPEOF_COR_ERRS 16 /* as per PCI_ERR_COR_STATUS */ 41 #define AER_MAX_TYPEOF_UNCOR_ERRS 27 /* as per PCI_ERR_UNCOR_STATUS*/ 42 43 struct aer_err_source { 44 u32 status; /* PCI_ERR_ROOT_STATUS */ 45 u32 id; /* PCI_ERR_ROOT_ERR_SRC */ 46 }; 47 48 struct aer_rpc { 49 struct pci_dev *rpd; /* Root Port device */ 50 DECLARE_KFIFO(aer_fifo, struct aer_err_source, AER_ERROR_SOURCES_MAX); 51 }; 52 53 /* AER stats for the device */ 54 struct aer_stats { 55 56 /* 57 * Fields for all AER capable devices. They indicate the errors 58 * "as seen by this device". Note that this may mean that if an 59 * end point is causing problems, the AER counters may increment 60 * at its link partner (e.g. root port) because the errors will be 61 * "seen" by the link partner and not the problematic end point 62 * itself (which may report all counters as 0 as it never saw any 63 * problems). 64 */ 65 /* Counters for different type of correctable errors */ 66 u64 dev_cor_errs[AER_MAX_TYPEOF_COR_ERRS]; 67 /* Counters for different type of fatal uncorrectable errors */ 68 u64 dev_fatal_errs[AER_MAX_TYPEOF_UNCOR_ERRS]; 69 /* Counters for different type of nonfatal uncorrectable errors */ 70 u64 dev_nonfatal_errs[AER_MAX_TYPEOF_UNCOR_ERRS]; 71 /* Total number of ERR_COR sent by this device */ 72 u64 dev_total_cor_errs; 73 /* Total number of ERR_FATAL sent by this device */ 74 u64 dev_total_fatal_errs; 75 /* Total number of ERR_NONFATAL sent by this device */ 76 u64 dev_total_nonfatal_errs; 77 78 /* 79 * Fields for Root ports & root complex event collectors only, these 80 * indicate the total number of ERR_COR, ERR_FATAL, and ERR_NONFATAL 81 * messages received by the root port / event collector, INCLUDING the 82 * ones that are generated internally (by the rootport itself) 83 */ 84 u64 rootport_total_cor_errs; 85 u64 rootport_total_fatal_errs; 86 u64 rootport_total_nonfatal_errs; 87 }; 88 89 #define AER_LOG_TLP_MASKS (PCI_ERR_UNC_POISON_TLP| \ 90 PCI_ERR_UNC_ECRC| \ 91 PCI_ERR_UNC_UNSUP| \ 92 PCI_ERR_UNC_COMP_ABORT| \ 93 PCI_ERR_UNC_UNX_COMP| \ 94 PCI_ERR_UNC_MALF_TLP) 95 96 #define SYSTEM_ERROR_INTR_ON_MESG_MASK (PCI_EXP_RTCTL_SECEE| \ 97 PCI_EXP_RTCTL_SENFEE| \ 98 PCI_EXP_RTCTL_SEFEE) 99 #define ROOT_PORT_INTR_ON_MESG_MASK (PCI_ERR_ROOT_CMD_COR_EN| \ 100 PCI_ERR_ROOT_CMD_NONFATAL_EN| \ 101 PCI_ERR_ROOT_CMD_FATAL_EN) 102 #define ERR_COR_ID(d) (d & 0xffff) 103 #define ERR_UNCOR_ID(d) (d >> 16) 104 105 #define AER_ERR_STATUS_MASK (PCI_ERR_ROOT_UNCOR_RCV | \ 106 PCI_ERR_ROOT_COR_RCV | \ 107 PCI_ERR_ROOT_MULTI_COR_RCV | \ 108 PCI_ERR_ROOT_MULTI_UNCOR_RCV) 109 110 static int pcie_aer_disable; 111 static pci_ers_result_t aer_root_reset(struct pci_dev *dev); 112 113 void pci_no_aer(void) 114 { 115 pcie_aer_disable = 1; 116 } 117 118 bool pci_aer_available(void) 119 { 120 return !pcie_aer_disable && pci_msi_enabled(); 121 } 122 123 #ifdef CONFIG_PCIE_ECRC 124 125 #define ECRC_POLICY_DEFAULT 0 /* ECRC set by BIOS */ 126 #define ECRC_POLICY_OFF 1 /* ECRC off for performance */ 127 #define ECRC_POLICY_ON 2 /* ECRC on for data integrity */ 128 129 static int ecrc_policy = ECRC_POLICY_DEFAULT; 130 131 static const char * const ecrc_policy_str[] = { 132 [ECRC_POLICY_DEFAULT] = "bios", 133 [ECRC_POLICY_OFF] = "off", 134 [ECRC_POLICY_ON] = "on" 135 }; 136 137 /** 138 * enable_ecrc_checking - enable PCIe ECRC checking for a device 139 * @dev: the PCI device 140 * 141 * Returns 0 on success, or negative on failure. 142 */ 143 static int enable_ecrc_checking(struct pci_dev *dev) 144 { 145 int aer = dev->aer_cap; 146 u32 reg32; 147 148 if (!aer) 149 return -ENODEV; 150 151 pci_read_config_dword(dev, aer + PCI_ERR_CAP, ®32); 152 if (reg32 & PCI_ERR_CAP_ECRC_GENC) 153 reg32 |= PCI_ERR_CAP_ECRC_GENE; 154 if (reg32 & PCI_ERR_CAP_ECRC_CHKC) 155 reg32 |= PCI_ERR_CAP_ECRC_CHKE; 156 pci_write_config_dword(dev, aer + PCI_ERR_CAP, reg32); 157 158 return 0; 159 } 160 161 /** 162 * disable_ecrc_checking - disables PCIe ECRC checking for a device 163 * @dev: the PCI device 164 * 165 * Returns 0 on success, or negative on failure. 166 */ 167 static int disable_ecrc_checking(struct pci_dev *dev) 168 { 169 int aer = dev->aer_cap; 170 u32 reg32; 171 172 if (!aer) 173 return -ENODEV; 174 175 pci_read_config_dword(dev, aer + PCI_ERR_CAP, ®32); 176 reg32 &= ~(PCI_ERR_CAP_ECRC_GENE | PCI_ERR_CAP_ECRC_CHKE); 177 pci_write_config_dword(dev, aer + PCI_ERR_CAP, reg32); 178 179 return 0; 180 } 181 182 /** 183 * pcie_set_ecrc_checking - set/unset PCIe ECRC checking for a device based 184 * on global policy 185 * @dev: the PCI device 186 */ 187 void pcie_set_ecrc_checking(struct pci_dev *dev) 188 { 189 if (!pcie_aer_is_native(dev)) 190 return; 191 192 switch (ecrc_policy) { 193 case ECRC_POLICY_DEFAULT: 194 return; 195 case ECRC_POLICY_OFF: 196 disable_ecrc_checking(dev); 197 break; 198 case ECRC_POLICY_ON: 199 enable_ecrc_checking(dev); 200 break; 201 default: 202 return; 203 } 204 } 205 206 /** 207 * pcie_ecrc_get_policy - parse kernel command-line ecrc option 208 * @str: ECRC policy from kernel command line to use 209 */ 210 void pcie_ecrc_get_policy(char *str) 211 { 212 int i; 213 214 i = match_string(ecrc_policy_str, ARRAY_SIZE(ecrc_policy_str), str); 215 if (i < 0) 216 return; 217 218 ecrc_policy = i; 219 } 220 #endif /* CONFIG_PCIE_ECRC */ 221 222 #define PCI_EXP_AER_FLAGS (PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE | \ 223 PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE) 224 225 int pcie_aer_is_native(struct pci_dev *dev) 226 { 227 struct pci_host_bridge *host = pci_find_host_bridge(dev->bus); 228 229 if (!dev->aer_cap) 230 return 0; 231 232 return pcie_ports_native || host->native_aer; 233 } 234 EXPORT_SYMBOL_NS_GPL(pcie_aer_is_native, CXL); 235 236 static int pci_enable_pcie_error_reporting(struct pci_dev *dev) 237 { 238 int rc; 239 240 if (!pcie_aer_is_native(dev)) 241 return -EIO; 242 243 rc = pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_AER_FLAGS); 244 return pcibios_err_to_errno(rc); 245 } 246 247 int pci_aer_clear_nonfatal_status(struct pci_dev *dev) 248 { 249 int aer = dev->aer_cap; 250 u32 status, sev; 251 252 if (!pcie_aer_is_native(dev)) 253 return -EIO; 254 255 /* Clear status bits for ERR_NONFATAL errors only */ 256 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status); 257 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, &sev); 258 status &= ~sev; 259 if (status) 260 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, status); 261 262 return 0; 263 } 264 EXPORT_SYMBOL_GPL(pci_aer_clear_nonfatal_status); 265 266 void pci_aer_clear_fatal_status(struct pci_dev *dev) 267 { 268 int aer = dev->aer_cap; 269 u32 status, sev; 270 271 if (!pcie_aer_is_native(dev)) 272 return; 273 274 /* Clear status bits for ERR_FATAL errors only */ 275 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status); 276 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, &sev); 277 status &= sev; 278 if (status) 279 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, status); 280 } 281 282 /** 283 * pci_aer_raw_clear_status - Clear AER error registers. 284 * @dev: the PCI device 285 * 286 * Clearing AER error status registers unconditionally, regardless of 287 * whether they're owned by firmware or the OS. 288 * 289 * Returns 0 on success, or negative on failure. 290 */ 291 int pci_aer_raw_clear_status(struct pci_dev *dev) 292 { 293 int aer = dev->aer_cap; 294 u32 status; 295 int port_type; 296 297 if (!aer) 298 return -EIO; 299 300 port_type = pci_pcie_type(dev); 301 if (port_type == PCI_EXP_TYPE_ROOT_PORT || 302 port_type == PCI_EXP_TYPE_RC_EC) { 303 pci_read_config_dword(dev, aer + PCI_ERR_ROOT_STATUS, &status); 304 pci_write_config_dword(dev, aer + PCI_ERR_ROOT_STATUS, status); 305 } 306 307 pci_read_config_dword(dev, aer + PCI_ERR_COR_STATUS, &status); 308 pci_write_config_dword(dev, aer + PCI_ERR_COR_STATUS, status); 309 310 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status); 311 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, status); 312 313 return 0; 314 } 315 316 int pci_aer_clear_status(struct pci_dev *dev) 317 { 318 if (!pcie_aer_is_native(dev)) 319 return -EIO; 320 321 return pci_aer_raw_clear_status(dev); 322 } 323 324 void pci_save_aer_state(struct pci_dev *dev) 325 { 326 int aer = dev->aer_cap; 327 struct pci_cap_saved_state *save_state; 328 u32 *cap; 329 330 if (!aer) 331 return; 332 333 save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_ERR); 334 if (!save_state) 335 return; 336 337 cap = &save_state->cap.data[0]; 338 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, cap++); 339 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, cap++); 340 pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK, cap++); 341 pci_read_config_dword(dev, aer + PCI_ERR_CAP, cap++); 342 if (pcie_cap_has_rtctl(dev)) 343 pci_read_config_dword(dev, aer + PCI_ERR_ROOT_COMMAND, cap++); 344 } 345 346 void pci_restore_aer_state(struct pci_dev *dev) 347 { 348 int aer = dev->aer_cap; 349 struct pci_cap_saved_state *save_state; 350 u32 *cap; 351 352 if (!aer) 353 return; 354 355 save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_ERR); 356 if (!save_state) 357 return; 358 359 cap = &save_state->cap.data[0]; 360 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, *cap++); 361 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, *cap++); 362 pci_write_config_dword(dev, aer + PCI_ERR_COR_MASK, *cap++); 363 pci_write_config_dword(dev, aer + PCI_ERR_CAP, *cap++); 364 if (pcie_cap_has_rtctl(dev)) 365 pci_write_config_dword(dev, aer + PCI_ERR_ROOT_COMMAND, *cap++); 366 } 367 368 void pci_aer_init(struct pci_dev *dev) 369 { 370 int n; 371 372 dev->aer_cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); 373 if (!dev->aer_cap) 374 return; 375 376 dev->aer_stats = kzalloc(sizeof(struct aer_stats), GFP_KERNEL); 377 378 /* 379 * We save/restore PCI_ERR_UNCOR_MASK, PCI_ERR_UNCOR_SEVER, 380 * PCI_ERR_COR_MASK, and PCI_ERR_CAP. Root and Root Complex Event 381 * Collectors also implement PCI_ERR_ROOT_COMMAND (PCIe r5.0, sec 382 * 7.8.4). 383 */ 384 n = pcie_cap_has_rtctl(dev) ? 5 : 4; 385 pci_add_ext_cap_save_buffer(dev, PCI_EXT_CAP_ID_ERR, sizeof(u32) * n); 386 387 pci_aer_clear_status(dev); 388 389 if (pci_aer_available()) 390 pci_enable_pcie_error_reporting(dev); 391 392 pcie_set_ecrc_checking(dev); 393 } 394 395 void pci_aer_exit(struct pci_dev *dev) 396 { 397 kfree(dev->aer_stats); 398 dev->aer_stats = NULL; 399 } 400 401 #define AER_AGENT_RECEIVER 0 402 #define AER_AGENT_REQUESTER 1 403 #define AER_AGENT_COMPLETER 2 404 #define AER_AGENT_TRANSMITTER 3 405 406 #define AER_AGENT_REQUESTER_MASK(t) ((t == AER_CORRECTABLE) ? \ 407 0 : (PCI_ERR_UNC_COMP_TIME|PCI_ERR_UNC_UNSUP)) 408 #define AER_AGENT_COMPLETER_MASK(t) ((t == AER_CORRECTABLE) ? \ 409 0 : PCI_ERR_UNC_COMP_ABORT) 410 #define AER_AGENT_TRANSMITTER_MASK(t) ((t == AER_CORRECTABLE) ? \ 411 (PCI_ERR_COR_REP_ROLL|PCI_ERR_COR_REP_TIMER) : 0) 412 413 #define AER_GET_AGENT(t, e) \ 414 ((e & AER_AGENT_COMPLETER_MASK(t)) ? AER_AGENT_COMPLETER : \ 415 (e & AER_AGENT_REQUESTER_MASK(t)) ? AER_AGENT_REQUESTER : \ 416 (e & AER_AGENT_TRANSMITTER_MASK(t)) ? AER_AGENT_TRANSMITTER : \ 417 AER_AGENT_RECEIVER) 418 419 #define AER_PHYSICAL_LAYER_ERROR 0 420 #define AER_DATA_LINK_LAYER_ERROR 1 421 #define AER_TRANSACTION_LAYER_ERROR 2 422 423 #define AER_PHYSICAL_LAYER_ERROR_MASK(t) ((t == AER_CORRECTABLE) ? \ 424 PCI_ERR_COR_RCVR : 0) 425 #define AER_DATA_LINK_LAYER_ERROR_MASK(t) ((t == AER_CORRECTABLE) ? \ 426 (PCI_ERR_COR_BAD_TLP| \ 427 PCI_ERR_COR_BAD_DLLP| \ 428 PCI_ERR_COR_REP_ROLL| \ 429 PCI_ERR_COR_REP_TIMER) : PCI_ERR_UNC_DLP) 430 431 #define AER_GET_LAYER_ERROR(t, e) \ 432 ((e & AER_PHYSICAL_LAYER_ERROR_MASK(t)) ? AER_PHYSICAL_LAYER_ERROR : \ 433 (e & AER_DATA_LINK_LAYER_ERROR_MASK(t)) ? AER_DATA_LINK_LAYER_ERROR : \ 434 AER_TRANSACTION_LAYER_ERROR) 435 436 /* 437 * AER error strings 438 */ 439 static const char * const aer_error_severity_string[] = { 440 "Uncorrectable (Non-Fatal)", 441 "Uncorrectable (Fatal)", 442 "Correctable" 443 }; 444 445 static const char *aer_error_layer[] = { 446 "Physical Layer", 447 "Data Link Layer", 448 "Transaction Layer" 449 }; 450 451 static const char *aer_correctable_error_string[] = { 452 "RxErr", /* Bit Position 0 */ 453 NULL, 454 NULL, 455 NULL, 456 NULL, 457 NULL, 458 "BadTLP", /* Bit Position 6 */ 459 "BadDLLP", /* Bit Position 7 */ 460 "Rollover", /* Bit Position 8 */ 461 NULL, 462 NULL, 463 NULL, 464 "Timeout", /* Bit Position 12 */ 465 "NonFatalErr", /* Bit Position 13 */ 466 "CorrIntErr", /* Bit Position 14 */ 467 "HeaderOF", /* Bit Position 15 */ 468 NULL, /* Bit Position 16 */ 469 NULL, /* Bit Position 17 */ 470 NULL, /* Bit Position 18 */ 471 NULL, /* Bit Position 19 */ 472 NULL, /* Bit Position 20 */ 473 NULL, /* Bit Position 21 */ 474 NULL, /* Bit Position 22 */ 475 NULL, /* Bit Position 23 */ 476 NULL, /* Bit Position 24 */ 477 NULL, /* Bit Position 25 */ 478 NULL, /* Bit Position 26 */ 479 NULL, /* Bit Position 27 */ 480 NULL, /* Bit Position 28 */ 481 NULL, /* Bit Position 29 */ 482 NULL, /* Bit Position 30 */ 483 NULL, /* Bit Position 31 */ 484 }; 485 486 static const char *aer_uncorrectable_error_string[] = { 487 "Undefined", /* Bit Position 0 */ 488 NULL, 489 NULL, 490 NULL, 491 "DLP", /* Bit Position 4 */ 492 "SDES", /* Bit Position 5 */ 493 NULL, 494 NULL, 495 NULL, 496 NULL, 497 NULL, 498 NULL, 499 "TLP", /* Bit Position 12 */ 500 "FCP", /* Bit Position 13 */ 501 "CmpltTO", /* Bit Position 14 */ 502 "CmpltAbrt", /* Bit Position 15 */ 503 "UnxCmplt", /* Bit Position 16 */ 504 "RxOF", /* Bit Position 17 */ 505 "MalfTLP", /* Bit Position 18 */ 506 "ECRC", /* Bit Position 19 */ 507 "UnsupReq", /* Bit Position 20 */ 508 "ACSViol", /* Bit Position 21 */ 509 "UncorrIntErr", /* Bit Position 22 */ 510 "BlockedTLP", /* Bit Position 23 */ 511 "AtomicOpBlocked", /* Bit Position 24 */ 512 "TLPBlockedErr", /* Bit Position 25 */ 513 "PoisonTLPBlocked", /* Bit Position 26 */ 514 NULL, /* Bit Position 27 */ 515 NULL, /* Bit Position 28 */ 516 NULL, /* Bit Position 29 */ 517 NULL, /* Bit Position 30 */ 518 NULL, /* Bit Position 31 */ 519 }; 520 521 static const char *aer_agent_string[] = { 522 "Receiver ID", 523 "Requester ID", 524 "Completer ID", 525 "Transmitter ID" 526 }; 527 528 #define aer_stats_dev_attr(name, stats_array, strings_array, \ 529 total_string, total_field) \ 530 static ssize_t \ 531 name##_show(struct device *dev, struct device_attribute *attr, \ 532 char *buf) \ 533 { \ 534 unsigned int i; \ 535 struct pci_dev *pdev = to_pci_dev(dev); \ 536 u64 *stats = pdev->aer_stats->stats_array; \ 537 size_t len = 0; \ 538 \ 539 for (i = 0; i < ARRAY_SIZE(pdev->aer_stats->stats_array); i++) {\ 540 if (strings_array[i]) \ 541 len += sysfs_emit_at(buf, len, "%s %llu\n", \ 542 strings_array[i], \ 543 stats[i]); \ 544 else if (stats[i]) \ 545 len += sysfs_emit_at(buf, len, \ 546 #stats_array "_bit[%d] %llu\n",\ 547 i, stats[i]); \ 548 } \ 549 len += sysfs_emit_at(buf, len, "TOTAL_%s %llu\n", total_string, \ 550 pdev->aer_stats->total_field); \ 551 return len; \ 552 } \ 553 static DEVICE_ATTR_RO(name) 554 555 aer_stats_dev_attr(aer_dev_correctable, dev_cor_errs, 556 aer_correctable_error_string, "ERR_COR", 557 dev_total_cor_errs); 558 aer_stats_dev_attr(aer_dev_fatal, dev_fatal_errs, 559 aer_uncorrectable_error_string, "ERR_FATAL", 560 dev_total_fatal_errs); 561 aer_stats_dev_attr(aer_dev_nonfatal, dev_nonfatal_errs, 562 aer_uncorrectable_error_string, "ERR_NONFATAL", 563 dev_total_nonfatal_errs); 564 565 #define aer_stats_rootport_attr(name, field) \ 566 static ssize_t \ 567 name##_show(struct device *dev, struct device_attribute *attr, \ 568 char *buf) \ 569 { \ 570 struct pci_dev *pdev = to_pci_dev(dev); \ 571 return sysfs_emit(buf, "%llu\n", pdev->aer_stats->field); \ 572 } \ 573 static DEVICE_ATTR_RO(name) 574 575 aer_stats_rootport_attr(aer_rootport_total_err_cor, 576 rootport_total_cor_errs); 577 aer_stats_rootport_attr(aer_rootport_total_err_fatal, 578 rootport_total_fatal_errs); 579 aer_stats_rootport_attr(aer_rootport_total_err_nonfatal, 580 rootport_total_nonfatal_errs); 581 582 static struct attribute *aer_stats_attrs[] __ro_after_init = { 583 &dev_attr_aer_dev_correctable.attr, 584 &dev_attr_aer_dev_fatal.attr, 585 &dev_attr_aer_dev_nonfatal.attr, 586 &dev_attr_aer_rootport_total_err_cor.attr, 587 &dev_attr_aer_rootport_total_err_fatal.attr, 588 &dev_attr_aer_rootport_total_err_nonfatal.attr, 589 NULL 590 }; 591 592 static umode_t aer_stats_attrs_are_visible(struct kobject *kobj, 593 struct attribute *a, int n) 594 { 595 struct device *dev = kobj_to_dev(kobj); 596 struct pci_dev *pdev = to_pci_dev(dev); 597 598 if (!pdev->aer_stats) 599 return 0; 600 601 if ((a == &dev_attr_aer_rootport_total_err_cor.attr || 602 a == &dev_attr_aer_rootport_total_err_fatal.attr || 603 a == &dev_attr_aer_rootport_total_err_nonfatal.attr) && 604 ((pci_pcie_type(pdev) != PCI_EXP_TYPE_ROOT_PORT) && 605 (pci_pcie_type(pdev) != PCI_EXP_TYPE_RC_EC))) 606 return 0; 607 608 return a->mode; 609 } 610 611 const struct attribute_group aer_stats_attr_group = { 612 .attrs = aer_stats_attrs, 613 .is_visible = aer_stats_attrs_are_visible, 614 }; 615 616 static void pci_dev_aer_stats_incr(struct pci_dev *pdev, 617 struct aer_err_info *info) 618 { 619 unsigned long status = info->status & ~info->mask; 620 int i, max = -1; 621 u64 *counter = NULL; 622 struct aer_stats *aer_stats = pdev->aer_stats; 623 624 if (!aer_stats) 625 return; 626 627 switch (info->severity) { 628 case AER_CORRECTABLE: 629 aer_stats->dev_total_cor_errs++; 630 counter = &aer_stats->dev_cor_errs[0]; 631 max = AER_MAX_TYPEOF_COR_ERRS; 632 break; 633 case AER_NONFATAL: 634 aer_stats->dev_total_nonfatal_errs++; 635 counter = &aer_stats->dev_nonfatal_errs[0]; 636 max = AER_MAX_TYPEOF_UNCOR_ERRS; 637 break; 638 case AER_FATAL: 639 aer_stats->dev_total_fatal_errs++; 640 counter = &aer_stats->dev_fatal_errs[0]; 641 max = AER_MAX_TYPEOF_UNCOR_ERRS; 642 break; 643 } 644 645 for_each_set_bit(i, &status, max) 646 counter[i]++; 647 } 648 649 static void pci_rootport_aer_stats_incr(struct pci_dev *pdev, 650 struct aer_err_source *e_src) 651 { 652 struct aer_stats *aer_stats = pdev->aer_stats; 653 654 if (!aer_stats) 655 return; 656 657 if (e_src->status & PCI_ERR_ROOT_COR_RCV) 658 aer_stats->rootport_total_cor_errs++; 659 660 if (e_src->status & PCI_ERR_ROOT_UNCOR_RCV) { 661 if (e_src->status & PCI_ERR_ROOT_FATAL_RCV) 662 aer_stats->rootport_total_fatal_errs++; 663 else 664 aer_stats->rootport_total_nonfatal_errs++; 665 } 666 } 667 668 static void __print_tlp_header(struct pci_dev *dev, struct pcie_tlp_log *t) 669 { 670 pci_err(dev, " TLP Header: %08x %08x %08x %08x\n", 671 t->dw[0], t->dw[1], t->dw[2], t->dw[3]); 672 } 673 674 static void __aer_print_error(struct pci_dev *dev, 675 struct aer_err_info *info) 676 { 677 const char **strings; 678 unsigned long status = info->status & ~info->mask; 679 const char *level, *errmsg; 680 int i; 681 682 if (info->severity == AER_CORRECTABLE) { 683 strings = aer_correctable_error_string; 684 level = KERN_WARNING; 685 } else { 686 strings = aer_uncorrectable_error_string; 687 level = KERN_ERR; 688 } 689 690 for_each_set_bit(i, &status, 32) { 691 errmsg = strings[i]; 692 if (!errmsg) 693 errmsg = "Unknown Error Bit"; 694 695 pci_printk(level, dev, " [%2d] %-22s%s\n", i, errmsg, 696 info->first_error == i ? " (First)" : ""); 697 } 698 pci_dev_aer_stats_incr(dev, info); 699 } 700 701 void aer_print_error(struct pci_dev *dev, struct aer_err_info *info) 702 { 703 int layer, agent; 704 int id = pci_dev_id(dev); 705 const char *level; 706 707 if (!info->status) { 708 pci_err(dev, "PCIe Bus Error: severity=%s, type=Inaccessible, (Unregistered Agent ID)\n", 709 aer_error_severity_string[info->severity]); 710 goto out; 711 } 712 713 layer = AER_GET_LAYER_ERROR(info->severity, info->status); 714 agent = AER_GET_AGENT(info->severity, info->status); 715 716 level = (info->severity == AER_CORRECTABLE) ? KERN_WARNING : KERN_ERR; 717 718 pci_printk(level, dev, "PCIe Bus Error: severity=%s, type=%s, (%s)\n", 719 aer_error_severity_string[info->severity], 720 aer_error_layer[layer], aer_agent_string[agent]); 721 722 pci_printk(level, dev, " device [%04x:%04x] error status/mask=%08x/%08x\n", 723 dev->vendor, dev->device, info->status, info->mask); 724 725 __aer_print_error(dev, info); 726 727 if (info->tlp_header_valid) 728 __print_tlp_header(dev, &info->tlp); 729 730 out: 731 if (info->id && info->error_dev_num > 1 && info->id == id) 732 pci_err(dev, " Error of this Agent is reported first\n"); 733 734 trace_aer_event(dev_name(&dev->dev), (info->status & ~info->mask), 735 info->severity, info->tlp_header_valid, &info->tlp); 736 } 737 738 static void aer_print_port_info(struct pci_dev *dev, struct aer_err_info *info) 739 { 740 u8 bus = info->id >> 8; 741 u8 devfn = info->id & 0xff; 742 743 pci_info(dev, "%s%s error message received from %04x:%02x:%02x.%d\n", 744 info->multi_error_valid ? "Multiple " : "", 745 aer_error_severity_string[info->severity], 746 pci_domain_nr(dev->bus), bus, PCI_SLOT(devfn), 747 PCI_FUNC(devfn)); 748 } 749 750 #ifdef CONFIG_ACPI_APEI_PCIEAER 751 int cper_severity_to_aer(int cper_severity) 752 { 753 switch (cper_severity) { 754 case CPER_SEV_RECOVERABLE: 755 return AER_NONFATAL; 756 case CPER_SEV_FATAL: 757 return AER_FATAL; 758 default: 759 return AER_CORRECTABLE; 760 } 761 } 762 EXPORT_SYMBOL_GPL(cper_severity_to_aer); 763 #endif 764 765 void pci_print_aer(struct pci_dev *dev, int aer_severity, 766 struct aer_capability_regs *aer) 767 { 768 int layer, agent, tlp_header_valid = 0; 769 u32 status, mask; 770 struct aer_err_info info; 771 772 if (aer_severity == AER_CORRECTABLE) { 773 status = aer->cor_status; 774 mask = aer->cor_mask; 775 } else { 776 status = aer->uncor_status; 777 mask = aer->uncor_mask; 778 tlp_header_valid = status & AER_LOG_TLP_MASKS; 779 } 780 781 layer = AER_GET_LAYER_ERROR(aer_severity, status); 782 agent = AER_GET_AGENT(aer_severity, status); 783 784 memset(&info, 0, sizeof(info)); 785 info.severity = aer_severity; 786 info.status = status; 787 info.mask = mask; 788 info.first_error = PCI_ERR_CAP_FEP(aer->cap_control); 789 790 pci_err(dev, "aer_status: 0x%08x, aer_mask: 0x%08x\n", status, mask); 791 __aer_print_error(dev, &info); 792 pci_err(dev, "aer_layer=%s, aer_agent=%s\n", 793 aer_error_layer[layer], aer_agent_string[agent]); 794 795 if (aer_severity != AER_CORRECTABLE) 796 pci_err(dev, "aer_uncor_severity: 0x%08x\n", 797 aer->uncor_severity); 798 799 if (tlp_header_valid) 800 __print_tlp_header(dev, &aer->header_log); 801 802 trace_aer_event(dev_name(&dev->dev), (status & ~mask), 803 aer_severity, tlp_header_valid, &aer->header_log); 804 } 805 EXPORT_SYMBOL_NS_GPL(pci_print_aer, CXL); 806 807 /** 808 * add_error_device - list device to be handled 809 * @e_info: pointer to error info 810 * @dev: pointer to pci_dev to be added 811 */ 812 static int add_error_device(struct aer_err_info *e_info, struct pci_dev *dev) 813 { 814 if (e_info->error_dev_num < AER_MAX_MULTI_ERR_DEVICES) { 815 e_info->dev[e_info->error_dev_num] = pci_dev_get(dev); 816 e_info->error_dev_num++; 817 return 0; 818 } 819 return -ENOSPC; 820 } 821 822 /** 823 * is_error_source - check whether the device is source of reported error 824 * @dev: pointer to pci_dev to be checked 825 * @e_info: pointer to reported error info 826 */ 827 static bool is_error_source(struct pci_dev *dev, struct aer_err_info *e_info) 828 { 829 int aer = dev->aer_cap; 830 u32 status, mask; 831 u16 reg16; 832 833 /* 834 * When bus id is equal to 0, it might be a bad id 835 * reported by root port. 836 */ 837 if ((PCI_BUS_NUM(e_info->id) != 0) && 838 !(dev->bus->bus_flags & PCI_BUS_FLAGS_NO_AERSID)) { 839 /* Device ID match? */ 840 if (e_info->id == pci_dev_id(dev)) 841 return true; 842 843 /* Continue id comparing if there is no multiple error */ 844 if (!e_info->multi_error_valid) 845 return false; 846 } 847 848 /* 849 * When either 850 * 1) bus id is equal to 0. Some ports might lose the bus 851 * id of error source id; 852 * 2) bus flag PCI_BUS_FLAGS_NO_AERSID is set 853 * 3) There are multiple errors and prior ID comparing fails; 854 * We check AER status registers to find possible reporter. 855 */ 856 if (atomic_read(&dev->enable_cnt) == 0) 857 return false; 858 859 /* Check if AER is enabled */ 860 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, ®16); 861 if (!(reg16 & PCI_EXP_AER_FLAGS)) 862 return false; 863 864 if (!aer) 865 return false; 866 867 /* Check if error is recorded */ 868 if (e_info->severity == AER_CORRECTABLE) { 869 pci_read_config_dword(dev, aer + PCI_ERR_COR_STATUS, &status); 870 pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK, &mask); 871 } else { 872 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status); 873 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, &mask); 874 } 875 if (status & ~mask) 876 return true; 877 878 return false; 879 } 880 881 static int find_device_iter(struct pci_dev *dev, void *data) 882 { 883 struct aer_err_info *e_info = (struct aer_err_info *)data; 884 885 if (is_error_source(dev, e_info)) { 886 /* List this device */ 887 if (add_error_device(e_info, dev)) { 888 /* We cannot handle more... Stop iteration */ 889 /* TODO: Should print error message here? */ 890 return 1; 891 } 892 893 /* If there is only a single error, stop iteration */ 894 if (!e_info->multi_error_valid) 895 return 1; 896 } 897 return 0; 898 } 899 900 /** 901 * find_source_device - search through device hierarchy for source device 902 * @parent: pointer to Root Port pci_dev data structure 903 * @e_info: including detailed error information such like id 904 * 905 * Return true if found. 906 * 907 * Invoked by DPC when error is detected at the Root Port. 908 * Caller of this function must set id, severity, and multi_error_valid of 909 * struct aer_err_info pointed by @e_info properly. This function must fill 910 * e_info->error_dev_num and e_info->dev[], based on the given information. 911 */ 912 static bool find_source_device(struct pci_dev *parent, 913 struct aer_err_info *e_info) 914 { 915 struct pci_dev *dev = parent; 916 int result; 917 918 /* Must reset in this function */ 919 e_info->error_dev_num = 0; 920 921 /* Is Root Port an agent that sends error message? */ 922 result = find_device_iter(dev, e_info); 923 if (result) 924 return true; 925 926 if (pci_pcie_type(parent) == PCI_EXP_TYPE_RC_EC) 927 pcie_walk_rcec(parent, find_device_iter, e_info); 928 else 929 pci_walk_bus(parent->subordinate, find_device_iter, e_info); 930 931 if (!e_info->error_dev_num) { 932 u8 bus = e_info->id >> 8; 933 u8 devfn = e_info->id & 0xff; 934 935 pci_info(parent, "found no error details for %04x:%02x:%02x.%d\n", 936 pci_domain_nr(parent->bus), bus, PCI_SLOT(devfn), 937 PCI_FUNC(devfn)); 938 return false; 939 } 940 return true; 941 } 942 943 #ifdef CONFIG_PCIEAER_CXL 944 945 /** 946 * pci_aer_unmask_internal_errors - unmask internal errors 947 * @dev: pointer to the pcie_dev data structure 948 * 949 * Unmasks internal errors in the Uncorrectable and Correctable Error 950 * Mask registers. 951 * 952 * Note: AER must be enabled and supported by the device which must be 953 * checked in advance, e.g. with pcie_aer_is_native(). 954 */ 955 static void pci_aer_unmask_internal_errors(struct pci_dev *dev) 956 { 957 int aer = dev->aer_cap; 958 u32 mask; 959 960 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, &mask); 961 mask &= ~PCI_ERR_UNC_INTN; 962 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, mask); 963 964 pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK, &mask); 965 mask &= ~PCI_ERR_COR_INTERNAL; 966 pci_write_config_dword(dev, aer + PCI_ERR_COR_MASK, mask); 967 } 968 969 static bool is_cxl_mem_dev(struct pci_dev *dev) 970 { 971 /* 972 * The capability, status, and control fields in Device 0, 973 * Function 0 DVSEC control the CXL functionality of the 974 * entire device (CXL 3.0, 8.1.3). 975 */ 976 if (dev->devfn != PCI_DEVFN(0, 0)) 977 return false; 978 979 /* 980 * CXL Memory Devices must have the 502h class code set (CXL 981 * 3.0, 8.1.12.1). 982 */ 983 if ((dev->class >> 8) != PCI_CLASS_MEMORY_CXL) 984 return false; 985 986 return true; 987 } 988 989 static bool cxl_error_is_native(struct pci_dev *dev) 990 { 991 struct pci_host_bridge *host = pci_find_host_bridge(dev->bus); 992 993 return (pcie_ports_native || host->native_aer); 994 } 995 996 static bool is_internal_error(struct aer_err_info *info) 997 { 998 if (info->severity == AER_CORRECTABLE) 999 return info->status & PCI_ERR_COR_INTERNAL; 1000 1001 return info->status & PCI_ERR_UNC_INTN; 1002 } 1003 1004 static int cxl_rch_handle_error_iter(struct pci_dev *dev, void *data) 1005 { 1006 struct aer_err_info *info = (struct aer_err_info *)data; 1007 const struct pci_error_handlers *err_handler; 1008 1009 if (!is_cxl_mem_dev(dev) || !cxl_error_is_native(dev)) 1010 return 0; 1011 1012 /* protect dev->driver */ 1013 device_lock(&dev->dev); 1014 1015 err_handler = dev->driver ? dev->driver->err_handler : NULL; 1016 if (!err_handler) 1017 goto out; 1018 1019 if (info->severity == AER_CORRECTABLE) { 1020 if (err_handler->cor_error_detected) 1021 err_handler->cor_error_detected(dev); 1022 } else if (err_handler->error_detected) { 1023 if (info->severity == AER_NONFATAL) 1024 err_handler->error_detected(dev, pci_channel_io_normal); 1025 else if (info->severity == AER_FATAL) 1026 err_handler->error_detected(dev, pci_channel_io_frozen); 1027 } 1028 out: 1029 device_unlock(&dev->dev); 1030 return 0; 1031 } 1032 1033 static void cxl_rch_handle_error(struct pci_dev *dev, struct aer_err_info *info) 1034 { 1035 /* 1036 * Internal errors of an RCEC indicate an AER error in an 1037 * RCH's downstream port. Check and handle them in the CXL.mem 1038 * device driver. 1039 */ 1040 if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_EC && 1041 is_internal_error(info)) 1042 pcie_walk_rcec(dev, cxl_rch_handle_error_iter, info); 1043 } 1044 1045 static int handles_cxl_error_iter(struct pci_dev *dev, void *data) 1046 { 1047 bool *handles_cxl = data; 1048 1049 if (!*handles_cxl) 1050 *handles_cxl = is_cxl_mem_dev(dev) && cxl_error_is_native(dev); 1051 1052 /* Non-zero terminates iteration */ 1053 return *handles_cxl; 1054 } 1055 1056 static bool handles_cxl_errors(struct pci_dev *rcec) 1057 { 1058 bool handles_cxl = false; 1059 1060 if (pci_pcie_type(rcec) == PCI_EXP_TYPE_RC_EC && 1061 pcie_aer_is_native(rcec)) 1062 pcie_walk_rcec(rcec, handles_cxl_error_iter, &handles_cxl); 1063 1064 return handles_cxl; 1065 } 1066 1067 static void cxl_rch_enable_rcec(struct pci_dev *rcec) 1068 { 1069 if (!handles_cxl_errors(rcec)) 1070 return; 1071 1072 pci_aer_unmask_internal_errors(rcec); 1073 pci_info(rcec, "CXL: Internal errors unmasked"); 1074 } 1075 1076 #else 1077 static inline void cxl_rch_enable_rcec(struct pci_dev *dev) { } 1078 static inline void cxl_rch_handle_error(struct pci_dev *dev, 1079 struct aer_err_info *info) { } 1080 #endif 1081 1082 /** 1083 * pci_aer_handle_error - handle logging error into an event log 1084 * @dev: pointer to pci_dev data structure of error source device 1085 * @info: comprehensive error information 1086 * 1087 * Invoked when an error being detected by Root Port. 1088 */ 1089 static void pci_aer_handle_error(struct pci_dev *dev, struct aer_err_info *info) 1090 { 1091 int aer = dev->aer_cap; 1092 1093 if (info->severity == AER_CORRECTABLE) { 1094 /* 1095 * Correctable error does not need software intervention. 1096 * No need to go through error recovery process. 1097 */ 1098 if (aer) 1099 pci_write_config_dword(dev, aer + PCI_ERR_COR_STATUS, 1100 info->status); 1101 if (pcie_aer_is_native(dev)) { 1102 struct pci_driver *pdrv = dev->driver; 1103 1104 if (pdrv && pdrv->err_handler && 1105 pdrv->err_handler->cor_error_detected) 1106 pdrv->err_handler->cor_error_detected(dev); 1107 pcie_clear_device_status(dev); 1108 } 1109 } else if (info->severity == AER_NONFATAL) 1110 pcie_do_recovery(dev, pci_channel_io_normal, aer_root_reset); 1111 else if (info->severity == AER_FATAL) 1112 pcie_do_recovery(dev, pci_channel_io_frozen, aer_root_reset); 1113 } 1114 1115 static void handle_error_source(struct pci_dev *dev, struct aer_err_info *info) 1116 { 1117 cxl_rch_handle_error(dev, info); 1118 pci_aer_handle_error(dev, info); 1119 pci_dev_put(dev); 1120 } 1121 1122 #ifdef CONFIG_ACPI_APEI_PCIEAER 1123 1124 #define AER_RECOVER_RING_SIZE 16 1125 1126 struct aer_recover_entry { 1127 u8 bus; 1128 u8 devfn; 1129 u16 domain; 1130 int severity; 1131 struct aer_capability_regs *regs; 1132 }; 1133 1134 static DEFINE_KFIFO(aer_recover_ring, struct aer_recover_entry, 1135 AER_RECOVER_RING_SIZE); 1136 1137 static void aer_recover_work_func(struct work_struct *work) 1138 { 1139 struct aer_recover_entry entry; 1140 struct pci_dev *pdev; 1141 1142 while (kfifo_get(&aer_recover_ring, &entry)) { 1143 pdev = pci_get_domain_bus_and_slot(entry.domain, entry.bus, 1144 entry.devfn); 1145 if (!pdev) { 1146 pr_err("no pci_dev for %04x:%02x:%02x.%x\n", 1147 entry.domain, entry.bus, 1148 PCI_SLOT(entry.devfn), PCI_FUNC(entry.devfn)); 1149 continue; 1150 } 1151 pci_print_aer(pdev, entry.severity, entry.regs); 1152 1153 /* 1154 * Memory for aer_capability_regs(entry.regs) is being 1155 * allocated from the ghes_estatus_pool to protect it from 1156 * overwriting when multiple sections are present in the 1157 * error status. Thus free the same after processing the 1158 * data. 1159 */ 1160 ghes_estatus_pool_region_free((unsigned long)entry.regs, 1161 sizeof(struct aer_capability_regs)); 1162 1163 if (entry.severity == AER_NONFATAL) 1164 pcie_do_recovery(pdev, pci_channel_io_normal, 1165 aer_root_reset); 1166 else if (entry.severity == AER_FATAL) 1167 pcie_do_recovery(pdev, pci_channel_io_frozen, 1168 aer_root_reset); 1169 pci_dev_put(pdev); 1170 } 1171 } 1172 1173 /* 1174 * Mutual exclusion for writers of aer_recover_ring, reader side don't 1175 * need lock, because there is only one reader and lock is not needed 1176 * between reader and writer. 1177 */ 1178 static DEFINE_SPINLOCK(aer_recover_ring_lock); 1179 static DECLARE_WORK(aer_recover_work, aer_recover_work_func); 1180 1181 void aer_recover_queue(int domain, unsigned int bus, unsigned int devfn, 1182 int severity, struct aer_capability_regs *aer_regs) 1183 { 1184 struct aer_recover_entry entry = { 1185 .bus = bus, 1186 .devfn = devfn, 1187 .domain = domain, 1188 .severity = severity, 1189 .regs = aer_regs, 1190 }; 1191 1192 if (kfifo_in_spinlocked(&aer_recover_ring, &entry, 1, 1193 &aer_recover_ring_lock)) 1194 schedule_work(&aer_recover_work); 1195 else 1196 pr_err("buffer overflow in recovery for %04x:%02x:%02x.%x\n", 1197 domain, bus, PCI_SLOT(devfn), PCI_FUNC(devfn)); 1198 } 1199 EXPORT_SYMBOL_GPL(aer_recover_queue); 1200 #endif 1201 1202 /** 1203 * aer_get_device_error_info - read error status from dev and store it to info 1204 * @dev: pointer to the device expected to have a error record 1205 * @info: pointer to structure to store the error record 1206 * 1207 * Return 1 on success, 0 on error. 1208 * 1209 * Note that @info is reused among all error devices. Clear fields properly. 1210 */ 1211 int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info) 1212 { 1213 int type = pci_pcie_type(dev); 1214 int aer = dev->aer_cap; 1215 u32 aercc; 1216 1217 /* Must reset in this function */ 1218 info->status = 0; 1219 info->tlp_header_valid = 0; 1220 1221 /* The device might not support AER */ 1222 if (!aer) 1223 return 0; 1224 1225 if (info->severity == AER_CORRECTABLE) { 1226 pci_read_config_dword(dev, aer + PCI_ERR_COR_STATUS, 1227 &info->status); 1228 pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK, 1229 &info->mask); 1230 if (!(info->status & ~info->mask)) 1231 return 0; 1232 } else if (type == PCI_EXP_TYPE_ROOT_PORT || 1233 type == PCI_EXP_TYPE_RC_EC || 1234 type == PCI_EXP_TYPE_DOWNSTREAM || 1235 info->severity == AER_NONFATAL) { 1236 1237 /* Link is still healthy for IO reads */ 1238 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, 1239 &info->status); 1240 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, 1241 &info->mask); 1242 if (!(info->status & ~info->mask)) 1243 return 0; 1244 1245 /* Get First Error Pointer */ 1246 pci_read_config_dword(dev, aer + PCI_ERR_CAP, &aercc); 1247 info->first_error = PCI_ERR_CAP_FEP(aercc); 1248 1249 if (info->status & AER_LOG_TLP_MASKS) { 1250 info->tlp_header_valid = 1; 1251 pcie_read_tlp_log(dev, aer + PCI_ERR_HEADER_LOG, &info->tlp); 1252 } 1253 } 1254 1255 return 1; 1256 } 1257 1258 static inline void aer_process_err_devices(struct aer_err_info *e_info) 1259 { 1260 int i; 1261 1262 /* Report all before handle them, not to lost records by reset etc. */ 1263 for (i = 0; i < e_info->error_dev_num && e_info->dev[i]; i++) { 1264 if (aer_get_device_error_info(e_info->dev[i], e_info)) 1265 aer_print_error(e_info->dev[i], e_info); 1266 } 1267 for (i = 0; i < e_info->error_dev_num && e_info->dev[i]; i++) { 1268 if (aer_get_device_error_info(e_info->dev[i], e_info)) 1269 handle_error_source(e_info->dev[i], e_info); 1270 } 1271 } 1272 1273 /** 1274 * aer_isr_one_error - consume an error detected by root port 1275 * @rpc: pointer to the root port which holds an error 1276 * @e_src: pointer to an error source 1277 */ 1278 static void aer_isr_one_error(struct aer_rpc *rpc, 1279 struct aer_err_source *e_src) 1280 { 1281 struct pci_dev *pdev = rpc->rpd; 1282 struct aer_err_info e_info; 1283 1284 pci_rootport_aer_stats_incr(pdev, e_src); 1285 1286 /* 1287 * There is a possibility that both correctable error and 1288 * uncorrectable error being logged. Report correctable error first. 1289 */ 1290 if (e_src->status & PCI_ERR_ROOT_COR_RCV) { 1291 e_info.id = ERR_COR_ID(e_src->id); 1292 e_info.severity = AER_CORRECTABLE; 1293 1294 if (e_src->status & PCI_ERR_ROOT_MULTI_COR_RCV) 1295 e_info.multi_error_valid = 1; 1296 else 1297 e_info.multi_error_valid = 0; 1298 aer_print_port_info(pdev, &e_info); 1299 1300 if (find_source_device(pdev, &e_info)) 1301 aer_process_err_devices(&e_info); 1302 } 1303 1304 if (e_src->status & PCI_ERR_ROOT_UNCOR_RCV) { 1305 e_info.id = ERR_UNCOR_ID(e_src->id); 1306 1307 if (e_src->status & PCI_ERR_ROOT_FATAL_RCV) 1308 e_info.severity = AER_FATAL; 1309 else 1310 e_info.severity = AER_NONFATAL; 1311 1312 if (e_src->status & PCI_ERR_ROOT_MULTI_UNCOR_RCV) 1313 e_info.multi_error_valid = 1; 1314 else 1315 e_info.multi_error_valid = 0; 1316 1317 aer_print_port_info(pdev, &e_info); 1318 1319 if (find_source_device(pdev, &e_info)) 1320 aer_process_err_devices(&e_info); 1321 } 1322 } 1323 1324 /** 1325 * aer_isr - consume errors detected by root port 1326 * @irq: IRQ assigned to Root Port 1327 * @context: pointer to Root Port data structure 1328 * 1329 * Invoked, as DPC, when root port records new detected error 1330 */ 1331 static irqreturn_t aer_isr(int irq, void *context) 1332 { 1333 struct pcie_device *dev = (struct pcie_device *)context; 1334 struct aer_rpc *rpc = get_service_data(dev); 1335 struct aer_err_source e_src; 1336 1337 if (kfifo_is_empty(&rpc->aer_fifo)) 1338 return IRQ_NONE; 1339 1340 while (kfifo_get(&rpc->aer_fifo, &e_src)) 1341 aer_isr_one_error(rpc, &e_src); 1342 return IRQ_HANDLED; 1343 } 1344 1345 /** 1346 * aer_irq - Root Port's ISR 1347 * @irq: IRQ assigned to Root Port 1348 * @context: pointer to Root Port data structure 1349 * 1350 * Invoked when Root Port detects AER messages. 1351 */ 1352 static irqreturn_t aer_irq(int irq, void *context) 1353 { 1354 struct pcie_device *pdev = (struct pcie_device *)context; 1355 struct aer_rpc *rpc = get_service_data(pdev); 1356 struct pci_dev *rp = rpc->rpd; 1357 int aer = rp->aer_cap; 1358 struct aer_err_source e_src = {}; 1359 1360 pci_read_config_dword(rp, aer + PCI_ERR_ROOT_STATUS, &e_src.status); 1361 if (!(e_src.status & AER_ERR_STATUS_MASK)) 1362 return IRQ_NONE; 1363 1364 pci_read_config_dword(rp, aer + PCI_ERR_ROOT_ERR_SRC, &e_src.id); 1365 pci_write_config_dword(rp, aer + PCI_ERR_ROOT_STATUS, e_src.status); 1366 1367 if (!kfifo_put(&rpc->aer_fifo, e_src)) 1368 return IRQ_HANDLED; 1369 1370 return IRQ_WAKE_THREAD; 1371 } 1372 1373 static void aer_enable_irq(struct pci_dev *pdev) 1374 { 1375 int aer = pdev->aer_cap; 1376 u32 reg32; 1377 1378 /* Enable Root Port's interrupt in response to error messages */ 1379 pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, ®32); 1380 reg32 |= ROOT_PORT_INTR_ON_MESG_MASK; 1381 pci_write_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, reg32); 1382 } 1383 1384 static void aer_disable_irq(struct pci_dev *pdev) 1385 { 1386 int aer = pdev->aer_cap; 1387 u32 reg32; 1388 1389 /* Disable Root's interrupt in response to error messages */ 1390 pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, ®32); 1391 reg32 &= ~ROOT_PORT_INTR_ON_MESG_MASK; 1392 pci_write_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, reg32); 1393 } 1394 1395 /** 1396 * aer_enable_rootport - enable Root Port's interrupts when receiving messages 1397 * @rpc: pointer to a Root Port data structure 1398 * 1399 * Invoked when PCIe bus loads AER service driver. 1400 */ 1401 static void aer_enable_rootport(struct aer_rpc *rpc) 1402 { 1403 struct pci_dev *pdev = rpc->rpd; 1404 int aer = pdev->aer_cap; 1405 u16 reg16; 1406 u32 reg32; 1407 1408 /* Clear PCIe Capability's Device Status */ 1409 pcie_capability_read_word(pdev, PCI_EXP_DEVSTA, ®16); 1410 pcie_capability_write_word(pdev, PCI_EXP_DEVSTA, reg16); 1411 1412 /* Disable system error generation in response to error messages */ 1413 pcie_capability_clear_word(pdev, PCI_EXP_RTCTL, 1414 SYSTEM_ERROR_INTR_ON_MESG_MASK); 1415 1416 /* Clear error status */ 1417 pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_STATUS, ®32); 1418 pci_write_config_dword(pdev, aer + PCI_ERR_ROOT_STATUS, reg32); 1419 pci_read_config_dword(pdev, aer + PCI_ERR_COR_STATUS, ®32); 1420 pci_write_config_dword(pdev, aer + PCI_ERR_COR_STATUS, reg32); 1421 pci_read_config_dword(pdev, aer + PCI_ERR_UNCOR_STATUS, ®32); 1422 pci_write_config_dword(pdev, aer + PCI_ERR_UNCOR_STATUS, reg32); 1423 1424 aer_enable_irq(pdev); 1425 } 1426 1427 /** 1428 * aer_disable_rootport - disable Root Port's interrupts when receiving messages 1429 * @rpc: pointer to a Root Port data structure 1430 * 1431 * Invoked when PCIe bus unloads AER service driver. 1432 */ 1433 static void aer_disable_rootport(struct aer_rpc *rpc) 1434 { 1435 struct pci_dev *pdev = rpc->rpd; 1436 int aer = pdev->aer_cap; 1437 u32 reg32; 1438 1439 aer_disable_irq(pdev); 1440 1441 /* Clear Root's error status reg */ 1442 pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_STATUS, ®32); 1443 pci_write_config_dword(pdev, aer + PCI_ERR_ROOT_STATUS, reg32); 1444 } 1445 1446 /** 1447 * aer_remove - clean up resources 1448 * @dev: pointer to the pcie_dev data structure 1449 * 1450 * Invoked when PCI Express bus unloads or AER probe fails. 1451 */ 1452 static void aer_remove(struct pcie_device *dev) 1453 { 1454 struct aer_rpc *rpc = get_service_data(dev); 1455 1456 aer_disable_rootport(rpc); 1457 } 1458 1459 /** 1460 * aer_probe - initialize resources 1461 * @dev: pointer to the pcie_dev data structure 1462 * 1463 * Invoked when PCI Express bus loads AER service driver. 1464 */ 1465 static int aer_probe(struct pcie_device *dev) 1466 { 1467 int status; 1468 struct aer_rpc *rpc; 1469 struct device *device = &dev->device; 1470 struct pci_dev *port = dev->port; 1471 1472 BUILD_BUG_ON(ARRAY_SIZE(aer_correctable_error_string) < 1473 AER_MAX_TYPEOF_COR_ERRS); 1474 BUILD_BUG_ON(ARRAY_SIZE(aer_uncorrectable_error_string) < 1475 AER_MAX_TYPEOF_UNCOR_ERRS); 1476 1477 /* Limit to Root Ports or Root Complex Event Collectors */ 1478 if ((pci_pcie_type(port) != PCI_EXP_TYPE_RC_EC) && 1479 (pci_pcie_type(port) != PCI_EXP_TYPE_ROOT_PORT)) 1480 return -ENODEV; 1481 1482 rpc = devm_kzalloc(device, sizeof(struct aer_rpc), GFP_KERNEL); 1483 if (!rpc) 1484 return -ENOMEM; 1485 1486 rpc->rpd = port; 1487 INIT_KFIFO(rpc->aer_fifo); 1488 set_service_data(dev, rpc); 1489 1490 status = devm_request_threaded_irq(device, dev->irq, aer_irq, aer_isr, 1491 IRQF_SHARED, "aerdrv", dev); 1492 if (status) { 1493 pci_err(port, "request AER IRQ %d failed\n", dev->irq); 1494 return status; 1495 } 1496 1497 cxl_rch_enable_rcec(port); 1498 aer_enable_rootport(rpc); 1499 pci_info(port, "enabled with IRQ %d\n", dev->irq); 1500 return 0; 1501 } 1502 1503 static int aer_suspend(struct pcie_device *dev) 1504 { 1505 struct aer_rpc *rpc = get_service_data(dev); 1506 1507 aer_disable_rootport(rpc); 1508 return 0; 1509 } 1510 1511 static int aer_resume(struct pcie_device *dev) 1512 { 1513 struct aer_rpc *rpc = get_service_data(dev); 1514 1515 aer_enable_rootport(rpc); 1516 return 0; 1517 } 1518 1519 /** 1520 * aer_root_reset - reset Root Port hierarchy, RCEC, or RCiEP 1521 * @dev: pointer to Root Port, RCEC, or RCiEP 1522 * 1523 * Invoked by Port Bus driver when performing reset. 1524 */ 1525 static pci_ers_result_t aer_root_reset(struct pci_dev *dev) 1526 { 1527 int type = pci_pcie_type(dev); 1528 struct pci_dev *root; 1529 int aer; 1530 struct pci_host_bridge *host = pci_find_host_bridge(dev->bus); 1531 u32 reg32; 1532 int rc; 1533 1534 /* 1535 * Only Root Ports and RCECs have AER Root Command and Root Status 1536 * registers. If "dev" is an RCiEP, the relevant registers are in 1537 * the RCEC. 1538 */ 1539 if (type == PCI_EXP_TYPE_RC_END) 1540 root = dev->rcec; 1541 else 1542 root = pcie_find_root_port(dev); 1543 1544 /* 1545 * If the platform retained control of AER, an RCiEP may not have 1546 * an RCEC visible to us, so dev->rcec ("root") may be NULL. In 1547 * that case, firmware is responsible for these registers. 1548 */ 1549 aer = root ? root->aer_cap : 0; 1550 1551 if ((host->native_aer || pcie_ports_native) && aer) 1552 aer_disable_irq(root); 1553 1554 if (type == PCI_EXP_TYPE_RC_EC || type == PCI_EXP_TYPE_RC_END) { 1555 rc = pcie_reset_flr(dev, PCI_RESET_DO_RESET); 1556 if (!rc) 1557 pci_info(dev, "has been reset\n"); 1558 else 1559 pci_info(dev, "not reset (no FLR support: %d)\n", rc); 1560 } else { 1561 rc = pci_bus_error_reset(dev); 1562 pci_info(dev, "%s Port link has been reset (%d)\n", 1563 pci_is_root_bus(dev->bus) ? "Root" : "Downstream", rc); 1564 } 1565 1566 if ((host->native_aer || pcie_ports_native) && aer) { 1567 /* Clear Root Error Status */ 1568 pci_read_config_dword(root, aer + PCI_ERR_ROOT_STATUS, ®32); 1569 pci_write_config_dword(root, aer + PCI_ERR_ROOT_STATUS, reg32); 1570 1571 aer_enable_irq(root); 1572 } 1573 1574 return rc ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED; 1575 } 1576 1577 static struct pcie_port_service_driver aerdriver = { 1578 .name = "aer", 1579 .port_type = PCIE_ANY_PORT, 1580 .service = PCIE_PORT_SERVICE_AER, 1581 1582 .probe = aer_probe, 1583 .suspend = aer_suspend, 1584 .resume = aer_resume, 1585 .remove = aer_remove, 1586 }; 1587 1588 /** 1589 * pcie_aer_init - register AER root service driver 1590 * 1591 * Invoked when AER root service driver is loaded. 1592 */ 1593 int __init pcie_aer_init(void) 1594 { 1595 if (!pci_aer_available()) 1596 return -ENXIO; 1597 return pcie_port_service_register(&aerdriver); 1598 } 1599