xref: /linux/drivers/pci/pcie/Kconfig (revision 71e2f4dd5a65bd8dbca0b77661e75eea471168f8) 
1# SPDX-License-Identifier: GPL-2.0
2#
3# PCI Express Port Bus Configuration
4#
5config PCIEPORTBUS
6	bool "PCI Express Port Bus support"
7	depends on PCI
8	help
9	  This enables PCI Express Port Bus support. Users can then enable
10	  support for Native Hot-Plug, Advanced Error Reporting, Power
11	  Management Events, and Downstream Port Containment.
12
13#
14# Include service Kconfig here
15#
16config HOTPLUG_PCI_PCIE
17	bool "PCI Express Hotplug driver"
18	depends on HOTPLUG_PCI && PCIEPORTBUS
19	help
20	  Say Y here if you have a motherboard that supports PCI Express Native
21	  Hotplug
22
23	  When in doubt, say N.
24
25config PCIEAER
26	bool "PCI Express Advanced Error Reporting support"
27	depends on PCIEPORTBUS
28	select RAS
29	default y
30	help
31	  This enables PCI Express Root Port Advanced Error Reporting
32	  (AER) driver support. Error reporting messages sent to Root
33	  Port will be handled by PCI Express AER driver.
34
35config PCIEAER_INJECT
36	tristate "PCI Express error injection support"
37	depends on PCIEAER
38	help
39	  This enables PCI Express Root Port Advanced Error Reporting
40	  (AER) software error injector.
41
42	  Debugging AER code is quite difficult because it is hard
43	  to trigger various real hardware errors. Software-based
44	  error injection can fake almost all kinds of errors with the
45	  help of a user space helper tool aer-inject, which can be
46	  gotten from:
47	     http://www.kernel.org/pub/linux/utils/pci/aer-inject/
48
49#
50# PCI Express ECRC
51#
52config PCIE_ECRC
53	bool "PCI Express ECRC settings control"
54	depends on PCIEAER
55	help
56	  Used to override firmware/bios settings for PCI Express ECRC
57	  (transaction layer end-to-end CRC checking).
58
59	  When in doubt, say N.
60
61#
62# PCI Express ASPM
63#
64config PCIEASPM
65	bool "PCI Express ASPM control" if EXPERT
66	depends on PCI && PCIEPORTBUS
67	default y
68	help
69	  This enables OS control over PCI Express ASPM (Active State
70	  Power Management) and Clock Power Management. ASPM supports
71	  state L0/L0s/L1.
72
73	  ASPM is initially set up by the firmware. With this option enabled,
74	  Linux can modify this state in order to disable ASPM on known-bad
75	  hardware or configurations and enable it when known-safe.
76
77	  ASPM can be disabled or enabled at runtime via
78	  /sys/module/pcie_aspm/parameters/policy
79
80	  When in doubt, say Y.
81
82config PCIEASPM_DEBUG
83	bool "Debug PCI Express ASPM"
84	depends on PCIEASPM
85	help
86	  This enables PCI Express ASPM debug support. It will add per-device
87	  interface to control ASPM.
88
89choice
90	prompt "Default ASPM policy"
91	default PCIEASPM_DEFAULT
92	depends on PCIEASPM
93
94config PCIEASPM_DEFAULT
95	bool "BIOS default"
96	depends on PCIEASPM
97	help
98	  Use the BIOS defaults for PCI Express ASPM.
99
100config PCIEASPM_POWERSAVE
101	bool "Powersave"
102	depends on PCIEASPM
103	help
104	  Enable PCI Express ASPM L0s and L1 where possible, even if the
105	  BIOS did not.
106
107config PCIEASPM_POWER_SUPERSAVE
108	bool "Power Supersave"
109	depends on PCIEASPM
110	help
111	  Same as PCIEASPM_POWERSAVE, except it also enables L1 substates where
112	  possible. This would result in higher power savings while staying in L1
113	  where the components support it.
114
115config PCIEASPM_PERFORMANCE
116	bool "Performance"
117	depends on PCIEASPM
118	help
119	  Disable PCI Express ASPM L0s and L1, even if the BIOS enabled them.
120endchoice
121
122config PCIE_PME
123	def_bool y
124	depends on PCIEPORTBUS && PM
125
126config PCIE_DPC
127	bool "PCI Express Downstream Port Containment support"
128	depends on PCIEPORTBUS && PCIEAER
129	help
130	  This enables PCI Express Downstream Port Containment (DPC)
131	  driver support.  DPC events from Root and Downstream ports
132	  will be handled by the DPC driver.  If your system doesn't
133	  have this capability or you do not want to use this feature,
134	  it is safe to answer N.
135
136config PCIE_PTM
137	bool "PCI Express Precision Time Measurement support"
138	depends on PCIEPORTBUS
139	help
140	  This enables PCI Express Precision Time Measurement (PTM)
141	  support.
142
143	  This is only useful if you have devices that support PTM, but it
144	  is safe to enable even if you don't.
145
146config PCIE_BW
147	bool "PCI Express Bandwidth Change Notification"
148	depends on PCIEPORTBUS
149	help
150	  This enables PCI Express Bandwidth Change Notification.  If
151	  you know link width or rate changes occur only to correct
152	  unreliable links, you may answer Y.
153