11da177e4SLinus Torvalds# 21da177e4SLinus Torvalds# PCI Express Port Bus Configuration 31da177e4SLinus Torvalds# 41da177e4SLinus Torvaldsconfig PCIEPORTBUS 5d47af0bcSEzequiel Garcia bool "PCI Express Port Bus support" 61da177e4SLinus Torvalds depends on PCI 71da177e4SLinus Torvalds help 81da177e4SLinus Torvalds This automatically enables PCI Express Port Bus support. Users can 91da177e4SLinus Torvalds choose Native Hot-Plug support, Advanced Error Reporting support, 101da177e4SLinus Torvalds Power Management Event support and Virtual Channel support to run 111da177e4SLinus Torvalds on PCI Express Ports (Root or Switch). 121da177e4SLinus Torvalds 131da177e4SLinus Torvalds# 141da177e4SLinus Torvalds# Include service Kconfig here 151da177e4SLinus Torvalds# 161da177e4SLinus Torvaldsconfig HOTPLUG_PCI_PCIE 17c10cc483SBjorn Helgaas bool "PCI Express Hotplug driver" 181da177e4SLinus Torvalds depends on HOTPLUG_PCI && PCIEPORTBUS 191da177e4SLinus Torvalds help 201da177e4SLinus Torvalds Say Y here if you have a motherboard that supports PCI Express Native 211da177e4SLinus Torvalds Hotplug 221da177e4SLinus Torvalds 231da177e4SLinus Torvalds When in doubt, say N. 241da177e4SLinus Torvalds 256c2b374dSZhang, Yanminsource "drivers/pci/pcie/aer/Kconfig" 267d715a6cSShaohua Li 277d715a6cSShaohua Li# 287d715a6cSShaohua Li# PCI Express ASPM 297d715a6cSShaohua Li# 307d715a6cSShaohua Liconfig PCIEASPM 316a108a14SDavid Rientjes bool "PCI Express ASPM control" if EXPERT 32ea5f9fc5SMatthew Garrett depends on PCI && PCIEPORTBUS 33ea5f9fc5SMatthew Garrett default y 347d715a6cSShaohua Li help 35ea5f9fc5SMatthew Garrett This enables OS control over PCI Express ASPM (Active State 36ea5f9fc5SMatthew Garrett Power Management) and Clock Power Management. ASPM supports 37ea5f9fc5SMatthew Garrett state L0/L0s/L1. 387d715a6cSShaohua Li 39d56641c7SP. Christeas ASPM is initially set up by the firmware. With this option enabled, 40ea5f9fc5SMatthew Garrett Linux can modify this state in order to disable ASPM on known-bad 41ea5f9fc5SMatthew Garrett hardware or configurations and enable it when known-safe. 42ea5f9fc5SMatthew Garrett 43ea5f9fc5SMatthew Garrett ASPM can be disabled or enabled at runtime via 44ea5f9fc5SMatthew Garrett /sys/module/pcie_aspm/parameters/policy 45ea5f9fc5SMatthew Garrett 46ea5f9fc5SMatthew Garrett When in doubt, say Y. 47cc73176cSAndreas Ziegler 487d715a6cSShaohua Liconfig PCIEASPM_DEBUG 497d715a6cSShaohua Li bool "Debug PCI Express ASPM" 507d715a6cSShaohua Li depends on PCIEASPM 517d715a6cSShaohua Li default n 527d715a6cSShaohua Li help 537d715a6cSShaohua Li This enables PCI Express ASPM debug support. It will add per-device 547d715a6cSShaohua Li interface to control ASPM. 55c7f48656SRafael J. Wysocki 56ad71c962SMatthew Garrettchoice 57ad71c962SMatthew Garrett prompt "Default ASPM policy" 58ad71c962SMatthew Garrett default PCIEASPM_DEFAULT 59ad71c962SMatthew Garrett depends on PCIEASPM 60ad71c962SMatthew Garrett 61ad71c962SMatthew Garrettconfig PCIEASPM_DEFAULT 62ad71c962SMatthew Garrett bool "BIOS default" 63ad71c962SMatthew Garrett depends on PCIEASPM 64ad71c962SMatthew Garrett help 65ad71c962SMatthew Garrett Use the BIOS defaults for PCI Express ASPM. 66ad71c962SMatthew Garrett 67ad71c962SMatthew Garrettconfig PCIEASPM_POWERSAVE 68ad71c962SMatthew Garrett bool "Powersave" 69ad71c962SMatthew Garrett depends on PCIEASPM 70ad71c962SMatthew Garrett help 71ad71c962SMatthew Garrett Enable PCI Express ASPM L0s and L1 where possible, even if the 72ad71c962SMatthew Garrett BIOS did not. 73ad71c962SMatthew Garrett 74b2103ccbSRajat Jainconfig PCIEASPM_POWER_SUPERSAVE 75b2103ccbSRajat Jain bool "Power Supersave" 76b2103ccbSRajat Jain depends on PCIEASPM 77b2103ccbSRajat Jain help 78b2103ccbSRajat Jain Same as PCIEASPM_POWERSAVE, except it also enables L1 substates where 79b2103ccbSRajat Jain possible. This would result in higher power savings while staying in L1 80b2103ccbSRajat Jain where the components support it. 81b2103ccbSRajat Jain 82ad71c962SMatthew Garrettconfig PCIEASPM_PERFORMANCE 83ad71c962SMatthew Garrett bool "Performance" 84ad71c962SMatthew Garrett depends on PCIEASPM 85ad71c962SMatthew Garrett help 86ad71c962SMatthew Garrett Disable PCI Express ASPM L0s and L1, even if the BIOS enabled them. 87ad71c962SMatthew Garrettendchoice 88ad71c962SMatthew Garrett 89c7f48656SRafael J. Wysockiconfig PCIE_PME 90c7f48656SRafael J. Wysocki def_bool y 91fbb988beSRafael J. Wysocki depends on PCIEPORTBUS && PM 9226e51571SKeith Busch 9326e51571SKeith Buschconfig PCIE_DPC 94a4959d8cSKeith Busch bool "PCIe Downstream Port Containment support" 95*eed85ff4SKeith Busch depends on PCIEPORTBUS && PCIEAER 9626e51571SKeith Busch default n 9726e51571SKeith Busch help 9826e51571SKeith Busch This enables PCI Express Downstream Port Containment (DPC) 9926e51571SKeith Busch driver support. DPC events from Root and Downstream ports 10026e51571SKeith Busch will be handled by the DPC driver. If your system doesn't 10126e51571SKeith Busch have this capability or you do not want to use this feature, 10226e51571SKeith Busch it is safe to answer N. 1039bb04a0cSJonathan Yong 1049bb04a0cSJonathan Yongconfig PCIE_PTM 1059bb04a0cSJonathan Yong bool "PCIe Precision Time Measurement support" 1069bb04a0cSJonathan Yong default n 1079bb04a0cSJonathan Yong depends on PCIEPORTBUS 1089bb04a0cSJonathan Yong help 1099bb04a0cSJonathan Yong This enables PCI Express Precision Time Measurement (PTM) 1109bb04a0cSJonathan Yong support. 1119bb04a0cSJonathan Yong 1129bb04a0cSJonathan Yong This is only useful if you have devices that support PTM, but it 1139bb04a0cSJonathan Yong is safe to enable even if you don't. 114