17328c8f4SBjorn Helgaas# SPDX-License-Identifier: GPL-2.0 21da177e4SLinus Torvalds# 31da177e4SLinus Torvalds# PCI Express Port Bus Configuration 41da177e4SLinus Torvalds# 51da177e4SLinus Torvaldsconfig PCIEPORTBUS 6d47af0bcSEzequiel Garcia bool "PCI Express Port Bus support" 71da177e4SLinus Torvalds help 88f55ed3fSHou Zhiqiang This enables PCI Express Port Bus support. Users can then enable 98f55ed3fSHou Zhiqiang support for Native Hot-Plug, Advanced Error Reporting, Power 108f55ed3fSHou Zhiqiang Management Events, and Downstream Port Containment. 111da177e4SLinus Torvalds 121da177e4SLinus Torvalds# 131da177e4SLinus Torvalds# Include service Kconfig here 141da177e4SLinus Torvalds# 151da177e4SLinus Torvaldsconfig HOTPLUG_PCI_PCIE 16c10cc483SBjorn Helgaas bool "PCI Express Hotplug driver" 171da177e4SLinus Torvalds depends on HOTPLUG_PCI && PCIEPORTBUS 181da177e4SLinus Torvalds help 191da177e4SLinus Torvalds Say Y here if you have a motherboard that supports PCI Express Native 201da177e4SLinus Torvalds Hotplug 211da177e4SLinus Torvalds 221da177e4SLinus Torvalds When in doubt, say N. 231da177e4SLinus Torvalds 244696b828SBjorn Helgaasconfig PCIEAER 250b15f1e3SBjorn Helgaas bool "PCI Express Advanced Error Reporting support" 264696b828SBjorn Helgaas depends on PCIEPORTBUS 274696b828SBjorn Helgaas select RAS 284696b828SBjorn Helgaas default y 294696b828SBjorn Helgaas help 304696b828SBjorn Helgaas This enables PCI Express Root Port Advanced Error Reporting 314696b828SBjorn Helgaas (AER) driver support. Error reporting messages sent to Root 324696b828SBjorn Helgaas Port will be handled by PCI Express AER driver. 334696b828SBjorn Helgaas 344696b828SBjorn Helgaasconfig PCIEAER_INJECT 350b15f1e3SBjorn Helgaas tristate "PCI Express error injection support" 364696b828SBjorn Helgaas depends on PCIEAER 374696b828SBjorn Helgaas help 384696b828SBjorn Helgaas This enables PCI Express Root Port Advanced Error Reporting 394696b828SBjorn Helgaas (AER) software error injector. 404696b828SBjorn Helgaas 410b15f1e3SBjorn Helgaas Debugging AER code is quite difficult because it is hard 420b15f1e3SBjorn Helgaas to trigger various real hardware errors. Software-based 434696b828SBjorn Helgaas error injection can fake almost all kinds of errors with the 444696b828SBjorn Helgaas help of a user space helper tool aer-inject, which can be 454696b828SBjorn Helgaas gotten from: 464696b828SBjorn Helgaas http://www.kernel.org/pub/linux/utils/pci/aer-inject/ 474696b828SBjorn Helgaas 484696b828SBjorn Helgaas# 494696b828SBjorn Helgaas# PCI Express ECRC 504696b828SBjorn Helgaas# 514696b828SBjorn Helgaasconfig PCIE_ECRC 524696b828SBjorn Helgaas bool "PCI Express ECRC settings control" 534696b828SBjorn Helgaas depends on PCIEAER 544696b828SBjorn Helgaas help 554696b828SBjorn Helgaas Used to override firmware/bios settings for PCI Express ECRC 564696b828SBjorn Helgaas (transaction layer end-to-end CRC checking). 574696b828SBjorn Helgaas 584696b828SBjorn Helgaas When in doubt, say N. 597d715a6cSShaohua Li 607d715a6cSShaohua Li# 617d715a6cSShaohua Li# PCI Express ASPM 627d715a6cSShaohua Li# 637d715a6cSShaohua Liconfig PCIEASPM 646a108a14SDavid Rientjes bool "PCI Express ASPM control" if EXPERT 65ea5f9fc5SMatthew Garrett default y 667d715a6cSShaohua Li help 67ea5f9fc5SMatthew Garrett This enables OS control over PCI Express ASPM (Active State 68ea5f9fc5SMatthew Garrett Power Management) and Clock Power Management. ASPM supports 69ea5f9fc5SMatthew Garrett state L0/L0s/L1. 707d715a6cSShaohua Li 71d56641c7SP. Christeas ASPM is initially set up by the firmware. With this option enabled, 72ea5f9fc5SMatthew Garrett Linux can modify this state in order to disable ASPM on known-bad 73ea5f9fc5SMatthew Garrett hardware or configurations and enable it when known-safe. 74ea5f9fc5SMatthew Garrett 75ea5f9fc5SMatthew Garrett ASPM can be disabled or enabled at runtime via 76ea5f9fc5SMatthew Garrett /sys/module/pcie_aspm/parameters/policy 77ea5f9fc5SMatthew Garrett 78ea5f9fc5SMatthew Garrett When in doubt, say Y. 79cc73176cSAndreas Ziegler 80ad71c962SMatthew Garrettchoice 81ad71c962SMatthew Garrett prompt "Default ASPM policy" 82ad71c962SMatthew Garrett default PCIEASPM_DEFAULT 83ad71c962SMatthew Garrett depends on PCIEASPM 84ad71c962SMatthew Garrett 85ad71c962SMatthew Garrettconfig PCIEASPM_DEFAULT 86ad71c962SMatthew Garrett bool "BIOS default" 87ad71c962SMatthew Garrett depends on PCIEASPM 88ad71c962SMatthew Garrett help 89ad71c962SMatthew Garrett Use the BIOS defaults for PCI Express ASPM. 90ad71c962SMatthew Garrett 91ad71c962SMatthew Garrettconfig PCIEASPM_POWERSAVE 92ad71c962SMatthew Garrett bool "Powersave" 93ad71c962SMatthew Garrett depends on PCIEASPM 94ad71c962SMatthew Garrett help 95ad71c962SMatthew Garrett Enable PCI Express ASPM L0s and L1 where possible, even if the 96ad71c962SMatthew Garrett BIOS did not. 97ad71c962SMatthew Garrett 98b2103ccbSRajat Jainconfig PCIEASPM_POWER_SUPERSAVE 99b2103ccbSRajat Jain bool "Power Supersave" 100b2103ccbSRajat Jain depends on PCIEASPM 101b2103ccbSRajat Jain help 102b2103ccbSRajat Jain Same as PCIEASPM_POWERSAVE, except it also enables L1 substates where 103b2103ccbSRajat Jain possible. This would result in higher power savings while staying in L1 104b2103ccbSRajat Jain where the components support it. 105b2103ccbSRajat Jain 106ad71c962SMatthew Garrettconfig PCIEASPM_PERFORMANCE 107ad71c962SMatthew Garrett bool "Performance" 108ad71c962SMatthew Garrett depends on PCIEASPM 109ad71c962SMatthew Garrett help 110ad71c962SMatthew Garrett Disable PCI Express ASPM L0s and L1, even if the BIOS enabled them. 111ad71c962SMatthew Garrettendchoice 112ad71c962SMatthew Garrett 113c7f48656SRafael J. Wysockiconfig PCIE_PME 114c7f48656SRafael J. Wysocki def_bool y 115fbb988beSRafael J. Wysocki depends on PCIEPORTBUS && PM 11626e51571SKeith Busch 11726e51571SKeith Buschconfig PCIE_DPC 1180b15f1e3SBjorn Helgaas bool "PCI Express Downstream Port Containment support" 119eed85ff4SKeith Busch depends on PCIEPORTBUS && PCIEAER 12026e51571SKeith Busch help 12126e51571SKeith Busch This enables PCI Express Downstream Port Containment (DPC) 12226e51571SKeith Busch driver support. DPC events from Root and Downstream ports 12326e51571SKeith Busch will be handled by the DPC driver. If your system doesn't 12426e51571SKeith Busch have this capability or you do not want to use this feature, 12526e51571SKeith Busch it is safe to answer N. 1269bb04a0cSJonathan Yong 1279bb04a0cSJonathan Yongconfig PCIE_PTM 1280b15f1e3SBjorn Helgaas bool "PCI Express Precision Time Measurement support" 1299bb04a0cSJonathan Yong help 1309bb04a0cSJonathan Yong This enables PCI Express Precision Time Measurement (PTM) 1319bb04a0cSJonathan Yong support. 1329bb04a0cSJonathan Yong 1339bb04a0cSJonathan Yong This is only useful if you have devices that support PTM, but it 1349bb04a0cSJonathan Yong is safe to enable even if you don't. 1352078e1e7SKeith Busch 1362078e1e7SKeith Buschconfig PCIE_BW 1372078e1e7SKeith Busch bool "PCI Express Bandwidth Change Notification" 1382078e1e7SKeith Busch depends on PCIEPORTBUS 1392078e1e7SKeith Busch help 1402078e1e7SKeith Busch This enables PCI Express Bandwidth Change Notification. If 1412078e1e7SKeith Busch you know link width or rate changes occur only to correct 1422078e1e7SKeith Busch unreliable links, you may answer Y. 143*ac1c8e35SKuppuswamy Sathyanarayanan 144*ac1c8e35SKuppuswamy Sathyanarayananconfig PCIE_EDR 145*ac1c8e35SKuppuswamy Sathyanarayanan bool "PCI Express Error Disconnect Recover support" 146*ac1c8e35SKuppuswamy Sathyanarayanan depends on PCIE_DPC && ACPI 147*ac1c8e35SKuppuswamy Sathyanarayanan help 148*ac1c8e35SKuppuswamy Sathyanarayanan This option adds Error Disconnect Recover support as specified 149*ac1c8e35SKuppuswamy Sathyanarayanan in the Downstream Port Containment Related Enhancements ECN to 150*ac1c8e35SKuppuswamy Sathyanarayanan the PCI Firmware Specification r3.2. Enable this if you want to 151*ac1c8e35SKuppuswamy Sathyanarayanan support hybrid DPC model which uses both firmware and OS to 152*ac1c8e35SKuppuswamy Sathyanarayanan implement DPC. 153