xref: /linux/drivers/pci/pcie/Kconfig (revision 36ec807b627b4c0a0a382f0ae48eac7187d14b2b)
17328c8f4SBjorn Helgaas# SPDX-License-Identifier: GPL-2.0
21da177e4SLinus Torvalds#
31da177e4SLinus Torvalds# PCI Express Port Bus Configuration
41da177e4SLinus Torvalds#
51da177e4SLinus Torvaldsconfig PCIEPORTBUS
6d47af0bcSEzequiel Garcia	bool "PCI Express Port Bus support"
7e67ad935SAlbert Zhou	default y if USB4
81da177e4SLinus Torvalds	help
98f55ed3fSHou Zhiqiang	  This enables PCI Express Port Bus support. Users can then enable
108f55ed3fSHou Zhiqiang	  support for Native Hot-Plug, Advanced Error Reporting, Power
118f55ed3fSHou Zhiqiang	  Management Events, and Downstream Port Containment.
121da177e4SLinus Torvalds
131da177e4SLinus Torvalds#
141da177e4SLinus Torvalds# Include service Kconfig here
151da177e4SLinus Torvalds#
161da177e4SLinus Torvaldsconfig HOTPLUG_PCI_PCIE
17c10cc483SBjorn Helgaas	bool "PCI Express Hotplug driver"
181da177e4SLinus Torvalds	depends on HOTPLUG_PCI && PCIEPORTBUS
19e67ad935SAlbert Zhou	default y if USB4
201da177e4SLinus Torvalds	help
21e67ad935SAlbert Zhou	  Say Y here if you have a motherboard that supports PCIe native
22e67ad935SAlbert Zhou	  hotplug.
23e67ad935SAlbert Zhou
24e67ad935SAlbert Zhou	  Thunderbolt/USB4 PCIe tunneling depends on native PCIe hotplug.
251da177e4SLinus Torvalds
261da177e4SLinus Torvalds	  When in doubt, say N.
271da177e4SLinus Torvalds
284696b828SBjorn Helgaasconfig PCIEAER
290b15f1e3SBjorn Helgaas	bool "PCI Express Advanced Error Reporting support"
304696b828SBjorn Helgaas	depends on PCIEPORTBUS
314696b828SBjorn Helgaas	select RAS
324696b828SBjorn Helgaas	help
334696b828SBjorn Helgaas	  This enables PCI Express Root Port Advanced Error Reporting
344696b828SBjorn Helgaas	  (AER) driver support. Error reporting messages sent to Root
354696b828SBjorn Helgaas	  Port will be handled by PCI Express AER driver.
364696b828SBjorn Helgaas
374696b828SBjorn Helgaasconfig PCIEAER_INJECT
380b15f1e3SBjorn Helgaas	tristate "PCI Express error injection support"
394696b828SBjorn Helgaas	depends on PCIEAER
409ae05225SThomas Gleixner	select GENERIC_IRQ_INJECTION
414696b828SBjorn Helgaas	help
424696b828SBjorn Helgaas	  This enables PCI Express Root Port Advanced Error Reporting
434696b828SBjorn Helgaas	  (AER) software error injector.
444696b828SBjorn Helgaas
450b15f1e3SBjorn Helgaas	  Debugging AER code is quite difficult because it is hard
460b15f1e3SBjorn Helgaas	  to trigger various real hardware errors. Software-based
474696b828SBjorn Helgaas	  error injection can fake almost all kinds of errors with the
484696b828SBjorn Helgaas	  help of a user space helper tool aer-inject, which can be
494696b828SBjorn Helgaas	  gotten from:
50*a29e5290SKuppuswamy Sathyanarayanan	     https://github.com/intel/aer-inject.git
514696b828SBjorn Helgaas
520a867568SRobert Richterconfig PCIEAER_CXL
530a867568SRobert Richter	bool "PCI Express CXL RAS support"
540a867568SRobert Richter	default y
550a867568SRobert Richter	depends on PCIEAER && CXL_PCI
560a867568SRobert Richter	help
570a867568SRobert Richter	  Enables CXL error handling.
580a867568SRobert Richter
590a867568SRobert Richter	  If unsure, say Y.
600a867568SRobert Richter
614696b828SBjorn Helgaas#
624696b828SBjorn Helgaas# PCI Express ECRC
634696b828SBjorn Helgaas#
644696b828SBjorn Helgaasconfig PCIE_ECRC
654696b828SBjorn Helgaas	bool "PCI Express ECRC settings control"
664696b828SBjorn Helgaas	depends on PCIEAER
674696b828SBjorn Helgaas	help
684696b828SBjorn Helgaas	  Used to override firmware/bios settings for PCI Express ECRC
694696b828SBjorn Helgaas	  (transaction layer end-to-end CRC checking).
704696b828SBjorn Helgaas
714696b828SBjorn Helgaas	  When in doubt, say N.
727d715a6cSShaohua Li
737d715a6cSShaohua Li#
747d715a6cSShaohua Li# PCI Express ASPM
757d715a6cSShaohua Li#
767d715a6cSShaohua Liconfig PCIEASPM
776a108a14SDavid Rientjes	bool "PCI Express ASPM control" if EXPERT
78ea5f9fc5SMatthew Garrett	default y
797d715a6cSShaohua Li	help
80ea5f9fc5SMatthew Garrett	  This enables OS control over PCI Express ASPM (Active State
81ea5f9fc5SMatthew Garrett	  Power Management) and Clock Power Management. ASPM supports
82ea5f9fc5SMatthew Garrett	  state L0/L0s/L1.
837d715a6cSShaohua Li
84d56641c7SP. Christeas	  ASPM is initially set up by the firmware. With this option enabled,
85ea5f9fc5SMatthew Garrett	  Linux can modify this state in order to disable ASPM on known-bad
86ea5f9fc5SMatthew Garrett	  hardware or configurations and enable it when known-safe.
87ea5f9fc5SMatthew Garrett
88ea5f9fc5SMatthew Garrett	  ASPM can be disabled or enabled at runtime via
89ea5f9fc5SMatthew Garrett	  /sys/module/pcie_aspm/parameters/policy
90ea5f9fc5SMatthew Garrett
91ea5f9fc5SMatthew Garrett	  When in doubt, say Y.
92cc73176cSAndreas Ziegler
93ad71c962SMatthew Garrettchoice
94ad71c962SMatthew Garrett	prompt "Default ASPM policy"
95ad71c962SMatthew Garrett	default PCIEASPM_DEFAULT
96ad71c962SMatthew Garrett	depends on PCIEASPM
97ad71c962SMatthew Garrett
98ad71c962SMatthew Garrettconfig PCIEASPM_DEFAULT
99ad71c962SMatthew Garrett	bool "BIOS default"
100ad71c962SMatthew Garrett	depends on PCIEASPM
101ad71c962SMatthew Garrett	help
102ad71c962SMatthew Garrett	  Use the BIOS defaults for PCI Express ASPM.
103ad71c962SMatthew Garrett
104ad71c962SMatthew Garrettconfig PCIEASPM_POWERSAVE
105ad71c962SMatthew Garrett	bool "Powersave"
106ad71c962SMatthew Garrett	depends on PCIEASPM
107ad71c962SMatthew Garrett	help
108ad71c962SMatthew Garrett	  Enable PCI Express ASPM L0s and L1 where possible, even if the
109ad71c962SMatthew Garrett	  BIOS did not.
110ad71c962SMatthew Garrett
111b2103ccbSRajat Jainconfig PCIEASPM_POWER_SUPERSAVE
112b2103ccbSRajat Jain	bool "Power Supersave"
113b2103ccbSRajat Jain	depends on PCIEASPM
114b2103ccbSRajat Jain	help
115b2103ccbSRajat Jain	  Same as PCIEASPM_POWERSAVE, except it also enables L1 substates where
116b2103ccbSRajat Jain	  possible. This would result in higher power savings while staying in L1
117b2103ccbSRajat Jain	  where the components support it.
118b2103ccbSRajat Jain
119ad71c962SMatthew Garrettconfig PCIEASPM_PERFORMANCE
120ad71c962SMatthew Garrett	bool "Performance"
121ad71c962SMatthew Garrett	depends on PCIEASPM
122ad71c962SMatthew Garrett	help
123ad71c962SMatthew Garrett	  Disable PCI Express ASPM L0s and L1, even if the BIOS enabled them.
124ad71c962SMatthew Garrettendchoice
125ad71c962SMatthew Garrett
126c7f48656SRafael J. Wysockiconfig PCIE_PME
127c7f48656SRafael J. Wysocki	def_bool y
128fbb988beSRafael J. Wysocki	depends on PCIEPORTBUS && PM
12926e51571SKeith Busch
13026e51571SKeith Buschconfig PCIE_DPC
1310b15f1e3SBjorn Helgaas	bool "PCI Express Downstream Port Containment support"
132eed85ff4SKeith Busch	depends on PCIEPORTBUS && PCIEAER
13326e51571SKeith Busch	help
13426e51571SKeith Busch	  This enables PCI Express Downstream Port Containment (DPC)
13526e51571SKeith Busch	  driver support.  DPC events from Root and Downstream ports
13626e51571SKeith Busch	  will be handled by the DPC driver.  If your system doesn't
13726e51571SKeith Busch	  have this capability or you do not want to use this feature,
13826e51571SKeith Busch	  it is safe to answer N.
1399bb04a0cSJonathan Yong
1409bb04a0cSJonathan Yongconfig PCIE_PTM
1410b15f1e3SBjorn Helgaas	bool "PCI Express Precision Time Measurement support"
1429bb04a0cSJonathan Yong	help
1439bb04a0cSJonathan Yong	  This enables PCI Express Precision Time Measurement (PTM)
1449bb04a0cSJonathan Yong	  support.
1459bb04a0cSJonathan Yong
1469bb04a0cSJonathan Yong	  This is only useful if you have devices that support PTM, but it
1479bb04a0cSJonathan Yong	  is safe to enable even if you don't.
1482078e1e7SKeith Busch
149ac1c8e35SKuppuswamy Sathyanarayananconfig PCIE_EDR
150ac1c8e35SKuppuswamy Sathyanarayanan	bool "PCI Express Error Disconnect Recover support"
151ac1c8e35SKuppuswamy Sathyanarayanan	depends on PCIE_DPC && ACPI
152ac1c8e35SKuppuswamy Sathyanarayanan	help
153ac1c8e35SKuppuswamy Sathyanarayanan	  This option adds Error Disconnect Recover support as specified
154ac1c8e35SKuppuswamy Sathyanarayanan	  in the Downstream Port Containment Related Enhancements ECN to
155ac1c8e35SKuppuswamy Sathyanarayanan	  the PCI Firmware Specification r3.2.  Enable this if you want to
156ac1c8e35SKuppuswamy Sathyanarayanan	  support hybrid DPC model which uses both firmware and OS to
157ac1c8e35SKuppuswamy Sathyanarayanan	  implement DPC.
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