1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef DRIVERS_PCI_H 3 #define DRIVERS_PCI_H 4 5 #include <linux/align.h> 6 #include <linux/bitfield.h> 7 #include <linux/pci.h> 8 9 struct pcie_tlp_log; 10 11 /* Number of possible devfns: 0.0 to 1f.7 inclusive */ 12 #define MAX_NR_DEVFNS 256 13 #define PCI_MAX_NR_DEVS 32 14 15 #define MAX_NR_LANES 16 16 17 #define PCI_FIND_CAP_TTL 48 18 19 #define PCI_VSEC_ID_INTEL_TBT 0x1234 /* Thunderbolt */ 20 21 #define PCIE_LINK_RETRAIN_TIMEOUT_MS 1000 22 23 /* 24 * Power stable to PERST# inactive. 25 * 26 * See the "Power Sequencing and Reset Signal Timings" table of the PCI Express 27 * Card Electromechanical Specification, Revision 5.1, Section 2.9.2, Symbol 28 * "T_PVPERL". 29 */ 30 #define PCIE_T_PVPERL_MS 100 31 32 /* 33 * REFCLK stable before PERST# inactive. 34 * 35 * See the "Power Sequencing and Reset Signal Timings" table of the PCI Express 36 * Card Electromechanical Specification, Revision 5.1, Section 2.9.2, Symbol 37 * "T_PERST-CLK". 38 */ 39 #define PCIE_T_PERST_CLK_US 100 40 41 /* 42 * PCIe r6.0, sec 5.3.3.2.1 <PME Synchronization> 43 * Recommends 1ms to 10ms timeout to check L2 ready. 44 */ 45 #define PCIE_PME_TO_L2_TIMEOUT_US 10000 46 47 /* 48 * PCIe r6.0, sec 6.6.1 <Conventional Reset> 49 * 50 * - "With a Downstream Port that does not support Link speeds greater 51 * than 5.0 GT/s, software must wait a minimum of 100 ms following exit 52 * from a Conventional Reset before sending a Configuration Request to 53 * the device immediately below that Port." 54 * 55 * - "With a Downstream Port that supports Link speeds greater than 56 * 5.0 GT/s, software must wait a minimum of 100 ms after Link training 57 * completes before sending a Configuration Request to the device 58 * immediately below that Port." 59 */ 60 #define PCIE_RESET_CONFIG_WAIT_MS 100 61 62 /* Parameters for the waiting for link up routine */ 63 #define PCIE_LINK_WAIT_MAX_RETRIES 10 64 #define PCIE_LINK_WAIT_SLEEP_MS 90 65 66 /* Message Routing (r[2:0]); PCIe r6.0, sec 2.2.8 */ 67 #define PCIE_MSG_TYPE_R_RC 0 68 #define PCIE_MSG_TYPE_R_ADDR 1 69 #define PCIE_MSG_TYPE_R_ID 2 70 #define PCIE_MSG_TYPE_R_BC 3 71 #define PCIE_MSG_TYPE_R_LOCAL 4 72 #define PCIE_MSG_TYPE_R_GATHER 5 73 74 /* Power Management Messages; PCIe r6.0, sec 2.2.8.2 */ 75 #define PCIE_MSG_CODE_PME_TURN_OFF 0x19 76 77 /* INTx Mechanism Messages; PCIe r6.0, sec 2.2.8.1 */ 78 #define PCIE_MSG_CODE_ASSERT_INTA 0x20 79 #define PCIE_MSG_CODE_ASSERT_INTB 0x21 80 #define PCIE_MSG_CODE_ASSERT_INTC 0x22 81 #define PCIE_MSG_CODE_ASSERT_INTD 0x23 82 #define PCIE_MSG_CODE_DEASSERT_INTA 0x24 83 #define PCIE_MSG_CODE_DEASSERT_INTB 0x25 84 #define PCIE_MSG_CODE_DEASSERT_INTC 0x26 85 #define PCIE_MSG_CODE_DEASSERT_INTD 0x27 86 87 #define PCI_BUS_BRIDGE_IO_WINDOW 0 88 #define PCI_BUS_BRIDGE_MEM_WINDOW 1 89 #define PCI_BUS_BRIDGE_PREF_MEM_WINDOW 2 90 91 extern const unsigned char pcie_link_speed[]; 92 extern bool pci_early_dump; 93 94 extern struct mutex pci_rescan_remove_lock; 95 96 bool pcie_cap_has_lnkctl(const struct pci_dev *dev); 97 bool pcie_cap_has_lnkctl2(const struct pci_dev *dev); 98 bool pcie_cap_has_rtctl(const struct pci_dev *dev); 99 100 /* Standard Capability finder */ 101 /** 102 * PCI_FIND_NEXT_CAP - Find a PCI standard capability 103 * @read_cfg: Function pointer for reading PCI config space 104 * @start: Starting position to begin search 105 * @cap: Capability ID to find 106 * @args: Arguments to pass to read_cfg function 107 * 108 * Search the capability list in PCI config space to find @cap. 109 * Implements TTL (time-to-live) protection against infinite loops. 110 * 111 * Return: Position of the capability if found, 0 otherwise. 112 */ 113 #define PCI_FIND_NEXT_CAP(read_cfg, start, cap, args...) \ 114 ({ \ 115 int __ttl = PCI_FIND_CAP_TTL; \ 116 u8 __id, __found_pos = 0; \ 117 u8 __pos = (start); \ 118 u16 __ent; \ 119 \ 120 read_cfg##_byte(args, __pos, &__pos); \ 121 \ 122 while (__ttl--) { \ 123 if (__pos < PCI_STD_HEADER_SIZEOF) \ 124 break; \ 125 \ 126 __pos = ALIGN_DOWN(__pos, 4); \ 127 read_cfg##_word(args, __pos, &__ent); \ 128 \ 129 __id = FIELD_GET(PCI_CAP_ID_MASK, __ent); \ 130 if (__id == 0xff) \ 131 break; \ 132 \ 133 if (__id == (cap)) { \ 134 __found_pos = __pos; \ 135 break; \ 136 } \ 137 \ 138 __pos = FIELD_GET(PCI_CAP_LIST_NEXT_MASK, __ent); \ 139 } \ 140 __found_pos; \ 141 }) 142 143 /* Extended Capability finder */ 144 /** 145 * PCI_FIND_NEXT_EXT_CAP - Find a PCI extended capability 146 * @read_cfg: Function pointer for reading PCI config space 147 * @start: Starting position to begin search (0 for initial search) 148 * @cap: Extended capability ID to find 149 * @args: Arguments to pass to read_cfg function 150 * 151 * Search the extended capability list in PCI config space to find @cap. 152 * Implements TTL protection against infinite loops using a calculated 153 * maximum search count. 154 * 155 * Return: Position of the capability if found, 0 otherwise. 156 */ 157 #define PCI_FIND_NEXT_EXT_CAP(read_cfg, start, cap, args...) \ 158 ({ \ 159 u16 __pos = (start) ?: PCI_CFG_SPACE_SIZE; \ 160 u16 __found_pos = 0; \ 161 int __ttl, __ret; \ 162 u32 __header; \ 163 \ 164 __ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; \ 165 while (__ttl-- > 0 && __pos >= PCI_CFG_SPACE_SIZE) { \ 166 __ret = read_cfg##_dword(args, __pos, &__header); \ 167 if (__ret != PCIBIOS_SUCCESSFUL) \ 168 break; \ 169 \ 170 if (__header == 0) \ 171 break; \ 172 \ 173 if (PCI_EXT_CAP_ID(__header) == (cap) && __pos != start) {\ 174 __found_pos = __pos; \ 175 break; \ 176 } \ 177 \ 178 __pos = PCI_EXT_CAP_NEXT(__header); \ 179 } \ 180 __found_pos; \ 181 }) 182 183 /* Functions internal to the PCI core code */ 184 185 #ifdef CONFIG_DMI 186 extern const struct attribute_group pci_dev_smbios_attr_group; 187 #endif 188 189 enum pci_mmap_api { 190 PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */ 191 PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */ 192 }; 193 int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai, 194 enum pci_mmap_api mmap_api); 195 196 bool pci_reset_supported(struct pci_dev *dev); 197 void pci_init_reset_methods(struct pci_dev *dev); 198 int pci_bridge_secondary_bus_reset(struct pci_dev *dev); 199 int pci_bus_error_reset(struct pci_dev *dev); 200 int __pci_reset_bus(struct pci_bus *bus); 201 202 struct pci_cap_saved_data { 203 u16 cap_nr; 204 bool cap_extended; 205 unsigned int size; 206 u32 data[]; 207 }; 208 209 struct pci_cap_saved_state { 210 struct hlist_node next; 211 struct pci_cap_saved_data cap; 212 }; 213 214 void pci_allocate_cap_save_buffers(struct pci_dev *dev); 215 void pci_free_cap_save_buffers(struct pci_dev *dev); 216 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size); 217 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, 218 u16 cap, unsigned int size); 219 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap); 220 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, 221 u16 cap); 222 223 #define PCI_PM_D2_DELAY 200 /* usec; see PCIe r4.0, sec 5.9.1 */ 224 #define PCI_PM_D3HOT_WAIT 10 /* msec */ 225 #define PCI_PM_D3COLD_WAIT 100 /* msec */ 226 227 void pci_update_current_state(struct pci_dev *dev, pci_power_t state); 228 void pci_refresh_power_state(struct pci_dev *dev); 229 int pci_power_up(struct pci_dev *dev); 230 void pci_disable_enabled_device(struct pci_dev *dev); 231 int pci_finish_runtime_suspend(struct pci_dev *dev); 232 void pcie_clear_device_status(struct pci_dev *dev); 233 void pcie_clear_root_pme_status(struct pci_dev *dev); 234 bool pci_check_pme_status(struct pci_dev *dev); 235 void pci_pme_wakeup_bus(struct pci_bus *bus); 236 void pci_pme_restore(struct pci_dev *dev); 237 bool pci_dev_need_resume(struct pci_dev *dev); 238 void pci_dev_adjust_pme(struct pci_dev *dev); 239 void pci_dev_complete_resume(struct pci_dev *pci_dev); 240 void pci_config_pm_runtime_get(struct pci_dev *dev); 241 void pci_config_pm_runtime_put(struct pci_dev *dev); 242 void pci_pm_power_up_and_verify_state(struct pci_dev *pci_dev); 243 void pci_pm_init(struct pci_dev *dev); 244 void pci_ea_init(struct pci_dev *dev); 245 void pci_msi_init(struct pci_dev *dev); 246 void pci_msix_init(struct pci_dev *dev); 247 bool pci_bridge_d3_possible(struct pci_dev *dev); 248 void pci_bridge_d3_update(struct pci_dev *dev); 249 int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type); 250 251 static inline bool pci_bus_rrs_vendor_id(u32 l) 252 { 253 return (l & 0xffff) == PCI_VENDOR_ID_PCI_SIG; 254 } 255 256 static inline void pci_wakeup_event(struct pci_dev *dev) 257 { 258 /* Wait 100 ms before the system can be put into a sleep state. */ 259 pm_wakeup_event(&dev->dev, 100); 260 } 261 262 /** 263 * pci_bar_index_is_valid - Check whether a BAR index is within valid range 264 * @bar: BAR index 265 * 266 * Protects against overflowing &struct pci_dev.resource array. 267 * 268 * Return: true for valid index, false otherwise. 269 */ 270 static inline bool pci_bar_index_is_valid(int bar) 271 { 272 if (bar >= 0 && bar < PCI_NUM_RESOURCES) 273 return true; 274 275 return false; 276 } 277 278 static inline bool pci_has_subordinate(struct pci_dev *pci_dev) 279 { 280 return !!(pci_dev->subordinate); 281 } 282 283 static inline bool pci_power_manageable(struct pci_dev *pci_dev) 284 { 285 /* 286 * Currently we allow normal PCI devices and PCI bridges transition 287 * into D3 if their bridge_d3 is set. 288 */ 289 return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3; 290 } 291 292 static inline bool pcie_downstream_port(const struct pci_dev *dev) 293 { 294 int type = pci_pcie_type(dev); 295 296 return type == PCI_EXP_TYPE_ROOT_PORT || 297 type == PCI_EXP_TYPE_DOWNSTREAM || 298 type == PCI_EXP_TYPE_PCIE_BRIDGE; 299 } 300 301 void pci_vpd_init(struct pci_dev *dev); 302 extern const struct attribute_group pci_dev_vpd_attr_group; 303 304 /* PCI Virtual Channel */ 305 int pci_save_vc_state(struct pci_dev *dev); 306 void pci_restore_vc_state(struct pci_dev *dev); 307 void pci_allocate_vc_save_buffers(struct pci_dev *dev); 308 309 /* PCI /proc functions */ 310 #ifdef CONFIG_PROC_FS 311 int pci_proc_attach_device(struct pci_dev *dev); 312 int pci_proc_detach_device(struct pci_dev *dev); 313 int pci_proc_detach_bus(struct pci_bus *bus); 314 #else 315 static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; } 316 static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; } 317 static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; } 318 #endif 319 320 /* Functions for PCI Hotplug drivers to use */ 321 int pci_hp_add_bridge(struct pci_dev *dev); 322 bool pci_hp_spurious_link_change(struct pci_dev *pdev); 323 324 #if defined(CONFIG_SYSFS) && defined(HAVE_PCI_LEGACY) 325 void pci_create_legacy_files(struct pci_bus *bus); 326 void pci_remove_legacy_files(struct pci_bus *bus); 327 #else 328 static inline void pci_create_legacy_files(struct pci_bus *bus) { } 329 static inline void pci_remove_legacy_files(struct pci_bus *bus) { } 330 #endif 331 332 /* Lock for read/write access to pci device and bus lists */ 333 extern struct rw_semaphore pci_bus_sem; 334 extern struct mutex pci_slot_mutex; 335 336 extern raw_spinlock_t pci_lock; 337 338 extern unsigned int pci_pm_d3hot_delay; 339 340 #ifdef CONFIG_PCI_MSI 341 void pci_no_msi(void); 342 #else 343 static inline void pci_no_msi(void) { } 344 #endif 345 346 void pci_realloc_get_opt(char *); 347 348 static inline int pci_no_d1d2(struct pci_dev *dev) 349 { 350 unsigned int parent_dstates = 0; 351 352 if (dev->bus->self) 353 parent_dstates = dev->bus->self->no_d1d2; 354 return (dev->no_d1d2 || parent_dstates); 355 356 } 357 358 #ifdef CONFIG_SYSFS 359 int pci_create_sysfs_dev_files(struct pci_dev *pdev); 360 void pci_remove_sysfs_dev_files(struct pci_dev *pdev); 361 extern const struct attribute_group *pci_dev_groups[]; 362 extern const struct attribute_group *pci_dev_attr_groups[]; 363 extern const struct attribute_group *pcibus_groups[]; 364 extern const struct attribute_group *pci_bus_groups[]; 365 extern const struct attribute_group pci_doe_sysfs_group; 366 #else 367 static inline int pci_create_sysfs_dev_files(struct pci_dev *pdev) { return 0; } 368 static inline void pci_remove_sysfs_dev_files(struct pci_dev *pdev) { } 369 #define pci_dev_groups NULL 370 #define pci_dev_attr_groups NULL 371 #define pcibus_groups NULL 372 #define pci_bus_groups NULL 373 #endif 374 375 extern unsigned long pci_hotplug_io_size; 376 extern unsigned long pci_hotplug_mmio_size; 377 extern unsigned long pci_hotplug_mmio_pref_size; 378 extern unsigned long pci_hotplug_bus_size; 379 extern unsigned long pci_cardbus_io_size; 380 extern unsigned long pci_cardbus_mem_size; 381 382 /** 383 * pci_match_one_device - Tell if a PCI device structure has a matching 384 * PCI device id structure 385 * @id: single PCI device id structure to match 386 * @dev: the PCI device structure to match against 387 * 388 * Returns the matching pci_device_id structure or %NULL if there is no match. 389 */ 390 static inline const struct pci_device_id * 391 pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev) 392 { 393 if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) && 394 (id->device == PCI_ANY_ID || id->device == dev->device) && 395 (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) && 396 (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) && 397 !((id->class ^ dev->class) & id->class_mask)) 398 return id; 399 return NULL; 400 } 401 402 /* PCI slot sysfs helper code */ 403 #define to_pci_slot(s) container_of(s, struct pci_slot, kobj) 404 405 extern struct kset *pci_slots_kset; 406 407 struct pci_slot_attribute { 408 struct attribute attr; 409 ssize_t (*show)(struct pci_slot *, char *); 410 ssize_t (*store)(struct pci_slot *, const char *, size_t); 411 }; 412 #define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr) 413 414 enum pci_bar_type { 415 pci_bar_unknown, /* Standard PCI BAR probe */ 416 pci_bar_io, /* An I/O port BAR */ 417 pci_bar_mem32, /* A 32-bit memory BAR */ 418 pci_bar_mem64, /* A 64-bit memory BAR */ 419 }; 420 421 struct device *pci_get_host_bridge_device(struct pci_dev *dev); 422 void pci_put_host_bridge_device(struct device *dev); 423 424 void pci_resize_resource_set_size(struct pci_dev *dev, int resno, int size); 425 int pci_do_resource_release_and_resize(struct pci_dev *dev, int resno, int size, 426 int exclude_bars); 427 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge); 428 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align); 429 430 int pci_configure_extended_tags(struct pci_dev *dev, void *ign); 431 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl, 432 int rrs_timeout); 433 bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl, 434 int rrs_timeout); 435 int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *pl, int rrs_timeout); 436 437 int pci_setup_device(struct pci_dev *dev); 438 void __pci_size_stdbars(struct pci_dev *dev, int count, 439 unsigned int pos, u32 *sizes); 440 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, 441 struct resource *res, unsigned int reg, u32 *sizes); 442 void pci_configure_ari(struct pci_dev *dev); 443 void __pci_bus_size_bridges(struct pci_bus *bus, 444 struct list_head *realloc_head); 445 void __pci_bus_assign_resources(const struct pci_bus *bus, 446 struct list_head *realloc_head, 447 struct list_head *fail_head); 448 bool pci_bus_clip_resource(struct pci_dev *dev, int idx); 449 void pci_walk_bus_locked(struct pci_bus *top, 450 int (*cb)(struct pci_dev *, void *), 451 void *userdata); 452 453 const char *pci_resource_name(struct pci_dev *dev, unsigned int i); 454 bool pci_resource_is_optional(const struct pci_dev *dev, int resno); 455 456 /** 457 * pci_resource_num - Reverse lookup resource number from device resources 458 * @dev: PCI device 459 * @res: Resource to lookup index for (MUST be a @dev's resource) 460 * 461 * Perform reverse lookup to determine the resource number for @res within 462 * @dev resource array. NOTE: The caller is responsible for ensuring @res is 463 * among @dev's resources! 464 * 465 * Returns: resource number. 466 */ 467 static inline int pci_resource_num(const struct pci_dev *dev, 468 const struct resource *res) 469 { 470 int resno = res - &dev->resource[0]; 471 472 /* Passing a resource that is not among dev's resources? */ 473 WARN_ON_ONCE(resno >= PCI_NUM_RESOURCES); 474 475 return resno; 476 } 477 478 struct resource *pbus_select_window(struct pci_bus *bus, 479 const struct resource *res); 480 void pci_reassigndev_resource_alignment(struct pci_dev *dev); 481 void pci_disable_bridge_window(struct pci_dev *dev); 482 struct pci_bus *pci_bus_get(struct pci_bus *bus); 483 void pci_bus_put(struct pci_bus *bus); 484 485 #define PCIE_LNKCAP_SLS2SPEED(lnkcap) \ 486 ({ \ 487 u32 lnkcap_sls = (lnkcap) & PCI_EXP_LNKCAP_SLS; \ 488 \ 489 (lnkcap_sls == PCI_EXP_LNKCAP_SLS_64_0GB ? PCIE_SPEED_64_0GT : \ 490 lnkcap_sls == PCI_EXP_LNKCAP_SLS_32_0GB ? PCIE_SPEED_32_0GT : \ 491 lnkcap_sls == PCI_EXP_LNKCAP_SLS_16_0GB ? PCIE_SPEED_16_0GT : \ 492 lnkcap_sls == PCI_EXP_LNKCAP_SLS_8_0GB ? PCIE_SPEED_8_0GT : \ 493 lnkcap_sls == PCI_EXP_LNKCAP_SLS_5_0GB ? PCIE_SPEED_5_0GT : \ 494 lnkcap_sls == PCI_EXP_LNKCAP_SLS_2_5GB ? PCIE_SPEED_2_5GT : \ 495 PCI_SPEED_UNKNOWN); \ 496 }) 497 498 /* PCIe link information from Link Capabilities 2 */ 499 #define PCIE_LNKCAP2_SLS2SPEED(lnkcap2) \ 500 ((lnkcap2) & PCI_EXP_LNKCAP2_SLS_64_0GB ? PCIE_SPEED_64_0GT : \ 501 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_32_0GB ? PCIE_SPEED_32_0GT : \ 502 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_16_0GB ? PCIE_SPEED_16_0GT : \ 503 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_8_0GB ? PCIE_SPEED_8_0GT : \ 504 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_5_0GB ? PCIE_SPEED_5_0GT : \ 505 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_2_5GB ? PCIE_SPEED_2_5GT : \ 506 PCI_SPEED_UNKNOWN) 507 508 #define PCIE_LNKCTL2_TLS2SPEED(lnkctl2) \ 509 ({ \ 510 u16 lnkctl2_tls = (lnkctl2) & PCI_EXP_LNKCTL2_TLS; \ 511 \ 512 (lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_64_0GT ? PCIE_SPEED_64_0GT : \ 513 lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_32_0GT ? PCIE_SPEED_32_0GT : \ 514 lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_16_0GT ? PCIE_SPEED_16_0GT : \ 515 lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_8_0GT ? PCIE_SPEED_8_0GT : \ 516 lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_5_0GT ? PCIE_SPEED_5_0GT : \ 517 lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_2_5GT ? PCIE_SPEED_2_5GT : \ 518 PCI_SPEED_UNKNOWN); \ 519 }) 520 521 /* PCIe speed to Mb/s reduced by encoding overhead */ 522 #define PCIE_SPEED2MBS_ENC(speed) \ 523 ((speed) == PCIE_SPEED_64_0GT ? 64000*1/1 : \ 524 (speed) == PCIE_SPEED_32_0GT ? 32000*128/130 : \ 525 (speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \ 526 (speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \ 527 (speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \ 528 (speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \ 529 0) 530 531 static inline int pcie_dev_speed_mbps(enum pci_bus_speed speed) 532 { 533 switch (speed) { 534 case PCIE_SPEED_2_5GT: 535 return 2500; 536 case PCIE_SPEED_5_0GT: 537 return 5000; 538 case PCIE_SPEED_8_0GT: 539 return 8000; 540 case PCIE_SPEED_16_0GT: 541 return 16000; 542 case PCIE_SPEED_32_0GT: 543 return 32000; 544 case PCIE_SPEED_64_0GT: 545 return 64000; 546 default: 547 break; 548 } 549 550 return -EINVAL; 551 } 552 553 u8 pcie_get_supported_speeds(struct pci_dev *dev); 554 const char *pci_speed_string(enum pci_bus_speed speed); 555 void __pcie_print_link_status(struct pci_dev *dev, bool verbose); 556 void pcie_report_downtraining(struct pci_dev *dev); 557 558 static inline void __pcie_update_link_speed(struct pci_bus *bus, u16 linksta, u16 linksta2) 559 { 560 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS]; 561 bus->flit_mode = (linksta2 & PCI_EXP_LNKSTA2_FLIT) ? 1 : 0; 562 } 563 void pcie_update_link_speed(struct pci_bus *bus); 564 565 /* Single Root I/O Virtualization */ 566 struct pci_sriov { 567 int pos; /* Capability position */ 568 int nres; /* Number of resources */ 569 u32 cap; /* SR-IOV Capabilities */ 570 u16 ctrl; /* SR-IOV Control */ 571 u16 total_VFs; /* Total VFs associated with the PF */ 572 u16 initial_VFs; /* Initial VFs associated with the PF */ 573 u16 num_VFs; /* Number of VFs available */ 574 u16 offset; /* First VF Routing ID offset */ 575 u16 stride; /* Following VF stride */ 576 u16 vf_device; /* VF device ID */ 577 u32 pgsz; /* Page size for BAR alignment */ 578 u8 link; /* Function Dependency Link */ 579 u8 max_VF_buses; /* Max buses consumed by VFs */ 580 u16 driver_max_VFs; /* Max num VFs driver supports */ 581 struct pci_dev *dev; /* Lowest numbered PF */ 582 struct pci_dev *self; /* This PF */ 583 u32 class; /* VF device */ 584 u8 hdr_type; /* VF header type */ 585 u16 subsystem_vendor; /* VF subsystem vendor */ 586 u16 subsystem_device; /* VF subsystem device */ 587 resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */ 588 u16 vf_rebar_cap; /* VF Resizable BAR capability offset */ 589 bool drivers_autoprobe; /* Auto probing of VFs by driver */ 590 }; 591 592 #ifdef CONFIG_PCI_DOE 593 void pci_doe_init(struct pci_dev *pdev); 594 void pci_doe_destroy(struct pci_dev *pdev); 595 void pci_doe_disconnected(struct pci_dev *pdev); 596 #else 597 static inline void pci_doe_init(struct pci_dev *pdev) { } 598 static inline void pci_doe_destroy(struct pci_dev *pdev) { } 599 static inline void pci_doe_disconnected(struct pci_dev *pdev) { } 600 #endif 601 602 #ifdef CONFIG_PCI_NPEM 603 void pci_npem_create(struct pci_dev *dev); 604 void pci_npem_remove(struct pci_dev *dev); 605 #else 606 static inline void pci_npem_create(struct pci_dev *dev) { } 607 static inline void pci_npem_remove(struct pci_dev *dev) { } 608 #endif 609 610 #if defined(CONFIG_PCI_DOE) && defined(CONFIG_SYSFS) 611 void pci_doe_sysfs_init(struct pci_dev *pci_dev); 612 void pci_doe_sysfs_teardown(struct pci_dev *pdev); 613 #else 614 static inline void pci_doe_sysfs_init(struct pci_dev *pdev) { } 615 static inline void pci_doe_sysfs_teardown(struct pci_dev *pdev) { } 616 #endif 617 618 #ifdef CONFIG_PCI_IDE 619 void pci_ide_init(struct pci_dev *dev); 620 void pci_ide_init_host_bridge(struct pci_host_bridge *hb); 621 void pci_ide_destroy(struct pci_dev *dev); 622 extern const struct attribute_group pci_ide_attr_group; 623 #else 624 static inline void pci_ide_init(struct pci_dev *dev) { } 625 static inline void pci_ide_init_host_bridge(struct pci_host_bridge *hb) { } 626 static inline void pci_ide_destroy(struct pci_dev *dev) { } 627 #endif 628 629 #ifdef CONFIG_PCI_TSM 630 void pci_tsm_init(struct pci_dev *pdev); 631 void pci_tsm_destroy(struct pci_dev *pdev); 632 extern const struct attribute_group pci_tsm_attr_group; 633 extern const struct attribute_group pci_tsm_auth_attr_group; 634 #else 635 static inline void pci_tsm_init(struct pci_dev *pdev) { } 636 static inline void pci_tsm_destroy(struct pci_dev *pdev) { } 637 #endif 638 639 /** 640 * pci_dev_set_io_state - Set the new error state if possible. 641 * 642 * @dev: PCI device to set new error_state 643 * @new: the state we want dev to be in 644 * 645 * If the device is experiencing perm_failure, it has to remain in that state. 646 * Any other transition is allowed. 647 * 648 * Returns true if state has been changed to the requested state. 649 */ 650 static inline bool pci_dev_set_io_state(struct pci_dev *dev, 651 pci_channel_state_t new) 652 { 653 pci_channel_state_t old; 654 655 switch (new) { 656 case pci_channel_io_perm_failure: 657 xchg(&dev->error_state, pci_channel_io_perm_failure); 658 return true; 659 case pci_channel_io_frozen: 660 old = cmpxchg(&dev->error_state, pci_channel_io_normal, 661 pci_channel_io_frozen); 662 return old != pci_channel_io_perm_failure; 663 case pci_channel_io_normal: 664 old = cmpxchg(&dev->error_state, pci_channel_io_frozen, 665 pci_channel_io_normal); 666 return old != pci_channel_io_perm_failure; 667 default: 668 return false; 669 } 670 } 671 672 static inline int pci_dev_set_disconnected(struct pci_dev *dev, void *unused) 673 { 674 pci_dev_set_io_state(dev, pci_channel_io_perm_failure); 675 pci_doe_disconnected(dev); 676 677 return 0; 678 } 679 680 /* pci_dev priv_flags */ 681 #define PCI_DEV_ADDED 0 682 #define PCI_DPC_RECOVERED 1 683 #define PCI_DPC_RECOVERING 2 684 #define PCI_DEV_REMOVED 3 685 #define PCI_LINK_CHANGED 4 686 #define PCI_LINK_CHANGING 5 687 #define PCI_LINK_LBMS_SEEN 6 688 #define PCI_DEV_ALLOW_BINDING 7 689 690 static inline void pci_dev_assign_added(struct pci_dev *dev) 691 { 692 smp_mb__before_atomic(); 693 set_bit(PCI_DEV_ADDED, &dev->priv_flags); 694 smp_mb__after_atomic(); 695 } 696 697 static inline bool pci_dev_test_and_clear_added(struct pci_dev *dev) 698 { 699 return test_and_clear_bit(PCI_DEV_ADDED, &dev->priv_flags); 700 } 701 702 static inline bool pci_dev_is_added(const struct pci_dev *dev) 703 { 704 return test_bit(PCI_DEV_ADDED, &dev->priv_flags); 705 } 706 707 static inline bool pci_dev_test_and_set_removed(struct pci_dev *dev) 708 { 709 return test_and_set_bit(PCI_DEV_REMOVED, &dev->priv_flags); 710 } 711 712 static inline void pci_dev_allow_binding(struct pci_dev *dev) 713 { 714 set_bit(PCI_DEV_ALLOW_BINDING, &dev->priv_flags); 715 } 716 717 static inline bool pci_dev_binding_disallowed(struct pci_dev *dev) 718 { 719 return !test_bit(PCI_DEV_ALLOW_BINDING, &dev->priv_flags); 720 } 721 722 #ifdef CONFIG_PCIEAER 723 #include <linux/aer.h> 724 725 #define AER_MAX_MULTI_ERR_DEVICES 5 /* Not likely to have more */ 726 727 struct aer_err_info { 728 struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES]; 729 int ratelimit_print[AER_MAX_MULTI_ERR_DEVICES]; 730 int error_dev_num; 731 const char *level; /* printk level */ 732 733 unsigned int id:16; 734 735 unsigned int severity:2; /* 0:NONFATAL | 1:FATAL | 2:COR */ 736 unsigned int root_ratelimit_print:1; /* 0=skip, 1=print */ 737 unsigned int __pad1:4; 738 unsigned int multi_error_valid:1; 739 740 unsigned int first_error:5; 741 unsigned int __pad2:2; 742 unsigned int tlp_header_valid:1; 743 744 unsigned int status; /* COR/UNCOR Error Status */ 745 unsigned int mask; /* COR/UNCOR Error Mask */ 746 struct pcie_tlp_log tlp; /* TLP Header */ 747 }; 748 749 int aer_get_device_error_info(struct aer_err_info *info, int i); 750 void aer_print_error(struct aer_err_info *info, int i); 751 752 int pcie_read_tlp_log(struct pci_dev *dev, int where, int where2, 753 unsigned int tlp_len, bool flit, 754 struct pcie_tlp_log *log); 755 unsigned int aer_tlp_log_len(struct pci_dev *dev, u32 aercc); 756 void pcie_print_tlp_log(const struct pci_dev *dev, 757 const struct pcie_tlp_log *log, const char *level, 758 const char *pfx); 759 #endif /* CONFIG_PCIEAER */ 760 761 #ifdef CONFIG_PCIEPORTBUS 762 /* Cached RCEC Endpoint Association */ 763 struct rcec_ea { 764 u8 nextbusn; 765 u8 lastbusn; 766 u32 bitmap; 767 }; 768 #endif 769 770 #ifdef CONFIG_PCIE_DPC 771 void pci_save_dpc_state(struct pci_dev *dev); 772 void pci_restore_dpc_state(struct pci_dev *dev); 773 void pci_dpc_init(struct pci_dev *pdev); 774 void dpc_process_error(struct pci_dev *pdev); 775 pci_ers_result_t dpc_reset_link(struct pci_dev *pdev); 776 bool pci_dpc_recovered(struct pci_dev *pdev); 777 unsigned int dpc_tlp_log_len(struct pci_dev *dev); 778 #else 779 static inline void pci_save_dpc_state(struct pci_dev *dev) { } 780 static inline void pci_restore_dpc_state(struct pci_dev *dev) { } 781 static inline void pci_dpc_init(struct pci_dev *pdev) { } 782 static inline bool pci_dpc_recovered(struct pci_dev *pdev) { return false; } 783 #endif 784 785 #ifdef CONFIG_PCIEPORTBUS 786 void pci_rcec_init(struct pci_dev *dev); 787 void pci_rcec_exit(struct pci_dev *dev); 788 void pcie_link_rcec(struct pci_dev *rcec); 789 void pcie_walk_rcec(struct pci_dev *rcec, 790 int (*cb)(struct pci_dev *, void *), 791 void *userdata); 792 #else 793 static inline void pci_rcec_init(struct pci_dev *dev) { } 794 static inline void pci_rcec_exit(struct pci_dev *dev) { } 795 static inline void pcie_link_rcec(struct pci_dev *rcec) { } 796 static inline void pcie_walk_rcec(struct pci_dev *rcec, 797 int (*cb)(struct pci_dev *, void *), 798 void *userdata) { } 799 #endif 800 801 #ifdef CONFIG_PCI_ATS 802 /* Address Translation Service */ 803 void pci_ats_init(struct pci_dev *dev); 804 void pci_restore_ats_state(struct pci_dev *dev); 805 #else 806 static inline void pci_ats_init(struct pci_dev *d) { } 807 static inline void pci_restore_ats_state(struct pci_dev *dev) { } 808 #endif /* CONFIG_PCI_ATS */ 809 810 #ifdef CONFIG_PCI_PRI 811 void pci_pri_init(struct pci_dev *dev); 812 void pci_restore_pri_state(struct pci_dev *pdev); 813 #else 814 static inline void pci_pri_init(struct pci_dev *dev) { } 815 static inline void pci_restore_pri_state(struct pci_dev *pdev) { } 816 #endif 817 818 #ifdef CONFIG_PCI_PASID 819 void pci_pasid_init(struct pci_dev *dev); 820 void pci_restore_pasid_state(struct pci_dev *pdev); 821 #else 822 static inline void pci_pasid_init(struct pci_dev *dev) { } 823 static inline void pci_restore_pasid_state(struct pci_dev *pdev) { } 824 #endif 825 826 #ifdef CONFIG_PCI_IOV 827 int pci_iov_init(struct pci_dev *dev); 828 void pci_iov_release(struct pci_dev *dev); 829 void pci_iov_remove(struct pci_dev *dev); 830 void pci_iov_update_resource(struct pci_dev *dev, int resno); 831 resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno); 832 void pci_restore_iov_state(struct pci_dev *dev); 833 int pci_iov_bus_range(struct pci_bus *bus); 834 void pci_iov_resource_set_size(struct pci_dev *dev, int resno, int size); 835 bool pci_iov_is_memory_decoding_enabled(struct pci_dev *dev); 836 static inline u16 pci_iov_vf_rebar_cap(struct pci_dev *dev) 837 { 838 if (!dev->is_physfn) 839 return 0; 840 841 return dev->sriov->vf_rebar_cap; 842 } 843 static inline bool pci_resource_is_iov(int resno) 844 { 845 return resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END; 846 } 847 static inline int pci_resource_num_from_vf_bar(int resno) 848 { 849 return resno + PCI_IOV_RESOURCES; 850 } 851 static inline int pci_resource_num_to_vf_bar(int resno) 852 { 853 return resno - PCI_IOV_RESOURCES; 854 } 855 extern const struct attribute_group sriov_pf_dev_attr_group; 856 extern const struct attribute_group sriov_vf_dev_attr_group; 857 #else 858 static inline int pci_iov_init(struct pci_dev *dev) 859 { 860 return -ENODEV; 861 } 862 static inline void pci_iov_release(struct pci_dev *dev) { } 863 static inline void pci_iov_remove(struct pci_dev *dev) { } 864 static inline void pci_iov_update_resource(struct pci_dev *dev, int resno) { } 865 static inline resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, 866 int resno) 867 { 868 return 0; 869 } 870 static inline void pci_restore_iov_state(struct pci_dev *dev) { } 871 static inline int pci_iov_bus_range(struct pci_bus *bus) 872 { 873 return 0; 874 } 875 static inline void pci_iov_resource_set_size(struct pci_dev *dev, int resno, 876 int size) { } 877 static inline bool pci_iov_is_memory_decoding_enabled(struct pci_dev *dev) 878 { 879 return false; 880 } 881 static inline u16 pci_iov_vf_rebar_cap(struct pci_dev *dev) 882 { 883 return 0; 884 } 885 static inline bool pci_resource_is_iov(int resno) 886 { 887 return false; 888 } 889 static inline int pci_resource_num_from_vf_bar(int resno) 890 { 891 WARN_ON_ONCE(1); 892 return -ENODEV; 893 } 894 static inline int pci_resource_num_to_vf_bar(int resno) 895 { 896 WARN_ON_ONCE(1); 897 return -ENODEV; 898 } 899 #endif /* CONFIG_PCI_IOV */ 900 901 #ifdef CONFIG_PCIE_TPH 902 void pci_restore_tph_state(struct pci_dev *dev); 903 void pci_save_tph_state(struct pci_dev *dev); 904 void pci_no_tph(void); 905 void pci_tph_init(struct pci_dev *dev); 906 #else 907 static inline void pci_restore_tph_state(struct pci_dev *dev) { } 908 static inline void pci_save_tph_state(struct pci_dev *dev) { } 909 static inline void pci_no_tph(void) { } 910 static inline void pci_tph_init(struct pci_dev *dev) { } 911 #endif 912 913 #ifdef CONFIG_PCIE_PTM 914 void pci_ptm_init(struct pci_dev *dev); 915 void pci_save_ptm_state(struct pci_dev *dev); 916 void pci_restore_ptm_state(struct pci_dev *dev); 917 void pci_suspend_ptm(struct pci_dev *dev); 918 void pci_resume_ptm(struct pci_dev *dev); 919 #else 920 static inline void pci_ptm_init(struct pci_dev *dev) { } 921 static inline void pci_save_ptm_state(struct pci_dev *dev) { } 922 static inline void pci_restore_ptm_state(struct pci_dev *dev) { } 923 static inline void pci_suspend_ptm(struct pci_dev *dev) { } 924 static inline void pci_resume_ptm(struct pci_dev *dev) { } 925 #endif 926 927 unsigned long pci_cardbus_resource_alignment(struct resource *); 928 929 static inline resource_size_t pci_resource_alignment(struct pci_dev *dev, 930 struct resource *res) 931 { 932 int resno = pci_resource_num(dev, res); 933 934 if (pci_resource_is_iov(resno)) 935 return pci_sriov_resource_alignment(dev, resno); 936 if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS) 937 return pci_cardbus_resource_alignment(res); 938 return resource_alignment(res); 939 } 940 941 void pci_acs_init(struct pci_dev *dev); 942 #ifdef CONFIG_PCI_QUIRKS 943 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags); 944 int pci_dev_specific_enable_acs(struct pci_dev *dev); 945 int pci_dev_specific_disable_acs_redir(struct pci_dev *dev); 946 int pcie_failed_link_retrain(struct pci_dev *dev); 947 #else 948 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev, 949 u16 acs_flags) 950 { 951 return -ENOTTY; 952 } 953 static inline int pci_dev_specific_enable_acs(struct pci_dev *dev) 954 { 955 return -ENOTTY; 956 } 957 static inline int pci_dev_specific_disable_acs_redir(struct pci_dev *dev) 958 { 959 return -ENOTTY; 960 } 961 static inline int pcie_failed_link_retrain(struct pci_dev *dev) 962 { 963 return -ENOTTY; 964 } 965 #endif 966 967 /* PCI error reporting and recovery */ 968 pci_ers_result_t pcie_do_recovery(struct pci_dev *dev, 969 pci_channel_state_t state, 970 pci_ers_result_t (*reset_subordinates)(struct pci_dev *pdev)); 971 972 bool pcie_wait_for_link(struct pci_dev *pdev, bool active); 973 int pcie_retrain_link(struct pci_dev *pdev, bool use_lt); 974 975 /* ASPM-related functionality we need even without CONFIG_PCIEASPM */ 976 void pci_save_ltr_state(struct pci_dev *dev); 977 void pci_restore_ltr_state(struct pci_dev *dev); 978 void pci_configure_aspm_l1ss(struct pci_dev *dev); 979 void pci_save_aspm_l1ss_state(struct pci_dev *dev); 980 void pci_restore_aspm_l1ss_state(struct pci_dev *dev); 981 982 #ifdef CONFIG_PCIEASPM 983 void pcie_aspm_remove_cap(struct pci_dev *pdev, u32 lnkcap); 984 void pcie_aspm_init_link_state(struct pci_dev *pdev); 985 void pcie_aspm_exit_link_state(struct pci_dev *pdev); 986 void pcie_aspm_pm_state_change(struct pci_dev *pdev, bool locked); 987 void pcie_aspm_powersave_config_link(struct pci_dev *pdev); 988 void pci_configure_ltr(struct pci_dev *pdev); 989 void pci_bridge_reconfigure_ltr(struct pci_dev *pdev); 990 #else 991 static inline void pcie_aspm_remove_cap(struct pci_dev *pdev, u32 lnkcap) { } 992 static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { } 993 static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { } 994 static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev, bool locked) { } 995 static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { } 996 static inline void pci_configure_ltr(struct pci_dev *pdev) { } 997 static inline void pci_bridge_reconfigure_ltr(struct pci_dev *pdev) { } 998 #endif 999 1000 #ifdef CONFIG_PCIE_ECRC 1001 void pcie_set_ecrc_checking(struct pci_dev *dev); 1002 void pcie_ecrc_get_policy(char *str); 1003 #else 1004 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { } 1005 static inline void pcie_ecrc_get_policy(char *str) { } 1006 #endif 1007 1008 #ifdef CONFIG_PCIEPORTBUS 1009 void pcie_reset_lbms(struct pci_dev *port); 1010 #else 1011 static inline void pcie_reset_lbms(struct pci_dev *port) {} 1012 #endif 1013 1014 struct pci_dev_reset_methods { 1015 u16 vendor; 1016 u16 device; 1017 int (*reset)(struct pci_dev *dev, bool probe); 1018 }; 1019 1020 struct pci_reset_fn_method { 1021 int (*reset_fn)(struct pci_dev *pdev, bool probe); 1022 char *name; 1023 }; 1024 extern const struct pci_reset_fn_method pci_reset_fn_methods[]; 1025 1026 #ifdef CONFIG_PCI_QUIRKS 1027 int pci_dev_specific_reset(struct pci_dev *dev, bool probe); 1028 #else 1029 static inline int pci_dev_specific_reset(struct pci_dev *dev, bool probe) 1030 { 1031 return -ENOTTY; 1032 } 1033 #endif 1034 1035 #if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64) 1036 int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment, 1037 struct resource *res); 1038 #else 1039 static inline int acpi_get_rc_resources(struct device *dev, const char *hid, 1040 u16 segment, struct resource *res) 1041 { 1042 return -ENODEV; 1043 } 1044 #endif 1045 1046 void pci_rebar_init(struct pci_dev *pdev); 1047 void pci_restore_rebar_state(struct pci_dev *pdev); 1048 int pci_rebar_get_current_size(struct pci_dev *pdev, int bar); 1049 int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size); 1050 1051 struct device_node; 1052 1053 #define PCI_EQ_RESV 0xff 1054 1055 enum equalization_preset_type { 1056 EQ_PRESET_TYPE_8GTS, 1057 EQ_PRESET_TYPE_16GTS, 1058 EQ_PRESET_TYPE_32GTS, 1059 EQ_PRESET_TYPE_64GTS, 1060 EQ_PRESET_TYPE_MAX 1061 }; 1062 1063 struct pci_eq_presets { 1064 u16 eq_presets_8gts[MAX_NR_LANES]; 1065 u8 eq_presets_Ngts[EQ_PRESET_TYPE_MAX - 1][MAX_NR_LANES]; 1066 }; 1067 1068 #ifdef CONFIG_OF 1069 int of_get_pci_domain_nr(struct device_node *node); 1070 int of_pci_get_max_link_speed(struct device_node *node); 1071 u32 of_pci_get_slot_power_limit(struct device_node *node, 1072 u8 *slot_power_limit_value, 1073 u8 *slot_power_limit_scale); 1074 bool of_pci_preserve_config(struct device_node *node); 1075 int pci_set_of_node(struct pci_dev *dev); 1076 void pci_release_of_node(struct pci_dev *dev); 1077 void pci_set_bus_of_node(struct pci_bus *bus); 1078 void pci_release_bus_of_node(struct pci_bus *bus); 1079 1080 int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge); 1081 bool of_pci_supply_present(struct device_node *np); 1082 int of_pci_get_equalization_presets(struct device *dev, 1083 struct pci_eq_presets *presets, 1084 int num_lanes); 1085 #else 1086 static inline int 1087 of_get_pci_domain_nr(struct device_node *node) 1088 { 1089 return -1; 1090 } 1091 1092 static inline int 1093 of_pci_get_max_link_speed(struct device_node *node) 1094 { 1095 return -EINVAL; 1096 } 1097 1098 static inline u32 1099 of_pci_get_slot_power_limit(struct device_node *node, 1100 u8 *slot_power_limit_value, 1101 u8 *slot_power_limit_scale) 1102 { 1103 if (slot_power_limit_value) 1104 *slot_power_limit_value = 0; 1105 if (slot_power_limit_scale) 1106 *slot_power_limit_scale = 0; 1107 return 0; 1108 } 1109 1110 static inline bool of_pci_preserve_config(struct device_node *node) 1111 { 1112 return false; 1113 } 1114 1115 static inline int pci_set_of_node(struct pci_dev *dev) { return 0; } 1116 static inline void pci_release_of_node(struct pci_dev *dev) { } 1117 static inline void pci_set_bus_of_node(struct pci_bus *bus) { } 1118 static inline void pci_release_bus_of_node(struct pci_bus *bus) { } 1119 1120 static inline int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge) 1121 { 1122 return 0; 1123 } 1124 1125 static inline bool of_pci_supply_present(struct device_node *np) 1126 { 1127 return false; 1128 } 1129 1130 static inline int of_pci_get_equalization_presets(struct device *dev, 1131 struct pci_eq_presets *presets, 1132 int num_lanes) 1133 { 1134 presets->eq_presets_8gts[0] = PCI_EQ_RESV; 1135 for (int i = 0; i < EQ_PRESET_TYPE_MAX - 1; i++) 1136 presets->eq_presets_Ngts[i][0] = PCI_EQ_RESV; 1137 1138 return 0; 1139 } 1140 #endif /* CONFIG_OF */ 1141 1142 struct of_changeset; 1143 1144 #ifdef CONFIG_PCI_DYNAMIC_OF_NODES 1145 void of_pci_make_dev_node(struct pci_dev *pdev); 1146 void of_pci_remove_node(struct pci_dev *pdev); 1147 int of_pci_add_properties(struct pci_dev *pdev, struct of_changeset *ocs, 1148 struct device_node *np); 1149 void of_pci_make_host_bridge_node(struct pci_host_bridge *bridge); 1150 void of_pci_remove_host_bridge_node(struct pci_host_bridge *bridge); 1151 int of_pci_add_host_bridge_properties(struct pci_host_bridge *bridge, 1152 struct of_changeset *ocs, 1153 struct device_node *np); 1154 #else 1155 static inline void of_pci_make_dev_node(struct pci_dev *pdev) { } 1156 static inline void of_pci_remove_node(struct pci_dev *pdev) { } 1157 static inline void of_pci_make_host_bridge_node(struct pci_host_bridge *bridge) { } 1158 static inline void of_pci_remove_host_bridge_node(struct pci_host_bridge *bridge) { } 1159 #endif 1160 1161 #ifdef CONFIG_PCIEAER 1162 void pci_no_aer(void); 1163 void pci_aer_init(struct pci_dev *dev); 1164 void pci_aer_exit(struct pci_dev *dev); 1165 extern const struct attribute_group aer_stats_attr_group; 1166 extern const struct attribute_group aer_attr_group; 1167 void pci_aer_clear_fatal_status(struct pci_dev *dev); 1168 int pci_aer_clear_status(struct pci_dev *dev); 1169 int pci_aer_raw_clear_status(struct pci_dev *dev); 1170 void pci_save_aer_state(struct pci_dev *dev); 1171 void pci_restore_aer_state(struct pci_dev *dev); 1172 #else 1173 static inline void pci_no_aer(void) { } 1174 static inline void pci_aer_init(struct pci_dev *d) { } 1175 static inline void pci_aer_exit(struct pci_dev *d) { } 1176 static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { } 1177 static inline int pci_aer_clear_status(struct pci_dev *dev) { return -EINVAL; } 1178 static inline int pci_aer_raw_clear_status(struct pci_dev *dev) { return -EINVAL; } 1179 static inline void pci_save_aer_state(struct pci_dev *dev) { } 1180 static inline void pci_restore_aer_state(struct pci_dev *dev) { } 1181 #endif 1182 1183 #ifdef CONFIG_ACPI 1184 bool pci_acpi_preserve_config(struct pci_host_bridge *bridge); 1185 int pci_acpi_program_hp_params(struct pci_dev *dev); 1186 extern const struct attribute_group pci_dev_acpi_attr_group; 1187 void pci_set_acpi_fwnode(struct pci_dev *dev); 1188 int pci_dev_acpi_reset(struct pci_dev *dev, bool probe); 1189 bool acpi_pci_power_manageable(struct pci_dev *dev); 1190 bool acpi_pci_bridge_d3(struct pci_dev *dev); 1191 int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state); 1192 pci_power_t acpi_pci_get_power_state(struct pci_dev *dev); 1193 void acpi_pci_refresh_power_state(struct pci_dev *dev); 1194 int acpi_pci_wakeup(struct pci_dev *dev, bool enable); 1195 bool acpi_pci_need_resume(struct pci_dev *dev); 1196 pci_power_t acpi_pci_choose_state(struct pci_dev *pdev); 1197 #else 1198 static inline bool pci_acpi_preserve_config(struct pci_host_bridge *bridge) 1199 { 1200 return false; 1201 } 1202 static inline int pci_dev_acpi_reset(struct pci_dev *dev, bool probe) 1203 { 1204 return -ENOTTY; 1205 } 1206 static inline void pci_set_acpi_fwnode(struct pci_dev *dev) { } 1207 static inline int pci_acpi_program_hp_params(struct pci_dev *dev) 1208 { 1209 return -ENODEV; 1210 } 1211 static inline bool acpi_pci_power_manageable(struct pci_dev *dev) 1212 { 1213 return false; 1214 } 1215 static inline bool acpi_pci_bridge_d3(struct pci_dev *dev) 1216 { 1217 return false; 1218 } 1219 static inline int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state) 1220 { 1221 return -ENODEV; 1222 } 1223 static inline pci_power_t acpi_pci_get_power_state(struct pci_dev *dev) 1224 { 1225 return PCI_UNKNOWN; 1226 } 1227 static inline void acpi_pci_refresh_power_state(struct pci_dev *dev) { } 1228 static inline int acpi_pci_wakeup(struct pci_dev *dev, bool enable) 1229 { 1230 return -ENODEV; 1231 } 1232 static inline bool acpi_pci_need_resume(struct pci_dev *dev) 1233 { 1234 return false; 1235 } 1236 static inline pci_power_t acpi_pci_choose_state(struct pci_dev *pdev) 1237 { 1238 return PCI_POWER_ERROR; 1239 } 1240 #endif 1241 1242 #ifdef CONFIG_PCIEASPM 1243 extern const struct attribute_group aspm_ctrl_attr_group; 1244 #endif 1245 1246 #ifdef CONFIG_X86_INTEL_MID 1247 bool pci_use_mid_pm(void); 1248 int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state); 1249 pci_power_t mid_pci_get_power_state(struct pci_dev *pdev); 1250 #else 1251 static inline bool pci_use_mid_pm(void) 1252 { 1253 return false; 1254 } 1255 static inline int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state) 1256 { 1257 return -ENODEV; 1258 } 1259 static inline pci_power_t mid_pci_get_power_state(struct pci_dev *pdev) 1260 { 1261 return PCI_UNKNOWN; 1262 } 1263 #endif 1264 1265 #ifdef CONFIG_PCI_MSI 1266 int pci_msix_write_tph_tag(struct pci_dev *pdev, unsigned int index, u16 tag); 1267 #else 1268 static inline int pci_msix_write_tph_tag(struct pci_dev *pdev, unsigned int index, u16 tag) 1269 { 1270 return -ENODEV; 1271 } 1272 #endif 1273 1274 /* 1275 * Config Address for PCI Configuration Mechanism #1 1276 * 1277 * See PCI Local Bus Specification, Revision 3.0, 1278 * Section 3.2.2.3.2, Figure 3-2, p. 50. 1279 */ 1280 1281 #define PCI_CONF1_BUS_SHIFT 16 /* Bus number */ 1282 #define PCI_CONF1_DEV_SHIFT 11 /* Device number */ 1283 #define PCI_CONF1_FUNC_SHIFT 8 /* Function number */ 1284 1285 #define PCI_CONF1_BUS_MASK 0xff 1286 #define PCI_CONF1_DEV_MASK 0x1f 1287 #define PCI_CONF1_FUNC_MASK 0x7 1288 #define PCI_CONF1_REG_MASK 0xfc /* Limit aligned offset to a maximum of 256B */ 1289 1290 #define PCI_CONF1_ENABLE BIT(31) 1291 #define PCI_CONF1_BUS(x) (((x) & PCI_CONF1_BUS_MASK) << PCI_CONF1_BUS_SHIFT) 1292 #define PCI_CONF1_DEV(x) (((x) & PCI_CONF1_DEV_MASK) << PCI_CONF1_DEV_SHIFT) 1293 #define PCI_CONF1_FUNC(x) (((x) & PCI_CONF1_FUNC_MASK) << PCI_CONF1_FUNC_SHIFT) 1294 #define PCI_CONF1_REG(x) ((x) & PCI_CONF1_REG_MASK) 1295 1296 #define PCI_CONF1_ADDRESS(bus, dev, func, reg) \ 1297 (PCI_CONF1_ENABLE | \ 1298 PCI_CONF1_BUS(bus) | \ 1299 PCI_CONF1_DEV(dev) | \ 1300 PCI_CONF1_FUNC(func) | \ 1301 PCI_CONF1_REG(reg)) 1302 1303 /* 1304 * Extension of PCI Config Address for accessing extended PCIe registers 1305 * 1306 * No standardized specification, but used on lot of non-ECAM-compliant ARM SoCs 1307 * or on AMD Barcelona and new CPUs. Reserved bits [27:24] of PCI Config Address 1308 * are used for specifying additional 4 high bits of PCI Express register. 1309 */ 1310 1311 #define PCI_CONF1_EXT_REG_SHIFT 16 1312 #define PCI_CONF1_EXT_REG_MASK 0xf00 1313 #define PCI_CONF1_EXT_REG(x) (((x) & PCI_CONF1_EXT_REG_MASK) << PCI_CONF1_EXT_REG_SHIFT) 1314 1315 #define PCI_CONF1_EXT_ADDRESS(bus, dev, func, reg) \ 1316 (PCI_CONF1_ADDRESS(bus, dev, func, reg) | \ 1317 PCI_CONF1_EXT_REG(reg)) 1318 1319 #endif /* DRIVERS_PCI_H */ 1320