1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef DRIVERS_PCI_H 3 #define DRIVERS_PCI_H 4 5 #include <linux/pci.h> 6 7 /* Number of possible devfns: 0.0 to 1f.7 inclusive */ 8 #define MAX_NR_DEVFNS 256 9 10 #define PCI_FIND_CAP_TTL 48 11 12 #define PCI_VSEC_ID_INTEL_TBT 0x1234 /* Thunderbolt */ 13 14 #define PCIE_LINK_RETRAIN_TIMEOUT_MS 1000 15 16 /* Power stable to PERST# inactive from PCIe card Electromechanical Spec */ 17 #define PCIE_T_PVPERL_MS 100 18 19 /* 20 * PCIe r6.0, sec 5.3.3.2.1 <PME Synchronization> 21 * Recommends 1ms to 10ms timeout to check L2 ready. 22 */ 23 #define PCIE_PME_TO_L2_TIMEOUT_US 10000 24 25 extern const unsigned char pcie_link_speed[]; 26 extern bool pci_early_dump; 27 28 bool pcie_cap_has_lnkctl(const struct pci_dev *dev); 29 bool pcie_cap_has_lnkctl2(const struct pci_dev *dev); 30 bool pcie_cap_has_rtctl(const struct pci_dev *dev); 31 32 /* Functions internal to the PCI core code */ 33 34 #ifdef CONFIG_DMI 35 extern const struct attribute_group pci_dev_smbios_attr_group; 36 #endif 37 38 enum pci_mmap_api { 39 PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */ 40 PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */ 41 }; 42 int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai, 43 enum pci_mmap_api mmap_api); 44 45 bool pci_reset_supported(struct pci_dev *dev); 46 void pci_init_reset_methods(struct pci_dev *dev); 47 int pci_bridge_secondary_bus_reset(struct pci_dev *dev); 48 int pci_bus_error_reset(struct pci_dev *dev); 49 50 struct pci_cap_saved_data { 51 u16 cap_nr; 52 bool cap_extended; 53 unsigned int size; 54 u32 data[]; 55 }; 56 57 struct pci_cap_saved_state { 58 struct hlist_node next; 59 struct pci_cap_saved_data cap; 60 }; 61 62 void pci_allocate_cap_save_buffers(struct pci_dev *dev); 63 void pci_free_cap_save_buffers(struct pci_dev *dev); 64 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size); 65 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, 66 u16 cap, unsigned int size); 67 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap); 68 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, 69 u16 cap); 70 71 #define PCI_PM_D2_DELAY 200 /* usec; see PCIe r4.0, sec 5.9.1 */ 72 #define PCI_PM_D3HOT_WAIT 10 /* msec */ 73 #define PCI_PM_D3COLD_WAIT 100 /* msec */ 74 75 void pci_update_current_state(struct pci_dev *dev, pci_power_t state); 76 void pci_refresh_power_state(struct pci_dev *dev); 77 int pci_power_up(struct pci_dev *dev); 78 void pci_disable_enabled_device(struct pci_dev *dev); 79 int pci_finish_runtime_suspend(struct pci_dev *dev); 80 void pcie_clear_device_status(struct pci_dev *dev); 81 void pcie_clear_root_pme_status(struct pci_dev *dev); 82 bool pci_check_pme_status(struct pci_dev *dev); 83 void pci_pme_wakeup_bus(struct pci_bus *bus); 84 int __pci_pme_wakeup(struct pci_dev *dev, void *ign); 85 void pci_pme_restore(struct pci_dev *dev); 86 bool pci_dev_need_resume(struct pci_dev *dev); 87 void pci_dev_adjust_pme(struct pci_dev *dev); 88 void pci_dev_complete_resume(struct pci_dev *pci_dev); 89 void pci_config_pm_runtime_get(struct pci_dev *dev); 90 void pci_config_pm_runtime_put(struct pci_dev *dev); 91 void pci_pm_init(struct pci_dev *dev); 92 void pci_ea_init(struct pci_dev *dev); 93 void pci_msi_init(struct pci_dev *dev); 94 void pci_msix_init(struct pci_dev *dev); 95 bool pci_bridge_d3_possible(struct pci_dev *dev); 96 void pci_bridge_d3_update(struct pci_dev *dev); 97 int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type); 98 99 static inline void pci_wakeup_event(struct pci_dev *dev) 100 { 101 /* Wait 100 ms before the system can be put into a sleep state. */ 102 pm_wakeup_event(&dev->dev, 100); 103 } 104 105 static inline bool pci_has_subordinate(struct pci_dev *pci_dev) 106 { 107 return !!(pci_dev->subordinate); 108 } 109 110 static inline bool pci_power_manageable(struct pci_dev *pci_dev) 111 { 112 /* 113 * Currently we allow normal PCI devices and PCI bridges transition 114 * into D3 if their bridge_d3 is set. 115 */ 116 return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3; 117 } 118 119 static inline bool pcie_downstream_port(const struct pci_dev *dev) 120 { 121 int type = pci_pcie_type(dev); 122 123 return type == PCI_EXP_TYPE_ROOT_PORT || 124 type == PCI_EXP_TYPE_DOWNSTREAM || 125 type == PCI_EXP_TYPE_PCIE_BRIDGE; 126 } 127 128 void pci_vpd_init(struct pci_dev *dev); 129 void pci_vpd_release(struct pci_dev *dev); 130 extern const struct attribute_group pci_dev_vpd_attr_group; 131 132 /* PCI Virtual Channel */ 133 int pci_save_vc_state(struct pci_dev *dev); 134 void pci_restore_vc_state(struct pci_dev *dev); 135 void pci_allocate_vc_save_buffers(struct pci_dev *dev); 136 137 /* PCI /proc functions */ 138 #ifdef CONFIG_PROC_FS 139 int pci_proc_attach_device(struct pci_dev *dev); 140 int pci_proc_detach_device(struct pci_dev *dev); 141 int pci_proc_detach_bus(struct pci_bus *bus); 142 #else 143 static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; } 144 static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; } 145 static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; } 146 #endif 147 148 /* Functions for PCI Hotplug drivers to use */ 149 int pci_hp_add_bridge(struct pci_dev *dev); 150 151 #if defined(CONFIG_SYSFS) && defined(HAVE_PCI_LEGACY) 152 void pci_create_legacy_files(struct pci_bus *bus); 153 void pci_remove_legacy_files(struct pci_bus *bus); 154 #else 155 static inline void pci_create_legacy_files(struct pci_bus *bus) { } 156 static inline void pci_remove_legacy_files(struct pci_bus *bus) { } 157 #endif 158 159 /* Lock for read/write access to pci device and bus lists */ 160 extern struct rw_semaphore pci_bus_sem; 161 extern struct mutex pci_slot_mutex; 162 163 extern raw_spinlock_t pci_lock; 164 165 extern unsigned int pci_pm_d3hot_delay; 166 167 #ifdef CONFIG_PCI_MSI 168 void pci_no_msi(void); 169 #else 170 static inline void pci_no_msi(void) { } 171 #endif 172 173 void pci_realloc_get_opt(char *); 174 175 static inline int pci_no_d1d2(struct pci_dev *dev) 176 { 177 unsigned int parent_dstates = 0; 178 179 if (dev->bus->self) 180 parent_dstates = dev->bus->self->no_d1d2; 181 return (dev->no_d1d2 || parent_dstates); 182 183 } 184 185 #ifdef CONFIG_SYSFS 186 int pci_create_sysfs_dev_files(struct pci_dev *pdev); 187 void pci_remove_sysfs_dev_files(struct pci_dev *pdev); 188 extern const struct attribute_group *pci_dev_groups[]; 189 extern const struct attribute_group *pci_dev_attr_groups[]; 190 extern const struct attribute_group *pcibus_groups[]; 191 extern const struct attribute_group *pci_bus_groups[]; 192 #else 193 static inline int pci_create_sysfs_dev_files(struct pci_dev *pdev) { return 0; } 194 static inline void pci_remove_sysfs_dev_files(struct pci_dev *pdev) { } 195 #define pci_dev_groups NULL 196 #define pci_dev_attr_groups NULL 197 #define pcibus_groups NULL 198 #define pci_bus_groups NULL 199 #endif 200 201 extern unsigned long pci_hotplug_io_size; 202 extern unsigned long pci_hotplug_mmio_size; 203 extern unsigned long pci_hotplug_mmio_pref_size; 204 extern unsigned long pci_hotplug_bus_size; 205 206 /** 207 * pci_match_one_device - Tell if a PCI device structure has a matching 208 * PCI device id structure 209 * @id: single PCI device id structure to match 210 * @dev: the PCI device structure to match against 211 * 212 * Returns the matching pci_device_id structure or %NULL if there is no match. 213 */ 214 static inline const struct pci_device_id * 215 pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev) 216 { 217 if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) && 218 (id->device == PCI_ANY_ID || id->device == dev->device) && 219 (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) && 220 (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) && 221 !((id->class ^ dev->class) & id->class_mask)) 222 return id; 223 return NULL; 224 } 225 226 /* PCI slot sysfs helper code */ 227 #define to_pci_slot(s) container_of(s, struct pci_slot, kobj) 228 229 extern struct kset *pci_slots_kset; 230 231 struct pci_slot_attribute { 232 struct attribute attr; 233 ssize_t (*show)(struct pci_slot *, char *); 234 ssize_t (*store)(struct pci_slot *, const char *, size_t); 235 }; 236 #define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr) 237 238 enum pci_bar_type { 239 pci_bar_unknown, /* Standard PCI BAR probe */ 240 pci_bar_io, /* An I/O port BAR */ 241 pci_bar_mem32, /* A 32-bit memory BAR */ 242 pci_bar_mem64, /* A 64-bit memory BAR */ 243 }; 244 245 struct device *pci_get_host_bridge_device(struct pci_dev *dev); 246 void pci_put_host_bridge_device(struct device *dev); 247 248 int pci_configure_extended_tags(struct pci_dev *dev, void *ign); 249 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl, 250 int crs_timeout); 251 bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl, 252 int crs_timeout); 253 int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *pl, int crs_timeout); 254 255 int pci_setup_device(struct pci_dev *dev); 256 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, 257 struct resource *res, unsigned int reg); 258 void pci_configure_ari(struct pci_dev *dev); 259 void __pci_bus_size_bridges(struct pci_bus *bus, 260 struct list_head *realloc_head); 261 void __pci_bus_assign_resources(const struct pci_bus *bus, 262 struct list_head *realloc_head, 263 struct list_head *fail_head); 264 bool pci_bus_clip_resource(struct pci_dev *dev, int idx); 265 266 const char *pci_resource_name(struct pci_dev *dev, unsigned int i); 267 268 void pci_reassigndev_resource_alignment(struct pci_dev *dev); 269 void pci_disable_bridge_window(struct pci_dev *dev); 270 struct pci_bus *pci_bus_get(struct pci_bus *bus); 271 void pci_bus_put(struct pci_bus *bus); 272 273 /* PCIe link information from Link Capabilities 2 */ 274 #define PCIE_LNKCAP2_SLS2SPEED(lnkcap2) \ 275 ((lnkcap2) & PCI_EXP_LNKCAP2_SLS_64_0GB ? PCIE_SPEED_64_0GT : \ 276 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_32_0GB ? PCIE_SPEED_32_0GT : \ 277 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_16_0GB ? PCIE_SPEED_16_0GT : \ 278 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_8_0GB ? PCIE_SPEED_8_0GT : \ 279 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_5_0GB ? PCIE_SPEED_5_0GT : \ 280 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_2_5GB ? PCIE_SPEED_2_5GT : \ 281 PCI_SPEED_UNKNOWN) 282 283 /* PCIe speed to Mb/s reduced by encoding overhead */ 284 #define PCIE_SPEED2MBS_ENC(speed) \ 285 ((speed) == PCIE_SPEED_64_0GT ? 64000*1/1 : \ 286 (speed) == PCIE_SPEED_32_0GT ? 32000*128/130 : \ 287 (speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \ 288 (speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \ 289 (speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \ 290 (speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \ 291 0) 292 293 const char *pci_speed_string(enum pci_bus_speed speed); 294 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev); 295 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev); 296 void __pcie_print_link_status(struct pci_dev *dev, bool verbose); 297 void pcie_report_downtraining(struct pci_dev *dev); 298 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status); 299 300 /* Single Root I/O Virtualization */ 301 struct pci_sriov { 302 int pos; /* Capability position */ 303 int nres; /* Number of resources */ 304 u32 cap; /* SR-IOV Capabilities */ 305 u16 ctrl; /* SR-IOV Control */ 306 u16 total_VFs; /* Total VFs associated with the PF */ 307 u16 initial_VFs; /* Initial VFs associated with the PF */ 308 u16 num_VFs; /* Number of VFs available */ 309 u16 offset; /* First VF Routing ID offset */ 310 u16 stride; /* Following VF stride */ 311 u16 vf_device; /* VF device ID */ 312 u32 pgsz; /* Page size for BAR alignment */ 313 u8 link; /* Function Dependency Link */ 314 u8 max_VF_buses; /* Max buses consumed by VFs */ 315 u16 driver_max_VFs; /* Max num VFs driver supports */ 316 struct pci_dev *dev; /* Lowest numbered PF */ 317 struct pci_dev *self; /* This PF */ 318 u32 class; /* VF device */ 319 u8 hdr_type; /* VF header type */ 320 u16 subsystem_vendor; /* VF subsystem vendor */ 321 u16 subsystem_device; /* VF subsystem device */ 322 resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */ 323 bool drivers_autoprobe; /* Auto probing of VFs by driver */ 324 }; 325 326 #ifdef CONFIG_PCI_DOE 327 void pci_doe_init(struct pci_dev *pdev); 328 void pci_doe_destroy(struct pci_dev *pdev); 329 void pci_doe_disconnected(struct pci_dev *pdev); 330 #else 331 static inline void pci_doe_init(struct pci_dev *pdev) { } 332 static inline void pci_doe_destroy(struct pci_dev *pdev) { } 333 static inline void pci_doe_disconnected(struct pci_dev *pdev) { } 334 #endif 335 336 /** 337 * pci_dev_set_io_state - Set the new error state if possible. 338 * 339 * @dev: PCI device to set new error_state 340 * @new: the state we want dev to be in 341 * 342 * If the device is experiencing perm_failure, it has to remain in that state. 343 * Any other transition is allowed. 344 * 345 * Returns true if state has been changed to the requested state. 346 */ 347 static inline bool pci_dev_set_io_state(struct pci_dev *dev, 348 pci_channel_state_t new) 349 { 350 pci_channel_state_t old; 351 352 switch (new) { 353 case pci_channel_io_perm_failure: 354 xchg(&dev->error_state, pci_channel_io_perm_failure); 355 return true; 356 case pci_channel_io_frozen: 357 old = cmpxchg(&dev->error_state, pci_channel_io_normal, 358 pci_channel_io_frozen); 359 return old != pci_channel_io_perm_failure; 360 case pci_channel_io_normal: 361 old = cmpxchg(&dev->error_state, pci_channel_io_frozen, 362 pci_channel_io_normal); 363 return old != pci_channel_io_perm_failure; 364 default: 365 return false; 366 } 367 } 368 369 static inline int pci_dev_set_disconnected(struct pci_dev *dev, void *unused) 370 { 371 pci_dev_set_io_state(dev, pci_channel_io_perm_failure); 372 pci_doe_disconnected(dev); 373 374 return 0; 375 } 376 377 /* pci_dev priv_flags */ 378 #define PCI_DEV_ADDED 0 379 #define PCI_DPC_RECOVERED 1 380 #define PCI_DPC_RECOVERING 2 381 382 static inline void pci_dev_assign_added(struct pci_dev *dev, bool added) 383 { 384 assign_bit(PCI_DEV_ADDED, &dev->priv_flags, added); 385 } 386 387 static inline bool pci_dev_is_added(const struct pci_dev *dev) 388 { 389 return test_bit(PCI_DEV_ADDED, &dev->priv_flags); 390 } 391 392 #ifdef CONFIG_PCIEAER 393 #include <linux/aer.h> 394 395 #define AER_MAX_MULTI_ERR_DEVICES 5 /* Not likely to have more */ 396 397 struct aer_err_info { 398 struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES]; 399 int error_dev_num; 400 401 unsigned int id:16; 402 403 unsigned int severity:2; /* 0:NONFATAL | 1:FATAL | 2:COR */ 404 unsigned int __pad1:5; 405 unsigned int multi_error_valid:1; 406 407 unsigned int first_error:5; 408 unsigned int __pad2:2; 409 unsigned int tlp_header_valid:1; 410 411 unsigned int status; /* COR/UNCOR Error Status */ 412 unsigned int mask; /* COR/UNCOR Error Mask */ 413 struct pcie_tlp_log tlp; /* TLP Header */ 414 }; 415 416 int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info); 417 void aer_print_error(struct pci_dev *dev, struct aer_err_info *info); 418 #endif /* CONFIG_PCIEAER */ 419 420 #ifdef CONFIG_PCIEPORTBUS 421 /* Cached RCEC Endpoint Association */ 422 struct rcec_ea { 423 u8 nextbusn; 424 u8 lastbusn; 425 u32 bitmap; 426 }; 427 #endif 428 429 #ifdef CONFIG_PCIE_DPC 430 void pci_save_dpc_state(struct pci_dev *dev); 431 void pci_restore_dpc_state(struct pci_dev *dev); 432 void pci_dpc_init(struct pci_dev *pdev); 433 void dpc_process_error(struct pci_dev *pdev); 434 pci_ers_result_t dpc_reset_link(struct pci_dev *pdev); 435 bool pci_dpc_recovered(struct pci_dev *pdev); 436 #else 437 static inline void pci_save_dpc_state(struct pci_dev *dev) { } 438 static inline void pci_restore_dpc_state(struct pci_dev *dev) { } 439 static inline void pci_dpc_init(struct pci_dev *pdev) { } 440 static inline bool pci_dpc_recovered(struct pci_dev *pdev) { return false; } 441 #endif 442 443 #ifdef CONFIG_PCIEPORTBUS 444 void pci_rcec_init(struct pci_dev *dev); 445 void pci_rcec_exit(struct pci_dev *dev); 446 void pcie_link_rcec(struct pci_dev *rcec); 447 void pcie_walk_rcec(struct pci_dev *rcec, 448 int (*cb)(struct pci_dev *, void *), 449 void *userdata); 450 #else 451 static inline void pci_rcec_init(struct pci_dev *dev) { } 452 static inline void pci_rcec_exit(struct pci_dev *dev) { } 453 static inline void pcie_link_rcec(struct pci_dev *rcec) { } 454 static inline void pcie_walk_rcec(struct pci_dev *rcec, 455 int (*cb)(struct pci_dev *, void *), 456 void *userdata) { } 457 #endif 458 459 #ifdef CONFIG_PCI_ATS 460 /* Address Translation Service */ 461 void pci_ats_init(struct pci_dev *dev); 462 void pci_restore_ats_state(struct pci_dev *dev); 463 #else 464 static inline void pci_ats_init(struct pci_dev *d) { } 465 static inline void pci_restore_ats_state(struct pci_dev *dev) { } 466 #endif /* CONFIG_PCI_ATS */ 467 468 #ifdef CONFIG_PCI_PRI 469 void pci_pri_init(struct pci_dev *dev); 470 void pci_restore_pri_state(struct pci_dev *pdev); 471 #else 472 static inline void pci_pri_init(struct pci_dev *dev) { } 473 static inline void pci_restore_pri_state(struct pci_dev *pdev) { } 474 #endif 475 476 #ifdef CONFIG_PCI_PASID 477 void pci_pasid_init(struct pci_dev *dev); 478 void pci_restore_pasid_state(struct pci_dev *pdev); 479 #else 480 static inline void pci_pasid_init(struct pci_dev *dev) { } 481 static inline void pci_restore_pasid_state(struct pci_dev *pdev) { } 482 #endif 483 484 #ifdef CONFIG_PCI_IOV 485 int pci_iov_init(struct pci_dev *dev); 486 void pci_iov_release(struct pci_dev *dev); 487 void pci_iov_remove(struct pci_dev *dev); 488 void pci_iov_update_resource(struct pci_dev *dev, int resno); 489 resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno); 490 void pci_restore_iov_state(struct pci_dev *dev); 491 int pci_iov_bus_range(struct pci_bus *bus); 492 extern const struct attribute_group sriov_pf_dev_attr_group; 493 extern const struct attribute_group sriov_vf_dev_attr_group; 494 #else 495 static inline int pci_iov_init(struct pci_dev *dev) 496 { 497 return -ENODEV; 498 } 499 static inline void pci_iov_release(struct pci_dev *dev) { } 500 static inline void pci_iov_remove(struct pci_dev *dev) { } 501 static inline void pci_restore_iov_state(struct pci_dev *dev) { } 502 static inline int pci_iov_bus_range(struct pci_bus *bus) 503 { 504 return 0; 505 } 506 507 #endif /* CONFIG_PCI_IOV */ 508 509 #ifdef CONFIG_PCIE_PTM 510 void pci_ptm_init(struct pci_dev *dev); 511 void pci_save_ptm_state(struct pci_dev *dev); 512 void pci_restore_ptm_state(struct pci_dev *dev); 513 void pci_suspend_ptm(struct pci_dev *dev); 514 void pci_resume_ptm(struct pci_dev *dev); 515 #else 516 static inline void pci_ptm_init(struct pci_dev *dev) { } 517 static inline void pci_save_ptm_state(struct pci_dev *dev) { } 518 static inline void pci_restore_ptm_state(struct pci_dev *dev) { } 519 static inline void pci_suspend_ptm(struct pci_dev *dev) { } 520 static inline void pci_resume_ptm(struct pci_dev *dev) { } 521 #endif 522 523 unsigned long pci_cardbus_resource_alignment(struct resource *); 524 525 static inline resource_size_t pci_resource_alignment(struct pci_dev *dev, 526 struct resource *res) 527 { 528 #ifdef CONFIG_PCI_IOV 529 int resno = res - dev->resource; 530 531 if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END) 532 return pci_sriov_resource_alignment(dev, resno); 533 #endif 534 if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS) 535 return pci_cardbus_resource_alignment(res); 536 return resource_alignment(res); 537 } 538 539 void pci_acs_init(struct pci_dev *dev); 540 #ifdef CONFIG_PCI_QUIRKS 541 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags); 542 int pci_dev_specific_enable_acs(struct pci_dev *dev); 543 int pci_dev_specific_disable_acs_redir(struct pci_dev *dev); 544 bool pcie_failed_link_retrain(struct pci_dev *dev); 545 #else 546 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev, 547 u16 acs_flags) 548 { 549 return -ENOTTY; 550 } 551 static inline int pci_dev_specific_enable_acs(struct pci_dev *dev) 552 { 553 return -ENOTTY; 554 } 555 static inline int pci_dev_specific_disable_acs_redir(struct pci_dev *dev) 556 { 557 return -ENOTTY; 558 } 559 static inline bool pcie_failed_link_retrain(struct pci_dev *dev) 560 { 561 return false; 562 } 563 #endif 564 565 /* PCI error reporting and recovery */ 566 pci_ers_result_t pcie_do_recovery(struct pci_dev *dev, 567 pci_channel_state_t state, 568 pci_ers_result_t (*reset_subordinates)(struct pci_dev *pdev)); 569 570 bool pcie_wait_for_link(struct pci_dev *pdev, bool active); 571 int pcie_retrain_link(struct pci_dev *pdev, bool use_lt); 572 573 /* ASPM-related functionality we need even without CONFIG_PCIEASPM */ 574 void pci_save_ltr_state(struct pci_dev *dev); 575 void pci_restore_ltr_state(struct pci_dev *dev); 576 void pci_configure_aspm_l1ss(struct pci_dev *dev); 577 void pci_save_aspm_l1ss_state(struct pci_dev *dev); 578 void pci_restore_aspm_l1ss_state(struct pci_dev *dev); 579 580 #ifdef CONFIG_PCIEASPM 581 void pcie_aspm_init_link_state(struct pci_dev *pdev); 582 void pcie_aspm_exit_link_state(struct pci_dev *pdev); 583 void pcie_aspm_pm_state_change(struct pci_dev *pdev, bool locked); 584 void pcie_aspm_powersave_config_link(struct pci_dev *pdev); 585 void pci_configure_ltr(struct pci_dev *pdev); 586 void pci_bridge_reconfigure_ltr(struct pci_dev *pdev); 587 #else 588 static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { } 589 static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { } 590 static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev, bool locked) { } 591 static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { } 592 static inline void pci_configure_ltr(struct pci_dev *pdev) { } 593 static inline void pci_bridge_reconfigure_ltr(struct pci_dev *pdev) { } 594 #endif 595 596 #ifdef CONFIG_PCIE_ECRC 597 void pcie_set_ecrc_checking(struct pci_dev *dev); 598 void pcie_ecrc_get_policy(char *str); 599 #else 600 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { } 601 static inline void pcie_ecrc_get_policy(char *str) { } 602 #endif 603 604 struct pci_dev_reset_methods { 605 u16 vendor; 606 u16 device; 607 int (*reset)(struct pci_dev *dev, bool probe); 608 }; 609 610 struct pci_reset_fn_method { 611 int (*reset_fn)(struct pci_dev *pdev, bool probe); 612 char *name; 613 }; 614 615 #ifdef CONFIG_PCI_QUIRKS 616 int pci_dev_specific_reset(struct pci_dev *dev, bool probe); 617 #else 618 static inline int pci_dev_specific_reset(struct pci_dev *dev, bool probe) 619 { 620 return -ENOTTY; 621 } 622 #endif 623 624 #if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64) 625 int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment, 626 struct resource *res); 627 #else 628 static inline int acpi_get_rc_resources(struct device *dev, const char *hid, 629 u16 segment, struct resource *res) 630 { 631 return -ENODEV; 632 } 633 #endif 634 635 int pci_rebar_get_current_size(struct pci_dev *pdev, int bar); 636 int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size); 637 static inline u64 pci_rebar_size_to_bytes(int size) 638 { 639 return 1ULL << (size + 20); 640 } 641 642 struct device_node; 643 644 #ifdef CONFIG_OF 645 int of_pci_parse_bus_range(struct device_node *node, struct resource *res); 646 int of_get_pci_domain_nr(struct device_node *node); 647 int of_pci_get_max_link_speed(struct device_node *node); 648 u32 of_pci_get_slot_power_limit(struct device_node *node, 649 u8 *slot_power_limit_value, 650 u8 *slot_power_limit_scale); 651 int pci_set_of_node(struct pci_dev *dev); 652 void pci_release_of_node(struct pci_dev *dev); 653 void pci_set_bus_of_node(struct pci_bus *bus); 654 void pci_release_bus_of_node(struct pci_bus *bus); 655 656 int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge); 657 658 #else 659 static inline int 660 of_pci_parse_bus_range(struct device_node *node, struct resource *res) 661 { 662 return -EINVAL; 663 } 664 665 static inline int 666 of_get_pci_domain_nr(struct device_node *node) 667 { 668 return -1; 669 } 670 671 static inline int 672 of_pci_get_max_link_speed(struct device_node *node) 673 { 674 return -EINVAL; 675 } 676 677 static inline u32 678 of_pci_get_slot_power_limit(struct device_node *node, 679 u8 *slot_power_limit_value, 680 u8 *slot_power_limit_scale) 681 { 682 if (slot_power_limit_value) 683 *slot_power_limit_value = 0; 684 if (slot_power_limit_scale) 685 *slot_power_limit_scale = 0; 686 return 0; 687 } 688 689 static inline int pci_set_of_node(struct pci_dev *dev) { return 0; } 690 static inline void pci_release_of_node(struct pci_dev *dev) { } 691 static inline void pci_set_bus_of_node(struct pci_bus *bus) { } 692 static inline void pci_release_bus_of_node(struct pci_bus *bus) { } 693 694 static inline int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge) 695 { 696 return 0; 697 } 698 699 #endif /* CONFIG_OF */ 700 701 struct of_changeset; 702 703 #ifdef CONFIG_PCI_DYNAMIC_OF_NODES 704 void of_pci_make_dev_node(struct pci_dev *pdev); 705 void of_pci_remove_node(struct pci_dev *pdev); 706 int of_pci_add_properties(struct pci_dev *pdev, struct of_changeset *ocs, 707 struct device_node *np); 708 #else 709 static inline void of_pci_make_dev_node(struct pci_dev *pdev) { } 710 static inline void of_pci_remove_node(struct pci_dev *pdev) { } 711 #endif 712 713 #ifdef CONFIG_PCIEAER 714 void pci_no_aer(void); 715 void pci_aer_init(struct pci_dev *dev); 716 void pci_aer_exit(struct pci_dev *dev); 717 extern const struct attribute_group aer_stats_attr_group; 718 void pci_aer_clear_fatal_status(struct pci_dev *dev); 719 int pci_aer_clear_status(struct pci_dev *dev); 720 int pci_aer_raw_clear_status(struct pci_dev *dev); 721 void pci_save_aer_state(struct pci_dev *dev); 722 void pci_restore_aer_state(struct pci_dev *dev); 723 #else 724 static inline void pci_no_aer(void) { } 725 static inline void pci_aer_init(struct pci_dev *d) { } 726 static inline void pci_aer_exit(struct pci_dev *d) { } 727 static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { } 728 static inline int pci_aer_clear_status(struct pci_dev *dev) { return -EINVAL; } 729 static inline int pci_aer_raw_clear_status(struct pci_dev *dev) { return -EINVAL; } 730 static inline void pci_save_aer_state(struct pci_dev *dev) { } 731 static inline void pci_restore_aer_state(struct pci_dev *dev) { } 732 #endif 733 734 #ifdef CONFIG_ACPI 735 int pci_acpi_program_hp_params(struct pci_dev *dev); 736 extern const struct attribute_group pci_dev_acpi_attr_group; 737 void pci_set_acpi_fwnode(struct pci_dev *dev); 738 int pci_dev_acpi_reset(struct pci_dev *dev, bool probe); 739 bool acpi_pci_power_manageable(struct pci_dev *dev); 740 bool acpi_pci_bridge_d3(struct pci_dev *dev); 741 int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state); 742 pci_power_t acpi_pci_get_power_state(struct pci_dev *dev); 743 void acpi_pci_refresh_power_state(struct pci_dev *dev); 744 int acpi_pci_wakeup(struct pci_dev *dev, bool enable); 745 bool acpi_pci_need_resume(struct pci_dev *dev); 746 pci_power_t acpi_pci_choose_state(struct pci_dev *pdev); 747 #else 748 static inline int pci_dev_acpi_reset(struct pci_dev *dev, bool probe) 749 { 750 return -ENOTTY; 751 } 752 static inline void pci_set_acpi_fwnode(struct pci_dev *dev) { } 753 static inline int pci_acpi_program_hp_params(struct pci_dev *dev) 754 { 755 return -ENODEV; 756 } 757 static inline bool acpi_pci_power_manageable(struct pci_dev *dev) 758 { 759 return false; 760 } 761 static inline bool acpi_pci_bridge_d3(struct pci_dev *dev) 762 { 763 return false; 764 } 765 static inline int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state) 766 { 767 return -ENODEV; 768 } 769 static inline pci_power_t acpi_pci_get_power_state(struct pci_dev *dev) 770 { 771 return PCI_UNKNOWN; 772 } 773 static inline void acpi_pci_refresh_power_state(struct pci_dev *dev) { } 774 static inline int acpi_pci_wakeup(struct pci_dev *dev, bool enable) 775 { 776 return -ENODEV; 777 } 778 static inline bool acpi_pci_need_resume(struct pci_dev *dev) 779 { 780 return false; 781 } 782 static inline pci_power_t acpi_pci_choose_state(struct pci_dev *pdev) 783 { 784 return PCI_POWER_ERROR; 785 } 786 #endif 787 788 #ifdef CONFIG_PCIEASPM 789 extern const struct attribute_group aspm_ctrl_attr_group; 790 #endif 791 792 extern const struct attribute_group pci_dev_reset_method_attr_group; 793 794 #ifdef CONFIG_X86_INTEL_MID 795 bool pci_use_mid_pm(void); 796 int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state); 797 pci_power_t mid_pci_get_power_state(struct pci_dev *pdev); 798 #else 799 static inline bool pci_use_mid_pm(void) 800 { 801 return false; 802 } 803 static inline int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state) 804 { 805 return -ENODEV; 806 } 807 static inline pci_power_t mid_pci_get_power_state(struct pci_dev *pdev) 808 { 809 return PCI_UNKNOWN; 810 } 811 #endif 812 813 /* 814 * Managed PCI resources. This manages device on/off, INTx/MSI/MSI-X 815 * on/off and BAR regions. pci_dev itself records MSI/MSI-X status, so 816 * there's no need to track it separately. pci_devres is initialized 817 * when a device is enabled using managed PCI device enable interface. 818 * 819 * TODO: Struct pci_devres and find_pci_dr() only need to be here because 820 * they're used in pci.c. Port or move these functions to devres.c and 821 * then remove them from here. 822 */ 823 struct pci_devres { 824 unsigned int enabled:1; 825 unsigned int pinned:1; 826 unsigned int orig_intx:1; 827 unsigned int restore_intx:1; 828 unsigned int mwi:1; 829 u32 region_mask; 830 }; 831 832 struct pci_devres *find_pci_dr(struct pci_dev *pdev); 833 834 /* 835 * Config Address for PCI Configuration Mechanism #1 836 * 837 * See PCI Local Bus Specification, Revision 3.0, 838 * Section 3.2.2.3.2, Figure 3-2, p. 50. 839 */ 840 841 #define PCI_CONF1_BUS_SHIFT 16 /* Bus number */ 842 #define PCI_CONF1_DEV_SHIFT 11 /* Device number */ 843 #define PCI_CONF1_FUNC_SHIFT 8 /* Function number */ 844 845 #define PCI_CONF1_BUS_MASK 0xff 846 #define PCI_CONF1_DEV_MASK 0x1f 847 #define PCI_CONF1_FUNC_MASK 0x7 848 #define PCI_CONF1_REG_MASK 0xfc /* Limit aligned offset to a maximum of 256B */ 849 850 #define PCI_CONF1_ENABLE BIT(31) 851 #define PCI_CONF1_BUS(x) (((x) & PCI_CONF1_BUS_MASK) << PCI_CONF1_BUS_SHIFT) 852 #define PCI_CONF1_DEV(x) (((x) & PCI_CONF1_DEV_MASK) << PCI_CONF1_DEV_SHIFT) 853 #define PCI_CONF1_FUNC(x) (((x) & PCI_CONF1_FUNC_MASK) << PCI_CONF1_FUNC_SHIFT) 854 #define PCI_CONF1_REG(x) ((x) & PCI_CONF1_REG_MASK) 855 856 #define PCI_CONF1_ADDRESS(bus, dev, func, reg) \ 857 (PCI_CONF1_ENABLE | \ 858 PCI_CONF1_BUS(bus) | \ 859 PCI_CONF1_DEV(dev) | \ 860 PCI_CONF1_FUNC(func) | \ 861 PCI_CONF1_REG(reg)) 862 863 /* 864 * Extension of PCI Config Address for accessing extended PCIe registers 865 * 866 * No standardized specification, but used on lot of non-ECAM-compliant ARM SoCs 867 * or on AMD Barcelona and new CPUs. Reserved bits [27:24] of PCI Config Address 868 * are used for specifying additional 4 high bits of PCI Express register. 869 */ 870 871 #define PCI_CONF1_EXT_REG_SHIFT 16 872 #define PCI_CONF1_EXT_REG_MASK 0xf00 873 #define PCI_CONF1_EXT_REG(x) (((x) & PCI_CONF1_EXT_REG_MASK) << PCI_CONF1_EXT_REG_SHIFT) 874 875 #define PCI_CONF1_EXT_ADDRESS(bus, dev, func, reg) \ 876 (PCI_CONF1_ADDRESS(bus, dev, func, reg) | \ 877 PCI_CONF1_EXT_REG(reg)) 878 879 #endif /* DRIVERS_PCI_H */ 880