1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef DRIVERS_PCI_H 3 #define DRIVERS_PCI_H 4 5 #include <linux/pci.h> 6 7 /* Number of possible devfns: 0.0 to 1f.7 inclusive */ 8 #define MAX_NR_DEVFNS 256 9 10 #define PCI_FIND_CAP_TTL 48 11 12 #define PCI_VSEC_ID_INTEL_TBT 0x1234 /* Thunderbolt */ 13 14 extern const unsigned char pcie_link_speed[]; 15 extern bool pci_early_dump; 16 17 bool pcie_cap_has_lnkctl(const struct pci_dev *dev); 18 bool pcie_cap_has_rtctl(const struct pci_dev *dev); 19 20 /* Functions internal to the PCI core code */ 21 22 int pci_create_sysfs_dev_files(struct pci_dev *pdev); 23 void pci_remove_sysfs_dev_files(struct pci_dev *pdev); 24 void pci_cleanup_rom(struct pci_dev *dev); 25 #ifdef CONFIG_DMI 26 extern const struct attribute_group pci_dev_smbios_attr_group; 27 #endif 28 29 enum pci_mmap_api { 30 PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */ 31 PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */ 32 }; 33 int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai, 34 enum pci_mmap_api mmap_api); 35 36 bool pci_reset_supported(struct pci_dev *dev); 37 void pci_init_reset_methods(struct pci_dev *dev); 38 int pci_bridge_secondary_bus_reset(struct pci_dev *dev); 39 int pci_bus_error_reset(struct pci_dev *dev); 40 41 struct pci_cap_saved_data { 42 u16 cap_nr; 43 bool cap_extended; 44 unsigned int size; 45 u32 data[]; 46 }; 47 48 struct pci_cap_saved_state { 49 struct hlist_node next; 50 struct pci_cap_saved_data cap; 51 }; 52 53 void pci_allocate_cap_save_buffers(struct pci_dev *dev); 54 void pci_free_cap_save_buffers(struct pci_dev *dev); 55 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size); 56 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, 57 u16 cap, unsigned int size); 58 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap); 59 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, 60 u16 cap); 61 62 #define PCI_PM_D2_DELAY 200 /* usec; see PCIe r4.0, sec 5.9.1 */ 63 #define PCI_PM_D3HOT_WAIT 10 /* msec */ 64 #define PCI_PM_D3COLD_WAIT 100 /* msec */ 65 66 /** 67 * struct pci_platform_pm_ops - Firmware PM callbacks 68 * 69 * @bridge_d3: Does the bridge allow entering into D3 70 * 71 * @is_manageable: returns 'true' if given device is power manageable by the 72 * platform firmware 73 * 74 * @set_state: invokes the platform firmware to set the device's power state 75 * 76 * @get_state: queries the platform firmware for a device's current power state 77 * 78 * @refresh_state: asks the platform to refresh the device's power state data 79 * 80 * @choose_state: returns PCI power state of given device preferred by the 81 * platform; to be used during system-wide transitions from a 82 * sleeping state to the working state and vice versa 83 * 84 * @set_wakeup: enables/disables wakeup capability for the device 85 * 86 * @need_resume: returns 'true' if the given device (which is currently 87 * suspended) needs to be resumed to be configured for system 88 * wakeup. 89 * 90 * If given platform is generally capable of power managing PCI devices, all of 91 * these callbacks are mandatory. 92 */ 93 struct pci_platform_pm_ops { 94 bool (*bridge_d3)(struct pci_dev *dev); 95 bool (*is_manageable)(struct pci_dev *dev); 96 int (*set_state)(struct pci_dev *dev, pci_power_t state); 97 pci_power_t (*get_state)(struct pci_dev *dev); 98 void (*refresh_state)(struct pci_dev *dev); 99 pci_power_t (*choose_state)(struct pci_dev *dev); 100 int (*set_wakeup)(struct pci_dev *dev, bool enable); 101 bool (*need_resume)(struct pci_dev *dev); 102 }; 103 104 int pci_set_platform_pm(const struct pci_platform_pm_ops *ops); 105 void pci_update_current_state(struct pci_dev *dev, pci_power_t state); 106 void pci_refresh_power_state(struct pci_dev *dev); 107 int pci_power_up(struct pci_dev *dev); 108 void pci_disable_enabled_device(struct pci_dev *dev); 109 int pci_finish_runtime_suspend(struct pci_dev *dev); 110 void pcie_clear_device_status(struct pci_dev *dev); 111 void pcie_clear_root_pme_status(struct pci_dev *dev); 112 bool pci_check_pme_status(struct pci_dev *dev); 113 void pci_pme_wakeup_bus(struct pci_bus *bus); 114 int __pci_pme_wakeup(struct pci_dev *dev, void *ign); 115 void pci_pme_restore(struct pci_dev *dev); 116 bool pci_dev_need_resume(struct pci_dev *dev); 117 void pci_dev_adjust_pme(struct pci_dev *dev); 118 void pci_dev_complete_resume(struct pci_dev *pci_dev); 119 void pci_config_pm_runtime_get(struct pci_dev *dev); 120 void pci_config_pm_runtime_put(struct pci_dev *dev); 121 void pci_pm_init(struct pci_dev *dev); 122 void pci_ea_init(struct pci_dev *dev); 123 void pci_msi_init(struct pci_dev *dev); 124 void pci_msix_init(struct pci_dev *dev); 125 bool pci_bridge_d3_possible(struct pci_dev *dev); 126 void pci_bridge_d3_update(struct pci_dev *dev); 127 void pci_bridge_wait_for_secondary_bus(struct pci_dev *dev); 128 129 static inline void pci_wakeup_event(struct pci_dev *dev) 130 { 131 /* Wait 100 ms before the system can be put into a sleep state. */ 132 pm_wakeup_event(&dev->dev, 100); 133 } 134 135 static inline bool pci_has_subordinate(struct pci_dev *pci_dev) 136 { 137 return !!(pci_dev->subordinate); 138 } 139 140 static inline bool pci_power_manageable(struct pci_dev *pci_dev) 141 { 142 /* 143 * Currently we allow normal PCI devices and PCI bridges transition 144 * into D3 if their bridge_d3 is set. 145 */ 146 return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3; 147 } 148 149 static inline bool pcie_downstream_port(const struct pci_dev *dev) 150 { 151 int type = pci_pcie_type(dev); 152 153 return type == PCI_EXP_TYPE_ROOT_PORT || 154 type == PCI_EXP_TYPE_DOWNSTREAM || 155 type == PCI_EXP_TYPE_PCIE_BRIDGE; 156 } 157 158 void pci_vpd_init(struct pci_dev *dev); 159 void pci_vpd_release(struct pci_dev *dev); 160 extern const struct attribute_group pci_dev_vpd_attr_group; 161 162 /* PCI Virtual Channel */ 163 int pci_save_vc_state(struct pci_dev *dev); 164 void pci_restore_vc_state(struct pci_dev *dev); 165 void pci_allocate_vc_save_buffers(struct pci_dev *dev); 166 167 /* PCI /proc functions */ 168 #ifdef CONFIG_PROC_FS 169 int pci_proc_attach_device(struct pci_dev *dev); 170 int pci_proc_detach_device(struct pci_dev *dev); 171 int pci_proc_detach_bus(struct pci_bus *bus); 172 #else 173 static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; } 174 static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; } 175 static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; } 176 #endif 177 178 /* Functions for PCI Hotplug drivers to use */ 179 int pci_hp_add_bridge(struct pci_dev *dev); 180 181 #ifdef HAVE_PCI_LEGACY 182 void pci_create_legacy_files(struct pci_bus *bus); 183 void pci_remove_legacy_files(struct pci_bus *bus); 184 #else 185 static inline void pci_create_legacy_files(struct pci_bus *bus) { return; } 186 static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; } 187 #endif 188 189 /* Lock for read/write access to pci device and bus lists */ 190 extern struct rw_semaphore pci_bus_sem; 191 extern struct mutex pci_slot_mutex; 192 193 extern raw_spinlock_t pci_lock; 194 195 extern unsigned int pci_pm_d3hot_delay; 196 197 #ifdef CONFIG_PCI_MSI 198 void pci_no_msi(void); 199 #else 200 static inline void pci_no_msi(void) { } 201 #endif 202 203 void pci_realloc_get_opt(char *); 204 205 static inline int pci_no_d1d2(struct pci_dev *dev) 206 { 207 unsigned int parent_dstates = 0; 208 209 if (dev->bus->self) 210 parent_dstates = dev->bus->self->no_d1d2; 211 return (dev->no_d1d2 || parent_dstates); 212 213 } 214 extern const struct attribute_group *pci_dev_groups[]; 215 extern const struct attribute_group *pcibus_groups[]; 216 extern const struct device_type pci_dev_type; 217 extern const struct attribute_group *pci_bus_groups[]; 218 219 extern unsigned long pci_hotplug_io_size; 220 extern unsigned long pci_hotplug_mmio_size; 221 extern unsigned long pci_hotplug_mmio_pref_size; 222 extern unsigned long pci_hotplug_bus_size; 223 224 /** 225 * pci_match_one_device - Tell if a PCI device structure has a matching 226 * PCI device id structure 227 * @id: single PCI device id structure to match 228 * @dev: the PCI device structure to match against 229 * 230 * Returns the matching pci_device_id structure or %NULL if there is no match. 231 */ 232 static inline const struct pci_device_id * 233 pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev) 234 { 235 if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) && 236 (id->device == PCI_ANY_ID || id->device == dev->device) && 237 (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) && 238 (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) && 239 !((id->class ^ dev->class) & id->class_mask)) 240 return id; 241 return NULL; 242 } 243 244 /* PCI slot sysfs helper code */ 245 #define to_pci_slot(s) container_of(s, struct pci_slot, kobj) 246 247 extern struct kset *pci_slots_kset; 248 249 struct pci_slot_attribute { 250 struct attribute attr; 251 ssize_t (*show)(struct pci_slot *, char *); 252 ssize_t (*store)(struct pci_slot *, const char *, size_t); 253 }; 254 #define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr) 255 256 enum pci_bar_type { 257 pci_bar_unknown, /* Standard PCI BAR probe */ 258 pci_bar_io, /* An I/O port BAR */ 259 pci_bar_mem32, /* A 32-bit memory BAR */ 260 pci_bar_mem64, /* A 64-bit memory BAR */ 261 }; 262 263 struct device *pci_get_host_bridge_device(struct pci_dev *dev); 264 void pci_put_host_bridge_device(struct device *dev); 265 266 int pci_configure_extended_tags(struct pci_dev *dev, void *ign); 267 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl, 268 int crs_timeout); 269 bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl, 270 int crs_timeout); 271 int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *pl, int crs_timeout); 272 273 int pci_setup_device(struct pci_dev *dev); 274 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, 275 struct resource *res, unsigned int reg); 276 void pci_configure_ari(struct pci_dev *dev); 277 void __pci_bus_size_bridges(struct pci_bus *bus, 278 struct list_head *realloc_head); 279 void __pci_bus_assign_resources(const struct pci_bus *bus, 280 struct list_head *realloc_head, 281 struct list_head *fail_head); 282 bool pci_bus_clip_resource(struct pci_dev *dev, int idx); 283 284 void pci_reassigndev_resource_alignment(struct pci_dev *dev); 285 void pci_disable_bridge_window(struct pci_dev *dev); 286 struct pci_bus *pci_bus_get(struct pci_bus *bus); 287 void pci_bus_put(struct pci_bus *bus); 288 289 /* PCIe link information from Link Capabilities 2 */ 290 #define PCIE_LNKCAP2_SLS2SPEED(lnkcap2) \ 291 ((lnkcap2) & PCI_EXP_LNKCAP2_SLS_64_0GB ? PCIE_SPEED_64_0GT : \ 292 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_32_0GB ? PCIE_SPEED_32_0GT : \ 293 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_16_0GB ? PCIE_SPEED_16_0GT : \ 294 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_8_0GB ? PCIE_SPEED_8_0GT : \ 295 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_5_0GB ? PCIE_SPEED_5_0GT : \ 296 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_2_5GB ? PCIE_SPEED_2_5GT : \ 297 PCI_SPEED_UNKNOWN) 298 299 /* PCIe speed to Mb/s reduced by encoding overhead */ 300 #define PCIE_SPEED2MBS_ENC(speed) \ 301 ((speed) == PCIE_SPEED_64_0GT ? 64000*128/130 : \ 302 (speed) == PCIE_SPEED_32_0GT ? 32000*128/130 : \ 303 (speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \ 304 (speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \ 305 (speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \ 306 (speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \ 307 0) 308 309 const char *pci_speed_string(enum pci_bus_speed speed); 310 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev); 311 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev); 312 u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed, 313 enum pcie_link_width *width); 314 void __pcie_print_link_status(struct pci_dev *dev, bool verbose); 315 void pcie_report_downtraining(struct pci_dev *dev); 316 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status); 317 318 /* Single Root I/O Virtualization */ 319 struct pci_sriov { 320 int pos; /* Capability position */ 321 int nres; /* Number of resources */ 322 u32 cap; /* SR-IOV Capabilities */ 323 u16 ctrl; /* SR-IOV Control */ 324 u16 total_VFs; /* Total VFs associated with the PF */ 325 u16 initial_VFs; /* Initial VFs associated with the PF */ 326 u16 num_VFs; /* Number of VFs available */ 327 u16 offset; /* First VF Routing ID offset */ 328 u16 stride; /* Following VF stride */ 329 u16 vf_device; /* VF device ID */ 330 u32 pgsz; /* Page size for BAR alignment */ 331 u8 link; /* Function Dependency Link */ 332 u8 max_VF_buses; /* Max buses consumed by VFs */ 333 u16 driver_max_VFs; /* Max num VFs driver supports */ 334 struct pci_dev *dev; /* Lowest numbered PF */ 335 struct pci_dev *self; /* This PF */ 336 u32 class; /* VF device */ 337 u8 hdr_type; /* VF header type */ 338 u16 subsystem_vendor; /* VF subsystem vendor */ 339 u16 subsystem_device; /* VF subsystem device */ 340 resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */ 341 bool drivers_autoprobe; /* Auto probing of VFs by driver */ 342 }; 343 344 /** 345 * pci_dev_set_io_state - Set the new error state if possible. 346 * 347 * @dev: PCI device to set new error_state 348 * @new: the state we want dev to be in 349 * 350 * Must be called with device_lock held. 351 * 352 * Returns true if state has been changed to the requested state. 353 */ 354 static inline bool pci_dev_set_io_state(struct pci_dev *dev, 355 pci_channel_state_t new) 356 { 357 bool changed = false; 358 359 device_lock_assert(&dev->dev); 360 switch (new) { 361 case pci_channel_io_perm_failure: 362 switch (dev->error_state) { 363 case pci_channel_io_frozen: 364 case pci_channel_io_normal: 365 case pci_channel_io_perm_failure: 366 changed = true; 367 break; 368 } 369 break; 370 case pci_channel_io_frozen: 371 switch (dev->error_state) { 372 case pci_channel_io_frozen: 373 case pci_channel_io_normal: 374 changed = true; 375 break; 376 } 377 break; 378 case pci_channel_io_normal: 379 switch (dev->error_state) { 380 case pci_channel_io_frozen: 381 case pci_channel_io_normal: 382 changed = true; 383 break; 384 } 385 break; 386 } 387 if (changed) 388 dev->error_state = new; 389 return changed; 390 } 391 392 static inline int pci_dev_set_disconnected(struct pci_dev *dev, void *unused) 393 { 394 device_lock(&dev->dev); 395 pci_dev_set_io_state(dev, pci_channel_io_perm_failure); 396 device_unlock(&dev->dev); 397 398 return 0; 399 } 400 401 static inline bool pci_dev_is_disconnected(const struct pci_dev *dev) 402 { 403 return dev->error_state == pci_channel_io_perm_failure; 404 } 405 406 /* pci_dev priv_flags */ 407 #define PCI_DEV_ADDED 0 408 #define PCI_DPC_RECOVERED 1 409 #define PCI_DPC_RECOVERING 2 410 411 static inline void pci_dev_assign_added(struct pci_dev *dev, bool added) 412 { 413 assign_bit(PCI_DEV_ADDED, &dev->priv_flags, added); 414 } 415 416 static inline bool pci_dev_is_added(const struct pci_dev *dev) 417 { 418 return test_bit(PCI_DEV_ADDED, &dev->priv_flags); 419 } 420 421 #ifdef CONFIG_PCIEAER 422 #include <linux/aer.h> 423 424 #define AER_MAX_MULTI_ERR_DEVICES 5 /* Not likely to have more */ 425 426 struct aer_err_info { 427 struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES]; 428 int error_dev_num; 429 430 unsigned int id:16; 431 432 unsigned int severity:2; /* 0:NONFATAL | 1:FATAL | 2:COR */ 433 unsigned int __pad1:5; 434 unsigned int multi_error_valid:1; 435 436 unsigned int first_error:5; 437 unsigned int __pad2:2; 438 unsigned int tlp_header_valid:1; 439 440 unsigned int status; /* COR/UNCOR Error Status */ 441 unsigned int mask; /* COR/UNCOR Error Mask */ 442 struct aer_header_log_regs tlp; /* TLP Header */ 443 }; 444 445 int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info); 446 void aer_print_error(struct pci_dev *dev, struct aer_err_info *info); 447 #endif /* CONFIG_PCIEAER */ 448 449 #ifdef CONFIG_PCIEPORTBUS 450 /* Cached RCEC Endpoint Association */ 451 struct rcec_ea { 452 u8 nextbusn; 453 u8 lastbusn; 454 u32 bitmap; 455 }; 456 #endif 457 458 #ifdef CONFIG_PCIE_DPC 459 void pci_save_dpc_state(struct pci_dev *dev); 460 void pci_restore_dpc_state(struct pci_dev *dev); 461 void pci_dpc_init(struct pci_dev *pdev); 462 void dpc_process_error(struct pci_dev *pdev); 463 pci_ers_result_t dpc_reset_link(struct pci_dev *pdev); 464 bool pci_dpc_recovered(struct pci_dev *pdev); 465 #else 466 static inline void pci_save_dpc_state(struct pci_dev *dev) {} 467 static inline void pci_restore_dpc_state(struct pci_dev *dev) {} 468 static inline void pci_dpc_init(struct pci_dev *pdev) {} 469 static inline bool pci_dpc_recovered(struct pci_dev *pdev) { return false; } 470 #endif 471 472 #ifdef CONFIG_PCIEPORTBUS 473 void pci_rcec_init(struct pci_dev *dev); 474 void pci_rcec_exit(struct pci_dev *dev); 475 void pcie_link_rcec(struct pci_dev *rcec); 476 void pcie_walk_rcec(struct pci_dev *rcec, 477 int (*cb)(struct pci_dev *, void *), 478 void *userdata); 479 #else 480 static inline void pci_rcec_init(struct pci_dev *dev) {} 481 static inline void pci_rcec_exit(struct pci_dev *dev) {} 482 static inline void pcie_link_rcec(struct pci_dev *rcec) {} 483 static inline void pcie_walk_rcec(struct pci_dev *rcec, 484 int (*cb)(struct pci_dev *, void *), 485 void *userdata) {} 486 #endif 487 488 #ifdef CONFIG_PCI_ATS 489 /* Address Translation Service */ 490 void pci_ats_init(struct pci_dev *dev); 491 void pci_restore_ats_state(struct pci_dev *dev); 492 #else 493 static inline void pci_ats_init(struct pci_dev *d) { } 494 static inline void pci_restore_ats_state(struct pci_dev *dev) { } 495 #endif /* CONFIG_PCI_ATS */ 496 497 #ifdef CONFIG_PCI_PRI 498 void pci_pri_init(struct pci_dev *dev); 499 void pci_restore_pri_state(struct pci_dev *pdev); 500 #else 501 static inline void pci_pri_init(struct pci_dev *dev) { } 502 static inline void pci_restore_pri_state(struct pci_dev *pdev) { } 503 #endif 504 505 #ifdef CONFIG_PCI_PASID 506 void pci_pasid_init(struct pci_dev *dev); 507 void pci_restore_pasid_state(struct pci_dev *pdev); 508 #else 509 static inline void pci_pasid_init(struct pci_dev *dev) { } 510 static inline void pci_restore_pasid_state(struct pci_dev *pdev) { } 511 #endif 512 513 #ifdef CONFIG_PCI_IOV 514 int pci_iov_init(struct pci_dev *dev); 515 void pci_iov_release(struct pci_dev *dev); 516 void pci_iov_remove(struct pci_dev *dev); 517 void pci_iov_update_resource(struct pci_dev *dev, int resno); 518 resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno); 519 void pci_restore_iov_state(struct pci_dev *dev); 520 int pci_iov_bus_range(struct pci_bus *bus); 521 extern const struct attribute_group sriov_pf_dev_attr_group; 522 extern const struct attribute_group sriov_vf_dev_attr_group; 523 #else 524 static inline int pci_iov_init(struct pci_dev *dev) 525 { 526 return -ENODEV; 527 } 528 static inline void pci_iov_release(struct pci_dev *dev) 529 530 { 531 } 532 static inline void pci_iov_remove(struct pci_dev *dev) 533 { 534 } 535 static inline void pci_restore_iov_state(struct pci_dev *dev) 536 { 537 } 538 static inline int pci_iov_bus_range(struct pci_bus *bus) 539 { 540 return 0; 541 } 542 543 #endif /* CONFIG_PCI_IOV */ 544 545 #ifdef CONFIG_PCIE_PTM 546 void pci_save_ptm_state(struct pci_dev *dev); 547 void pci_restore_ptm_state(struct pci_dev *dev); 548 void pci_disable_ptm(struct pci_dev *dev); 549 #else 550 static inline void pci_save_ptm_state(struct pci_dev *dev) { } 551 static inline void pci_restore_ptm_state(struct pci_dev *dev) { } 552 static inline void pci_disable_ptm(struct pci_dev *dev) { } 553 #endif 554 555 unsigned long pci_cardbus_resource_alignment(struct resource *); 556 557 static inline resource_size_t pci_resource_alignment(struct pci_dev *dev, 558 struct resource *res) 559 { 560 #ifdef CONFIG_PCI_IOV 561 int resno = res - dev->resource; 562 563 if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END) 564 return pci_sriov_resource_alignment(dev, resno); 565 #endif 566 if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS) 567 return pci_cardbus_resource_alignment(res); 568 return resource_alignment(res); 569 } 570 571 void pci_acs_init(struct pci_dev *dev); 572 #ifdef CONFIG_PCI_QUIRKS 573 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags); 574 int pci_dev_specific_enable_acs(struct pci_dev *dev); 575 int pci_dev_specific_disable_acs_redir(struct pci_dev *dev); 576 #else 577 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev, 578 u16 acs_flags) 579 { 580 return -ENOTTY; 581 } 582 static inline int pci_dev_specific_enable_acs(struct pci_dev *dev) 583 { 584 return -ENOTTY; 585 } 586 static inline int pci_dev_specific_disable_acs_redir(struct pci_dev *dev) 587 { 588 return -ENOTTY; 589 } 590 #endif 591 592 /* PCI error reporting and recovery */ 593 pci_ers_result_t pcie_do_recovery(struct pci_dev *dev, 594 pci_channel_state_t state, 595 pci_ers_result_t (*reset_subordinates)(struct pci_dev *pdev)); 596 597 bool pcie_wait_for_link(struct pci_dev *pdev, bool active); 598 #ifdef CONFIG_PCIEASPM 599 void pcie_aspm_init_link_state(struct pci_dev *pdev); 600 void pcie_aspm_exit_link_state(struct pci_dev *pdev); 601 void pcie_aspm_pm_state_change(struct pci_dev *pdev); 602 void pcie_aspm_powersave_config_link(struct pci_dev *pdev); 603 #else 604 static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { } 605 static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { } 606 static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev) { } 607 static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { } 608 #endif 609 610 #ifdef CONFIG_PCIE_ECRC 611 void pcie_set_ecrc_checking(struct pci_dev *dev); 612 void pcie_ecrc_get_policy(char *str); 613 #else 614 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { } 615 static inline void pcie_ecrc_get_policy(char *str) { } 616 #endif 617 618 #ifdef CONFIG_PCIE_PTM 619 void pci_ptm_init(struct pci_dev *dev); 620 #else 621 static inline void pci_ptm_init(struct pci_dev *dev) { } 622 #endif 623 624 struct pci_dev_reset_methods { 625 u16 vendor; 626 u16 device; 627 int (*reset)(struct pci_dev *dev, bool probe); 628 }; 629 630 struct pci_reset_fn_method { 631 int (*reset_fn)(struct pci_dev *pdev, bool probe); 632 char *name; 633 }; 634 635 #ifdef CONFIG_PCI_QUIRKS 636 int pci_dev_specific_reset(struct pci_dev *dev, bool probe); 637 #else 638 static inline int pci_dev_specific_reset(struct pci_dev *dev, bool probe) 639 { 640 return -ENOTTY; 641 } 642 #endif 643 644 #if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64) 645 int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment, 646 struct resource *res); 647 #else 648 static inline int acpi_get_rc_resources(struct device *dev, const char *hid, 649 u16 segment, struct resource *res) 650 { 651 return -ENODEV; 652 } 653 #endif 654 655 int pci_rebar_get_current_size(struct pci_dev *pdev, int bar); 656 int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size); 657 static inline u64 pci_rebar_size_to_bytes(int size) 658 { 659 return 1ULL << (size + 20); 660 } 661 662 struct device_node; 663 664 #ifdef CONFIG_OF 665 int of_pci_parse_bus_range(struct device_node *node, struct resource *res); 666 int of_get_pci_domain_nr(struct device_node *node); 667 int of_pci_get_max_link_speed(struct device_node *node); 668 void pci_set_of_node(struct pci_dev *dev); 669 void pci_release_of_node(struct pci_dev *dev); 670 void pci_set_bus_of_node(struct pci_bus *bus); 671 void pci_release_bus_of_node(struct pci_bus *bus); 672 673 int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge); 674 675 #else 676 static inline int 677 of_pci_parse_bus_range(struct device_node *node, struct resource *res) 678 { 679 return -EINVAL; 680 } 681 682 static inline int 683 of_get_pci_domain_nr(struct device_node *node) 684 { 685 return -1; 686 } 687 688 static inline int 689 of_pci_get_max_link_speed(struct device_node *node) 690 { 691 return -EINVAL; 692 } 693 694 static inline void pci_set_of_node(struct pci_dev *dev) { } 695 static inline void pci_release_of_node(struct pci_dev *dev) { } 696 static inline void pci_set_bus_of_node(struct pci_bus *bus) { } 697 static inline void pci_release_bus_of_node(struct pci_bus *bus) { } 698 699 static inline int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge) 700 { 701 return 0; 702 } 703 704 #endif /* CONFIG_OF */ 705 706 #ifdef CONFIG_PCIEAER 707 void pci_no_aer(void); 708 void pci_aer_init(struct pci_dev *dev); 709 void pci_aer_exit(struct pci_dev *dev); 710 extern const struct attribute_group aer_stats_attr_group; 711 void pci_aer_clear_fatal_status(struct pci_dev *dev); 712 int pci_aer_clear_status(struct pci_dev *dev); 713 int pci_aer_raw_clear_status(struct pci_dev *dev); 714 #else 715 static inline void pci_no_aer(void) { } 716 static inline void pci_aer_init(struct pci_dev *d) { } 717 static inline void pci_aer_exit(struct pci_dev *d) { } 718 static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { } 719 static inline int pci_aer_clear_status(struct pci_dev *dev) { return -EINVAL; } 720 static inline int pci_aer_raw_clear_status(struct pci_dev *dev) { return -EINVAL; } 721 #endif 722 723 #ifdef CONFIG_ACPI 724 int pci_acpi_program_hp_params(struct pci_dev *dev); 725 extern const struct attribute_group pci_dev_acpi_attr_group; 726 void pci_set_acpi_fwnode(struct pci_dev *dev); 727 int pci_dev_acpi_reset(struct pci_dev *dev, bool probe); 728 #else 729 static inline int pci_dev_acpi_reset(struct pci_dev *dev, bool probe) 730 { 731 return -ENOTTY; 732 } 733 734 static inline void pci_set_acpi_fwnode(struct pci_dev *dev) {} 735 static inline int pci_acpi_program_hp_params(struct pci_dev *dev) 736 { 737 return -ENODEV; 738 } 739 #endif 740 741 #ifdef CONFIG_PCIEASPM 742 extern const struct attribute_group aspm_ctrl_attr_group; 743 #endif 744 745 extern const struct attribute_group pci_dev_reset_method_attr_group; 746 747 #endif /* DRIVERS_PCI_H */ 748