1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef DRIVERS_PCI_H 3 #define DRIVERS_PCI_H 4 5 #include <linux/pci.h> 6 7 struct pcie_tlp_log; 8 9 /* Number of possible devfns: 0.0 to 1f.7 inclusive */ 10 #define MAX_NR_DEVFNS 256 11 12 #define PCI_FIND_CAP_TTL 48 13 14 #define PCI_VSEC_ID_INTEL_TBT 0x1234 /* Thunderbolt */ 15 16 #define PCIE_LINK_RETRAIN_TIMEOUT_MS 1000 17 18 /* 19 * Power stable to PERST# inactive. 20 * 21 * See the "Power Sequencing and Reset Signal Timings" table of the PCI Express 22 * Card Electromechanical Specification, Revision 5.1, Section 2.9.2, Symbol 23 * "T_PVPERL". 24 */ 25 #define PCIE_T_PVPERL_MS 100 26 27 /* 28 * REFCLK stable before PERST# inactive. 29 * 30 * See the "Power Sequencing and Reset Signal Timings" table of the PCI Express 31 * Card Electromechanical Specification, Revision 5.1, Section 2.9.2, Symbol 32 * "T_PERST-CLK". 33 */ 34 #define PCIE_T_PERST_CLK_US 100 35 36 /* 37 * End of conventional reset (PERST# de-asserted) to first configuration 38 * request (device able to respond with a "Request Retry Status" completion), 39 * from PCIe r6.0, sec 6.6.1. 40 */ 41 #define PCIE_T_RRS_READY_MS 100 42 43 /* 44 * PCIe r6.0, sec 5.3.3.2.1 <PME Synchronization> 45 * Recommends 1ms to 10ms timeout to check L2 ready. 46 */ 47 #define PCIE_PME_TO_L2_TIMEOUT_US 10000 48 49 /* 50 * PCIe r6.0, sec 6.6.1 <Conventional Reset> 51 * 52 * - "With a Downstream Port that does not support Link speeds greater 53 * than 5.0 GT/s, software must wait a minimum of 100 ms following exit 54 * from a Conventional Reset before sending a Configuration Request to 55 * the device immediately below that Port." 56 * 57 * - "With a Downstream Port that supports Link speeds greater than 58 * 5.0 GT/s, software must wait a minimum of 100 ms after Link training 59 * completes before sending a Configuration Request to the device 60 * immediately below that Port." 61 */ 62 #define PCIE_RESET_CONFIG_DEVICE_WAIT_MS 100 63 64 /* Message Routing (r[2:0]); PCIe r6.0, sec 2.2.8 */ 65 #define PCIE_MSG_TYPE_R_RC 0 66 #define PCIE_MSG_TYPE_R_ADDR 1 67 #define PCIE_MSG_TYPE_R_ID 2 68 #define PCIE_MSG_TYPE_R_BC 3 69 #define PCIE_MSG_TYPE_R_LOCAL 4 70 #define PCIE_MSG_TYPE_R_GATHER 5 71 72 /* Power Management Messages; PCIe r6.0, sec 2.2.8.2 */ 73 #define PCIE_MSG_CODE_PME_TURN_OFF 0x19 74 75 /* INTx Mechanism Messages; PCIe r6.0, sec 2.2.8.1 */ 76 #define PCIE_MSG_CODE_ASSERT_INTA 0x20 77 #define PCIE_MSG_CODE_ASSERT_INTB 0x21 78 #define PCIE_MSG_CODE_ASSERT_INTC 0x22 79 #define PCIE_MSG_CODE_ASSERT_INTD 0x23 80 #define PCIE_MSG_CODE_DEASSERT_INTA 0x24 81 #define PCIE_MSG_CODE_DEASSERT_INTB 0x25 82 #define PCIE_MSG_CODE_DEASSERT_INTC 0x26 83 #define PCIE_MSG_CODE_DEASSERT_INTD 0x27 84 85 extern const unsigned char pcie_link_speed[]; 86 extern bool pci_early_dump; 87 88 bool pcie_cap_has_lnkctl(const struct pci_dev *dev); 89 bool pcie_cap_has_lnkctl2(const struct pci_dev *dev); 90 bool pcie_cap_has_rtctl(const struct pci_dev *dev); 91 92 /* Functions internal to the PCI core code */ 93 94 #ifdef CONFIG_DMI 95 extern const struct attribute_group pci_dev_smbios_attr_group; 96 #endif 97 98 enum pci_mmap_api { 99 PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */ 100 PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */ 101 }; 102 int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai, 103 enum pci_mmap_api mmap_api); 104 105 bool pci_reset_supported(struct pci_dev *dev); 106 void pci_init_reset_methods(struct pci_dev *dev); 107 int pci_bridge_secondary_bus_reset(struct pci_dev *dev); 108 int pci_bus_error_reset(struct pci_dev *dev); 109 int __pci_reset_bus(struct pci_bus *bus); 110 111 struct pci_cap_saved_data { 112 u16 cap_nr; 113 bool cap_extended; 114 unsigned int size; 115 u32 data[]; 116 }; 117 118 struct pci_cap_saved_state { 119 struct hlist_node next; 120 struct pci_cap_saved_data cap; 121 }; 122 123 void pci_allocate_cap_save_buffers(struct pci_dev *dev); 124 void pci_free_cap_save_buffers(struct pci_dev *dev); 125 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size); 126 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, 127 u16 cap, unsigned int size); 128 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap); 129 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, 130 u16 cap); 131 132 #define PCI_PM_D2_DELAY 200 /* usec; see PCIe r4.0, sec 5.9.1 */ 133 #define PCI_PM_D3HOT_WAIT 10 /* msec */ 134 #define PCI_PM_D3COLD_WAIT 100 /* msec */ 135 136 void pci_update_current_state(struct pci_dev *dev, pci_power_t state); 137 void pci_refresh_power_state(struct pci_dev *dev); 138 int pci_power_up(struct pci_dev *dev); 139 void pci_disable_enabled_device(struct pci_dev *dev); 140 int pci_finish_runtime_suspend(struct pci_dev *dev); 141 void pcie_clear_device_status(struct pci_dev *dev); 142 void pcie_clear_root_pme_status(struct pci_dev *dev); 143 bool pci_check_pme_status(struct pci_dev *dev); 144 void pci_pme_wakeup_bus(struct pci_bus *bus); 145 void pci_pme_restore(struct pci_dev *dev); 146 bool pci_dev_need_resume(struct pci_dev *dev); 147 void pci_dev_adjust_pme(struct pci_dev *dev); 148 void pci_dev_complete_resume(struct pci_dev *pci_dev); 149 void pci_config_pm_runtime_get(struct pci_dev *dev); 150 void pci_config_pm_runtime_put(struct pci_dev *dev); 151 void pci_pm_init(struct pci_dev *dev); 152 void pci_ea_init(struct pci_dev *dev); 153 void pci_msi_init(struct pci_dev *dev); 154 void pci_msix_init(struct pci_dev *dev); 155 bool pci_bridge_d3_possible(struct pci_dev *dev); 156 void pci_bridge_d3_update(struct pci_dev *dev); 157 int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type); 158 159 static inline bool pci_bus_rrs_vendor_id(u32 l) 160 { 161 return (l & 0xffff) == PCI_VENDOR_ID_PCI_SIG; 162 } 163 164 static inline void pci_wakeup_event(struct pci_dev *dev) 165 { 166 /* Wait 100 ms before the system can be put into a sleep state. */ 167 pm_wakeup_event(&dev->dev, 100); 168 } 169 170 static inline bool pci_has_subordinate(struct pci_dev *pci_dev) 171 { 172 return !!(pci_dev->subordinate); 173 } 174 175 static inline bool pci_power_manageable(struct pci_dev *pci_dev) 176 { 177 /* 178 * Currently we allow normal PCI devices and PCI bridges transition 179 * into D3 if their bridge_d3 is set. 180 */ 181 return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3; 182 } 183 184 static inline bool pcie_downstream_port(const struct pci_dev *dev) 185 { 186 int type = pci_pcie_type(dev); 187 188 return type == PCI_EXP_TYPE_ROOT_PORT || 189 type == PCI_EXP_TYPE_DOWNSTREAM || 190 type == PCI_EXP_TYPE_PCIE_BRIDGE; 191 } 192 193 void pci_vpd_init(struct pci_dev *dev); 194 extern const struct attribute_group pci_dev_vpd_attr_group; 195 196 /* PCI Virtual Channel */ 197 int pci_save_vc_state(struct pci_dev *dev); 198 void pci_restore_vc_state(struct pci_dev *dev); 199 void pci_allocate_vc_save_buffers(struct pci_dev *dev); 200 201 /* PCI /proc functions */ 202 #ifdef CONFIG_PROC_FS 203 int pci_proc_attach_device(struct pci_dev *dev); 204 int pci_proc_detach_device(struct pci_dev *dev); 205 int pci_proc_detach_bus(struct pci_bus *bus); 206 #else 207 static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; } 208 static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; } 209 static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; } 210 #endif 211 212 /* Functions for PCI Hotplug drivers to use */ 213 int pci_hp_add_bridge(struct pci_dev *dev); 214 215 #if defined(CONFIG_SYSFS) && defined(HAVE_PCI_LEGACY) 216 void pci_create_legacy_files(struct pci_bus *bus); 217 void pci_remove_legacy_files(struct pci_bus *bus); 218 #else 219 static inline void pci_create_legacy_files(struct pci_bus *bus) { } 220 static inline void pci_remove_legacy_files(struct pci_bus *bus) { } 221 #endif 222 223 /* Lock for read/write access to pci device and bus lists */ 224 extern struct rw_semaphore pci_bus_sem; 225 extern struct mutex pci_slot_mutex; 226 227 extern raw_spinlock_t pci_lock; 228 229 extern unsigned int pci_pm_d3hot_delay; 230 231 #ifdef CONFIG_PCI_MSI 232 void pci_no_msi(void); 233 #else 234 static inline void pci_no_msi(void) { } 235 #endif 236 237 void pci_realloc_get_opt(char *); 238 239 static inline int pci_no_d1d2(struct pci_dev *dev) 240 { 241 unsigned int parent_dstates = 0; 242 243 if (dev->bus->self) 244 parent_dstates = dev->bus->self->no_d1d2; 245 return (dev->no_d1d2 || parent_dstates); 246 247 } 248 249 #ifdef CONFIG_SYSFS 250 int pci_create_sysfs_dev_files(struct pci_dev *pdev); 251 void pci_remove_sysfs_dev_files(struct pci_dev *pdev); 252 extern const struct attribute_group *pci_dev_groups[]; 253 extern const struct attribute_group *pci_dev_attr_groups[]; 254 extern const struct attribute_group *pcibus_groups[]; 255 extern const struct attribute_group *pci_bus_groups[]; 256 #else 257 static inline int pci_create_sysfs_dev_files(struct pci_dev *pdev) { return 0; } 258 static inline void pci_remove_sysfs_dev_files(struct pci_dev *pdev) { } 259 #define pci_dev_groups NULL 260 #define pci_dev_attr_groups NULL 261 #define pcibus_groups NULL 262 #define pci_bus_groups NULL 263 #endif 264 265 extern unsigned long pci_hotplug_io_size; 266 extern unsigned long pci_hotplug_mmio_size; 267 extern unsigned long pci_hotplug_mmio_pref_size; 268 extern unsigned long pci_hotplug_bus_size; 269 270 /** 271 * pci_match_one_device - Tell if a PCI device structure has a matching 272 * PCI device id structure 273 * @id: single PCI device id structure to match 274 * @dev: the PCI device structure to match against 275 * 276 * Returns the matching pci_device_id structure or %NULL if there is no match. 277 */ 278 static inline const struct pci_device_id * 279 pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev) 280 { 281 if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) && 282 (id->device == PCI_ANY_ID || id->device == dev->device) && 283 (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) && 284 (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) && 285 !((id->class ^ dev->class) & id->class_mask)) 286 return id; 287 return NULL; 288 } 289 290 /* PCI slot sysfs helper code */ 291 #define to_pci_slot(s) container_of(s, struct pci_slot, kobj) 292 293 extern struct kset *pci_slots_kset; 294 295 struct pci_slot_attribute { 296 struct attribute attr; 297 ssize_t (*show)(struct pci_slot *, char *); 298 ssize_t (*store)(struct pci_slot *, const char *, size_t); 299 }; 300 #define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr) 301 302 enum pci_bar_type { 303 pci_bar_unknown, /* Standard PCI BAR probe */ 304 pci_bar_io, /* An I/O port BAR */ 305 pci_bar_mem32, /* A 32-bit memory BAR */ 306 pci_bar_mem64, /* A 64-bit memory BAR */ 307 }; 308 309 struct device *pci_get_host_bridge_device(struct pci_dev *dev); 310 void pci_put_host_bridge_device(struct device *dev); 311 312 int pci_configure_extended_tags(struct pci_dev *dev, void *ign); 313 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl, 314 int rrs_timeout); 315 bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl, 316 int rrs_timeout); 317 int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *pl, int rrs_timeout); 318 319 int pci_setup_device(struct pci_dev *dev); 320 void __pci_size_stdbars(struct pci_dev *dev, int count, 321 unsigned int pos, u32 *sizes); 322 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, 323 struct resource *res, unsigned int reg, u32 *sizes); 324 void pci_configure_ari(struct pci_dev *dev); 325 void __pci_bus_size_bridges(struct pci_bus *bus, 326 struct list_head *realloc_head); 327 void __pci_bus_assign_resources(const struct pci_bus *bus, 328 struct list_head *realloc_head, 329 struct list_head *fail_head); 330 bool pci_bus_clip_resource(struct pci_dev *dev, int idx); 331 void pci_walk_bus_locked(struct pci_bus *top, 332 int (*cb)(struct pci_dev *, void *), 333 void *userdata); 334 335 const char *pci_resource_name(struct pci_dev *dev, unsigned int i); 336 337 void pci_reassigndev_resource_alignment(struct pci_dev *dev); 338 void pci_disable_bridge_window(struct pci_dev *dev); 339 struct pci_bus *pci_bus_get(struct pci_bus *bus); 340 void pci_bus_put(struct pci_bus *bus); 341 342 #define PCIE_LNKCAP_SLS2SPEED(lnkcap) \ 343 ({ \ 344 ((lnkcap) == PCI_EXP_LNKCAP_SLS_64_0GB ? PCIE_SPEED_64_0GT : \ 345 (lnkcap) == PCI_EXP_LNKCAP_SLS_32_0GB ? PCIE_SPEED_32_0GT : \ 346 (lnkcap) == PCI_EXP_LNKCAP_SLS_16_0GB ? PCIE_SPEED_16_0GT : \ 347 (lnkcap) == PCI_EXP_LNKCAP_SLS_8_0GB ? PCIE_SPEED_8_0GT : \ 348 (lnkcap) == PCI_EXP_LNKCAP_SLS_5_0GB ? PCIE_SPEED_5_0GT : \ 349 (lnkcap) == PCI_EXP_LNKCAP_SLS_2_5GB ? PCIE_SPEED_2_5GT : \ 350 PCI_SPEED_UNKNOWN); \ 351 }) 352 353 /* PCIe link information from Link Capabilities 2 */ 354 #define PCIE_LNKCAP2_SLS2SPEED(lnkcap2) \ 355 ((lnkcap2) & PCI_EXP_LNKCAP2_SLS_64_0GB ? PCIE_SPEED_64_0GT : \ 356 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_32_0GB ? PCIE_SPEED_32_0GT : \ 357 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_16_0GB ? PCIE_SPEED_16_0GT : \ 358 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_8_0GB ? PCIE_SPEED_8_0GT : \ 359 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_5_0GB ? PCIE_SPEED_5_0GT : \ 360 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_2_5GB ? PCIE_SPEED_2_5GT : \ 361 PCI_SPEED_UNKNOWN) 362 363 #define PCIE_LNKCTL2_TLS2SPEED(lnkctl2) \ 364 ((lnkctl2) == PCI_EXP_LNKCTL2_TLS_64_0GT ? PCIE_SPEED_64_0GT : \ 365 (lnkctl2) == PCI_EXP_LNKCTL2_TLS_32_0GT ? PCIE_SPEED_32_0GT : \ 366 (lnkctl2) == PCI_EXP_LNKCTL2_TLS_16_0GT ? PCIE_SPEED_16_0GT : \ 367 (lnkctl2) == PCI_EXP_LNKCTL2_TLS_8_0GT ? PCIE_SPEED_8_0GT : \ 368 (lnkctl2) == PCI_EXP_LNKCTL2_TLS_5_0GT ? PCIE_SPEED_5_0GT : \ 369 (lnkctl2) == PCI_EXP_LNKCTL2_TLS_2_5GT ? PCIE_SPEED_2_5GT : \ 370 PCI_SPEED_UNKNOWN) 371 372 /* PCIe speed to Mb/s reduced by encoding overhead */ 373 #define PCIE_SPEED2MBS_ENC(speed) \ 374 ((speed) == PCIE_SPEED_64_0GT ? 64000*1/1 : \ 375 (speed) == PCIE_SPEED_32_0GT ? 32000*128/130 : \ 376 (speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \ 377 (speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \ 378 (speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \ 379 (speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \ 380 0) 381 382 static inline int pcie_dev_speed_mbps(enum pci_bus_speed speed) 383 { 384 switch (speed) { 385 case PCIE_SPEED_2_5GT: 386 return 2500; 387 case PCIE_SPEED_5_0GT: 388 return 5000; 389 case PCIE_SPEED_8_0GT: 390 return 8000; 391 case PCIE_SPEED_16_0GT: 392 return 16000; 393 case PCIE_SPEED_32_0GT: 394 return 32000; 395 case PCIE_SPEED_64_0GT: 396 return 64000; 397 default: 398 break; 399 } 400 401 return -EINVAL; 402 } 403 404 u8 pcie_get_supported_speeds(struct pci_dev *dev); 405 const char *pci_speed_string(enum pci_bus_speed speed); 406 void __pcie_print_link_status(struct pci_dev *dev, bool verbose); 407 void pcie_report_downtraining(struct pci_dev *dev); 408 409 static inline void __pcie_update_link_speed(struct pci_bus *bus, u16 linksta) 410 { 411 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS]; 412 } 413 void pcie_update_link_speed(struct pci_bus *bus); 414 415 /* Single Root I/O Virtualization */ 416 struct pci_sriov { 417 int pos; /* Capability position */ 418 int nres; /* Number of resources */ 419 u32 cap; /* SR-IOV Capabilities */ 420 u16 ctrl; /* SR-IOV Control */ 421 u16 total_VFs; /* Total VFs associated with the PF */ 422 u16 initial_VFs; /* Initial VFs associated with the PF */ 423 u16 num_VFs; /* Number of VFs available */ 424 u16 offset; /* First VF Routing ID offset */ 425 u16 stride; /* Following VF stride */ 426 u16 vf_device; /* VF device ID */ 427 u32 pgsz; /* Page size for BAR alignment */ 428 u8 link; /* Function Dependency Link */ 429 u8 max_VF_buses; /* Max buses consumed by VFs */ 430 u16 driver_max_VFs; /* Max num VFs driver supports */ 431 struct pci_dev *dev; /* Lowest numbered PF */ 432 struct pci_dev *self; /* This PF */ 433 u32 class; /* VF device */ 434 u8 hdr_type; /* VF header type */ 435 u16 subsystem_vendor; /* VF subsystem vendor */ 436 u16 subsystem_device; /* VF subsystem device */ 437 resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */ 438 bool drivers_autoprobe; /* Auto probing of VFs by driver */ 439 }; 440 441 #ifdef CONFIG_PCI_DOE 442 void pci_doe_init(struct pci_dev *pdev); 443 void pci_doe_destroy(struct pci_dev *pdev); 444 void pci_doe_disconnected(struct pci_dev *pdev); 445 #else 446 static inline void pci_doe_init(struct pci_dev *pdev) { } 447 static inline void pci_doe_destroy(struct pci_dev *pdev) { } 448 static inline void pci_doe_disconnected(struct pci_dev *pdev) { } 449 #endif 450 451 #ifdef CONFIG_PCI_NPEM 452 void pci_npem_create(struct pci_dev *dev); 453 void pci_npem_remove(struct pci_dev *dev); 454 #else 455 static inline void pci_npem_create(struct pci_dev *dev) { } 456 static inline void pci_npem_remove(struct pci_dev *dev) { } 457 #endif 458 459 /** 460 * pci_dev_set_io_state - Set the new error state if possible. 461 * 462 * @dev: PCI device to set new error_state 463 * @new: the state we want dev to be in 464 * 465 * If the device is experiencing perm_failure, it has to remain in that state. 466 * Any other transition is allowed. 467 * 468 * Returns true if state has been changed to the requested state. 469 */ 470 static inline bool pci_dev_set_io_state(struct pci_dev *dev, 471 pci_channel_state_t new) 472 { 473 pci_channel_state_t old; 474 475 switch (new) { 476 case pci_channel_io_perm_failure: 477 xchg(&dev->error_state, pci_channel_io_perm_failure); 478 return true; 479 case pci_channel_io_frozen: 480 old = cmpxchg(&dev->error_state, pci_channel_io_normal, 481 pci_channel_io_frozen); 482 return old != pci_channel_io_perm_failure; 483 case pci_channel_io_normal: 484 old = cmpxchg(&dev->error_state, pci_channel_io_frozen, 485 pci_channel_io_normal); 486 return old != pci_channel_io_perm_failure; 487 default: 488 return false; 489 } 490 } 491 492 static inline int pci_dev_set_disconnected(struct pci_dev *dev, void *unused) 493 { 494 pci_dev_set_io_state(dev, pci_channel_io_perm_failure); 495 pci_doe_disconnected(dev); 496 497 return 0; 498 } 499 500 /* pci_dev priv_flags */ 501 #define PCI_DEV_ADDED 0 502 #define PCI_DPC_RECOVERED 1 503 #define PCI_DPC_RECOVERING 2 504 #define PCI_DEV_REMOVED 3 505 506 static inline void pci_dev_assign_added(struct pci_dev *dev) 507 { 508 smp_mb__before_atomic(); 509 set_bit(PCI_DEV_ADDED, &dev->priv_flags); 510 smp_mb__after_atomic(); 511 } 512 513 static inline bool pci_dev_test_and_clear_added(struct pci_dev *dev) 514 { 515 return test_and_clear_bit(PCI_DEV_ADDED, &dev->priv_flags); 516 } 517 518 static inline bool pci_dev_is_added(const struct pci_dev *dev) 519 { 520 return test_bit(PCI_DEV_ADDED, &dev->priv_flags); 521 } 522 523 static inline bool pci_dev_test_and_set_removed(struct pci_dev *dev) 524 { 525 return test_and_set_bit(PCI_DEV_REMOVED, &dev->priv_flags); 526 } 527 528 #ifdef CONFIG_PCIEAER 529 #include <linux/aer.h> 530 531 #define AER_MAX_MULTI_ERR_DEVICES 5 /* Not likely to have more */ 532 533 struct aer_err_info { 534 struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES]; 535 int error_dev_num; 536 537 unsigned int id:16; 538 539 unsigned int severity:2; /* 0:NONFATAL | 1:FATAL | 2:COR */ 540 unsigned int __pad1:5; 541 unsigned int multi_error_valid:1; 542 543 unsigned int first_error:5; 544 unsigned int __pad2:2; 545 unsigned int tlp_header_valid:1; 546 547 unsigned int status; /* COR/UNCOR Error Status */ 548 unsigned int mask; /* COR/UNCOR Error Mask */ 549 struct pcie_tlp_log tlp; /* TLP Header */ 550 }; 551 552 int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info); 553 void aer_print_error(struct pci_dev *dev, struct aer_err_info *info); 554 555 int pcie_read_tlp_log(struct pci_dev *dev, int where, int where2, 556 unsigned int tlp_len, struct pcie_tlp_log *log); 557 unsigned int aer_tlp_log_len(struct pci_dev *dev, u32 aercc); 558 void pcie_print_tlp_log(const struct pci_dev *dev, 559 const struct pcie_tlp_log *log, const char *pfx); 560 #endif /* CONFIG_PCIEAER */ 561 562 #ifdef CONFIG_PCIEPORTBUS 563 /* Cached RCEC Endpoint Association */ 564 struct rcec_ea { 565 u8 nextbusn; 566 u8 lastbusn; 567 u32 bitmap; 568 }; 569 #endif 570 571 #ifdef CONFIG_PCIE_DPC 572 void pci_save_dpc_state(struct pci_dev *dev); 573 void pci_restore_dpc_state(struct pci_dev *dev); 574 void pci_dpc_init(struct pci_dev *pdev); 575 void dpc_process_error(struct pci_dev *pdev); 576 pci_ers_result_t dpc_reset_link(struct pci_dev *pdev); 577 bool pci_dpc_recovered(struct pci_dev *pdev); 578 unsigned int dpc_tlp_log_len(struct pci_dev *dev); 579 #else 580 static inline void pci_save_dpc_state(struct pci_dev *dev) { } 581 static inline void pci_restore_dpc_state(struct pci_dev *dev) { } 582 static inline void pci_dpc_init(struct pci_dev *pdev) { } 583 static inline bool pci_dpc_recovered(struct pci_dev *pdev) { return false; } 584 #endif 585 586 #ifdef CONFIG_PCIEPORTBUS 587 void pci_rcec_init(struct pci_dev *dev); 588 void pci_rcec_exit(struct pci_dev *dev); 589 void pcie_link_rcec(struct pci_dev *rcec); 590 void pcie_walk_rcec(struct pci_dev *rcec, 591 int (*cb)(struct pci_dev *, void *), 592 void *userdata); 593 #else 594 static inline void pci_rcec_init(struct pci_dev *dev) { } 595 static inline void pci_rcec_exit(struct pci_dev *dev) { } 596 static inline void pcie_link_rcec(struct pci_dev *rcec) { } 597 static inline void pcie_walk_rcec(struct pci_dev *rcec, 598 int (*cb)(struct pci_dev *, void *), 599 void *userdata) { } 600 #endif 601 602 #ifdef CONFIG_PCI_ATS 603 /* Address Translation Service */ 604 void pci_ats_init(struct pci_dev *dev); 605 void pci_restore_ats_state(struct pci_dev *dev); 606 #else 607 static inline void pci_ats_init(struct pci_dev *d) { } 608 static inline void pci_restore_ats_state(struct pci_dev *dev) { } 609 #endif /* CONFIG_PCI_ATS */ 610 611 #ifdef CONFIG_PCI_PRI 612 void pci_pri_init(struct pci_dev *dev); 613 void pci_restore_pri_state(struct pci_dev *pdev); 614 #else 615 static inline void pci_pri_init(struct pci_dev *dev) { } 616 static inline void pci_restore_pri_state(struct pci_dev *pdev) { } 617 #endif 618 619 #ifdef CONFIG_PCI_PASID 620 void pci_pasid_init(struct pci_dev *dev); 621 void pci_restore_pasid_state(struct pci_dev *pdev); 622 #else 623 static inline void pci_pasid_init(struct pci_dev *dev) { } 624 static inline void pci_restore_pasid_state(struct pci_dev *pdev) { } 625 #endif 626 627 #ifdef CONFIG_PCI_IOV 628 int pci_iov_init(struct pci_dev *dev); 629 void pci_iov_release(struct pci_dev *dev); 630 void pci_iov_remove(struct pci_dev *dev); 631 void pci_iov_update_resource(struct pci_dev *dev, int resno); 632 resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno); 633 void pci_restore_iov_state(struct pci_dev *dev); 634 int pci_iov_bus_range(struct pci_bus *bus); 635 extern const struct attribute_group sriov_pf_dev_attr_group; 636 extern const struct attribute_group sriov_vf_dev_attr_group; 637 #else 638 static inline int pci_iov_init(struct pci_dev *dev) 639 { 640 return -ENODEV; 641 } 642 static inline void pci_iov_release(struct pci_dev *dev) { } 643 static inline void pci_iov_remove(struct pci_dev *dev) { } 644 static inline void pci_restore_iov_state(struct pci_dev *dev) { } 645 static inline int pci_iov_bus_range(struct pci_bus *bus) 646 { 647 return 0; 648 } 649 650 #endif /* CONFIG_PCI_IOV */ 651 652 #ifdef CONFIG_PCIE_TPH 653 void pci_restore_tph_state(struct pci_dev *dev); 654 void pci_save_tph_state(struct pci_dev *dev); 655 void pci_no_tph(void); 656 void pci_tph_init(struct pci_dev *dev); 657 #else 658 static inline void pci_restore_tph_state(struct pci_dev *dev) { } 659 static inline void pci_save_tph_state(struct pci_dev *dev) { } 660 static inline void pci_no_tph(void) { } 661 static inline void pci_tph_init(struct pci_dev *dev) { } 662 #endif 663 664 #ifdef CONFIG_PCIE_PTM 665 void pci_ptm_init(struct pci_dev *dev); 666 void pci_save_ptm_state(struct pci_dev *dev); 667 void pci_restore_ptm_state(struct pci_dev *dev); 668 void pci_suspend_ptm(struct pci_dev *dev); 669 void pci_resume_ptm(struct pci_dev *dev); 670 #else 671 static inline void pci_ptm_init(struct pci_dev *dev) { } 672 static inline void pci_save_ptm_state(struct pci_dev *dev) { } 673 static inline void pci_restore_ptm_state(struct pci_dev *dev) { } 674 static inline void pci_suspend_ptm(struct pci_dev *dev) { } 675 static inline void pci_resume_ptm(struct pci_dev *dev) { } 676 #endif 677 678 unsigned long pci_cardbus_resource_alignment(struct resource *); 679 680 static inline resource_size_t pci_resource_alignment(struct pci_dev *dev, 681 struct resource *res) 682 { 683 #ifdef CONFIG_PCI_IOV 684 int resno = res - dev->resource; 685 686 if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END) 687 return pci_sriov_resource_alignment(dev, resno); 688 #endif 689 if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS) 690 return pci_cardbus_resource_alignment(res); 691 return resource_alignment(res); 692 } 693 694 void pci_acs_init(struct pci_dev *dev); 695 #ifdef CONFIG_PCI_QUIRKS 696 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags); 697 int pci_dev_specific_enable_acs(struct pci_dev *dev); 698 int pci_dev_specific_disable_acs_redir(struct pci_dev *dev); 699 int pcie_failed_link_retrain(struct pci_dev *dev); 700 #else 701 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev, 702 u16 acs_flags) 703 { 704 return -ENOTTY; 705 } 706 static inline int pci_dev_specific_enable_acs(struct pci_dev *dev) 707 { 708 return -ENOTTY; 709 } 710 static inline int pci_dev_specific_disable_acs_redir(struct pci_dev *dev) 711 { 712 return -ENOTTY; 713 } 714 static inline int pcie_failed_link_retrain(struct pci_dev *dev) 715 { 716 return -ENOTTY; 717 } 718 #endif 719 720 /* PCI error reporting and recovery */ 721 pci_ers_result_t pcie_do_recovery(struct pci_dev *dev, 722 pci_channel_state_t state, 723 pci_ers_result_t (*reset_subordinates)(struct pci_dev *pdev)); 724 725 bool pcie_wait_for_link(struct pci_dev *pdev, bool active); 726 int pcie_retrain_link(struct pci_dev *pdev, bool use_lt); 727 728 /* ASPM-related functionality we need even without CONFIG_PCIEASPM */ 729 void pci_save_ltr_state(struct pci_dev *dev); 730 void pci_restore_ltr_state(struct pci_dev *dev); 731 void pci_configure_aspm_l1ss(struct pci_dev *dev); 732 void pci_save_aspm_l1ss_state(struct pci_dev *dev); 733 void pci_restore_aspm_l1ss_state(struct pci_dev *dev); 734 735 #ifdef CONFIG_PCIEASPM 736 void pcie_aspm_init_link_state(struct pci_dev *pdev); 737 void pcie_aspm_exit_link_state(struct pci_dev *pdev); 738 void pcie_aspm_pm_state_change(struct pci_dev *pdev, bool locked); 739 void pcie_aspm_powersave_config_link(struct pci_dev *pdev); 740 void pci_configure_ltr(struct pci_dev *pdev); 741 void pci_bridge_reconfigure_ltr(struct pci_dev *pdev); 742 #else 743 static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { } 744 static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { } 745 static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev, bool locked) { } 746 static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { } 747 static inline void pci_configure_ltr(struct pci_dev *pdev) { } 748 static inline void pci_bridge_reconfigure_ltr(struct pci_dev *pdev) { } 749 #endif 750 751 #ifdef CONFIG_PCIE_ECRC 752 void pcie_set_ecrc_checking(struct pci_dev *dev); 753 void pcie_ecrc_get_policy(char *str); 754 #else 755 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { } 756 static inline void pcie_ecrc_get_policy(char *str) { } 757 #endif 758 759 #ifdef CONFIG_PCIEPORTBUS 760 void pcie_reset_lbms_count(struct pci_dev *port); 761 int pcie_lbms_count(struct pci_dev *port, unsigned long *val); 762 #else 763 static inline void pcie_reset_lbms_count(struct pci_dev *port) {} 764 static inline int pcie_lbms_count(struct pci_dev *port, unsigned long *val) 765 { 766 return -EOPNOTSUPP; 767 } 768 #endif 769 770 struct pci_dev_reset_methods { 771 u16 vendor; 772 u16 device; 773 int (*reset)(struct pci_dev *dev, bool probe); 774 }; 775 776 struct pci_reset_fn_method { 777 int (*reset_fn)(struct pci_dev *pdev, bool probe); 778 char *name; 779 }; 780 extern const struct pci_reset_fn_method pci_reset_fn_methods[]; 781 782 #ifdef CONFIG_PCI_QUIRKS 783 int pci_dev_specific_reset(struct pci_dev *dev, bool probe); 784 #else 785 static inline int pci_dev_specific_reset(struct pci_dev *dev, bool probe) 786 { 787 return -ENOTTY; 788 } 789 #endif 790 791 #if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64) 792 int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment, 793 struct resource *res); 794 #else 795 static inline int acpi_get_rc_resources(struct device *dev, const char *hid, 796 u16 segment, struct resource *res) 797 { 798 return -ENODEV; 799 } 800 #endif 801 802 int pci_rebar_get_current_size(struct pci_dev *pdev, int bar); 803 int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size); 804 static inline u64 pci_rebar_size_to_bytes(int size) 805 { 806 return 1ULL << (size + 20); 807 } 808 809 struct device_node; 810 811 #ifdef CONFIG_OF 812 int of_get_pci_domain_nr(struct device_node *node); 813 int of_pci_get_max_link_speed(struct device_node *node); 814 u32 of_pci_get_slot_power_limit(struct device_node *node, 815 u8 *slot_power_limit_value, 816 u8 *slot_power_limit_scale); 817 bool of_pci_preserve_config(struct device_node *node); 818 int pci_set_of_node(struct pci_dev *dev); 819 void pci_release_of_node(struct pci_dev *dev); 820 void pci_set_bus_of_node(struct pci_bus *bus); 821 void pci_release_bus_of_node(struct pci_bus *bus); 822 823 int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge); 824 bool of_pci_supply_present(struct device_node *np); 825 826 #else 827 static inline int 828 of_get_pci_domain_nr(struct device_node *node) 829 { 830 return -1; 831 } 832 833 static inline int 834 of_pci_get_max_link_speed(struct device_node *node) 835 { 836 return -EINVAL; 837 } 838 839 static inline u32 840 of_pci_get_slot_power_limit(struct device_node *node, 841 u8 *slot_power_limit_value, 842 u8 *slot_power_limit_scale) 843 { 844 if (slot_power_limit_value) 845 *slot_power_limit_value = 0; 846 if (slot_power_limit_scale) 847 *slot_power_limit_scale = 0; 848 return 0; 849 } 850 851 static inline bool of_pci_preserve_config(struct device_node *node) 852 { 853 return false; 854 } 855 856 static inline int pci_set_of_node(struct pci_dev *dev) { return 0; } 857 static inline void pci_release_of_node(struct pci_dev *dev) { } 858 static inline void pci_set_bus_of_node(struct pci_bus *bus) { } 859 static inline void pci_release_bus_of_node(struct pci_bus *bus) { } 860 861 static inline int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge) 862 { 863 return 0; 864 } 865 866 static inline bool of_pci_supply_present(struct device_node *np) 867 { 868 return false; 869 } 870 #endif /* CONFIG_OF */ 871 872 struct of_changeset; 873 874 #ifdef CONFIG_PCI_DYNAMIC_OF_NODES 875 void of_pci_make_dev_node(struct pci_dev *pdev); 876 void of_pci_remove_node(struct pci_dev *pdev); 877 int of_pci_add_properties(struct pci_dev *pdev, struct of_changeset *ocs, 878 struct device_node *np); 879 #else 880 static inline void of_pci_make_dev_node(struct pci_dev *pdev) { } 881 static inline void of_pci_remove_node(struct pci_dev *pdev) { } 882 #endif 883 884 #ifdef CONFIG_PCIEAER 885 void pci_no_aer(void); 886 void pci_aer_init(struct pci_dev *dev); 887 void pci_aer_exit(struct pci_dev *dev); 888 extern const struct attribute_group aer_stats_attr_group; 889 void pci_aer_clear_fatal_status(struct pci_dev *dev); 890 int pci_aer_clear_status(struct pci_dev *dev); 891 int pci_aer_raw_clear_status(struct pci_dev *dev); 892 void pci_save_aer_state(struct pci_dev *dev); 893 void pci_restore_aer_state(struct pci_dev *dev); 894 #else 895 static inline void pci_no_aer(void) { } 896 static inline void pci_aer_init(struct pci_dev *d) { } 897 static inline void pci_aer_exit(struct pci_dev *d) { } 898 static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { } 899 static inline int pci_aer_clear_status(struct pci_dev *dev) { return -EINVAL; } 900 static inline int pci_aer_raw_clear_status(struct pci_dev *dev) { return -EINVAL; } 901 static inline void pci_save_aer_state(struct pci_dev *dev) { } 902 static inline void pci_restore_aer_state(struct pci_dev *dev) { } 903 #endif 904 905 #ifdef CONFIG_ACPI 906 bool pci_acpi_preserve_config(struct pci_host_bridge *bridge); 907 int pci_acpi_program_hp_params(struct pci_dev *dev); 908 extern const struct attribute_group pci_dev_acpi_attr_group; 909 void pci_set_acpi_fwnode(struct pci_dev *dev); 910 int pci_dev_acpi_reset(struct pci_dev *dev, bool probe); 911 bool acpi_pci_power_manageable(struct pci_dev *dev); 912 bool acpi_pci_bridge_d3(struct pci_dev *dev); 913 int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state); 914 pci_power_t acpi_pci_get_power_state(struct pci_dev *dev); 915 void acpi_pci_refresh_power_state(struct pci_dev *dev); 916 int acpi_pci_wakeup(struct pci_dev *dev, bool enable); 917 bool acpi_pci_need_resume(struct pci_dev *dev); 918 pci_power_t acpi_pci_choose_state(struct pci_dev *pdev); 919 #else 920 static inline bool pci_acpi_preserve_config(struct pci_host_bridge *bridge) 921 { 922 return false; 923 } 924 static inline int pci_dev_acpi_reset(struct pci_dev *dev, bool probe) 925 { 926 return -ENOTTY; 927 } 928 static inline void pci_set_acpi_fwnode(struct pci_dev *dev) { } 929 static inline int pci_acpi_program_hp_params(struct pci_dev *dev) 930 { 931 return -ENODEV; 932 } 933 static inline bool acpi_pci_power_manageable(struct pci_dev *dev) 934 { 935 return false; 936 } 937 static inline bool acpi_pci_bridge_d3(struct pci_dev *dev) 938 { 939 return false; 940 } 941 static inline int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state) 942 { 943 return -ENODEV; 944 } 945 static inline pci_power_t acpi_pci_get_power_state(struct pci_dev *dev) 946 { 947 return PCI_UNKNOWN; 948 } 949 static inline void acpi_pci_refresh_power_state(struct pci_dev *dev) { } 950 static inline int acpi_pci_wakeup(struct pci_dev *dev, bool enable) 951 { 952 return -ENODEV; 953 } 954 static inline bool acpi_pci_need_resume(struct pci_dev *dev) 955 { 956 return false; 957 } 958 static inline pci_power_t acpi_pci_choose_state(struct pci_dev *pdev) 959 { 960 return PCI_POWER_ERROR; 961 } 962 #endif 963 964 #ifdef CONFIG_PCIEASPM 965 extern const struct attribute_group aspm_ctrl_attr_group; 966 #endif 967 968 #ifdef CONFIG_X86_INTEL_MID 969 bool pci_use_mid_pm(void); 970 int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state); 971 pci_power_t mid_pci_get_power_state(struct pci_dev *pdev); 972 #else 973 static inline bool pci_use_mid_pm(void) 974 { 975 return false; 976 } 977 static inline int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state) 978 { 979 return -ENODEV; 980 } 981 static inline pci_power_t mid_pci_get_power_state(struct pci_dev *pdev) 982 { 983 return PCI_UNKNOWN; 984 } 985 #endif 986 987 int pcim_intx(struct pci_dev *dev, int enable); 988 int pcim_request_region_exclusive(struct pci_dev *pdev, int bar, 989 const char *name); 990 void pcim_release_region(struct pci_dev *pdev, int bar); 991 992 /* 993 * Config Address for PCI Configuration Mechanism #1 994 * 995 * See PCI Local Bus Specification, Revision 3.0, 996 * Section 3.2.2.3.2, Figure 3-2, p. 50. 997 */ 998 999 #define PCI_CONF1_BUS_SHIFT 16 /* Bus number */ 1000 #define PCI_CONF1_DEV_SHIFT 11 /* Device number */ 1001 #define PCI_CONF1_FUNC_SHIFT 8 /* Function number */ 1002 1003 #define PCI_CONF1_BUS_MASK 0xff 1004 #define PCI_CONF1_DEV_MASK 0x1f 1005 #define PCI_CONF1_FUNC_MASK 0x7 1006 #define PCI_CONF1_REG_MASK 0xfc /* Limit aligned offset to a maximum of 256B */ 1007 1008 #define PCI_CONF1_ENABLE BIT(31) 1009 #define PCI_CONF1_BUS(x) (((x) & PCI_CONF1_BUS_MASK) << PCI_CONF1_BUS_SHIFT) 1010 #define PCI_CONF1_DEV(x) (((x) & PCI_CONF1_DEV_MASK) << PCI_CONF1_DEV_SHIFT) 1011 #define PCI_CONF1_FUNC(x) (((x) & PCI_CONF1_FUNC_MASK) << PCI_CONF1_FUNC_SHIFT) 1012 #define PCI_CONF1_REG(x) ((x) & PCI_CONF1_REG_MASK) 1013 1014 #define PCI_CONF1_ADDRESS(bus, dev, func, reg) \ 1015 (PCI_CONF1_ENABLE | \ 1016 PCI_CONF1_BUS(bus) | \ 1017 PCI_CONF1_DEV(dev) | \ 1018 PCI_CONF1_FUNC(func) | \ 1019 PCI_CONF1_REG(reg)) 1020 1021 /* 1022 * Extension of PCI Config Address for accessing extended PCIe registers 1023 * 1024 * No standardized specification, but used on lot of non-ECAM-compliant ARM SoCs 1025 * or on AMD Barcelona and new CPUs. Reserved bits [27:24] of PCI Config Address 1026 * are used for specifying additional 4 high bits of PCI Express register. 1027 */ 1028 1029 #define PCI_CONF1_EXT_REG_SHIFT 16 1030 #define PCI_CONF1_EXT_REG_MASK 0xf00 1031 #define PCI_CONF1_EXT_REG(x) (((x) & PCI_CONF1_EXT_REG_MASK) << PCI_CONF1_EXT_REG_SHIFT) 1032 1033 #define PCI_CONF1_EXT_ADDRESS(bus, dev, func, reg) \ 1034 (PCI_CONF1_ADDRESS(bus, dev, func, reg) | \ 1035 PCI_CONF1_EXT_REG(reg)) 1036 1037 #endif /* DRIVERS_PCI_H */ 1038