1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef DRIVERS_PCI_H 3 #define DRIVERS_PCI_H 4 5 #include <linux/pci.h> 6 7 struct pcie_tlp_log; 8 9 /* Number of possible devfns: 0.0 to 1f.7 inclusive */ 10 #define MAX_NR_DEVFNS 256 11 12 #define PCI_FIND_CAP_TTL 48 13 14 #define PCI_VSEC_ID_INTEL_TBT 0x1234 /* Thunderbolt */ 15 16 #define PCIE_LINK_RETRAIN_TIMEOUT_MS 1000 17 18 /* 19 * Power stable to PERST# inactive. 20 * 21 * See the "Power Sequencing and Reset Signal Timings" table of the PCI Express 22 * Card Electromechanical Specification, Revision 5.1, Section 2.9.2, Symbol 23 * "T_PVPERL". 24 */ 25 #define PCIE_T_PVPERL_MS 100 26 27 /* 28 * REFCLK stable before PERST# inactive. 29 * 30 * See the "Power Sequencing and Reset Signal Timings" table of the PCI Express 31 * Card Electromechanical Specification, Revision 5.1, Section 2.9.2, Symbol 32 * "T_PERST-CLK". 33 */ 34 #define PCIE_T_PERST_CLK_US 100 35 36 /* 37 * End of conventional reset (PERST# de-asserted) to first configuration 38 * request (device able to respond with a "Request Retry Status" completion), 39 * from PCIe r6.0, sec 6.6.1. 40 */ 41 #define PCIE_T_RRS_READY_MS 100 42 43 /* 44 * PCIe r6.0, sec 5.3.3.2.1 <PME Synchronization> 45 * Recommends 1ms to 10ms timeout to check L2 ready. 46 */ 47 #define PCIE_PME_TO_L2_TIMEOUT_US 10000 48 49 /* 50 * PCIe r6.0, sec 6.6.1 <Conventional Reset> 51 * 52 * - "With a Downstream Port that does not support Link speeds greater 53 * than 5.0 GT/s, software must wait a minimum of 100 ms following exit 54 * from a Conventional Reset before sending a Configuration Request to 55 * the device immediately below that Port." 56 * 57 * - "With a Downstream Port that supports Link speeds greater than 58 * 5.0 GT/s, software must wait a minimum of 100 ms after Link training 59 * completes before sending a Configuration Request to the device 60 * immediately below that Port." 61 */ 62 #define PCIE_RESET_CONFIG_DEVICE_WAIT_MS 100 63 64 /* Message Routing (r[2:0]); PCIe r6.0, sec 2.2.8 */ 65 #define PCIE_MSG_TYPE_R_RC 0 66 #define PCIE_MSG_TYPE_R_ADDR 1 67 #define PCIE_MSG_TYPE_R_ID 2 68 #define PCIE_MSG_TYPE_R_BC 3 69 #define PCIE_MSG_TYPE_R_LOCAL 4 70 #define PCIE_MSG_TYPE_R_GATHER 5 71 72 /* Power Management Messages; PCIe r6.0, sec 2.2.8.2 */ 73 #define PCIE_MSG_CODE_PME_TURN_OFF 0x19 74 75 /* INTx Mechanism Messages; PCIe r6.0, sec 2.2.8.1 */ 76 #define PCIE_MSG_CODE_ASSERT_INTA 0x20 77 #define PCIE_MSG_CODE_ASSERT_INTB 0x21 78 #define PCIE_MSG_CODE_ASSERT_INTC 0x22 79 #define PCIE_MSG_CODE_ASSERT_INTD 0x23 80 #define PCIE_MSG_CODE_DEASSERT_INTA 0x24 81 #define PCIE_MSG_CODE_DEASSERT_INTB 0x25 82 #define PCIE_MSG_CODE_DEASSERT_INTC 0x26 83 #define PCIE_MSG_CODE_DEASSERT_INTD 0x27 84 85 extern const unsigned char pcie_link_speed[]; 86 extern bool pci_early_dump; 87 88 bool pcie_cap_has_lnkctl(const struct pci_dev *dev); 89 bool pcie_cap_has_lnkctl2(const struct pci_dev *dev); 90 bool pcie_cap_has_rtctl(const struct pci_dev *dev); 91 92 /* Functions internal to the PCI core code */ 93 94 #ifdef CONFIG_DMI 95 extern const struct attribute_group pci_dev_smbios_attr_group; 96 #endif 97 98 enum pci_mmap_api { 99 PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */ 100 PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */ 101 }; 102 int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai, 103 enum pci_mmap_api mmap_api); 104 105 bool pci_reset_supported(struct pci_dev *dev); 106 void pci_init_reset_methods(struct pci_dev *dev); 107 int pci_bridge_secondary_bus_reset(struct pci_dev *dev); 108 int pci_bus_error_reset(struct pci_dev *dev); 109 int __pci_reset_bus(struct pci_bus *bus); 110 111 struct pci_cap_saved_data { 112 u16 cap_nr; 113 bool cap_extended; 114 unsigned int size; 115 u32 data[]; 116 }; 117 118 struct pci_cap_saved_state { 119 struct hlist_node next; 120 struct pci_cap_saved_data cap; 121 }; 122 123 void pci_allocate_cap_save_buffers(struct pci_dev *dev); 124 void pci_free_cap_save_buffers(struct pci_dev *dev); 125 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size); 126 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, 127 u16 cap, unsigned int size); 128 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap); 129 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, 130 u16 cap); 131 132 #define PCI_PM_D2_DELAY 200 /* usec; see PCIe r4.0, sec 5.9.1 */ 133 #define PCI_PM_D3HOT_WAIT 10 /* msec */ 134 #define PCI_PM_D3COLD_WAIT 100 /* msec */ 135 136 void pci_update_current_state(struct pci_dev *dev, pci_power_t state); 137 void pci_refresh_power_state(struct pci_dev *dev); 138 int pci_power_up(struct pci_dev *dev); 139 void pci_disable_enabled_device(struct pci_dev *dev); 140 int pci_finish_runtime_suspend(struct pci_dev *dev); 141 void pcie_clear_device_status(struct pci_dev *dev); 142 void pcie_clear_root_pme_status(struct pci_dev *dev); 143 bool pci_check_pme_status(struct pci_dev *dev); 144 void pci_pme_wakeup_bus(struct pci_bus *bus); 145 void pci_pme_restore(struct pci_dev *dev); 146 bool pci_dev_need_resume(struct pci_dev *dev); 147 void pci_dev_adjust_pme(struct pci_dev *dev); 148 void pci_dev_complete_resume(struct pci_dev *pci_dev); 149 void pci_config_pm_runtime_get(struct pci_dev *dev); 150 void pci_config_pm_runtime_put(struct pci_dev *dev); 151 void pci_pm_init(struct pci_dev *dev); 152 void pci_ea_init(struct pci_dev *dev); 153 void pci_msi_init(struct pci_dev *dev); 154 void pci_msix_init(struct pci_dev *dev); 155 bool pci_bridge_d3_possible(struct pci_dev *dev); 156 void pci_bridge_d3_update(struct pci_dev *dev); 157 int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type); 158 159 static inline bool pci_bus_rrs_vendor_id(u32 l) 160 { 161 return (l & 0xffff) == PCI_VENDOR_ID_PCI_SIG; 162 } 163 164 static inline void pci_wakeup_event(struct pci_dev *dev) 165 { 166 /* Wait 100 ms before the system can be put into a sleep state. */ 167 pm_wakeup_event(&dev->dev, 100); 168 } 169 170 /** 171 * pci_bar_index_is_valid - Check whether a BAR index is within valid range 172 * @bar: BAR index 173 * 174 * Protects against overflowing &struct pci_dev.resource array. 175 * 176 * Return: true for valid index, false otherwise. 177 */ 178 static inline bool pci_bar_index_is_valid(int bar) 179 { 180 if (bar >= 0 && bar < PCI_NUM_RESOURCES) 181 return true; 182 183 return false; 184 } 185 186 static inline bool pci_has_subordinate(struct pci_dev *pci_dev) 187 { 188 return !!(pci_dev->subordinate); 189 } 190 191 static inline bool pci_power_manageable(struct pci_dev *pci_dev) 192 { 193 /* 194 * Currently we allow normal PCI devices and PCI bridges transition 195 * into D3 if their bridge_d3 is set. 196 */ 197 return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3; 198 } 199 200 static inline bool pcie_downstream_port(const struct pci_dev *dev) 201 { 202 int type = pci_pcie_type(dev); 203 204 return type == PCI_EXP_TYPE_ROOT_PORT || 205 type == PCI_EXP_TYPE_DOWNSTREAM || 206 type == PCI_EXP_TYPE_PCIE_BRIDGE; 207 } 208 209 void pci_vpd_init(struct pci_dev *dev); 210 extern const struct attribute_group pci_dev_vpd_attr_group; 211 212 /* PCI Virtual Channel */ 213 int pci_save_vc_state(struct pci_dev *dev); 214 void pci_restore_vc_state(struct pci_dev *dev); 215 void pci_allocate_vc_save_buffers(struct pci_dev *dev); 216 217 /* PCI /proc functions */ 218 #ifdef CONFIG_PROC_FS 219 int pci_proc_attach_device(struct pci_dev *dev); 220 int pci_proc_detach_device(struct pci_dev *dev); 221 int pci_proc_detach_bus(struct pci_bus *bus); 222 #else 223 static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; } 224 static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; } 225 static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; } 226 #endif 227 228 /* Functions for PCI Hotplug drivers to use */ 229 int pci_hp_add_bridge(struct pci_dev *dev); 230 231 #if defined(CONFIG_SYSFS) && defined(HAVE_PCI_LEGACY) 232 void pci_create_legacy_files(struct pci_bus *bus); 233 void pci_remove_legacy_files(struct pci_bus *bus); 234 #else 235 static inline void pci_create_legacy_files(struct pci_bus *bus) { } 236 static inline void pci_remove_legacy_files(struct pci_bus *bus) { } 237 #endif 238 239 /* Lock for read/write access to pci device and bus lists */ 240 extern struct rw_semaphore pci_bus_sem; 241 extern struct mutex pci_slot_mutex; 242 243 extern raw_spinlock_t pci_lock; 244 245 extern unsigned int pci_pm_d3hot_delay; 246 247 #ifdef CONFIG_PCI_MSI 248 void pci_no_msi(void); 249 #else 250 static inline void pci_no_msi(void) { } 251 #endif 252 253 void pci_realloc_get_opt(char *); 254 255 static inline int pci_no_d1d2(struct pci_dev *dev) 256 { 257 unsigned int parent_dstates = 0; 258 259 if (dev->bus->self) 260 parent_dstates = dev->bus->self->no_d1d2; 261 return (dev->no_d1d2 || parent_dstates); 262 263 } 264 265 #ifdef CONFIG_SYSFS 266 int pci_create_sysfs_dev_files(struct pci_dev *pdev); 267 void pci_remove_sysfs_dev_files(struct pci_dev *pdev); 268 extern const struct attribute_group *pci_dev_groups[]; 269 extern const struct attribute_group *pci_dev_attr_groups[]; 270 extern const struct attribute_group *pcibus_groups[]; 271 extern const struct attribute_group *pci_bus_groups[]; 272 extern const struct attribute_group pci_doe_sysfs_group; 273 #else 274 static inline int pci_create_sysfs_dev_files(struct pci_dev *pdev) { return 0; } 275 static inline void pci_remove_sysfs_dev_files(struct pci_dev *pdev) { } 276 #define pci_dev_groups NULL 277 #define pci_dev_attr_groups NULL 278 #define pcibus_groups NULL 279 #define pci_bus_groups NULL 280 #endif 281 282 extern unsigned long pci_hotplug_io_size; 283 extern unsigned long pci_hotplug_mmio_size; 284 extern unsigned long pci_hotplug_mmio_pref_size; 285 extern unsigned long pci_hotplug_bus_size; 286 extern unsigned long pci_cardbus_io_size; 287 extern unsigned long pci_cardbus_mem_size; 288 289 /** 290 * pci_match_one_device - Tell if a PCI device structure has a matching 291 * PCI device id structure 292 * @id: single PCI device id structure to match 293 * @dev: the PCI device structure to match against 294 * 295 * Returns the matching pci_device_id structure or %NULL if there is no match. 296 */ 297 static inline const struct pci_device_id * 298 pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev) 299 { 300 if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) && 301 (id->device == PCI_ANY_ID || id->device == dev->device) && 302 (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) && 303 (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) && 304 !((id->class ^ dev->class) & id->class_mask)) 305 return id; 306 return NULL; 307 } 308 309 /* PCI slot sysfs helper code */ 310 #define to_pci_slot(s) container_of(s, struct pci_slot, kobj) 311 312 extern struct kset *pci_slots_kset; 313 314 struct pci_slot_attribute { 315 struct attribute attr; 316 ssize_t (*show)(struct pci_slot *, char *); 317 ssize_t (*store)(struct pci_slot *, const char *, size_t); 318 }; 319 #define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr) 320 321 enum pci_bar_type { 322 pci_bar_unknown, /* Standard PCI BAR probe */ 323 pci_bar_io, /* An I/O port BAR */ 324 pci_bar_mem32, /* A 32-bit memory BAR */ 325 pci_bar_mem64, /* A 64-bit memory BAR */ 326 }; 327 328 struct device *pci_get_host_bridge_device(struct pci_dev *dev); 329 void pci_put_host_bridge_device(struct device *dev); 330 331 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge); 332 int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type); 333 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align); 334 335 int pci_configure_extended_tags(struct pci_dev *dev, void *ign); 336 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl, 337 int rrs_timeout); 338 bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl, 339 int rrs_timeout); 340 int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *pl, int rrs_timeout); 341 342 int pci_setup_device(struct pci_dev *dev); 343 void __pci_size_stdbars(struct pci_dev *dev, int count, 344 unsigned int pos, u32 *sizes); 345 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, 346 struct resource *res, unsigned int reg, u32 *sizes); 347 void pci_configure_ari(struct pci_dev *dev); 348 void __pci_bus_size_bridges(struct pci_bus *bus, 349 struct list_head *realloc_head); 350 void __pci_bus_assign_resources(const struct pci_bus *bus, 351 struct list_head *realloc_head, 352 struct list_head *fail_head); 353 bool pci_bus_clip_resource(struct pci_dev *dev, int idx); 354 void pci_walk_bus_locked(struct pci_bus *top, 355 int (*cb)(struct pci_dev *, void *), 356 void *userdata); 357 358 const char *pci_resource_name(struct pci_dev *dev, unsigned int i); 359 bool pci_resource_is_optional(const struct pci_dev *dev, int resno); 360 361 /** 362 * pci_resource_num - Reverse lookup resource number from device resources 363 * @dev: PCI device 364 * @res: Resource to lookup index for (MUST be a @dev's resource) 365 * 366 * Perform reverse lookup to determine the resource number for @res within 367 * @dev resource array. NOTE: The caller is responsible for ensuring @res is 368 * among @dev's resources! 369 * 370 * Returns: resource number. 371 */ 372 static inline int pci_resource_num(const struct pci_dev *dev, 373 const struct resource *res) 374 { 375 int resno = res - &dev->resource[0]; 376 377 /* Passing a resource that is not among dev's resources? */ 378 WARN_ON_ONCE(resno >= PCI_NUM_RESOURCES); 379 380 return resno; 381 } 382 383 void pci_reassigndev_resource_alignment(struct pci_dev *dev); 384 void pci_disable_bridge_window(struct pci_dev *dev); 385 struct pci_bus *pci_bus_get(struct pci_bus *bus); 386 void pci_bus_put(struct pci_bus *bus); 387 388 #define PCIE_LNKCAP_SLS2SPEED(lnkcap) \ 389 ({ \ 390 ((lnkcap) == PCI_EXP_LNKCAP_SLS_64_0GB ? PCIE_SPEED_64_0GT : \ 391 (lnkcap) == PCI_EXP_LNKCAP_SLS_32_0GB ? PCIE_SPEED_32_0GT : \ 392 (lnkcap) == PCI_EXP_LNKCAP_SLS_16_0GB ? PCIE_SPEED_16_0GT : \ 393 (lnkcap) == PCI_EXP_LNKCAP_SLS_8_0GB ? PCIE_SPEED_8_0GT : \ 394 (lnkcap) == PCI_EXP_LNKCAP_SLS_5_0GB ? PCIE_SPEED_5_0GT : \ 395 (lnkcap) == PCI_EXP_LNKCAP_SLS_2_5GB ? PCIE_SPEED_2_5GT : \ 396 PCI_SPEED_UNKNOWN); \ 397 }) 398 399 /* PCIe link information from Link Capabilities 2 */ 400 #define PCIE_LNKCAP2_SLS2SPEED(lnkcap2) \ 401 ((lnkcap2) & PCI_EXP_LNKCAP2_SLS_64_0GB ? PCIE_SPEED_64_0GT : \ 402 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_32_0GB ? PCIE_SPEED_32_0GT : \ 403 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_16_0GB ? PCIE_SPEED_16_0GT : \ 404 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_8_0GB ? PCIE_SPEED_8_0GT : \ 405 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_5_0GB ? PCIE_SPEED_5_0GT : \ 406 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_2_5GB ? PCIE_SPEED_2_5GT : \ 407 PCI_SPEED_UNKNOWN) 408 409 #define PCIE_LNKCTL2_TLS2SPEED(lnkctl2) \ 410 ((lnkctl2) == PCI_EXP_LNKCTL2_TLS_64_0GT ? PCIE_SPEED_64_0GT : \ 411 (lnkctl2) == PCI_EXP_LNKCTL2_TLS_32_0GT ? PCIE_SPEED_32_0GT : \ 412 (lnkctl2) == PCI_EXP_LNKCTL2_TLS_16_0GT ? PCIE_SPEED_16_0GT : \ 413 (lnkctl2) == PCI_EXP_LNKCTL2_TLS_8_0GT ? PCIE_SPEED_8_0GT : \ 414 (lnkctl2) == PCI_EXP_LNKCTL2_TLS_5_0GT ? PCIE_SPEED_5_0GT : \ 415 (lnkctl2) == PCI_EXP_LNKCTL2_TLS_2_5GT ? PCIE_SPEED_2_5GT : \ 416 PCI_SPEED_UNKNOWN) 417 418 /* PCIe speed to Mb/s reduced by encoding overhead */ 419 #define PCIE_SPEED2MBS_ENC(speed) \ 420 ((speed) == PCIE_SPEED_64_0GT ? 64000*1/1 : \ 421 (speed) == PCIE_SPEED_32_0GT ? 32000*128/130 : \ 422 (speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \ 423 (speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \ 424 (speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \ 425 (speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \ 426 0) 427 428 static inline int pcie_dev_speed_mbps(enum pci_bus_speed speed) 429 { 430 switch (speed) { 431 case PCIE_SPEED_2_5GT: 432 return 2500; 433 case PCIE_SPEED_5_0GT: 434 return 5000; 435 case PCIE_SPEED_8_0GT: 436 return 8000; 437 case PCIE_SPEED_16_0GT: 438 return 16000; 439 case PCIE_SPEED_32_0GT: 440 return 32000; 441 case PCIE_SPEED_64_0GT: 442 return 64000; 443 default: 444 break; 445 } 446 447 return -EINVAL; 448 } 449 450 u8 pcie_get_supported_speeds(struct pci_dev *dev); 451 const char *pci_speed_string(enum pci_bus_speed speed); 452 void __pcie_print_link_status(struct pci_dev *dev, bool verbose); 453 void pcie_report_downtraining(struct pci_dev *dev); 454 455 static inline void __pcie_update_link_speed(struct pci_bus *bus, u16 linksta, u16 linksta2) 456 { 457 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS]; 458 bus->flit_mode = (linksta2 & PCI_EXP_LNKSTA2_FLIT) ? 1 : 0; 459 } 460 void pcie_update_link_speed(struct pci_bus *bus); 461 462 /* Single Root I/O Virtualization */ 463 struct pci_sriov { 464 int pos; /* Capability position */ 465 int nres; /* Number of resources */ 466 u32 cap; /* SR-IOV Capabilities */ 467 u16 ctrl; /* SR-IOV Control */ 468 u16 total_VFs; /* Total VFs associated with the PF */ 469 u16 initial_VFs; /* Initial VFs associated with the PF */ 470 u16 num_VFs; /* Number of VFs available */ 471 u16 offset; /* First VF Routing ID offset */ 472 u16 stride; /* Following VF stride */ 473 u16 vf_device; /* VF device ID */ 474 u32 pgsz; /* Page size for BAR alignment */ 475 u8 link; /* Function Dependency Link */ 476 u8 max_VF_buses; /* Max buses consumed by VFs */ 477 u16 driver_max_VFs; /* Max num VFs driver supports */ 478 struct pci_dev *dev; /* Lowest numbered PF */ 479 struct pci_dev *self; /* This PF */ 480 u32 class; /* VF device */ 481 u8 hdr_type; /* VF header type */ 482 u16 subsystem_vendor; /* VF subsystem vendor */ 483 u16 subsystem_device; /* VF subsystem device */ 484 resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */ 485 bool drivers_autoprobe; /* Auto probing of VFs by driver */ 486 }; 487 488 #ifdef CONFIG_PCI_DOE 489 void pci_doe_init(struct pci_dev *pdev); 490 void pci_doe_destroy(struct pci_dev *pdev); 491 void pci_doe_disconnected(struct pci_dev *pdev); 492 #else 493 static inline void pci_doe_init(struct pci_dev *pdev) { } 494 static inline void pci_doe_destroy(struct pci_dev *pdev) { } 495 static inline void pci_doe_disconnected(struct pci_dev *pdev) { } 496 #endif 497 498 #ifdef CONFIG_PCI_NPEM 499 void pci_npem_create(struct pci_dev *dev); 500 void pci_npem_remove(struct pci_dev *dev); 501 #else 502 static inline void pci_npem_create(struct pci_dev *dev) { } 503 static inline void pci_npem_remove(struct pci_dev *dev) { } 504 #endif 505 506 #if defined(CONFIG_PCI_DOE) && defined(CONFIG_SYSFS) 507 void pci_doe_sysfs_init(struct pci_dev *pci_dev); 508 void pci_doe_sysfs_teardown(struct pci_dev *pdev); 509 #else 510 static inline void pci_doe_sysfs_init(struct pci_dev *pdev) { } 511 static inline void pci_doe_sysfs_teardown(struct pci_dev *pdev) { } 512 #endif 513 514 /** 515 * pci_dev_set_io_state - Set the new error state if possible. 516 * 517 * @dev: PCI device to set new error_state 518 * @new: the state we want dev to be in 519 * 520 * If the device is experiencing perm_failure, it has to remain in that state. 521 * Any other transition is allowed. 522 * 523 * Returns true if state has been changed to the requested state. 524 */ 525 static inline bool pci_dev_set_io_state(struct pci_dev *dev, 526 pci_channel_state_t new) 527 { 528 pci_channel_state_t old; 529 530 switch (new) { 531 case pci_channel_io_perm_failure: 532 xchg(&dev->error_state, pci_channel_io_perm_failure); 533 return true; 534 case pci_channel_io_frozen: 535 old = cmpxchg(&dev->error_state, pci_channel_io_normal, 536 pci_channel_io_frozen); 537 return old != pci_channel_io_perm_failure; 538 case pci_channel_io_normal: 539 old = cmpxchg(&dev->error_state, pci_channel_io_frozen, 540 pci_channel_io_normal); 541 return old != pci_channel_io_perm_failure; 542 default: 543 return false; 544 } 545 } 546 547 static inline int pci_dev_set_disconnected(struct pci_dev *dev, void *unused) 548 { 549 pci_dev_set_io_state(dev, pci_channel_io_perm_failure); 550 pci_doe_disconnected(dev); 551 552 return 0; 553 } 554 555 /* pci_dev priv_flags */ 556 #define PCI_DEV_ADDED 0 557 #define PCI_DPC_RECOVERED 1 558 #define PCI_DPC_RECOVERING 2 559 #define PCI_DEV_REMOVED 3 560 561 static inline void pci_dev_assign_added(struct pci_dev *dev) 562 { 563 smp_mb__before_atomic(); 564 set_bit(PCI_DEV_ADDED, &dev->priv_flags); 565 smp_mb__after_atomic(); 566 } 567 568 static inline bool pci_dev_test_and_clear_added(struct pci_dev *dev) 569 { 570 return test_and_clear_bit(PCI_DEV_ADDED, &dev->priv_flags); 571 } 572 573 static inline bool pci_dev_is_added(const struct pci_dev *dev) 574 { 575 return test_bit(PCI_DEV_ADDED, &dev->priv_flags); 576 } 577 578 static inline bool pci_dev_test_and_set_removed(struct pci_dev *dev) 579 { 580 return test_and_set_bit(PCI_DEV_REMOVED, &dev->priv_flags); 581 } 582 583 #ifdef CONFIG_PCIEAER 584 #include <linux/aer.h> 585 586 #define AER_MAX_MULTI_ERR_DEVICES 5 /* Not likely to have more */ 587 588 struct aer_err_info { 589 struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES]; 590 int error_dev_num; 591 592 unsigned int id:16; 593 594 unsigned int severity:2; /* 0:NONFATAL | 1:FATAL | 2:COR */ 595 unsigned int __pad1:5; 596 unsigned int multi_error_valid:1; 597 598 unsigned int first_error:5; 599 unsigned int __pad2:2; 600 unsigned int tlp_header_valid:1; 601 602 unsigned int status; /* COR/UNCOR Error Status */ 603 unsigned int mask; /* COR/UNCOR Error Mask */ 604 struct pcie_tlp_log tlp; /* TLP Header */ 605 }; 606 607 int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info); 608 void aer_print_error(struct pci_dev *dev, struct aer_err_info *info); 609 610 int pcie_read_tlp_log(struct pci_dev *dev, int where, int where2, 611 unsigned int tlp_len, bool flit, 612 struct pcie_tlp_log *log); 613 unsigned int aer_tlp_log_len(struct pci_dev *dev, u32 aercc); 614 void pcie_print_tlp_log(const struct pci_dev *dev, 615 const struct pcie_tlp_log *log, const char *pfx); 616 #endif /* CONFIG_PCIEAER */ 617 618 #ifdef CONFIG_PCIEPORTBUS 619 /* Cached RCEC Endpoint Association */ 620 struct rcec_ea { 621 u8 nextbusn; 622 u8 lastbusn; 623 u32 bitmap; 624 }; 625 #endif 626 627 #ifdef CONFIG_PCIE_DPC 628 void pci_save_dpc_state(struct pci_dev *dev); 629 void pci_restore_dpc_state(struct pci_dev *dev); 630 void pci_dpc_init(struct pci_dev *pdev); 631 void dpc_process_error(struct pci_dev *pdev); 632 pci_ers_result_t dpc_reset_link(struct pci_dev *pdev); 633 bool pci_dpc_recovered(struct pci_dev *pdev); 634 unsigned int dpc_tlp_log_len(struct pci_dev *dev); 635 #else 636 static inline void pci_save_dpc_state(struct pci_dev *dev) { } 637 static inline void pci_restore_dpc_state(struct pci_dev *dev) { } 638 static inline void pci_dpc_init(struct pci_dev *pdev) { } 639 static inline bool pci_dpc_recovered(struct pci_dev *pdev) { return false; } 640 #endif 641 642 #ifdef CONFIG_PCIEPORTBUS 643 void pci_rcec_init(struct pci_dev *dev); 644 void pci_rcec_exit(struct pci_dev *dev); 645 void pcie_link_rcec(struct pci_dev *rcec); 646 void pcie_walk_rcec(struct pci_dev *rcec, 647 int (*cb)(struct pci_dev *, void *), 648 void *userdata); 649 #else 650 static inline void pci_rcec_init(struct pci_dev *dev) { } 651 static inline void pci_rcec_exit(struct pci_dev *dev) { } 652 static inline void pcie_link_rcec(struct pci_dev *rcec) { } 653 static inline void pcie_walk_rcec(struct pci_dev *rcec, 654 int (*cb)(struct pci_dev *, void *), 655 void *userdata) { } 656 #endif 657 658 #ifdef CONFIG_PCI_ATS 659 /* Address Translation Service */ 660 void pci_ats_init(struct pci_dev *dev); 661 void pci_restore_ats_state(struct pci_dev *dev); 662 #else 663 static inline void pci_ats_init(struct pci_dev *d) { } 664 static inline void pci_restore_ats_state(struct pci_dev *dev) { } 665 #endif /* CONFIG_PCI_ATS */ 666 667 #ifdef CONFIG_PCI_PRI 668 void pci_pri_init(struct pci_dev *dev); 669 void pci_restore_pri_state(struct pci_dev *pdev); 670 #else 671 static inline void pci_pri_init(struct pci_dev *dev) { } 672 static inline void pci_restore_pri_state(struct pci_dev *pdev) { } 673 #endif 674 675 #ifdef CONFIG_PCI_PASID 676 void pci_pasid_init(struct pci_dev *dev); 677 void pci_restore_pasid_state(struct pci_dev *pdev); 678 #else 679 static inline void pci_pasid_init(struct pci_dev *dev) { } 680 static inline void pci_restore_pasid_state(struct pci_dev *pdev) { } 681 #endif 682 683 #ifdef CONFIG_PCI_IOV 684 int pci_iov_init(struct pci_dev *dev); 685 void pci_iov_release(struct pci_dev *dev); 686 void pci_iov_remove(struct pci_dev *dev); 687 void pci_iov_update_resource(struct pci_dev *dev, int resno); 688 resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno); 689 void pci_restore_iov_state(struct pci_dev *dev); 690 int pci_iov_bus_range(struct pci_bus *bus); 691 static inline bool pci_resource_is_iov(int resno) 692 { 693 return resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END; 694 } 695 extern const struct attribute_group sriov_pf_dev_attr_group; 696 extern const struct attribute_group sriov_vf_dev_attr_group; 697 #else 698 static inline int pci_iov_init(struct pci_dev *dev) 699 { 700 return -ENODEV; 701 } 702 static inline void pci_iov_release(struct pci_dev *dev) { } 703 static inline void pci_iov_remove(struct pci_dev *dev) { } 704 static inline void pci_iov_update_resource(struct pci_dev *dev, int resno) { } 705 static inline resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, 706 int resno) 707 { 708 return 0; 709 } 710 static inline void pci_restore_iov_state(struct pci_dev *dev) { } 711 static inline int pci_iov_bus_range(struct pci_bus *bus) 712 { 713 return 0; 714 } 715 static inline bool pci_resource_is_iov(int resno) 716 { 717 return false; 718 } 719 #endif /* CONFIG_PCI_IOV */ 720 721 #ifdef CONFIG_PCIE_TPH 722 void pci_restore_tph_state(struct pci_dev *dev); 723 void pci_save_tph_state(struct pci_dev *dev); 724 void pci_no_tph(void); 725 void pci_tph_init(struct pci_dev *dev); 726 #else 727 static inline void pci_restore_tph_state(struct pci_dev *dev) { } 728 static inline void pci_save_tph_state(struct pci_dev *dev) { } 729 static inline void pci_no_tph(void) { } 730 static inline void pci_tph_init(struct pci_dev *dev) { } 731 #endif 732 733 #ifdef CONFIG_PCIE_PTM 734 void pci_ptm_init(struct pci_dev *dev); 735 void pci_save_ptm_state(struct pci_dev *dev); 736 void pci_restore_ptm_state(struct pci_dev *dev); 737 void pci_suspend_ptm(struct pci_dev *dev); 738 void pci_resume_ptm(struct pci_dev *dev); 739 #else 740 static inline void pci_ptm_init(struct pci_dev *dev) { } 741 static inline void pci_save_ptm_state(struct pci_dev *dev) { } 742 static inline void pci_restore_ptm_state(struct pci_dev *dev) { } 743 static inline void pci_suspend_ptm(struct pci_dev *dev) { } 744 static inline void pci_resume_ptm(struct pci_dev *dev) { } 745 #endif 746 747 unsigned long pci_cardbus_resource_alignment(struct resource *); 748 749 static inline resource_size_t pci_resource_alignment(struct pci_dev *dev, 750 struct resource *res) 751 { 752 int resno = pci_resource_num(dev, res); 753 754 if (pci_resource_is_iov(resno)) 755 return pci_sriov_resource_alignment(dev, resno); 756 if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS) 757 return pci_cardbus_resource_alignment(res); 758 return resource_alignment(res); 759 } 760 761 void pci_acs_init(struct pci_dev *dev); 762 #ifdef CONFIG_PCI_QUIRKS 763 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags); 764 int pci_dev_specific_enable_acs(struct pci_dev *dev); 765 int pci_dev_specific_disable_acs_redir(struct pci_dev *dev); 766 int pcie_failed_link_retrain(struct pci_dev *dev); 767 #else 768 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev, 769 u16 acs_flags) 770 { 771 return -ENOTTY; 772 } 773 static inline int pci_dev_specific_enable_acs(struct pci_dev *dev) 774 { 775 return -ENOTTY; 776 } 777 static inline int pci_dev_specific_disable_acs_redir(struct pci_dev *dev) 778 { 779 return -ENOTTY; 780 } 781 static inline int pcie_failed_link_retrain(struct pci_dev *dev) 782 { 783 return -ENOTTY; 784 } 785 #endif 786 787 /* PCI error reporting and recovery */ 788 pci_ers_result_t pcie_do_recovery(struct pci_dev *dev, 789 pci_channel_state_t state, 790 pci_ers_result_t (*reset_subordinates)(struct pci_dev *pdev)); 791 792 bool pcie_wait_for_link(struct pci_dev *pdev, bool active); 793 int pcie_retrain_link(struct pci_dev *pdev, bool use_lt); 794 795 /* ASPM-related functionality we need even without CONFIG_PCIEASPM */ 796 void pci_save_ltr_state(struct pci_dev *dev); 797 void pci_restore_ltr_state(struct pci_dev *dev); 798 void pci_configure_aspm_l1ss(struct pci_dev *dev); 799 void pci_save_aspm_l1ss_state(struct pci_dev *dev); 800 void pci_restore_aspm_l1ss_state(struct pci_dev *dev); 801 802 #ifdef CONFIG_PCIEASPM 803 void pcie_aspm_init_link_state(struct pci_dev *pdev); 804 void pcie_aspm_exit_link_state(struct pci_dev *pdev); 805 void pcie_aspm_pm_state_change(struct pci_dev *pdev, bool locked); 806 void pcie_aspm_powersave_config_link(struct pci_dev *pdev); 807 void pci_configure_ltr(struct pci_dev *pdev); 808 void pci_bridge_reconfigure_ltr(struct pci_dev *pdev); 809 #else 810 static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { } 811 static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { } 812 static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev, bool locked) { } 813 static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { } 814 static inline void pci_configure_ltr(struct pci_dev *pdev) { } 815 static inline void pci_bridge_reconfigure_ltr(struct pci_dev *pdev) { } 816 #endif 817 818 #ifdef CONFIG_PCIE_ECRC 819 void pcie_set_ecrc_checking(struct pci_dev *dev); 820 void pcie_ecrc_get_policy(char *str); 821 #else 822 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { } 823 static inline void pcie_ecrc_get_policy(char *str) { } 824 #endif 825 826 #ifdef CONFIG_PCIEPORTBUS 827 void pcie_reset_lbms_count(struct pci_dev *port); 828 int pcie_lbms_count(struct pci_dev *port, unsigned long *val); 829 #else 830 static inline void pcie_reset_lbms_count(struct pci_dev *port) {} 831 static inline int pcie_lbms_count(struct pci_dev *port, unsigned long *val) 832 { 833 return -EOPNOTSUPP; 834 } 835 #endif 836 837 struct pci_dev_reset_methods { 838 u16 vendor; 839 u16 device; 840 int (*reset)(struct pci_dev *dev, bool probe); 841 }; 842 843 struct pci_reset_fn_method { 844 int (*reset_fn)(struct pci_dev *pdev, bool probe); 845 char *name; 846 }; 847 extern const struct pci_reset_fn_method pci_reset_fn_methods[]; 848 849 #ifdef CONFIG_PCI_QUIRKS 850 int pci_dev_specific_reset(struct pci_dev *dev, bool probe); 851 #else 852 static inline int pci_dev_specific_reset(struct pci_dev *dev, bool probe) 853 { 854 return -ENOTTY; 855 } 856 #endif 857 858 #if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64) 859 int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment, 860 struct resource *res); 861 #else 862 static inline int acpi_get_rc_resources(struct device *dev, const char *hid, 863 u16 segment, struct resource *res) 864 { 865 return -ENODEV; 866 } 867 #endif 868 869 void pci_rebar_init(struct pci_dev *pdev); 870 int pci_rebar_get_current_size(struct pci_dev *pdev, int bar); 871 int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size); 872 static inline u64 pci_rebar_size_to_bytes(int size) 873 { 874 return 1ULL << (size + 20); 875 } 876 877 struct device_node; 878 879 #ifdef CONFIG_OF 880 int of_get_pci_domain_nr(struct device_node *node); 881 int of_pci_get_max_link_speed(struct device_node *node); 882 u32 of_pci_get_slot_power_limit(struct device_node *node, 883 u8 *slot_power_limit_value, 884 u8 *slot_power_limit_scale); 885 bool of_pci_preserve_config(struct device_node *node); 886 int pci_set_of_node(struct pci_dev *dev); 887 void pci_release_of_node(struct pci_dev *dev); 888 void pci_set_bus_of_node(struct pci_bus *bus); 889 void pci_release_bus_of_node(struct pci_bus *bus); 890 891 int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge); 892 bool of_pci_supply_present(struct device_node *np); 893 894 #else 895 static inline int 896 of_get_pci_domain_nr(struct device_node *node) 897 { 898 return -1; 899 } 900 901 static inline int 902 of_pci_get_max_link_speed(struct device_node *node) 903 { 904 return -EINVAL; 905 } 906 907 static inline u32 908 of_pci_get_slot_power_limit(struct device_node *node, 909 u8 *slot_power_limit_value, 910 u8 *slot_power_limit_scale) 911 { 912 if (slot_power_limit_value) 913 *slot_power_limit_value = 0; 914 if (slot_power_limit_scale) 915 *slot_power_limit_scale = 0; 916 return 0; 917 } 918 919 static inline bool of_pci_preserve_config(struct device_node *node) 920 { 921 return false; 922 } 923 924 static inline int pci_set_of_node(struct pci_dev *dev) { return 0; } 925 static inline void pci_release_of_node(struct pci_dev *dev) { } 926 static inline void pci_set_bus_of_node(struct pci_bus *bus) { } 927 static inline void pci_release_bus_of_node(struct pci_bus *bus) { } 928 929 static inline int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge) 930 { 931 return 0; 932 } 933 934 static inline bool of_pci_supply_present(struct device_node *np) 935 { 936 return false; 937 } 938 #endif /* CONFIG_OF */ 939 940 struct of_changeset; 941 942 #ifdef CONFIG_PCI_DYNAMIC_OF_NODES 943 void of_pci_make_dev_node(struct pci_dev *pdev); 944 void of_pci_remove_node(struct pci_dev *pdev); 945 int of_pci_add_properties(struct pci_dev *pdev, struct of_changeset *ocs, 946 struct device_node *np); 947 void of_pci_make_host_bridge_node(struct pci_host_bridge *bridge); 948 void of_pci_remove_host_bridge_node(struct pci_host_bridge *bridge); 949 int of_pci_add_host_bridge_properties(struct pci_host_bridge *bridge, 950 struct of_changeset *ocs, 951 struct device_node *np); 952 #else 953 static inline void of_pci_make_dev_node(struct pci_dev *pdev) { } 954 static inline void of_pci_remove_node(struct pci_dev *pdev) { } 955 static inline void of_pci_make_host_bridge_node(struct pci_host_bridge *bridge) { } 956 static inline void of_pci_remove_host_bridge_node(struct pci_host_bridge *bridge) { } 957 #endif 958 959 #ifdef CONFIG_PCIEAER 960 void pci_no_aer(void); 961 void pci_aer_init(struct pci_dev *dev); 962 void pci_aer_exit(struct pci_dev *dev); 963 extern const struct attribute_group aer_stats_attr_group; 964 void pci_aer_clear_fatal_status(struct pci_dev *dev); 965 int pci_aer_clear_status(struct pci_dev *dev); 966 int pci_aer_raw_clear_status(struct pci_dev *dev); 967 void pci_save_aer_state(struct pci_dev *dev); 968 void pci_restore_aer_state(struct pci_dev *dev); 969 #else 970 static inline void pci_no_aer(void) { } 971 static inline void pci_aer_init(struct pci_dev *d) { } 972 static inline void pci_aer_exit(struct pci_dev *d) { } 973 static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { } 974 static inline int pci_aer_clear_status(struct pci_dev *dev) { return -EINVAL; } 975 static inline int pci_aer_raw_clear_status(struct pci_dev *dev) { return -EINVAL; } 976 static inline void pci_save_aer_state(struct pci_dev *dev) { } 977 static inline void pci_restore_aer_state(struct pci_dev *dev) { } 978 #endif 979 980 #ifdef CONFIG_ACPI 981 bool pci_acpi_preserve_config(struct pci_host_bridge *bridge); 982 int pci_acpi_program_hp_params(struct pci_dev *dev); 983 extern const struct attribute_group pci_dev_acpi_attr_group; 984 void pci_set_acpi_fwnode(struct pci_dev *dev); 985 int pci_dev_acpi_reset(struct pci_dev *dev, bool probe); 986 bool acpi_pci_power_manageable(struct pci_dev *dev); 987 bool acpi_pci_bridge_d3(struct pci_dev *dev); 988 int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state); 989 pci_power_t acpi_pci_get_power_state(struct pci_dev *dev); 990 void acpi_pci_refresh_power_state(struct pci_dev *dev); 991 int acpi_pci_wakeup(struct pci_dev *dev, bool enable); 992 bool acpi_pci_need_resume(struct pci_dev *dev); 993 pci_power_t acpi_pci_choose_state(struct pci_dev *pdev); 994 #else 995 static inline bool pci_acpi_preserve_config(struct pci_host_bridge *bridge) 996 { 997 return false; 998 } 999 static inline int pci_dev_acpi_reset(struct pci_dev *dev, bool probe) 1000 { 1001 return -ENOTTY; 1002 } 1003 static inline void pci_set_acpi_fwnode(struct pci_dev *dev) { } 1004 static inline int pci_acpi_program_hp_params(struct pci_dev *dev) 1005 { 1006 return -ENODEV; 1007 } 1008 static inline bool acpi_pci_power_manageable(struct pci_dev *dev) 1009 { 1010 return false; 1011 } 1012 static inline bool acpi_pci_bridge_d3(struct pci_dev *dev) 1013 { 1014 return false; 1015 } 1016 static inline int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state) 1017 { 1018 return -ENODEV; 1019 } 1020 static inline pci_power_t acpi_pci_get_power_state(struct pci_dev *dev) 1021 { 1022 return PCI_UNKNOWN; 1023 } 1024 static inline void acpi_pci_refresh_power_state(struct pci_dev *dev) { } 1025 static inline int acpi_pci_wakeup(struct pci_dev *dev, bool enable) 1026 { 1027 return -ENODEV; 1028 } 1029 static inline bool acpi_pci_need_resume(struct pci_dev *dev) 1030 { 1031 return false; 1032 } 1033 static inline pci_power_t acpi_pci_choose_state(struct pci_dev *pdev) 1034 { 1035 return PCI_POWER_ERROR; 1036 } 1037 #endif 1038 1039 #ifdef CONFIG_PCIEASPM 1040 extern const struct attribute_group aspm_ctrl_attr_group; 1041 #endif 1042 1043 #ifdef CONFIG_X86_INTEL_MID 1044 bool pci_use_mid_pm(void); 1045 int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state); 1046 pci_power_t mid_pci_get_power_state(struct pci_dev *pdev); 1047 #else 1048 static inline bool pci_use_mid_pm(void) 1049 { 1050 return false; 1051 } 1052 static inline int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state) 1053 { 1054 return -ENODEV; 1055 } 1056 static inline pci_power_t mid_pci_get_power_state(struct pci_dev *pdev) 1057 { 1058 return PCI_UNKNOWN; 1059 } 1060 #endif 1061 1062 int pcim_intx(struct pci_dev *dev, int enable); 1063 int pcim_request_region_exclusive(struct pci_dev *pdev, int bar, 1064 const char *name); 1065 void pcim_release_region(struct pci_dev *pdev, int bar); 1066 1067 /* 1068 * Config Address for PCI Configuration Mechanism #1 1069 * 1070 * See PCI Local Bus Specification, Revision 3.0, 1071 * Section 3.2.2.3.2, Figure 3-2, p. 50. 1072 */ 1073 1074 #define PCI_CONF1_BUS_SHIFT 16 /* Bus number */ 1075 #define PCI_CONF1_DEV_SHIFT 11 /* Device number */ 1076 #define PCI_CONF1_FUNC_SHIFT 8 /* Function number */ 1077 1078 #define PCI_CONF1_BUS_MASK 0xff 1079 #define PCI_CONF1_DEV_MASK 0x1f 1080 #define PCI_CONF1_FUNC_MASK 0x7 1081 #define PCI_CONF1_REG_MASK 0xfc /* Limit aligned offset to a maximum of 256B */ 1082 1083 #define PCI_CONF1_ENABLE BIT(31) 1084 #define PCI_CONF1_BUS(x) (((x) & PCI_CONF1_BUS_MASK) << PCI_CONF1_BUS_SHIFT) 1085 #define PCI_CONF1_DEV(x) (((x) & PCI_CONF1_DEV_MASK) << PCI_CONF1_DEV_SHIFT) 1086 #define PCI_CONF1_FUNC(x) (((x) & PCI_CONF1_FUNC_MASK) << PCI_CONF1_FUNC_SHIFT) 1087 #define PCI_CONF1_REG(x) ((x) & PCI_CONF1_REG_MASK) 1088 1089 #define PCI_CONF1_ADDRESS(bus, dev, func, reg) \ 1090 (PCI_CONF1_ENABLE | \ 1091 PCI_CONF1_BUS(bus) | \ 1092 PCI_CONF1_DEV(dev) | \ 1093 PCI_CONF1_FUNC(func) | \ 1094 PCI_CONF1_REG(reg)) 1095 1096 /* 1097 * Extension of PCI Config Address for accessing extended PCIe registers 1098 * 1099 * No standardized specification, but used on lot of non-ECAM-compliant ARM SoCs 1100 * or on AMD Barcelona and new CPUs. Reserved bits [27:24] of PCI Config Address 1101 * are used for specifying additional 4 high bits of PCI Express register. 1102 */ 1103 1104 #define PCI_CONF1_EXT_REG_SHIFT 16 1105 #define PCI_CONF1_EXT_REG_MASK 0xf00 1106 #define PCI_CONF1_EXT_REG(x) (((x) & PCI_CONF1_EXT_REG_MASK) << PCI_CONF1_EXT_REG_SHIFT) 1107 1108 #define PCI_CONF1_EXT_ADDRESS(bus, dev, func, reg) \ 1109 (PCI_CONF1_ADDRESS(bus, dev, func, reg) | \ 1110 PCI_CONF1_EXT_REG(reg)) 1111 1112 #endif /* DRIVERS_PCI_H */ 1113