1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef DRIVERS_PCI_H 3 #define DRIVERS_PCI_H 4 5 #include <linux/pci.h> 6 7 /* Number of possible devfns: 0.0 to 1f.7 inclusive */ 8 #define MAX_NR_DEVFNS 256 9 10 #define PCI_FIND_CAP_TTL 48 11 12 #define PCI_VSEC_ID_INTEL_TBT 0x1234 /* Thunderbolt */ 13 14 #define PCIE_LINK_RETRAIN_TIMEOUT_MS 1000 15 16 /* Power stable to PERST# inactive from PCIe card Electromechanical Spec */ 17 #define PCIE_T_PVPERL_MS 100 18 19 /* 20 * End of conventional reset (PERST# de-asserted) to first configuration 21 * request (device able to respond with a "Request Retry Status" completion), 22 * from PCIe r6.0, sec 6.6.1. 23 */ 24 #define PCIE_T_RRS_READY_MS 100 25 26 /* 27 * PCIe r6.0, sec 5.3.3.2.1 <PME Synchronization> 28 * Recommends 1ms to 10ms timeout to check L2 ready. 29 */ 30 #define PCIE_PME_TO_L2_TIMEOUT_US 10000 31 32 /* 33 * PCIe r6.0, sec 6.6.1 <Conventional Reset> 34 * 35 * - "With a Downstream Port that does not support Link speeds greater 36 * than 5.0 GT/s, software must wait a minimum of 100 ms following exit 37 * from a Conventional Reset before sending a Configuration Request to 38 * the device immediately below that Port." 39 * 40 * - "With a Downstream Port that supports Link speeds greater than 41 * 5.0 GT/s, software must wait a minimum of 100 ms after Link training 42 * completes before sending a Configuration Request to the device 43 * immediately below that Port." 44 */ 45 #define PCIE_RESET_CONFIG_DEVICE_WAIT_MS 100 46 47 /* Message Routing (r[2:0]); PCIe r6.0, sec 2.2.8 */ 48 #define PCIE_MSG_TYPE_R_RC 0 49 #define PCIE_MSG_TYPE_R_ADDR 1 50 #define PCIE_MSG_TYPE_R_ID 2 51 #define PCIE_MSG_TYPE_R_BC 3 52 #define PCIE_MSG_TYPE_R_LOCAL 4 53 #define PCIE_MSG_TYPE_R_GATHER 5 54 55 /* Power Management Messages; PCIe r6.0, sec 2.2.8.2 */ 56 #define PCIE_MSG_CODE_PME_TURN_OFF 0x19 57 58 /* INTx Mechanism Messages; PCIe r6.0, sec 2.2.8.1 */ 59 #define PCIE_MSG_CODE_ASSERT_INTA 0x20 60 #define PCIE_MSG_CODE_ASSERT_INTB 0x21 61 #define PCIE_MSG_CODE_ASSERT_INTC 0x22 62 #define PCIE_MSG_CODE_ASSERT_INTD 0x23 63 #define PCIE_MSG_CODE_DEASSERT_INTA 0x24 64 #define PCIE_MSG_CODE_DEASSERT_INTB 0x25 65 #define PCIE_MSG_CODE_DEASSERT_INTC 0x26 66 #define PCIE_MSG_CODE_DEASSERT_INTD 0x27 67 68 extern const unsigned char pcie_link_speed[]; 69 extern bool pci_early_dump; 70 71 bool pcie_cap_has_lnkctl(const struct pci_dev *dev); 72 bool pcie_cap_has_lnkctl2(const struct pci_dev *dev); 73 bool pcie_cap_has_rtctl(const struct pci_dev *dev); 74 75 /* Functions internal to the PCI core code */ 76 77 #ifdef CONFIG_DMI 78 extern const struct attribute_group pci_dev_smbios_attr_group; 79 #endif 80 81 enum pci_mmap_api { 82 PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */ 83 PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */ 84 }; 85 int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai, 86 enum pci_mmap_api mmap_api); 87 88 bool pci_reset_supported(struct pci_dev *dev); 89 void pci_init_reset_methods(struct pci_dev *dev); 90 int pci_bridge_secondary_bus_reset(struct pci_dev *dev); 91 int pci_bus_error_reset(struct pci_dev *dev); 92 93 struct pci_cap_saved_data { 94 u16 cap_nr; 95 bool cap_extended; 96 unsigned int size; 97 u32 data[]; 98 }; 99 100 struct pci_cap_saved_state { 101 struct hlist_node next; 102 struct pci_cap_saved_data cap; 103 }; 104 105 void pci_allocate_cap_save_buffers(struct pci_dev *dev); 106 void pci_free_cap_save_buffers(struct pci_dev *dev); 107 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size); 108 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, 109 u16 cap, unsigned int size); 110 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap); 111 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, 112 u16 cap); 113 114 #define PCI_PM_D2_DELAY 200 /* usec; see PCIe r4.0, sec 5.9.1 */ 115 #define PCI_PM_D3HOT_WAIT 10 /* msec */ 116 #define PCI_PM_D3COLD_WAIT 100 /* msec */ 117 118 void pci_update_current_state(struct pci_dev *dev, pci_power_t state); 119 void pci_refresh_power_state(struct pci_dev *dev); 120 int pci_power_up(struct pci_dev *dev); 121 void pci_disable_enabled_device(struct pci_dev *dev); 122 int pci_finish_runtime_suspend(struct pci_dev *dev); 123 void pcie_clear_device_status(struct pci_dev *dev); 124 void pcie_clear_root_pme_status(struct pci_dev *dev); 125 bool pci_check_pme_status(struct pci_dev *dev); 126 void pci_pme_wakeup_bus(struct pci_bus *bus); 127 int __pci_pme_wakeup(struct pci_dev *dev, void *ign); 128 void pci_pme_restore(struct pci_dev *dev); 129 bool pci_dev_need_resume(struct pci_dev *dev); 130 void pci_dev_adjust_pme(struct pci_dev *dev); 131 void pci_dev_complete_resume(struct pci_dev *pci_dev); 132 void pci_config_pm_runtime_get(struct pci_dev *dev); 133 void pci_config_pm_runtime_put(struct pci_dev *dev); 134 void pci_pm_init(struct pci_dev *dev); 135 void pci_ea_init(struct pci_dev *dev); 136 void pci_msi_init(struct pci_dev *dev); 137 void pci_msix_init(struct pci_dev *dev); 138 bool pci_bridge_d3_possible(struct pci_dev *dev); 139 void pci_bridge_d3_update(struct pci_dev *dev); 140 int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type); 141 142 static inline void pci_wakeup_event(struct pci_dev *dev) 143 { 144 /* Wait 100 ms before the system can be put into a sleep state. */ 145 pm_wakeup_event(&dev->dev, 100); 146 } 147 148 static inline bool pci_has_subordinate(struct pci_dev *pci_dev) 149 { 150 return !!(pci_dev->subordinate); 151 } 152 153 static inline bool pci_power_manageable(struct pci_dev *pci_dev) 154 { 155 /* 156 * Currently we allow normal PCI devices and PCI bridges transition 157 * into D3 if their bridge_d3 is set. 158 */ 159 return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3; 160 } 161 162 static inline bool pcie_downstream_port(const struct pci_dev *dev) 163 { 164 int type = pci_pcie_type(dev); 165 166 return type == PCI_EXP_TYPE_ROOT_PORT || 167 type == PCI_EXP_TYPE_DOWNSTREAM || 168 type == PCI_EXP_TYPE_PCIE_BRIDGE; 169 } 170 171 void pci_vpd_init(struct pci_dev *dev); 172 void pci_vpd_release(struct pci_dev *dev); 173 extern const struct attribute_group pci_dev_vpd_attr_group; 174 175 /* PCI Virtual Channel */ 176 int pci_save_vc_state(struct pci_dev *dev); 177 void pci_restore_vc_state(struct pci_dev *dev); 178 void pci_allocate_vc_save_buffers(struct pci_dev *dev); 179 180 /* PCI /proc functions */ 181 #ifdef CONFIG_PROC_FS 182 int pci_proc_attach_device(struct pci_dev *dev); 183 int pci_proc_detach_device(struct pci_dev *dev); 184 int pci_proc_detach_bus(struct pci_bus *bus); 185 #else 186 static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; } 187 static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; } 188 static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; } 189 #endif 190 191 /* Functions for PCI Hotplug drivers to use */ 192 int pci_hp_add_bridge(struct pci_dev *dev); 193 194 #if defined(CONFIG_SYSFS) && defined(HAVE_PCI_LEGACY) 195 void pci_create_legacy_files(struct pci_bus *bus); 196 void pci_remove_legacy_files(struct pci_bus *bus); 197 #else 198 static inline void pci_create_legacy_files(struct pci_bus *bus) { } 199 static inline void pci_remove_legacy_files(struct pci_bus *bus) { } 200 #endif 201 202 /* Lock for read/write access to pci device and bus lists */ 203 extern struct rw_semaphore pci_bus_sem; 204 extern struct mutex pci_slot_mutex; 205 206 extern raw_spinlock_t pci_lock; 207 208 extern unsigned int pci_pm_d3hot_delay; 209 210 #ifdef CONFIG_PCI_MSI 211 void pci_no_msi(void); 212 #else 213 static inline void pci_no_msi(void) { } 214 #endif 215 216 void pci_realloc_get_opt(char *); 217 218 static inline int pci_no_d1d2(struct pci_dev *dev) 219 { 220 unsigned int parent_dstates = 0; 221 222 if (dev->bus->self) 223 parent_dstates = dev->bus->self->no_d1d2; 224 return (dev->no_d1d2 || parent_dstates); 225 226 } 227 228 #ifdef CONFIG_SYSFS 229 int pci_create_sysfs_dev_files(struct pci_dev *pdev); 230 void pci_remove_sysfs_dev_files(struct pci_dev *pdev); 231 extern const struct attribute_group *pci_dev_groups[]; 232 extern const struct attribute_group *pci_dev_attr_groups[]; 233 extern const struct attribute_group *pcibus_groups[]; 234 extern const struct attribute_group *pci_bus_groups[]; 235 #else 236 static inline int pci_create_sysfs_dev_files(struct pci_dev *pdev) { return 0; } 237 static inline void pci_remove_sysfs_dev_files(struct pci_dev *pdev) { } 238 #define pci_dev_groups NULL 239 #define pci_dev_attr_groups NULL 240 #define pcibus_groups NULL 241 #define pci_bus_groups NULL 242 #endif 243 244 extern unsigned long pci_hotplug_io_size; 245 extern unsigned long pci_hotplug_mmio_size; 246 extern unsigned long pci_hotplug_mmio_pref_size; 247 extern unsigned long pci_hotplug_bus_size; 248 249 /** 250 * pci_match_one_device - Tell if a PCI device structure has a matching 251 * PCI device id structure 252 * @id: single PCI device id structure to match 253 * @dev: the PCI device structure to match against 254 * 255 * Returns the matching pci_device_id structure or %NULL if there is no match. 256 */ 257 static inline const struct pci_device_id * 258 pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev) 259 { 260 if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) && 261 (id->device == PCI_ANY_ID || id->device == dev->device) && 262 (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) && 263 (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) && 264 !((id->class ^ dev->class) & id->class_mask)) 265 return id; 266 return NULL; 267 } 268 269 /* PCI slot sysfs helper code */ 270 #define to_pci_slot(s) container_of(s, struct pci_slot, kobj) 271 272 extern struct kset *pci_slots_kset; 273 274 struct pci_slot_attribute { 275 struct attribute attr; 276 ssize_t (*show)(struct pci_slot *, char *); 277 ssize_t (*store)(struct pci_slot *, const char *, size_t); 278 }; 279 #define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr) 280 281 enum pci_bar_type { 282 pci_bar_unknown, /* Standard PCI BAR probe */ 283 pci_bar_io, /* An I/O port BAR */ 284 pci_bar_mem32, /* A 32-bit memory BAR */ 285 pci_bar_mem64, /* A 64-bit memory BAR */ 286 }; 287 288 struct device *pci_get_host_bridge_device(struct pci_dev *dev); 289 void pci_put_host_bridge_device(struct device *dev); 290 291 int pci_configure_extended_tags(struct pci_dev *dev, void *ign); 292 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl, 293 int crs_timeout); 294 bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl, 295 int crs_timeout); 296 int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *pl, int crs_timeout); 297 298 int pci_setup_device(struct pci_dev *dev); 299 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, 300 struct resource *res, unsigned int reg); 301 void pci_configure_ari(struct pci_dev *dev); 302 void __pci_bus_size_bridges(struct pci_bus *bus, 303 struct list_head *realloc_head); 304 void __pci_bus_assign_resources(const struct pci_bus *bus, 305 struct list_head *realloc_head, 306 struct list_head *fail_head); 307 bool pci_bus_clip_resource(struct pci_dev *dev, int idx); 308 309 const char *pci_resource_name(struct pci_dev *dev, unsigned int i); 310 311 void pci_reassigndev_resource_alignment(struct pci_dev *dev); 312 void pci_disable_bridge_window(struct pci_dev *dev); 313 struct pci_bus *pci_bus_get(struct pci_bus *bus); 314 void pci_bus_put(struct pci_bus *bus); 315 316 /* PCIe link information from Link Capabilities 2 */ 317 #define PCIE_LNKCAP2_SLS2SPEED(lnkcap2) \ 318 ((lnkcap2) & PCI_EXP_LNKCAP2_SLS_64_0GB ? PCIE_SPEED_64_0GT : \ 319 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_32_0GB ? PCIE_SPEED_32_0GT : \ 320 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_16_0GB ? PCIE_SPEED_16_0GT : \ 321 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_8_0GB ? PCIE_SPEED_8_0GT : \ 322 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_5_0GB ? PCIE_SPEED_5_0GT : \ 323 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_2_5GB ? PCIE_SPEED_2_5GT : \ 324 PCI_SPEED_UNKNOWN) 325 326 /* PCIe speed to Mb/s reduced by encoding overhead */ 327 #define PCIE_SPEED2MBS_ENC(speed) \ 328 ((speed) == PCIE_SPEED_64_0GT ? 64000*1/1 : \ 329 (speed) == PCIE_SPEED_32_0GT ? 32000*128/130 : \ 330 (speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \ 331 (speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \ 332 (speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \ 333 (speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \ 334 0) 335 336 static inline int pcie_dev_speed_mbps(enum pci_bus_speed speed) 337 { 338 switch (speed) { 339 case PCIE_SPEED_2_5GT: 340 return 2500; 341 case PCIE_SPEED_5_0GT: 342 return 5000; 343 case PCIE_SPEED_8_0GT: 344 return 8000; 345 case PCIE_SPEED_16_0GT: 346 return 16000; 347 case PCIE_SPEED_32_0GT: 348 return 32000; 349 case PCIE_SPEED_64_0GT: 350 return 64000; 351 default: 352 break; 353 } 354 355 return -EINVAL; 356 } 357 358 const char *pci_speed_string(enum pci_bus_speed speed); 359 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev); 360 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev); 361 void __pcie_print_link_status(struct pci_dev *dev, bool verbose); 362 void pcie_report_downtraining(struct pci_dev *dev); 363 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status); 364 365 /* Single Root I/O Virtualization */ 366 struct pci_sriov { 367 int pos; /* Capability position */ 368 int nres; /* Number of resources */ 369 u32 cap; /* SR-IOV Capabilities */ 370 u16 ctrl; /* SR-IOV Control */ 371 u16 total_VFs; /* Total VFs associated with the PF */ 372 u16 initial_VFs; /* Initial VFs associated with the PF */ 373 u16 num_VFs; /* Number of VFs available */ 374 u16 offset; /* First VF Routing ID offset */ 375 u16 stride; /* Following VF stride */ 376 u16 vf_device; /* VF device ID */ 377 u32 pgsz; /* Page size for BAR alignment */ 378 u8 link; /* Function Dependency Link */ 379 u8 max_VF_buses; /* Max buses consumed by VFs */ 380 u16 driver_max_VFs; /* Max num VFs driver supports */ 381 struct pci_dev *dev; /* Lowest numbered PF */ 382 struct pci_dev *self; /* This PF */ 383 u32 class; /* VF device */ 384 u8 hdr_type; /* VF header type */ 385 u16 subsystem_vendor; /* VF subsystem vendor */ 386 u16 subsystem_device; /* VF subsystem device */ 387 resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */ 388 bool drivers_autoprobe; /* Auto probing of VFs by driver */ 389 }; 390 391 #ifdef CONFIG_PCI_DOE 392 void pci_doe_init(struct pci_dev *pdev); 393 void pci_doe_destroy(struct pci_dev *pdev); 394 void pci_doe_disconnected(struct pci_dev *pdev); 395 #else 396 static inline void pci_doe_init(struct pci_dev *pdev) { } 397 static inline void pci_doe_destroy(struct pci_dev *pdev) { } 398 static inline void pci_doe_disconnected(struct pci_dev *pdev) { } 399 #endif 400 401 /** 402 * pci_dev_set_io_state - Set the new error state if possible. 403 * 404 * @dev: PCI device to set new error_state 405 * @new: the state we want dev to be in 406 * 407 * If the device is experiencing perm_failure, it has to remain in that state. 408 * Any other transition is allowed. 409 * 410 * Returns true if state has been changed to the requested state. 411 */ 412 static inline bool pci_dev_set_io_state(struct pci_dev *dev, 413 pci_channel_state_t new) 414 { 415 pci_channel_state_t old; 416 417 switch (new) { 418 case pci_channel_io_perm_failure: 419 xchg(&dev->error_state, pci_channel_io_perm_failure); 420 return true; 421 case pci_channel_io_frozen: 422 old = cmpxchg(&dev->error_state, pci_channel_io_normal, 423 pci_channel_io_frozen); 424 return old != pci_channel_io_perm_failure; 425 case pci_channel_io_normal: 426 old = cmpxchg(&dev->error_state, pci_channel_io_frozen, 427 pci_channel_io_normal); 428 return old != pci_channel_io_perm_failure; 429 default: 430 return false; 431 } 432 } 433 434 static inline int pci_dev_set_disconnected(struct pci_dev *dev, void *unused) 435 { 436 pci_dev_set_io_state(dev, pci_channel_io_perm_failure); 437 pci_doe_disconnected(dev); 438 439 return 0; 440 } 441 442 /* pci_dev priv_flags */ 443 #define PCI_DEV_ADDED 0 444 #define PCI_DPC_RECOVERED 1 445 #define PCI_DPC_RECOVERING 2 446 447 static inline void pci_dev_assign_added(struct pci_dev *dev, bool added) 448 { 449 assign_bit(PCI_DEV_ADDED, &dev->priv_flags, added); 450 } 451 452 static inline bool pci_dev_is_added(const struct pci_dev *dev) 453 { 454 return test_bit(PCI_DEV_ADDED, &dev->priv_flags); 455 } 456 457 #ifdef CONFIG_PCIEAER 458 #include <linux/aer.h> 459 460 #define AER_MAX_MULTI_ERR_DEVICES 5 /* Not likely to have more */ 461 462 struct aer_err_info { 463 struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES]; 464 int error_dev_num; 465 466 unsigned int id:16; 467 468 unsigned int severity:2; /* 0:NONFATAL | 1:FATAL | 2:COR */ 469 unsigned int __pad1:5; 470 unsigned int multi_error_valid:1; 471 472 unsigned int first_error:5; 473 unsigned int __pad2:2; 474 unsigned int tlp_header_valid:1; 475 476 unsigned int status; /* COR/UNCOR Error Status */ 477 unsigned int mask; /* COR/UNCOR Error Mask */ 478 struct pcie_tlp_log tlp; /* TLP Header */ 479 }; 480 481 int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info); 482 void aer_print_error(struct pci_dev *dev, struct aer_err_info *info); 483 #endif /* CONFIG_PCIEAER */ 484 485 #ifdef CONFIG_PCIEPORTBUS 486 /* Cached RCEC Endpoint Association */ 487 struct rcec_ea { 488 u8 nextbusn; 489 u8 lastbusn; 490 u32 bitmap; 491 }; 492 #endif 493 494 #ifdef CONFIG_PCIE_DPC 495 void pci_save_dpc_state(struct pci_dev *dev); 496 void pci_restore_dpc_state(struct pci_dev *dev); 497 void pci_dpc_init(struct pci_dev *pdev); 498 void dpc_process_error(struct pci_dev *pdev); 499 pci_ers_result_t dpc_reset_link(struct pci_dev *pdev); 500 bool pci_dpc_recovered(struct pci_dev *pdev); 501 #else 502 static inline void pci_save_dpc_state(struct pci_dev *dev) { } 503 static inline void pci_restore_dpc_state(struct pci_dev *dev) { } 504 static inline void pci_dpc_init(struct pci_dev *pdev) { } 505 static inline bool pci_dpc_recovered(struct pci_dev *pdev) { return false; } 506 #endif 507 508 #ifdef CONFIG_PCIEPORTBUS 509 void pci_rcec_init(struct pci_dev *dev); 510 void pci_rcec_exit(struct pci_dev *dev); 511 void pcie_link_rcec(struct pci_dev *rcec); 512 void pcie_walk_rcec(struct pci_dev *rcec, 513 int (*cb)(struct pci_dev *, void *), 514 void *userdata); 515 #else 516 static inline void pci_rcec_init(struct pci_dev *dev) { } 517 static inline void pci_rcec_exit(struct pci_dev *dev) { } 518 static inline void pcie_link_rcec(struct pci_dev *rcec) { } 519 static inline void pcie_walk_rcec(struct pci_dev *rcec, 520 int (*cb)(struct pci_dev *, void *), 521 void *userdata) { } 522 #endif 523 524 #ifdef CONFIG_PCI_ATS 525 /* Address Translation Service */ 526 void pci_ats_init(struct pci_dev *dev); 527 void pci_restore_ats_state(struct pci_dev *dev); 528 #else 529 static inline void pci_ats_init(struct pci_dev *d) { } 530 static inline void pci_restore_ats_state(struct pci_dev *dev) { } 531 #endif /* CONFIG_PCI_ATS */ 532 533 #ifdef CONFIG_PCI_PRI 534 void pci_pri_init(struct pci_dev *dev); 535 void pci_restore_pri_state(struct pci_dev *pdev); 536 #else 537 static inline void pci_pri_init(struct pci_dev *dev) { } 538 static inline void pci_restore_pri_state(struct pci_dev *pdev) { } 539 #endif 540 541 #ifdef CONFIG_PCI_PASID 542 void pci_pasid_init(struct pci_dev *dev); 543 void pci_restore_pasid_state(struct pci_dev *pdev); 544 #else 545 static inline void pci_pasid_init(struct pci_dev *dev) { } 546 static inline void pci_restore_pasid_state(struct pci_dev *pdev) { } 547 #endif 548 549 #ifdef CONFIG_PCI_IOV 550 int pci_iov_init(struct pci_dev *dev); 551 void pci_iov_release(struct pci_dev *dev); 552 void pci_iov_remove(struct pci_dev *dev); 553 void pci_iov_update_resource(struct pci_dev *dev, int resno); 554 resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno); 555 void pci_restore_iov_state(struct pci_dev *dev); 556 int pci_iov_bus_range(struct pci_bus *bus); 557 extern const struct attribute_group sriov_pf_dev_attr_group; 558 extern const struct attribute_group sriov_vf_dev_attr_group; 559 #else 560 static inline int pci_iov_init(struct pci_dev *dev) 561 { 562 return -ENODEV; 563 } 564 static inline void pci_iov_release(struct pci_dev *dev) { } 565 static inline void pci_iov_remove(struct pci_dev *dev) { } 566 static inline void pci_restore_iov_state(struct pci_dev *dev) { } 567 static inline int pci_iov_bus_range(struct pci_bus *bus) 568 { 569 return 0; 570 } 571 572 #endif /* CONFIG_PCI_IOV */ 573 574 #ifdef CONFIG_PCIE_PTM 575 void pci_ptm_init(struct pci_dev *dev); 576 void pci_save_ptm_state(struct pci_dev *dev); 577 void pci_restore_ptm_state(struct pci_dev *dev); 578 void pci_suspend_ptm(struct pci_dev *dev); 579 void pci_resume_ptm(struct pci_dev *dev); 580 #else 581 static inline void pci_ptm_init(struct pci_dev *dev) { } 582 static inline void pci_save_ptm_state(struct pci_dev *dev) { } 583 static inline void pci_restore_ptm_state(struct pci_dev *dev) { } 584 static inline void pci_suspend_ptm(struct pci_dev *dev) { } 585 static inline void pci_resume_ptm(struct pci_dev *dev) { } 586 #endif 587 588 unsigned long pci_cardbus_resource_alignment(struct resource *); 589 590 static inline resource_size_t pci_resource_alignment(struct pci_dev *dev, 591 struct resource *res) 592 { 593 #ifdef CONFIG_PCI_IOV 594 int resno = res - dev->resource; 595 596 if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END) 597 return pci_sriov_resource_alignment(dev, resno); 598 #endif 599 if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS) 600 return pci_cardbus_resource_alignment(res); 601 return resource_alignment(res); 602 } 603 604 void pci_acs_init(struct pci_dev *dev); 605 #ifdef CONFIG_PCI_QUIRKS 606 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags); 607 int pci_dev_specific_enable_acs(struct pci_dev *dev); 608 int pci_dev_specific_disable_acs_redir(struct pci_dev *dev); 609 bool pcie_failed_link_retrain(struct pci_dev *dev); 610 #else 611 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev, 612 u16 acs_flags) 613 { 614 return -ENOTTY; 615 } 616 static inline int pci_dev_specific_enable_acs(struct pci_dev *dev) 617 { 618 return -ENOTTY; 619 } 620 static inline int pci_dev_specific_disable_acs_redir(struct pci_dev *dev) 621 { 622 return -ENOTTY; 623 } 624 static inline bool pcie_failed_link_retrain(struct pci_dev *dev) 625 { 626 return false; 627 } 628 #endif 629 630 /* PCI error reporting and recovery */ 631 pci_ers_result_t pcie_do_recovery(struct pci_dev *dev, 632 pci_channel_state_t state, 633 pci_ers_result_t (*reset_subordinates)(struct pci_dev *pdev)); 634 635 bool pcie_wait_for_link(struct pci_dev *pdev, bool active); 636 int pcie_retrain_link(struct pci_dev *pdev, bool use_lt); 637 638 /* ASPM-related functionality we need even without CONFIG_PCIEASPM */ 639 void pci_save_ltr_state(struct pci_dev *dev); 640 void pci_restore_ltr_state(struct pci_dev *dev); 641 void pci_configure_aspm_l1ss(struct pci_dev *dev); 642 void pci_save_aspm_l1ss_state(struct pci_dev *dev); 643 void pci_restore_aspm_l1ss_state(struct pci_dev *dev); 644 645 #ifdef CONFIG_PCIEASPM 646 void pcie_aspm_init_link_state(struct pci_dev *pdev); 647 void pcie_aspm_exit_link_state(struct pci_dev *pdev); 648 void pcie_aspm_pm_state_change(struct pci_dev *pdev, bool locked); 649 void pcie_aspm_powersave_config_link(struct pci_dev *pdev); 650 void pci_configure_ltr(struct pci_dev *pdev); 651 void pci_bridge_reconfigure_ltr(struct pci_dev *pdev); 652 #else 653 static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { } 654 static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { } 655 static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev, bool locked) { } 656 static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { } 657 static inline void pci_configure_ltr(struct pci_dev *pdev) { } 658 static inline void pci_bridge_reconfigure_ltr(struct pci_dev *pdev) { } 659 #endif 660 661 #ifdef CONFIG_PCIE_ECRC 662 void pcie_set_ecrc_checking(struct pci_dev *dev); 663 void pcie_ecrc_get_policy(char *str); 664 #else 665 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { } 666 static inline void pcie_ecrc_get_policy(char *str) { } 667 #endif 668 669 struct pci_dev_reset_methods { 670 u16 vendor; 671 u16 device; 672 int (*reset)(struct pci_dev *dev, bool probe); 673 }; 674 675 struct pci_reset_fn_method { 676 int (*reset_fn)(struct pci_dev *pdev, bool probe); 677 char *name; 678 }; 679 680 #ifdef CONFIG_PCI_QUIRKS 681 int pci_dev_specific_reset(struct pci_dev *dev, bool probe); 682 #else 683 static inline int pci_dev_specific_reset(struct pci_dev *dev, bool probe) 684 { 685 return -ENOTTY; 686 } 687 #endif 688 689 #if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64) 690 int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment, 691 struct resource *res); 692 #else 693 static inline int acpi_get_rc_resources(struct device *dev, const char *hid, 694 u16 segment, struct resource *res) 695 { 696 return -ENODEV; 697 } 698 #endif 699 700 int pci_rebar_get_current_size(struct pci_dev *pdev, int bar); 701 int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size); 702 static inline u64 pci_rebar_size_to_bytes(int size) 703 { 704 return 1ULL << (size + 20); 705 } 706 707 struct device_node; 708 709 #ifdef CONFIG_OF 710 int of_pci_parse_bus_range(struct device_node *node, struct resource *res); 711 int of_get_pci_domain_nr(struct device_node *node); 712 int of_pci_get_max_link_speed(struct device_node *node); 713 u32 of_pci_get_slot_power_limit(struct device_node *node, 714 u8 *slot_power_limit_value, 715 u8 *slot_power_limit_scale); 716 bool of_pci_preserve_config(struct device_node *node); 717 int pci_set_of_node(struct pci_dev *dev); 718 void pci_release_of_node(struct pci_dev *dev); 719 void pci_set_bus_of_node(struct pci_bus *bus); 720 void pci_release_bus_of_node(struct pci_bus *bus); 721 722 int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge); 723 724 #else 725 static inline int 726 of_pci_parse_bus_range(struct device_node *node, struct resource *res) 727 { 728 return -EINVAL; 729 } 730 731 static inline int 732 of_get_pci_domain_nr(struct device_node *node) 733 { 734 return -1; 735 } 736 737 static inline int 738 of_pci_get_max_link_speed(struct device_node *node) 739 { 740 return -EINVAL; 741 } 742 743 static inline u32 744 of_pci_get_slot_power_limit(struct device_node *node, 745 u8 *slot_power_limit_value, 746 u8 *slot_power_limit_scale) 747 { 748 if (slot_power_limit_value) 749 *slot_power_limit_value = 0; 750 if (slot_power_limit_scale) 751 *slot_power_limit_scale = 0; 752 return 0; 753 } 754 755 static inline bool of_pci_preserve_config(struct device_node *node) 756 { 757 return false; 758 } 759 760 static inline int pci_set_of_node(struct pci_dev *dev) { return 0; } 761 static inline void pci_release_of_node(struct pci_dev *dev) { } 762 static inline void pci_set_bus_of_node(struct pci_bus *bus) { } 763 static inline void pci_release_bus_of_node(struct pci_bus *bus) { } 764 765 static inline int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge) 766 { 767 return 0; 768 } 769 770 #endif /* CONFIG_OF */ 771 772 struct of_changeset; 773 774 #ifdef CONFIG_PCI_DYNAMIC_OF_NODES 775 void of_pci_make_dev_node(struct pci_dev *pdev); 776 void of_pci_remove_node(struct pci_dev *pdev); 777 int of_pci_add_properties(struct pci_dev *pdev, struct of_changeset *ocs, 778 struct device_node *np); 779 #else 780 static inline void of_pci_make_dev_node(struct pci_dev *pdev) { } 781 static inline void of_pci_remove_node(struct pci_dev *pdev) { } 782 #endif 783 784 #ifdef CONFIG_PCIEAER 785 void pci_no_aer(void); 786 void pci_aer_init(struct pci_dev *dev); 787 void pci_aer_exit(struct pci_dev *dev); 788 extern const struct attribute_group aer_stats_attr_group; 789 void pci_aer_clear_fatal_status(struct pci_dev *dev); 790 int pci_aer_clear_status(struct pci_dev *dev); 791 int pci_aer_raw_clear_status(struct pci_dev *dev); 792 void pci_save_aer_state(struct pci_dev *dev); 793 void pci_restore_aer_state(struct pci_dev *dev); 794 #else 795 static inline void pci_no_aer(void) { } 796 static inline void pci_aer_init(struct pci_dev *d) { } 797 static inline void pci_aer_exit(struct pci_dev *d) { } 798 static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { } 799 static inline int pci_aer_clear_status(struct pci_dev *dev) { return -EINVAL; } 800 static inline int pci_aer_raw_clear_status(struct pci_dev *dev) { return -EINVAL; } 801 static inline void pci_save_aer_state(struct pci_dev *dev) { } 802 static inline void pci_restore_aer_state(struct pci_dev *dev) { } 803 #endif 804 805 #ifdef CONFIG_ACPI 806 bool pci_acpi_preserve_config(struct pci_host_bridge *bridge); 807 int pci_acpi_program_hp_params(struct pci_dev *dev); 808 extern const struct attribute_group pci_dev_acpi_attr_group; 809 void pci_set_acpi_fwnode(struct pci_dev *dev); 810 int pci_dev_acpi_reset(struct pci_dev *dev, bool probe); 811 bool acpi_pci_power_manageable(struct pci_dev *dev); 812 bool acpi_pci_bridge_d3(struct pci_dev *dev); 813 int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state); 814 pci_power_t acpi_pci_get_power_state(struct pci_dev *dev); 815 void acpi_pci_refresh_power_state(struct pci_dev *dev); 816 int acpi_pci_wakeup(struct pci_dev *dev, bool enable); 817 bool acpi_pci_need_resume(struct pci_dev *dev); 818 pci_power_t acpi_pci_choose_state(struct pci_dev *pdev); 819 #else 820 static inline bool pci_acpi_preserve_config(struct pci_host_bridge *bridge) 821 { 822 return false; 823 } 824 static inline int pci_dev_acpi_reset(struct pci_dev *dev, bool probe) 825 { 826 return -ENOTTY; 827 } 828 static inline void pci_set_acpi_fwnode(struct pci_dev *dev) { } 829 static inline int pci_acpi_program_hp_params(struct pci_dev *dev) 830 { 831 return -ENODEV; 832 } 833 static inline bool acpi_pci_power_manageable(struct pci_dev *dev) 834 { 835 return false; 836 } 837 static inline bool acpi_pci_bridge_d3(struct pci_dev *dev) 838 { 839 return false; 840 } 841 static inline int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state) 842 { 843 return -ENODEV; 844 } 845 static inline pci_power_t acpi_pci_get_power_state(struct pci_dev *dev) 846 { 847 return PCI_UNKNOWN; 848 } 849 static inline void acpi_pci_refresh_power_state(struct pci_dev *dev) { } 850 static inline int acpi_pci_wakeup(struct pci_dev *dev, bool enable) 851 { 852 return -ENODEV; 853 } 854 static inline bool acpi_pci_need_resume(struct pci_dev *dev) 855 { 856 return false; 857 } 858 static inline pci_power_t acpi_pci_choose_state(struct pci_dev *pdev) 859 { 860 return PCI_POWER_ERROR; 861 } 862 #endif 863 864 #ifdef CONFIG_PCIEASPM 865 extern const struct attribute_group aspm_ctrl_attr_group; 866 #endif 867 868 extern const struct attribute_group pci_dev_reset_method_attr_group; 869 870 #ifdef CONFIG_X86_INTEL_MID 871 bool pci_use_mid_pm(void); 872 int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state); 873 pci_power_t mid_pci_get_power_state(struct pci_dev *pdev); 874 #else 875 static inline bool pci_use_mid_pm(void) 876 { 877 return false; 878 } 879 static inline int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state) 880 { 881 return -ENODEV; 882 } 883 static inline pci_power_t mid_pci_get_power_state(struct pci_dev *pdev) 884 { 885 return PCI_UNKNOWN; 886 } 887 #endif 888 889 int pcim_intx(struct pci_dev *dev, int enable); 890 891 int pcim_request_region(struct pci_dev *pdev, int bar, const char *name); 892 int pcim_request_region_exclusive(struct pci_dev *pdev, int bar, 893 const char *name); 894 void pcim_release_region(struct pci_dev *pdev, int bar); 895 896 /* 897 * Config Address for PCI Configuration Mechanism #1 898 * 899 * See PCI Local Bus Specification, Revision 3.0, 900 * Section 3.2.2.3.2, Figure 3-2, p. 50. 901 */ 902 903 #define PCI_CONF1_BUS_SHIFT 16 /* Bus number */ 904 #define PCI_CONF1_DEV_SHIFT 11 /* Device number */ 905 #define PCI_CONF1_FUNC_SHIFT 8 /* Function number */ 906 907 #define PCI_CONF1_BUS_MASK 0xff 908 #define PCI_CONF1_DEV_MASK 0x1f 909 #define PCI_CONF1_FUNC_MASK 0x7 910 #define PCI_CONF1_REG_MASK 0xfc /* Limit aligned offset to a maximum of 256B */ 911 912 #define PCI_CONF1_ENABLE BIT(31) 913 #define PCI_CONF1_BUS(x) (((x) & PCI_CONF1_BUS_MASK) << PCI_CONF1_BUS_SHIFT) 914 #define PCI_CONF1_DEV(x) (((x) & PCI_CONF1_DEV_MASK) << PCI_CONF1_DEV_SHIFT) 915 #define PCI_CONF1_FUNC(x) (((x) & PCI_CONF1_FUNC_MASK) << PCI_CONF1_FUNC_SHIFT) 916 #define PCI_CONF1_REG(x) ((x) & PCI_CONF1_REG_MASK) 917 918 #define PCI_CONF1_ADDRESS(bus, dev, func, reg) \ 919 (PCI_CONF1_ENABLE | \ 920 PCI_CONF1_BUS(bus) | \ 921 PCI_CONF1_DEV(dev) | \ 922 PCI_CONF1_FUNC(func) | \ 923 PCI_CONF1_REG(reg)) 924 925 /* 926 * Extension of PCI Config Address for accessing extended PCIe registers 927 * 928 * No standardized specification, but used on lot of non-ECAM-compliant ARM SoCs 929 * or on AMD Barcelona and new CPUs. Reserved bits [27:24] of PCI Config Address 930 * are used for specifying additional 4 high bits of PCI Express register. 931 */ 932 933 #define PCI_CONF1_EXT_REG_SHIFT 16 934 #define PCI_CONF1_EXT_REG_MASK 0xf00 935 #define PCI_CONF1_EXT_REG(x) (((x) & PCI_CONF1_EXT_REG_MASK) << PCI_CONF1_EXT_REG_SHIFT) 936 937 #define PCI_CONF1_EXT_ADDRESS(bus, dev, func, reg) \ 938 (PCI_CONF1_ADDRESS(bus, dev, func, reg) | \ 939 PCI_CONF1_EXT_REG(reg)) 940 941 #endif /* DRIVERS_PCI_H */ 942