1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef DRIVERS_PCI_H 3 #define DRIVERS_PCI_H 4 5 #include <linux/bug.h> 6 #include <linux/align.h> 7 #include <linux/bitfield.h> 8 #include <linux/pci.h> 9 #include <trace/events/pci.h> 10 11 struct pcie_tlp_log; 12 13 /* Number of possible devfns: 0.0 to 1f.7 inclusive */ 14 #define MAX_NR_DEVFNS 256 15 #define PCI_MAX_NR_DEVS 32 16 17 #define MAX_NR_LANES 16 18 19 #define PCI_FIND_CAP_TTL 48 20 21 #define PCI_VSEC_ID_INTEL_TBT 0x1234 /* Thunderbolt */ 22 23 #define PCIE_LINK_RETRAIN_TIMEOUT_MS 1000 24 25 /* 26 * Power stable to PERST# inactive. 27 * 28 * See the "Power Sequencing and Reset Signal Timings" table of the PCI Express 29 * Card Electromechanical Specification, Revision 5.1, Section 2.9.2, Symbol 30 * "T_PVPERL". 31 */ 32 #define PCIE_T_PVPERL_MS 100 33 34 /* 35 * REFCLK stable before PERST# inactive. 36 * 37 * See the "Power Sequencing and Reset Signal Timings" table of the PCI Express 38 * Card Electromechanical Specification, Revision 5.1, Section 2.9.2, Symbol 39 * "T_PERST-CLK". 40 */ 41 #define PCIE_T_PERST_CLK_US 100 42 43 /* 44 * PCIe r6.0, sec 5.3.3.2.1 <PME Synchronization> 45 * Recommends 1ms to 10ms timeout to check L2 ready. 46 */ 47 #define PCIE_PME_TO_L2_TIMEOUT_US 10000 48 49 /* 50 * PCIe r6.0, sec 6.6.1 <Conventional Reset> 51 * 52 * - "With a Downstream Port that does not support Link speeds greater 53 * than 5.0 GT/s, software must wait a minimum of 100 ms following exit 54 * from a Conventional Reset before sending a Configuration Request to 55 * the device immediately below that Port." 56 * 57 * - "With a Downstream Port that supports Link speeds greater than 58 * 5.0 GT/s, software must wait a minimum of 100 ms after Link training 59 * completes before sending a Configuration Request to the device 60 * immediately below that Port." 61 */ 62 #define PCIE_RESET_CONFIG_WAIT_MS 100 63 64 /* Parameters for the waiting for link up routine */ 65 #define PCIE_LINK_WAIT_MAX_RETRIES 10 66 #define PCIE_LINK_WAIT_SLEEP_MS 90 67 68 /* Format of TLP; PCIe r7.0, sec 2.2.1 */ 69 #define PCIE_TLP_FMT_3DW_NO_DATA 0x00 /* 3DW header, no data */ 70 #define PCIE_TLP_FMT_4DW_NO_DATA 0x01 /* 4DW header, no data */ 71 #define PCIE_TLP_FMT_3DW_DATA 0x02 /* 3DW header, with data */ 72 #define PCIE_TLP_FMT_4DW_DATA 0x03 /* 4DW header, with data */ 73 74 /* Type of TLP; PCIe r7.0, sec 2.2.1 */ 75 #define PCIE_TLP_TYPE_MEM_RDWR 0x00 /* Memory Read/Write Request */ 76 #define PCIE_TLP_TYPE_IO_RDWR 0x02 /* I/O Read/Write Request */ 77 #define PCIE_TLP_TYPE_CFG0_RDWR 0x04 /* Config Type 0 Read/Write Request */ 78 #define PCIE_TLP_TYPE_CFG1_RDWR 0x05 /* Config Type 1 Read/Write Request */ 79 #define PCIE_TLP_TYPE_MSG 0x10 /* Message With/Without data Request */ 80 81 /* Message Routing (r[2:0]); PCIe r6.0, sec 2.2.8 */ 82 #define PCIE_MSG_TYPE_R_RC 0 83 #define PCIE_MSG_TYPE_R_ADDR 1 84 #define PCIE_MSG_TYPE_R_ID 2 85 #define PCIE_MSG_TYPE_R_BC 3 86 #define PCIE_MSG_TYPE_R_LOCAL 4 87 #define PCIE_MSG_TYPE_R_GATHER 5 88 89 /* Power Management Messages; PCIe r6.0, sec 2.2.8.2 */ 90 #define PCIE_MSG_CODE_PME_TURN_OFF 0x19 91 92 /* INTx Mechanism Messages; PCIe r6.0, sec 2.2.8.1 */ 93 #define PCIE_MSG_CODE_ASSERT_INTA 0x20 94 #define PCIE_MSG_CODE_ASSERT_INTB 0x21 95 #define PCIE_MSG_CODE_ASSERT_INTC 0x22 96 #define PCIE_MSG_CODE_ASSERT_INTD 0x23 97 #define PCIE_MSG_CODE_DEASSERT_INTA 0x24 98 #define PCIE_MSG_CODE_DEASSERT_INTB 0x25 99 #define PCIE_MSG_CODE_DEASSERT_INTC 0x26 100 #define PCIE_MSG_CODE_DEASSERT_INTD 0x27 101 102 /* Cpl. status of Complete; PCIe r7.0, sec 2.2.9.1 */ 103 #define PCIE_CPL_STS_SUCCESS 0x00 /* Successful Completion */ 104 105 #define PCI_BUS_BRIDGE_IO_WINDOW 0 106 #define PCI_BUS_BRIDGE_MEM_WINDOW 1 107 #define PCI_BUS_BRIDGE_PREF_MEM_WINDOW 2 108 109 #define PCI_EXP_AER_FLAGS (PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE | \ 110 PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE) 111 112 extern const unsigned char pcie_link_speed[]; 113 unsigned char pcie_get_link_speed(unsigned int speed); 114 115 extern bool pci_early_dump; 116 117 extern struct mutex pci_rescan_remove_lock; 118 119 bool pcie_cap_has_lnkctl(const struct pci_dev *dev); 120 bool pcie_cap_has_lnkctl2(const struct pci_dev *dev); 121 bool pcie_cap_has_rtctl(const struct pci_dev *dev); 122 123 /* Standard Capability finder */ 124 /** 125 * PCI_FIND_NEXT_CAP - Find a PCI standard capability 126 * @read_cfg: Function pointer for reading PCI config space 127 * @start: Starting position to begin search 128 * @cap: Capability ID to find 129 * @prev_ptr: Pointer to store position of preceding capability (optional) 130 * @args: Arguments to pass to read_cfg function 131 * 132 * Search the capability list in PCI config space to find @cap. If 133 * found, update *prev_ptr with the position of the preceding capability 134 * (if prev_ptr != NULL) 135 * Implements TTL (time-to-live) protection against infinite loops. 136 * 137 * Return: Position of the capability if found, 0 otherwise. 138 */ 139 #define PCI_FIND_NEXT_CAP(read_cfg, start, cap, prev_ptr, args...) \ 140 ({ \ 141 int __ttl = PCI_FIND_CAP_TTL; \ 142 u8 __id, __found_pos = 0; \ 143 u8 __prev_pos = (start); \ 144 u8 __pos = (start); \ 145 u16 __ent; \ 146 \ 147 read_cfg##_byte(args, __pos, &__pos); \ 148 \ 149 while (__ttl--) { \ 150 if (__pos < PCI_STD_HEADER_SIZEOF) \ 151 break; \ 152 \ 153 __pos = ALIGN_DOWN(__pos, 4); \ 154 read_cfg##_word(args, __pos, &__ent); \ 155 \ 156 __id = FIELD_GET(PCI_CAP_ID_MASK, __ent); \ 157 if (__id == 0xff) \ 158 break; \ 159 \ 160 if (__id == (cap)) { \ 161 __found_pos = __pos; \ 162 if (prev_ptr != NULL) \ 163 *(u8 *)prev_ptr = __prev_pos; \ 164 break; \ 165 } \ 166 \ 167 __prev_pos = __pos; \ 168 __pos = FIELD_GET(PCI_CAP_LIST_NEXT_MASK, __ent); \ 169 } \ 170 __found_pos; \ 171 }) 172 173 /* Extended Capability finder */ 174 /** 175 * PCI_FIND_NEXT_EXT_CAP - Find a PCI extended capability 176 * @read_cfg: Function pointer for reading PCI config space 177 * @start: Starting position to begin search (0 for initial search) 178 * @cap: Extended capability ID to find 179 * @prev_ptr: Pointer to store position of preceding capability (optional) 180 * @args: Arguments to pass to read_cfg function 181 * 182 * Search the extended capability list in PCI config space to find @cap. 183 * If found, update *prev_ptr with the position of the preceding capability 184 * (if prev_ptr != NULL) 185 * Implements TTL protection against infinite loops using a calculated 186 * maximum search count. 187 * 188 * Return: Position of the capability if found, 0 otherwise. 189 */ 190 #define PCI_FIND_NEXT_EXT_CAP(read_cfg, start, cap, prev_ptr, args...) \ 191 ({ \ 192 u16 __pos = (start) ?: PCI_CFG_SPACE_SIZE; \ 193 u16 __found_pos = 0; \ 194 u16 __prev_pos; \ 195 int __ttl, __ret; \ 196 u32 __header; \ 197 \ 198 __prev_pos = __pos; \ 199 __ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; \ 200 while (__ttl-- > 0 && __pos >= PCI_CFG_SPACE_SIZE) { \ 201 __ret = read_cfg##_dword(args, __pos, &__header); \ 202 if (__ret != PCIBIOS_SUCCESSFUL) \ 203 break; \ 204 \ 205 if (__header == 0) \ 206 break; \ 207 \ 208 if (PCI_EXT_CAP_ID(__header) == (cap) && __pos != start) {\ 209 __found_pos = __pos; \ 210 if (prev_ptr != NULL) \ 211 *(u16 *)prev_ptr = __prev_pos; \ 212 break; \ 213 } \ 214 \ 215 __prev_pos = __pos; \ 216 __pos = PCI_EXT_CAP_NEXT(__header); \ 217 } \ 218 __found_pos; \ 219 }) 220 221 /* Functions internal to the PCI core code */ 222 223 #ifdef CONFIG_DMI 224 extern const struct attribute_group pci_dev_smbios_attr_group; 225 #endif 226 227 enum pci_mmap_api { 228 PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */ 229 PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */ 230 }; 231 int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai, 232 enum pci_mmap_api mmap_api); 233 234 bool pci_reset_supported(struct pci_dev *dev); 235 void pci_init_reset_methods(struct pci_dev *dev); 236 int pci_bridge_secondary_bus_reset(struct pci_dev *dev); 237 int pci_bus_error_reset(struct pci_dev *dev); 238 int pci_try_reset_bridge(struct pci_dev *bridge); 239 240 struct pci_cap_saved_data { 241 u16 cap_nr; 242 bool cap_extended; 243 unsigned int size; 244 u32 data[]; 245 }; 246 247 struct pci_cap_saved_state { 248 struct hlist_node next; 249 struct pci_cap_saved_data cap; 250 }; 251 252 void pci_allocate_cap_save_buffers(struct pci_dev *dev); 253 void pci_free_cap_save_buffers(struct pci_dev *dev); 254 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size); 255 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, 256 u16 cap, unsigned int size); 257 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap); 258 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, 259 u16 cap); 260 261 #define PCI_PM_D2_DELAY 200 /* usec; see PCIe r4.0, sec 5.9.1 */ 262 #define PCI_PM_D3HOT_WAIT 10 /* msec */ 263 #define PCI_PM_D3COLD_WAIT 100 /* msec */ 264 265 void pci_update_current_state(struct pci_dev *dev, pci_power_t state); 266 void pci_refresh_power_state(struct pci_dev *dev); 267 int pci_power_up(struct pci_dev *dev); 268 void pci_disable_enabled_device(struct pci_dev *dev); 269 int pci_finish_runtime_suspend(struct pci_dev *dev); 270 void pcie_clear_device_status(struct pci_dev *dev); 271 void pcie_clear_root_pme_status(struct pci_dev *dev); 272 bool pci_check_pme_status(struct pci_dev *dev); 273 void pci_pme_wakeup_bus(struct pci_bus *bus); 274 void pci_pme_restore(struct pci_dev *dev); 275 bool pci_dev_need_resume(struct pci_dev *dev); 276 void pci_dev_adjust_pme(struct pci_dev *dev); 277 void pci_dev_complete_resume(struct pci_dev *pci_dev); 278 void pci_config_pm_runtime_get(struct pci_dev *dev); 279 void pci_config_pm_runtime_put(struct pci_dev *dev); 280 void pci_pm_power_up_and_verify_state(struct pci_dev *pci_dev); 281 void pci_pm_init(struct pci_dev *dev); 282 void pci_ea_init(struct pci_dev *dev); 283 bool pci_ea_fixed_busnrs(struct pci_dev *dev, u8 *sec, u8 *sub); 284 void pci_msi_init(struct pci_dev *dev); 285 void pci_msix_init(struct pci_dev *dev); 286 bool pci_bridge_d3_possible(struct pci_dev *dev); 287 void pci_bridge_d3_update(struct pci_dev *dev); 288 int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type); 289 void platform_pci_configure_wake(struct pci_dev *dev); 290 void platform_pci_remove_wake(struct pci_dev *dev); 291 292 static inline bool pci_bus_rrs_vendor_id(u32 l) 293 { 294 return (l & 0xffff) == PCI_VENDOR_ID_PCI_SIG; 295 } 296 297 static inline void pci_wakeup_event(struct pci_dev *dev) 298 { 299 /* Wait 100 ms before the system can be put into a sleep state. */ 300 pm_wakeup_event(&dev->dev, 100); 301 } 302 303 /** 304 * pci_bar_index_is_valid - Check whether a BAR index is within valid range 305 * @bar: BAR index 306 * 307 * Protects against overflowing &struct pci_dev.resource array. 308 * 309 * Return: true for valid index, false otherwise. 310 */ 311 static inline bool pci_bar_index_is_valid(int bar) 312 { 313 if (bar >= 0 && bar < PCI_NUM_RESOURCES) 314 return true; 315 316 return false; 317 } 318 319 static inline bool pci_has_subordinate(struct pci_dev *pci_dev) 320 { 321 return !!(pci_dev->subordinate); 322 } 323 324 static inline bool pci_power_manageable(struct pci_dev *pci_dev) 325 { 326 /* 327 * Currently we allow normal PCI devices and PCI bridges transition 328 * into D3 if their bridge_d3 is set. 329 */ 330 return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3; 331 } 332 333 static inline bool pcie_downstream_port(const struct pci_dev *dev) 334 { 335 int type = pci_pcie_type(dev); 336 337 return type == PCI_EXP_TYPE_ROOT_PORT || 338 type == PCI_EXP_TYPE_DOWNSTREAM || 339 type == PCI_EXP_TYPE_PCIE_BRIDGE; 340 } 341 342 void pci_vpd_init(struct pci_dev *dev); 343 extern const struct attribute_group pci_dev_vpd_attr_group; 344 345 /* PCI Virtual Channel */ 346 int pci_save_vc_state(struct pci_dev *dev); 347 void pci_restore_vc_state(struct pci_dev *dev); 348 void pci_allocate_vc_save_buffers(struct pci_dev *dev); 349 350 /* PCI /proc functions */ 351 #ifdef CONFIG_PROC_FS 352 int pci_proc_attach_device(struct pci_dev *dev); 353 int pci_proc_detach_device(struct pci_dev *dev); 354 int pci_proc_detach_bus(struct pci_bus *bus); 355 #else 356 static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; } 357 static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; } 358 static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; } 359 #endif 360 361 /* Functions for PCI Hotplug drivers to use */ 362 int pci_hp_add_bridge(struct pci_dev *dev); 363 bool pci_hp_spurious_link_change(struct pci_dev *pdev); 364 365 /* Lock for read/write access to pci device and bus lists */ 366 extern struct rw_semaphore pci_bus_sem; 367 extern struct mutex pci_slot_mutex; 368 369 extern raw_spinlock_t pci_lock; 370 371 extern unsigned int pci_pm_d3hot_delay; 372 373 #ifdef CONFIG_PCI_MSI 374 void pci_no_msi(void); 375 #else 376 static inline void pci_no_msi(void) { } 377 #endif 378 379 void pci_realloc_get_opt(char *); 380 381 static inline int pci_no_d1d2(struct pci_dev *dev) 382 { 383 unsigned int parent_dstates = 0; 384 385 if (dev->bus->self) 386 parent_dstates = dev->bus->self->no_d1d2; 387 return (dev->no_d1d2 || parent_dstates); 388 389 } 390 391 #ifdef HAVE_PCI_LEGACY 392 bool pci_legacy_has_sparse(struct pci_bus *bus, enum pci_mmap_state type); 393 #endif 394 395 #ifdef CONFIG_SYSFS 396 extern const struct attribute_group *pci_dev_groups[]; 397 extern const struct attribute_group *pci_dev_attr_groups[]; 398 extern const struct attribute_group *pcibus_groups[]; 399 extern const struct attribute_group *pci_bus_groups[]; 400 extern const struct attribute_group pci_doe_sysfs_group; 401 #else 402 #define pci_dev_groups NULL 403 #define pci_dev_attr_groups NULL 404 #define pcibus_groups NULL 405 #define pci_bus_groups NULL 406 #endif 407 408 extern unsigned long pci_hotplug_io_size; 409 extern unsigned long pci_hotplug_mmio_size; 410 extern unsigned long pci_hotplug_mmio_pref_size; 411 extern unsigned long pci_hotplug_bus_size; 412 413 static inline bool pci_is_cardbus_bridge(struct pci_dev *dev) 414 { 415 return dev->hdr_type == PCI_HEADER_TYPE_CARDBUS; 416 } 417 #ifdef CONFIG_CARDBUS 418 unsigned long pci_cardbus_resource_alignment(const struct resource *res); 419 int pci_bus_size_cardbus_bridge(struct pci_bus *bus, 420 struct list_head *realloc_head); 421 int pci_cardbus_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev, 422 u32 buses, int max, 423 unsigned int available_buses, int pass); 424 int pci_setup_cardbus(char *str); 425 426 #else 427 static inline unsigned long pci_cardbus_resource_alignment(const struct resource *res) 428 { 429 return 0; 430 } 431 static inline int pci_bus_size_cardbus_bridge(struct pci_bus *bus, 432 struct list_head *realloc_head) 433 { 434 return -EOPNOTSUPP; 435 } 436 static inline int pci_cardbus_scan_bridge_extend(struct pci_bus *bus, 437 struct pci_dev *dev, 438 u32 buses, int max, 439 unsigned int available_buses, 440 int pass) 441 { 442 return max; 443 } 444 static inline int pci_setup_cardbus(char *str) { return -ENOENT; } 445 #endif /* CONFIG_CARDBUS */ 446 447 /** 448 * pci_id_from_device - Obtain a pci_device_id from a PCI device 449 * @dev: the PCI device 450 * 451 * Return: a pci_device_id filled. 452 */ 453 static inline struct pci_device_id pci_id_from_device(const struct pci_dev *dev) 454 { 455 return (struct pci_device_id) { 456 .vendor = dev->vendor, 457 .device = dev->device, 458 .subvendor = dev->subsystem_vendor, 459 .subdevice = dev->subsystem_device, 460 .class = dev->class, 461 }; 462 } 463 464 /** 465 * pci_match_one_id - Tell if a PCI device ID matches a needle PCI device ID 466 * @id: single PCI device id structure to match against (needle) 467 * @dev_id: the actual ID from the PCI device 468 * 469 * ID can be retrieved from device using pci_id_from_device(). 470 * 471 * Return: the matching pci_device_id structure or %NULL if there is no match. 472 */ 473 static inline const struct pci_device_id * 474 pci_match_one_id(const struct pci_device_id *id, 475 const struct pci_device_id *dev_id) 476 { 477 if ((id->vendor == PCI_ANY_ID || id->vendor == dev_id->vendor) && 478 (id->device == PCI_ANY_ID || id->device == dev_id->device) && 479 (id->subvendor == PCI_ANY_ID || id->subvendor == dev_id->subvendor) && 480 (id->subdevice == PCI_ANY_ID || id->subdevice == dev_id->subdevice) && 481 !((id->class ^ dev_id->class) & id->class_mask)) 482 return id; 483 return NULL; 484 } 485 486 /* PCI slot sysfs helper code */ 487 #define to_pci_slot(s) container_of(s, struct pci_slot, kobj) 488 489 extern struct kset *pci_slots_kset; 490 491 struct pci_slot_attribute { 492 struct attribute attr; 493 ssize_t (*show)(struct pci_slot *, char *); 494 ssize_t (*store)(struct pci_slot *, const char *, size_t); 495 }; 496 #define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr) 497 498 enum pci_bar_type { 499 pci_bar_unknown, /* Standard PCI BAR probe */ 500 pci_bar_io, /* An I/O port BAR */ 501 pci_bar_mem32, /* A 32-bit memory BAR */ 502 pci_bar_mem64, /* A 64-bit memory BAR */ 503 }; 504 505 struct device *pci_get_host_bridge_device(struct pci_dev *dev); 506 void pci_put_host_bridge_device(struct device *dev); 507 508 void pci_resize_resource_set_size(struct pci_dev *dev, int resno, int size); 509 int pci_do_resource_release_and_resize(struct pci_dev *dev, int resno, int size, 510 int exclude_bars); 511 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge); 512 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align); 513 514 int pci_configure_extended_tags(struct pci_dev *dev, void *ign); 515 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl, 516 int rrs_timeout); 517 bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl, 518 int rrs_timeout); 519 520 int pci_setup_device(struct pci_dev *dev); 521 void __pci_size_stdbars(struct pci_dev *dev, int count, 522 unsigned int pos, u32 *sizes); 523 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, 524 struct resource *res, unsigned int reg, u32 *sizes); 525 void pci_configure_ari(struct pci_dev *dev); 526 527 int pci_dev_res_add_to_list(struct list_head *head, struct pci_dev *dev, 528 struct resource *res, resource_size_t add_size, 529 resource_size_t min_align); 530 void __pci_bus_size_bridges(struct pci_bus *bus, 531 struct list_head *realloc_head); 532 void __pci_bus_assign_resources(const struct pci_bus *bus, 533 struct list_head *add_list, 534 struct list_head *fail_head); 535 bool pci_bus_clip_resource(struct pci_dev *dev, int idx); 536 void pci_walk_bus_locked(struct pci_bus *top, 537 int (*cb)(struct pci_dev *, void *), 538 void *userdata); 539 540 const char *pci_resource_name(struct pci_dev *dev, unsigned int i); 541 bool pci_resource_is_optional(const struct pci_dev *dev, int resno); 542 static inline bool pci_resource_is_bridge_win(int resno) 543 { 544 return resno >= PCI_BRIDGE_RESOURCES && 545 resno <= PCI_BRIDGE_RESOURCE_END; 546 } 547 548 /** 549 * pci_resource_num - Reverse lookup resource number from device resources 550 * @dev: PCI device 551 * @res: Resource to lookup index for (MUST be a @dev's resource) 552 * 553 * Perform reverse lookup to determine the resource number for @res within 554 * @dev resource array. NOTE: The caller is responsible for ensuring @res is 555 * among @dev's resources! 556 * 557 * Returns: resource number. 558 */ 559 static inline int pci_resource_num(const struct pci_dev *dev, 560 const struct resource *res) 561 { 562 int resno = res - &dev->resource[0]; 563 564 /* Passing a resource that is not among dev's resources? */ 565 WARN_ON_ONCE(resno >= PCI_NUM_RESOURCES); 566 567 return resno; 568 } 569 570 void pbus_validate_busn(struct pci_bus *bus); 571 struct resource *pbus_select_window(struct pci_bus *bus, 572 const struct resource *res); 573 void pci_reassigndev_resource_alignment(struct pci_dev *dev); 574 void pci_disable_bridge_window(struct pci_dev *dev); 575 struct pci_bus *pci_bus_get(struct pci_bus *bus); 576 void pci_bus_put(struct pci_bus *bus); 577 578 #define PCIE_LNKCAP_SLS2SPEED(lnkcap) \ 579 ({ \ 580 u32 lnkcap_sls = (lnkcap) & PCI_EXP_LNKCAP_SLS; \ 581 \ 582 (lnkcap_sls == PCI_EXP_LNKCAP_SLS_64_0GB ? PCIE_SPEED_64_0GT : \ 583 lnkcap_sls == PCI_EXP_LNKCAP_SLS_32_0GB ? PCIE_SPEED_32_0GT : \ 584 lnkcap_sls == PCI_EXP_LNKCAP_SLS_16_0GB ? PCIE_SPEED_16_0GT : \ 585 lnkcap_sls == PCI_EXP_LNKCAP_SLS_8_0GB ? PCIE_SPEED_8_0GT : \ 586 lnkcap_sls == PCI_EXP_LNKCAP_SLS_5_0GB ? PCIE_SPEED_5_0GT : \ 587 lnkcap_sls == PCI_EXP_LNKCAP_SLS_2_5GB ? PCIE_SPEED_2_5GT : \ 588 PCI_SPEED_UNKNOWN); \ 589 }) 590 591 /* PCIe link information from Link Capabilities 2 */ 592 #define PCIE_LNKCAP2_SLS2SPEED(lnkcap2) \ 593 ((lnkcap2) & PCI_EXP_LNKCAP2_SLS_64_0GB ? PCIE_SPEED_64_0GT : \ 594 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_32_0GB ? PCIE_SPEED_32_0GT : \ 595 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_16_0GB ? PCIE_SPEED_16_0GT : \ 596 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_8_0GB ? PCIE_SPEED_8_0GT : \ 597 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_5_0GB ? PCIE_SPEED_5_0GT : \ 598 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_2_5GB ? PCIE_SPEED_2_5GT : \ 599 PCI_SPEED_UNKNOWN) 600 601 #define PCIE_LNKCTL2_TLS2SPEED(lnkctl2) \ 602 ({ \ 603 u16 lnkctl2_tls = (lnkctl2) & PCI_EXP_LNKCTL2_TLS; \ 604 \ 605 (lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_64_0GT ? PCIE_SPEED_64_0GT : \ 606 lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_32_0GT ? PCIE_SPEED_32_0GT : \ 607 lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_16_0GT ? PCIE_SPEED_16_0GT : \ 608 lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_8_0GT ? PCIE_SPEED_8_0GT : \ 609 lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_5_0GT ? PCIE_SPEED_5_0GT : \ 610 lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_2_5GT ? PCIE_SPEED_2_5GT : \ 611 PCI_SPEED_UNKNOWN); \ 612 }) 613 614 /* PCIe speed to Mb/s reduced by encoding overhead */ 615 #define PCIE_SPEED2MBS_ENC(speed) \ 616 ((speed) == PCIE_SPEED_64_0GT ? 64000*1/1 : \ 617 (speed) == PCIE_SPEED_32_0GT ? 32000*128/130 : \ 618 (speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \ 619 (speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \ 620 (speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \ 621 (speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \ 622 0) 623 624 static inline bool pcie_valid_speed(enum pci_bus_speed speed) 625 { 626 return (speed >= PCIE_SPEED_2_5GT) && (speed <= PCIE_SPEED_64_0GT); 627 } 628 629 static inline u16 pci_bus_speed2lnkctl2(enum pci_bus_speed speed) 630 { 631 static const u8 speed_conv[] = { 632 [PCIE_SPEED_2_5GT] = PCI_EXP_LNKCTL2_TLS_2_5GT, 633 [PCIE_SPEED_5_0GT] = PCI_EXP_LNKCTL2_TLS_5_0GT, 634 [PCIE_SPEED_8_0GT] = PCI_EXP_LNKCTL2_TLS_8_0GT, 635 [PCIE_SPEED_16_0GT] = PCI_EXP_LNKCTL2_TLS_16_0GT, 636 [PCIE_SPEED_32_0GT] = PCI_EXP_LNKCTL2_TLS_32_0GT, 637 [PCIE_SPEED_64_0GT] = PCI_EXP_LNKCTL2_TLS_64_0GT, 638 }; 639 640 if (WARN_ON_ONCE(!pcie_valid_speed(speed))) 641 return 0; 642 643 return speed_conv[speed]; 644 } 645 646 static inline int pcie_dev_speed_mbps(enum pci_bus_speed speed) 647 { 648 switch (speed) { 649 case PCIE_SPEED_2_5GT: 650 return 2500; 651 case PCIE_SPEED_5_0GT: 652 return 5000; 653 case PCIE_SPEED_8_0GT: 654 return 8000; 655 case PCIE_SPEED_16_0GT: 656 return 16000; 657 case PCIE_SPEED_32_0GT: 658 return 32000; 659 case PCIE_SPEED_64_0GT: 660 return 64000; 661 default: 662 break; 663 } 664 665 return -EINVAL; 666 } 667 668 u8 pcie_get_supported_speeds(struct pci_dev *dev); 669 const char *pci_speed_string(enum pci_bus_speed speed); 670 void __pcie_print_link_status(struct pci_dev *dev, bool verbose); 671 void pcie_report_downtraining(struct pci_dev *dev); 672 673 enum pcie_link_change_reason { 674 PCIE_LINK_RETRAIN, 675 PCIE_ADD_BUS, 676 PCIE_BWCTRL_ENABLE, 677 PCIE_BWCTRL_IRQ, 678 PCIE_HOTPLUG, 679 }; 680 681 static inline void __pcie_update_link_speed(struct pci_bus *bus, 682 enum pcie_link_change_reason reason, 683 u16 linksta, u16 linksta2) 684 { 685 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS]; 686 bus->flit_mode = (linksta2 & PCI_EXP_LNKSTA2_FLIT) ? 1 : 0; 687 688 trace_pcie_link_event(bus, 689 reason, 690 FIELD_GET(PCI_EXP_LNKSTA_NLW, linksta), 691 linksta & PCI_EXP_LNKSTA_LINK_STATUS_MASK); 692 } 693 694 void pcie_update_link_speed(struct pci_bus *bus, enum pcie_link_change_reason reason); 695 696 /* Single Root I/O Virtualization */ 697 struct pci_sriov { 698 int pos; /* Capability position */ 699 int nres; /* Number of resources */ 700 u32 cap; /* SR-IOV Capabilities */ 701 u16 ctrl; /* SR-IOV Control */ 702 u16 total_VFs; /* Total VFs associated with the PF */ 703 u16 initial_VFs; /* Initial VFs associated with the PF */ 704 u16 num_VFs; /* Number of VFs available */ 705 u16 offset; /* First VF Routing ID offset */ 706 u16 stride; /* Following VF stride */ 707 u16 vf_device; /* VF device ID */ 708 u32 pgsz; /* Page size for BAR alignment */ 709 u8 link; /* Function Dependency Link */ 710 u8 max_VF_buses; /* Max buses consumed by VFs */ 711 u16 driver_max_VFs; /* Max num VFs driver supports */ 712 struct pci_dev *dev; /* Lowest numbered PF */ 713 struct pci_dev *self; /* This PF */ 714 u32 class; /* VF device */ 715 u8 hdr_type; /* VF header type */ 716 u16 subsystem_vendor; /* VF subsystem vendor */ 717 u16 subsystem_device; /* VF subsystem device */ 718 resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */ 719 u16 vf_rebar_cap; /* VF Resizable BAR capability offset */ 720 bool drivers_autoprobe; /* Auto probing of VFs by driver */ 721 }; 722 723 #ifdef CONFIG_PCI_DOE 724 void pci_doe_init(struct pci_dev *pdev); 725 void pci_doe_destroy(struct pci_dev *pdev); 726 void pci_doe_disconnected(struct pci_dev *pdev); 727 #else 728 static inline void pci_doe_init(struct pci_dev *pdev) { } 729 static inline void pci_doe_destroy(struct pci_dev *pdev) { } 730 static inline void pci_doe_disconnected(struct pci_dev *pdev) { } 731 #endif 732 733 #ifdef CONFIG_PCI_NPEM 734 void pci_npem_create(struct pci_dev *dev); 735 void pci_npem_remove(struct pci_dev *dev); 736 #else 737 static inline void pci_npem_create(struct pci_dev *dev) { } 738 static inline void pci_npem_remove(struct pci_dev *dev) { } 739 #endif 740 741 #if defined(CONFIG_PCI_DOE) && defined(CONFIG_SYSFS) 742 void pci_doe_sysfs_init(struct pci_dev *pci_dev); 743 void pci_doe_sysfs_teardown(struct pci_dev *pdev); 744 #else 745 static inline void pci_doe_sysfs_init(struct pci_dev *pdev) { } 746 static inline void pci_doe_sysfs_teardown(struct pci_dev *pdev) { } 747 #endif 748 749 #ifdef CONFIG_PCI_IDE 750 void pci_ide_init(struct pci_dev *dev); 751 void pci_ide_init_host_bridge(struct pci_host_bridge *hb); 752 void pci_ide_destroy(struct pci_dev *dev); 753 extern const struct attribute_group pci_ide_attr_group; 754 #else 755 static inline void pci_ide_init(struct pci_dev *dev) { } 756 static inline void pci_ide_init_host_bridge(struct pci_host_bridge *hb) { } 757 static inline void pci_ide_destroy(struct pci_dev *dev) { } 758 #endif 759 760 #ifdef CONFIG_PCI_TSM 761 void pci_tsm_init(struct pci_dev *pdev); 762 void pci_tsm_destroy(struct pci_dev *pdev); 763 extern const struct attribute_group pci_tsm_attr_group; 764 extern const struct attribute_group pci_tsm_auth_attr_group; 765 #else 766 static inline void pci_tsm_init(struct pci_dev *pdev) { } 767 static inline void pci_tsm_destroy(struct pci_dev *pdev) { } 768 #endif 769 770 /** 771 * pci_dev_set_io_state - Set the new error state if possible. 772 * 773 * @dev: PCI device to set new error_state 774 * @new: the state we want dev to be in 775 * 776 * If the device is experiencing perm_failure, it has to remain in that state. 777 * Any other transition is allowed. 778 * 779 * Returns true if state has been changed to the requested state. 780 */ 781 static inline bool pci_dev_set_io_state(struct pci_dev *dev, 782 pci_channel_state_t new) 783 { 784 pci_channel_state_t old; 785 786 switch (new) { 787 case pci_channel_io_perm_failure: 788 xchg(&dev->error_state, pci_channel_io_perm_failure); 789 return true; 790 case pci_channel_io_frozen: 791 old = cmpxchg(&dev->error_state, pci_channel_io_normal, 792 pci_channel_io_frozen); 793 return old != pci_channel_io_perm_failure; 794 case pci_channel_io_normal: 795 old = cmpxchg(&dev->error_state, pci_channel_io_frozen, 796 pci_channel_io_normal); 797 return old != pci_channel_io_perm_failure; 798 default: 799 return false; 800 } 801 } 802 803 static inline int pci_dev_set_disconnected(struct pci_dev *dev, void *unused) 804 { 805 pci_dev_set_io_state(dev, pci_channel_io_perm_failure); 806 pci_doe_disconnected(dev); 807 808 return 0; 809 } 810 811 /* pci_dev priv_flags */ 812 #define PCI_DEV_ADDED 0 813 #define PCI_DPC_RECOVERED 1 814 #define PCI_DPC_RECOVERING 2 815 #define PCI_DEV_REMOVED 3 816 #define PCI_LINK_CHANGED 4 817 #define PCI_LINK_CHANGING 5 818 #define PCI_LINK_LBMS_SEEN 6 819 #define PCI_DEV_ALLOW_BINDING 7 820 821 static inline void pci_dev_assign_added(struct pci_dev *dev) 822 { 823 smp_mb__before_atomic(); 824 set_bit(PCI_DEV_ADDED, &dev->priv_flags); 825 smp_mb__after_atomic(); 826 } 827 828 static inline bool pci_dev_test_and_clear_added(struct pci_dev *dev) 829 { 830 return test_and_clear_bit(PCI_DEV_ADDED, &dev->priv_flags); 831 } 832 833 static inline bool pci_dev_is_added(const struct pci_dev *dev) 834 { 835 return test_bit(PCI_DEV_ADDED, &dev->priv_flags); 836 } 837 838 static inline bool pci_dev_test_and_set_removed(struct pci_dev *dev) 839 { 840 return test_and_set_bit(PCI_DEV_REMOVED, &dev->priv_flags); 841 } 842 843 static inline void pci_dev_allow_binding(struct pci_dev *dev) 844 { 845 set_bit(PCI_DEV_ALLOW_BINDING, &dev->priv_flags); 846 } 847 848 static inline bool pci_dev_binding_disallowed(struct pci_dev *dev) 849 { 850 return !test_bit(PCI_DEV_ALLOW_BINDING, &dev->priv_flags); 851 } 852 853 #ifdef CONFIG_PCIEAER 854 #include <linux/aer.h> 855 856 #define AER_MAX_MULTI_ERR_DEVICES 5 /* Not likely to have more */ 857 858 /** 859 * struct aer_err_info - AER Error Information 860 * @dev: Devices reporting error 861 * @ratelimit_print: Flag to log or not log the devices' error. 0=NotLog/1=Log 862 * @__pad1: Padding for alignment 863 * @error_dev_num: Number of devices reporting an error 864 * @level: printk level to use in logging 865 * @id: Value from register PCI_ERR_ROOT_ERR_SRC 866 * @severity: AER severity, 0-UNCOR Non-fatal, 1-UNCOR fatal, 2-COR 867 * @root_ratelimit_print: Flag to log or not log the root's error. 0=NotLog/1=Log 868 * @multi_error_valid: If multiple errors are reported 869 * @first_error: First reported error 870 * @__pad2: Padding for alignment 871 * @is_cxl: Bus type error: 0-PCI Bus error, 1-CXL Bus error 872 * @tlp_header_valid: Indicates if TLP field contains error information 873 * @status: COR/UNCOR error status 874 * @mask: COR/UNCOR mask 875 * @anfe_status: Advisory Non-Fatal Errors, i.e. Uncorrectable Errors signaled 876 * as Correctable Errors (PCIe r7.0 sec 6.2.4.3). Only used if @severity 877 * is AER_CORRECTABLE and @status has Advisory Non-Fatal Error Status set. 878 * @tlp: Transaction packet information 879 */ 880 struct aer_err_info { 881 struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES]; 882 int ratelimit_print[AER_MAX_MULTI_ERR_DEVICES]; 883 int error_dev_num; 884 const char *level; 885 886 unsigned int id:16; 887 888 unsigned int severity:2; 889 unsigned int root_ratelimit_print:1; 890 unsigned int __pad1:4; 891 unsigned int multi_error_valid:1; 892 893 unsigned int first_error:5; 894 unsigned int __pad2:1; 895 unsigned int is_cxl:1; 896 unsigned int tlp_header_valid:1; 897 898 unsigned int status; 899 unsigned int mask; 900 u32 anfe_status; 901 struct pcie_tlp_log tlp; 902 }; 903 904 int aer_get_device_error_info(struct aer_err_info *info, int i); 905 void aer_print_error(struct aer_err_info *info, int i); 906 907 static inline const char *aer_err_bus(struct aer_err_info *info) 908 { 909 return info->is_cxl ? "CXL" : "PCIe"; 910 } 911 912 int pcie_read_tlp_log(struct pci_dev *dev, int where, int where2, 913 unsigned int tlp_len, bool flit, 914 struct pcie_tlp_log *log); 915 unsigned int aer_tlp_log_len(struct pci_dev *dev, u32 aercc); 916 void pcie_print_tlp_log(const struct pci_dev *dev, 917 const struct pcie_tlp_log *log, const char *level, 918 const char *pfx); 919 #endif /* CONFIG_PCIEAER */ 920 921 #ifdef CONFIG_PCIEPORTBUS 922 /* Cached RCEC Endpoint Association */ 923 struct rcec_ea { 924 u8 nextbusn; 925 u8 lastbusn; 926 u32 bitmap; 927 }; 928 #endif 929 930 #ifdef CONFIG_PCIE_DPC 931 void pci_save_dpc_state(struct pci_dev *dev); 932 void pci_restore_dpc_state(struct pci_dev *dev); 933 void pci_dpc_init(struct pci_dev *pdev); 934 void dpc_process_error(struct pci_dev *pdev); 935 pci_ers_result_t dpc_reset_link(struct pci_dev *pdev); 936 bool pci_dpc_recovered(struct pci_dev *pdev); 937 unsigned int dpc_tlp_log_len(struct pci_dev *dev); 938 #else 939 static inline void pci_save_dpc_state(struct pci_dev *dev) { } 940 static inline void pci_restore_dpc_state(struct pci_dev *dev) { } 941 static inline void pci_dpc_init(struct pci_dev *pdev) { } 942 static inline bool pci_dpc_recovered(struct pci_dev *pdev) { return false; } 943 #endif 944 945 #ifdef CONFIG_PCIEPORTBUS 946 void pci_rcec_init(struct pci_dev *dev); 947 void pci_rcec_exit(struct pci_dev *dev); 948 void pcie_link_rcec(struct pci_dev *rcec); 949 void pcie_walk_rcec(struct pci_dev *rcec, 950 int (*cb)(struct pci_dev *, void *), 951 void *userdata); 952 #else 953 static inline void pci_rcec_init(struct pci_dev *dev) { } 954 static inline void pci_rcec_exit(struct pci_dev *dev) { } 955 static inline void pcie_link_rcec(struct pci_dev *rcec) { } 956 static inline void pcie_walk_rcec(struct pci_dev *rcec, 957 int (*cb)(struct pci_dev *, void *), 958 void *userdata) { } 959 #endif 960 961 #ifdef CONFIG_PCI_ATS 962 /* Address Translation Service */ 963 void pci_ats_init(struct pci_dev *dev); 964 void pci_restore_ats_state(struct pci_dev *dev); 965 #else 966 static inline void pci_ats_init(struct pci_dev *d) { } 967 static inline void pci_restore_ats_state(struct pci_dev *dev) { } 968 #endif /* CONFIG_PCI_ATS */ 969 970 #ifdef CONFIG_PCI_PRI 971 void pci_pri_init(struct pci_dev *dev); 972 void pci_restore_pri_state(struct pci_dev *pdev); 973 #else 974 static inline void pci_pri_init(struct pci_dev *dev) { } 975 static inline void pci_restore_pri_state(struct pci_dev *pdev) { } 976 #endif 977 978 #ifdef CONFIG_PCI_PASID 979 void pci_pasid_init(struct pci_dev *dev); 980 void pci_restore_pasid_state(struct pci_dev *pdev); 981 #else 982 static inline void pci_pasid_init(struct pci_dev *dev) { } 983 static inline void pci_restore_pasid_state(struct pci_dev *pdev) { } 984 #endif 985 986 #ifdef CONFIG_PCI_IOV 987 int pci_iov_init(struct pci_dev *dev); 988 void pci_iov_release(struct pci_dev *dev); 989 void pci_iov_remove(struct pci_dev *dev); 990 void pci_iov_update_resource(struct pci_dev *dev, int resno); 991 resource_size_t pci_sriov_resource_alignment(const struct pci_dev *dev, 992 int resno); 993 void pci_restore_iov_state(struct pci_dev *dev); 994 int pci_iov_bus_range(struct pci_bus *bus); 995 void pci_iov_resource_set_size(struct pci_dev *dev, int resno, int size); 996 bool pci_iov_is_memory_decoding_enabled(struct pci_dev *dev); 997 static inline u16 pci_iov_vf_rebar_cap(struct pci_dev *dev) 998 { 999 if (!dev->is_physfn) 1000 return 0; 1001 1002 return dev->sriov->vf_rebar_cap; 1003 } 1004 static inline bool pci_resource_is_iov(int resno) 1005 { 1006 return resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END; 1007 } 1008 static inline int pci_resource_num_from_vf_bar(int resno) 1009 { 1010 return resno + PCI_IOV_RESOURCES; 1011 } 1012 static inline int pci_resource_num_to_vf_bar(int resno) 1013 { 1014 return resno - PCI_IOV_RESOURCES; 1015 } 1016 extern const struct attribute_group sriov_pf_dev_attr_group; 1017 extern const struct attribute_group sriov_vf_dev_attr_group; 1018 #else 1019 static inline int pci_iov_init(struct pci_dev *dev) 1020 { 1021 return -ENODEV; 1022 } 1023 static inline void pci_iov_release(struct pci_dev *dev) { } 1024 static inline void pci_iov_remove(struct pci_dev *dev) { } 1025 static inline void pci_iov_update_resource(struct pci_dev *dev, int resno) { } 1026 static inline resource_size_t pci_sriov_resource_alignment(const struct pci_dev *dev, 1027 int resno) 1028 { 1029 return 0; 1030 } 1031 static inline void pci_restore_iov_state(struct pci_dev *dev) { } 1032 static inline int pci_iov_bus_range(struct pci_bus *bus) 1033 { 1034 return 0; 1035 } 1036 static inline void pci_iov_resource_set_size(struct pci_dev *dev, int resno, 1037 int size) { } 1038 static inline bool pci_iov_is_memory_decoding_enabled(struct pci_dev *dev) 1039 { 1040 return false; 1041 } 1042 static inline u16 pci_iov_vf_rebar_cap(struct pci_dev *dev) 1043 { 1044 return 0; 1045 } 1046 static inline bool pci_resource_is_iov(int resno) 1047 { 1048 return false; 1049 } 1050 static inline int pci_resource_num_from_vf_bar(int resno) 1051 { 1052 WARN_ON_ONCE(1); 1053 return -ENODEV; 1054 } 1055 static inline int pci_resource_num_to_vf_bar(int resno) 1056 { 1057 WARN_ON_ONCE(1); 1058 return -ENODEV; 1059 } 1060 #endif /* CONFIG_PCI_IOV */ 1061 1062 #ifdef CONFIG_PCIE_TPH 1063 void pci_restore_tph_state(struct pci_dev *dev); 1064 void pci_save_tph_state(struct pci_dev *dev); 1065 void pci_no_tph(void); 1066 void pci_tph_init(struct pci_dev *dev); 1067 #else 1068 static inline void pci_restore_tph_state(struct pci_dev *dev) { } 1069 static inline void pci_save_tph_state(struct pci_dev *dev) { } 1070 static inline void pci_no_tph(void) { } 1071 static inline void pci_tph_init(struct pci_dev *dev) { } 1072 #endif 1073 1074 #ifdef CONFIG_PCIE_PTM 1075 void pci_ptm_init(struct pci_dev *dev); 1076 void pci_save_ptm_state(struct pci_dev *dev); 1077 void pci_restore_ptm_state(struct pci_dev *dev); 1078 void pci_suspend_ptm(struct pci_dev *dev); 1079 void pci_resume_ptm(struct pci_dev *dev); 1080 #else 1081 static inline void pci_ptm_init(struct pci_dev *dev) { } 1082 static inline void pci_save_ptm_state(struct pci_dev *dev) { } 1083 static inline void pci_restore_ptm_state(struct pci_dev *dev) { } 1084 static inline void pci_suspend_ptm(struct pci_dev *dev) { } 1085 static inline void pci_resume_ptm(struct pci_dev *dev) { } 1086 #endif 1087 1088 resource_size_t pci_resource_alignment(const struct pci_dev *dev, 1089 const struct resource *res); 1090 1091 resource_size_t pci_min_window_alignment(struct pci_bus *bus, 1092 unsigned long type); 1093 1094 void pci_acs_init(struct pci_dev *dev); 1095 void pci_enable_acs(struct pci_dev *dev); 1096 #ifdef CONFIG_PCI_QUIRKS 1097 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags); 1098 int pci_dev_specific_enable_acs(struct pci_dev *dev); 1099 int pci_dev_specific_disable_acs_redir(struct pci_dev *dev); 1100 void pci_disable_broken_acs_cap(struct pci_dev *pdev); 1101 int pcie_failed_link_retrain(struct pci_dev *dev); 1102 #else 1103 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev, 1104 u16 acs_flags) 1105 { 1106 return -ENOTTY; 1107 } 1108 static inline int pci_dev_specific_enable_acs(struct pci_dev *dev) 1109 { 1110 return -ENOTTY; 1111 } 1112 static inline int pci_dev_specific_disable_acs_redir(struct pci_dev *dev) 1113 { 1114 return -ENOTTY; 1115 } 1116 static inline void pci_disable_broken_acs_cap(struct pci_dev *dev) { } 1117 static inline int pcie_failed_link_retrain(struct pci_dev *dev) 1118 { 1119 return -ENOTTY; 1120 } 1121 #endif 1122 1123 /* PCI error reporting and recovery */ 1124 pci_ers_result_t pcie_do_recovery(struct pci_dev *dev, 1125 pci_channel_state_t state, 1126 pci_ers_result_t (*reset_subordinates)(struct pci_dev *pdev)); 1127 1128 bool pcie_wait_for_link(struct pci_dev *pdev, bool active); 1129 int pcie_retrain_link(struct pci_dev *pdev, bool use_lt); 1130 1131 /* ASPM-related functionality we need even without CONFIG_PCIEASPM */ 1132 void pci_save_ltr_state(struct pci_dev *dev); 1133 void pci_restore_ltr_state(struct pci_dev *dev); 1134 void pci_configure_aspm_l1ss(struct pci_dev *dev); 1135 void pci_save_aspm_l1ss_state(struct pci_dev *dev); 1136 void pci_restore_aspm_l1ss_state(struct pci_dev *dev); 1137 1138 #ifdef CONFIG_PCIEASPM 1139 void pcie_aspm_remove_cap(struct pci_dev *pdev, u32 lnkcap); 1140 void pcie_aspm_init_link_state(struct pci_dev *pdev); 1141 void pcie_aspm_exit_link_state(struct pci_dev *pdev); 1142 void pcie_aspm_pm_state_change(struct pci_dev *pdev, bool locked); 1143 void pcie_aspm_powersave_config_link(struct pci_dev *pdev); 1144 void pci_configure_ltr(struct pci_dev *pdev); 1145 void pci_bridge_reconfigure_ltr(struct pci_dev *pdev); 1146 void pcie_encode_t_power_on(u32 t_power_on_us, u8 *scale, u8 *value); 1147 #else 1148 static inline void pcie_aspm_remove_cap(struct pci_dev *pdev, u32 lnkcap) { } 1149 static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { } 1150 static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { } 1151 static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev, bool locked) { } 1152 static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { } 1153 static inline void pci_configure_ltr(struct pci_dev *pdev) { } 1154 static inline void pci_bridge_reconfigure_ltr(struct pci_dev *pdev) { } 1155 static inline void pcie_encode_t_power_on(u32 t_power_on_us, u8 *scale, u8 *value) 1156 { 1157 *scale = 0; 1158 *value = 0; 1159 } 1160 #endif 1161 1162 #ifdef CONFIG_PCIE_ECRC 1163 void pcie_set_ecrc_checking(struct pci_dev *dev); 1164 void pcie_ecrc_get_policy(char *str); 1165 #else 1166 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { } 1167 static inline void pcie_ecrc_get_policy(char *str) { } 1168 #endif 1169 1170 #ifdef CONFIG_PCIEPORTBUS 1171 void pcie_reset_lbms(struct pci_dev *port); 1172 #else 1173 static inline void pcie_reset_lbms(struct pci_dev *port) {} 1174 #endif 1175 1176 struct pci_dev_reset_methods { 1177 u16 vendor; 1178 u16 device; 1179 int (*reset)(struct pci_dev *dev, bool probe); 1180 }; 1181 1182 struct pci_reset_fn_method { 1183 int (*reset_fn)(struct pci_dev *pdev, bool probe); 1184 char *name; 1185 }; 1186 extern const struct pci_reset_fn_method pci_reset_fn_methods[]; 1187 1188 #ifdef CONFIG_PCI_QUIRKS 1189 int pci_dev_specific_reset(struct pci_dev *dev, bool probe); 1190 #else 1191 static inline int pci_dev_specific_reset(struct pci_dev *dev, bool probe) 1192 { 1193 return -ENOTTY; 1194 } 1195 #endif 1196 1197 #if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_PCI_ATS) 1198 bool pci_dev_specific_ats_required(struct pci_dev *dev); 1199 #else 1200 static inline bool pci_dev_specific_ats_required(struct pci_dev *dev) 1201 { 1202 return false; 1203 } 1204 #endif 1205 1206 #if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64) 1207 int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment, 1208 struct resource *res); 1209 #else 1210 static inline int acpi_get_rc_resources(struct device *dev, const char *hid, 1211 u16 segment, struct resource *res) 1212 { 1213 return -ENODEV; 1214 } 1215 #endif 1216 1217 void pci_rebar_init(struct pci_dev *pdev); 1218 void pci_restore_rebar_state(struct pci_dev *pdev); 1219 int pci_rebar_get_current_size(struct pci_dev *pdev, int bar); 1220 int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size); 1221 1222 struct device_node; 1223 1224 #define PCI_EQ_RESV 0xff 1225 1226 enum equalization_preset_type { 1227 EQ_PRESET_TYPE_8GTS, 1228 EQ_PRESET_TYPE_16GTS, 1229 EQ_PRESET_TYPE_32GTS, 1230 EQ_PRESET_TYPE_64GTS, 1231 EQ_PRESET_TYPE_MAX 1232 }; 1233 1234 struct pci_eq_presets { 1235 u16 eq_presets_8gts[MAX_NR_LANES]; 1236 u8 eq_presets_Ngts[EQ_PRESET_TYPE_MAX - 1][MAX_NR_LANES]; 1237 }; 1238 1239 #ifdef CONFIG_OF 1240 int of_get_pci_domain_nr(struct device_node *node); 1241 int of_pci_get_max_link_speed(struct device_node *node); 1242 u32 of_pci_get_slot_power_limit(struct device_node *node, 1243 u8 *slot_power_limit_value, 1244 u8 *slot_power_limit_scale); 1245 bool of_pci_preserve_config(struct device_node *node); 1246 int pci_set_of_node(struct pci_dev *dev); 1247 void pci_release_of_node(struct pci_dev *dev); 1248 void pci_set_bus_of_node(struct pci_bus *bus); 1249 void pci_release_bus_of_node(struct pci_bus *bus); 1250 1251 int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge); 1252 bool of_pci_supply_present(struct device_node *np); 1253 int of_pci_get_equalization_presets(struct device *dev, 1254 struct pci_eq_presets *presets, 1255 int num_lanes); 1256 #else 1257 static inline int 1258 of_get_pci_domain_nr(struct device_node *node) 1259 { 1260 return -1; 1261 } 1262 1263 static inline int 1264 of_pci_get_max_link_speed(struct device_node *node) 1265 { 1266 return -EINVAL; 1267 } 1268 1269 static inline u32 1270 of_pci_get_slot_power_limit(struct device_node *node, 1271 u8 *slot_power_limit_value, 1272 u8 *slot_power_limit_scale) 1273 { 1274 if (slot_power_limit_value) 1275 *slot_power_limit_value = 0; 1276 if (slot_power_limit_scale) 1277 *slot_power_limit_scale = 0; 1278 return 0; 1279 } 1280 1281 static inline bool of_pci_preserve_config(struct device_node *node) 1282 { 1283 return false; 1284 } 1285 1286 static inline int pci_set_of_node(struct pci_dev *dev) { return 0; } 1287 static inline void pci_release_of_node(struct pci_dev *dev) { } 1288 static inline void pci_set_bus_of_node(struct pci_bus *bus) { } 1289 static inline void pci_release_bus_of_node(struct pci_bus *bus) { } 1290 1291 static inline int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge) 1292 { 1293 return 0; 1294 } 1295 1296 static inline bool of_pci_supply_present(struct device_node *np) 1297 { 1298 return false; 1299 } 1300 1301 static inline int of_pci_get_equalization_presets(struct device *dev, 1302 struct pci_eq_presets *presets, 1303 int num_lanes) 1304 { 1305 presets->eq_presets_8gts[0] = PCI_EQ_RESV; 1306 for (int i = 0; i < EQ_PRESET_TYPE_MAX - 1; i++) 1307 presets->eq_presets_Ngts[i][0] = PCI_EQ_RESV; 1308 1309 return 0; 1310 } 1311 #endif /* CONFIG_OF */ 1312 1313 struct of_changeset; 1314 1315 #ifdef CONFIG_PCI_DYNAMIC_OF_NODES 1316 void of_pci_make_dev_node(struct pci_dev *pdev); 1317 void of_pci_remove_node(struct pci_dev *pdev); 1318 int of_pci_add_properties(struct pci_dev *pdev, struct of_changeset *ocs, 1319 struct device_node *np); 1320 void of_pci_make_host_bridge_node(struct pci_host_bridge *bridge); 1321 void of_pci_remove_host_bridge_node(struct pci_host_bridge *bridge); 1322 int of_pci_add_host_bridge_properties(struct pci_host_bridge *bridge, 1323 struct of_changeset *ocs, 1324 struct device_node *np); 1325 #else 1326 static inline void of_pci_make_dev_node(struct pci_dev *pdev) { } 1327 static inline void of_pci_remove_node(struct pci_dev *pdev) { } 1328 static inline void of_pci_make_host_bridge_node(struct pci_host_bridge *bridge) { } 1329 static inline void of_pci_remove_host_bridge_node(struct pci_host_bridge *bridge) { } 1330 #endif 1331 1332 #ifdef CONFIG_PCIEAER 1333 void pci_no_aer(void); 1334 void pci_aer_init(struct pci_dev *dev); 1335 void pci_aer_exit(struct pci_dev *dev); 1336 extern const struct attribute_group aer_stats_attr_group; 1337 extern const struct attribute_group aer_attr_group; 1338 void pci_aer_clear_fatal_status(struct pci_dev *dev); 1339 int pci_aer_clear_status(struct pci_dev *dev); 1340 int pci_aer_raw_clear_status(struct pci_dev *dev); 1341 void pci_save_aer_state(struct pci_dev *dev); 1342 void pci_restore_aer_state(struct pci_dev *dev); 1343 #else 1344 static inline void pci_no_aer(void) { } 1345 static inline void pci_aer_init(struct pci_dev *d) { } 1346 static inline void pci_aer_exit(struct pci_dev *d) { } 1347 static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { } 1348 static inline int pci_aer_clear_status(struct pci_dev *dev) { return -EINVAL; } 1349 static inline int pci_aer_raw_clear_status(struct pci_dev *dev) { return -EINVAL; } 1350 static inline void pci_save_aer_state(struct pci_dev *dev) { } 1351 static inline void pci_restore_aer_state(struct pci_dev *dev) { } 1352 #endif 1353 1354 #ifdef CONFIG_ACPI 1355 bool pci_acpi_preserve_config(struct pci_host_bridge *bridge); 1356 int pci_acpi_program_hp_params(struct pci_dev *dev); 1357 extern const struct attribute_group pci_dev_acpi_attr_group; 1358 void pci_set_acpi_fwnode(struct pci_dev *dev); 1359 int pci_dev_acpi_reset(struct pci_dev *dev, bool probe); 1360 bool acpi_pci_power_manageable(struct pci_dev *dev); 1361 bool acpi_pci_bridge_d3(struct pci_dev *dev); 1362 int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state); 1363 pci_power_t acpi_pci_get_power_state(struct pci_dev *dev); 1364 void acpi_pci_refresh_power_state(struct pci_dev *dev); 1365 int acpi_pci_wakeup(struct pci_dev *dev, bool enable); 1366 bool acpi_pci_need_resume(struct pci_dev *dev); 1367 pci_power_t acpi_pci_choose_state(struct pci_dev *pdev); 1368 #else 1369 static inline bool pci_acpi_preserve_config(struct pci_host_bridge *bridge) 1370 { 1371 return false; 1372 } 1373 static inline int pci_dev_acpi_reset(struct pci_dev *dev, bool probe) 1374 { 1375 return -ENOTTY; 1376 } 1377 static inline void pci_set_acpi_fwnode(struct pci_dev *dev) { } 1378 static inline int pci_acpi_program_hp_params(struct pci_dev *dev) 1379 { 1380 return -ENODEV; 1381 } 1382 static inline bool acpi_pci_power_manageable(struct pci_dev *dev) 1383 { 1384 return false; 1385 } 1386 static inline bool acpi_pci_bridge_d3(struct pci_dev *dev) 1387 { 1388 return false; 1389 } 1390 static inline int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state) 1391 { 1392 return -ENODEV; 1393 } 1394 static inline pci_power_t acpi_pci_get_power_state(struct pci_dev *dev) 1395 { 1396 return PCI_UNKNOWN; 1397 } 1398 static inline void acpi_pci_refresh_power_state(struct pci_dev *dev) { } 1399 static inline int acpi_pci_wakeup(struct pci_dev *dev, bool enable) 1400 { 1401 return -ENODEV; 1402 } 1403 static inline bool acpi_pci_need_resume(struct pci_dev *dev) 1404 { 1405 return false; 1406 } 1407 static inline pci_power_t acpi_pci_choose_state(struct pci_dev *pdev) 1408 { 1409 return PCI_POWER_ERROR; 1410 } 1411 #endif 1412 1413 #ifdef CONFIG_PCIEASPM 1414 extern const struct attribute_group aspm_ctrl_attr_group; 1415 #endif 1416 1417 #ifdef CONFIG_X86_INTEL_MID 1418 bool pci_use_mid_pm(void); 1419 int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state); 1420 pci_power_t mid_pci_get_power_state(struct pci_dev *pdev); 1421 #else 1422 static inline bool pci_use_mid_pm(void) 1423 { 1424 return false; 1425 } 1426 static inline int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state) 1427 { 1428 return -ENODEV; 1429 } 1430 static inline pci_power_t mid_pci_get_power_state(struct pci_dev *pdev) 1431 { 1432 return PCI_UNKNOWN; 1433 } 1434 #endif 1435 1436 #ifdef CONFIG_PCI_MSI 1437 int pci_msix_write_tph_tag(struct pci_dev *pdev, unsigned int index, u16 tag); 1438 #else 1439 static inline int pci_msix_write_tph_tag(struct pci_dev *pdev, unsigned int index, u16 tag) 1440 { 1441 return -ENODEV; 1442 } 1443 #endif 1444 1445 /* 1446 * Config Address for PCI Configuration Mechanism #1 1447 * 1448 * See PCI Local Bus Specification, Revision 3.0, 1449 * Section 3.2.2.3.2, Figure 3-2, p. 50. 1450 */ 1451 1452 #define PCI_CONF1_BUS_SHIFT 16 /* Bus number */ 1453 #define PCI_CONF1_DEV_SHIFT 11 /* Device number */ 1454 #define PCI_CONF1_FUNC_SHIFT 8 /* Function number */ 1455 1456 #define PCI_CONF1_BUS_MASK 0xff 1457 #define PCI_CONF1_DEV_MASK 0x1f 1458 #define PCI_CONF1_FUNC_MASK 0x7 1459 #define PCI_CONF1_REG_MASK 0xfc /* Limit aligned offset to a maximum of 256B */ 1460 1461 #define PCI_CONF1_ENABLE BIT(31) 1462 #define PCI_CONF1_BUS(x) (((x) & PCI_CONF1_BUS_MASK) << PCI_CONF1_BUS_SHIFT) 1463 #define PCI_CONF1_DEV(x) (((x) & PCI_CONF1_DEV_MASK) << PCI_CONF1_DEV_SHIFT) 1464 #define PCI_CONF1_FUNC(x) (((x) & PCI_CONF1_FUNC_MASK) << PCI_CONF1_FUNC_SHIFT) 1465 #define PCI_CONF1_REG(x) ((x) & PCI_CONF1_REG_MASK) 1466 1467 #define PCI_CONF1_ADDRESS(bus, dev, func, reg) \ 1468 (PCI_CONF1_ENABLE | \ 1469 PCI_CONF1_BUS(bus) | \ 1470 PCI_CONF1_DEV(dev) | \ 1471 PCI_CONF1_FUNC(func) | \ 1472 PCI_CONF1_REG(reg)) 1473 1474 /* 1475 * Extension of PCI Config Address for accessing extended PCIe registers 1476 * 1477 * No standardized specification, but used on lot of non-ECAM-compliant ARM SoCs 1478 * or on AMD Barcelona and new CPUs. Reserved bits [27:24] of PCI Config Address 1479 * are used for specifying additional 4 high bits of PCI Express register. 1480 */ 1481 1482 #define PCI_CONF1_EXT_REG_SHIFT 16 1483 #define PCI_CONF1_EXT_REG_MASK 0xf00 1484 #define PCI_CONF1_EXT_REG(x) (((x) & PCI_CONF1_EXT_REG_MASK) << PCI_CONF1_EXT_REG_SHIFT) 1485 1486 #define PCI_CONF1_EXT_ADDRESS(bus, dev, func, reg) \ 1487 (PCI_CONF1_ADDRESS(bus, dev, func, reg) | \ 1488 PCI_CONF1_EXT_REG(reg)) 1489 1490 #endif /* DRIVERS_PCI_H */ 1491