1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef DRIVERS_PCI_H 3 #define DRIVERS_PCI_H 4 5 #include <linux/bug.h> 6 #include <linux/align.h> 7 #include <linux/bitfield.h> 8 #include <linux/pci.h> 9 #include <trace/events/pci.h> 10 11 struct pcie_tlp_log; 12 13 /* Number of possible devfns: 0.0 to 1f.7 inclusive */ 14 #define MAX_NR_DEVFNS 256 15 #define PCI_MAX_NR_DEVS 32 16 17 #define MAX_NR_LANES 16 18 19 #define PCI_FIND_CAP_TTL 48 20 21 #define PCI_VSEC_ID_INTEL_TBT 0x1234 /* Thunderbolt */ 22 23 #define PCIE_LINK_RETRAIN_TIMEOUT_MS 1000 24 25 /* 26 * Power stable to PERST# inactive. 27 * 28 * See the "Power Sequencing and Reset Signal Timings" table of the PCI Express 29 * Card Electromechanical Specification, Revision 5.1, Section 2.9.2, Symbol 30 * "T_PVPERL". 31 */ 32 #define PCIE_T_PVPERL_MS 100 33 34 /* 35 * REFCLK stable before PERST# inactive. 36 * 37 * See the "Power Sequencing and Reset Signal Timings" table of the PCI Express 38 * Card Electromechanical Specification, Revision 5.1, Section 2.9.2, Symbol 39 * "T_PERST-CLK". 40 */ 41 #define PCIE_T_PERST_CLK_US 100 42 43 /* 44 * PERST# active time. 45 * 46 * See the "Power Sequencing and Reset Signal Timings" table of the PCI Express 47 * Card Electromechanical Specification, Revision 6.0, Section 2.11.2, Symbol 48 * "T_PERST". 49 */ 50 #define PCIE_T_PERST_US 100 51 52 /* 53 * PCIe r6.0, sec 5.3.3.2.1 <PME Synchronization> 54 * Recommends 1ms to 10ms timeout to check L2 ready. 55 */ 56 #define PCIE_PME_TO_L2_TIMEOUT_US 10000 57 58 /* 59 * PCIe r6.0, sec 6.6.1 <Conventional Reset> 60 * 61 * - "With a Downstream Port that does not support Link speeds greater 62 * than 5.0 GT/s, software must wait a minimum of 100 ms following exit 63 * from a Conventional Reset before sending a Configuration Request to 64 * the device immediately below that Port." 65 * 66 * - "With a Downstream Port that supports Link speeds greater than 67 * 5.0 GT/s, software must wait a minimum of 100 ms after Link training 68 * completes before sending a Configuration Request to the device 69 * immediately below that Port." 70 */ 71 #define PCIE_RESET_CONFIG_WAIT_MS 100 72 73 /* Parameters for the waiting for link up routine */ 74 #define PCIE_LINK_WAIT_MAX_RETRIES 10 75 #define PCIE_LINK_WAIT_SLEEP_MS 90 76 77 /* Format of TLP; PCIe r7.0, sec 2.2.1 */ 78 #define PCIE_TLP_FMT_3DW_NO_DATA 0x00 /* 3DW header, no data */ 79 #define PCIE_TLP_FMT_4DW_NO_DATA 0x01 /* 4DW header, no data */ 80 #define PCIE_TLP_FMT_3DW_DATA 0x02 /* 3DW header, with data */ 81 #define PCIE_TLP_FMT_4DW_DATA 0x03 /* 4DW header, with data */ 82 83 /* Type of TLP; PCIe r7.0, sec 2.2.1 */ 84 #define PCIE_TLP_TYPE_MEM_RDWR 0x00 /* Memory Read/Write Request */ 85 #define PCIE_TLP_TYPE_IO_RDWR 0x02 /* I/O Read/Write Request */ 86 #define PCIE_TLP_TYPE_CFG0_RDWR 0x04 /* Config Type 0 Read/Write Request */ 87 #define PCIE_TLP_TYPE_CFG1_RDWR 0x05 /* Config Type 1 Read/Write Request */ 88 #define PCIE_TLP_TYPE_MSG 0x10 /* Message With/Without data Request */ 89 90 /* Message Routing (r[2:0]); PCIe r6.0, sec 2.2.8 */ 91 #define PCIE_MSG_TYPE_R_RC 0 92 #define PCIE_MSG_TYPE_R_ADDR 1 93 #define PCIE_MSG_TYPE_R_ID 2 94 #define PCIE_MSG_TYPE_R_BC 3 95 #define PCIE_MSG_TYPE_R_LOCAL 4 96 #define PCIE_MSG_TYPE_R_GATHER 5 97 98 /* Power Management Messages; PCIe r6.0, sec 2.2.8.2 */ 99 #define PCIE_MSG_CODE_PME_TURN_OFF 0x19 100 101 /* INTx Mechanism Messages; PCIe r6.0, sec 2.2.8.1 */ 102 #define PCIE_MSG_CODE_ASSERT_INTA 0x20 103 #define PCIE_MSG_CODE_ASSERT_INTB 0x21 104 #define PCIE_MSG_CODE_ASSERT_INTC 0x22 105 #define PCIE_MSG_CODE_ASSERT_INTD 0x23 106 #define PCIE_MSG_CODE_DEASSERT_INTA 0x24 107 #define PCIE_MSG_CODE_DEASSERT_INTB 0x25 108 #define PCIE_MSG_CODE_DEASSERT_INTC 0x26 109 #define PCIE_MSG_CODE_DEASSERT_INTD 0x27 110 111 /* Cpl. status of Complete; PCIe r7.0, sec 2.2.9.1 */ 112 #define PCIE_CPL_STS_SUCCESS 0x00 /* Successful Completion */ 113 114 #define PCI_BUS_BRIDGE_IO_WINDOW 0 115 #define PCI_BUS_BRIDGE_MEM_WINDOW 1 116 #define PCI_BUS_BRIDGE_PREF_MEM_WINDOW 2 117 118 #define PCI_EXP_AER_FLAGS (PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE | \ 119 PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE) 120 121 extern const unsigned char pcie_link_speed[]; 122 unsigned char pcie_get_link_speed(unsigned int speed); 123 124 extern bool pci_early_dump; 125 126 extern struct mutex pci_rescan_remove_lock; 127 128 bool pcie_cap_has_lnkctl(const struct pci_dev *dev); 129 bool pcie_cap_has_lnkctl2(const struct pci_dev *dev); 130 bool pcie_cap_has_rtctl(const struct pci_dev *dev); 131 132 /* Standard Capability finder */ 133 /** 134 * PCI_FIND_NEXT_CAP - Find a PCI standard capability 135 * @read_cfg: Function pointer for reading PCI config space 136 * @start: Starting position to begin search 137 * @cap: Capability ID to find 138 * @prev_ptr: Pointer to store position of preceding capability (optional) 139 * @args: Arguments to pass to read_cfg function 140 * 141 * Search the capability list in PCI config space to find @cap. If 142 * found, update *prev_ptr with the position of the preceding capability 143 * (if prev_ptr != NULL) 144 * Implements TTL (time-to-live) protection against infinite loops. 145 * 146 * Return: Position of the capability if found, 0 otherwise. 147 */ 148 #define PCI_FIND_NEXT_CAP(read_cfg, start, cap, prev_ptr, args...) \ 149 ({ \ 150 int __ttl = PCI_FIND_CAP_TTL; \ 151 u8 __id, __found_pos = 0; \ 152 u8 __prev_pos = (start); \ 153 u8 __pos = (start); \ 154 u16 __ent; \ 155 \ 156 read_cfg##_byte(args, __pos, &__pos); \ 157 \ 158 while (__ttl--) { \ 159 if (__pos < PCI_STD_HEADER_SIZEOF) \ 160 break; \ 161 \ 162 __pos = ALIGN_DOWN(__pos, 4); \ 163 read_cfg##_word(args, __pos, &__ent); \ 164 \ 165 __id = FIELD_GET(PCI_CAP_ID_MASK, __ent); \ 166 if (__id == 0xff) \ 167 break; \ 168 \ 169 if (__id == (cap)) { \ 170 __found_pos = __pos; \ 171 if (prev_ptr != NULL) \ 172 *(u8 *)prev_ptr = __prev_pos; \ 173 break; \ 174 } \ 175 \ 176 __prev_pos = __pos; \ 177 __pos = FIELD_GET(PCI_CAP_LIST_NEXT_MASK, __ent); \ 178 } \ 179 __found_pos; \ 180 }) 181 182 /* Extended Capability finder */ 183 /** 184 * PCI_FIND_NEXT_EXT_CAP - Find a PCI extended capability 185 * @read_cfg: Function pointer for reading PCI config space 186 * @start: Starting position to begin search (0 for initial search) 187 * @cap: Extended capability ID to find 188 * @prev_ptr: Pointer to store position of preceding capability (optional) 189 * @args: Arguments to pass to read_cfg function 190 * 191 * Search the extended capability list in PCI config space to find @cap. 192 * If found, update *prev_ptr with the position of the preceding capability 193 * (if prev_ptr != NULL) 194 * Implements TTL protection against infinite loops using a calculated 195 * maximum search count. 196 * 197 * Return: Position of the capability if found, 0 otherwise. 198 */ 199 #define PCI_FIND_NEXT_EXT_CAP(read_cfg, start, cap, prev_ptr, args...) \ 200 ({ \ 201 u16 __pos = (start) ?: PCI_CFG_SPACE_SIZE; \ 202 u16 __found_pos = 0; \ 203 u16 __prev_pos; \ 204 int __ttl, __ret; \ 205 u32 __header; \ 206 \ 207 __prev_pos = __pos; \ 208 __ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; \ 209 while (__ttl-- > 0 && __pos >= PCI_CFG_SPACE_SIZE) { \ 210 __ret = read_cfg##_dword(args, __pos, &__header); \ 211 if (__ret != PCIBIOS_SUCCESSFUL) \ 212 break; \ 213 \ 214 if (__header == 0) \ 215 break; \ 216 \ 217 if (PCI_EXT_CAP_ID(__header) == (cap) && __pos != start) {\ 218 __found_pos = __pos; \ 219 if (prev_ptr != NULL) \ 220 *(u16 *)prev_ptr = __prev_pos; \ 221 break; \ 222 } \ 223 \ 224 __prev_pos = __pos; \ 225 __pos = PCI_EXT_CAP_NEXT(__header); \ 226 } \ 227 __found_pos; \ 228 }) 229 230 /* Functions internal to the PCI core code */ 231 232 #ifdef CONFIG_DMI 233 extern const struct attribute_group pci_dev_smbios_attr_group; 234 #endif 235 236 enum pci_mmap_api { 237 PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */ 238 PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */ 239 }; 240 int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai, 241 enum pci_mmap_api mmap_api); 242 243 bool pci_reset_supported(struct pci_dev *dev); 244 void pci_init_reset_methods(struct pci_dev *dev); 245 int pci_bridge_secondary_bus_reset(struct pci_dev *dev); 246 int pci_bus_error_reset(struct pci_dev *dev); 247 int pci_try_reset_bridge(struct pci_dev *bridge); 248 249 struct pci_cap_saved_data { 250 u16 cap_nr; 251 bool cap_extended; 252 unsigned int size; 253 u32 data[]; 254 }; 255 256 struct pci_cap_saved_state { 257 struct hlist_node next; 258 struct pci_cap_saved_data cap; 259 }; 260 261 void pci_allocate_cap_save_buffers(struct pci_dev *dev); 262 void pci_free_cap_save_buffers(struct pci_dev *dev); 263 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size); 264 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, 265 u16 cap, unsigned int size); 266 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap); 267 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, 268 u16 cap); 269 270 #define PCI_PM_D2_DELAY 200 /* usec; see PCIe r4.0, sec 5.9.1 */ 271 #define PCI_PM_D3HOT_WAIT 10 /* msec */ 272 #define PCI_PM_D3COLD_WAIT 100 /* msec */ 273 274 void pci_update_current_state(struct pci_dev *dev, pci_power_t state); 275 void pci_refresh_power_state(struct pci_dev *dev); 276 int pci_power_up(struct pci_dev *dev); 277 void pci_disable_enabled_device(struct pci_dev *dev); 278 int pci_finish_runtime_suspend(struct pci_dev *dev); 279 void pcie_clear_device_status(struct pci_dev *dev); 280 void pcie_clear_root_pme_status(struct pci_dev *dev); 281 bool pci_check_pme_status(struct pci_dev *dev); 282 void pci_pme_wakeup_bus(struct pci_bus *bus); 283 void pci_pme_restore(struct pci_dev *dev); 284 bool pci_dev_need_resume(struct pci_dev *dev); 285 void pci_dev_adjust_pme(struct pci_dev *dev); 286 void pci_dev_complete_resume(struct pci_dev *pci_dev); 287 void pci_config_pm_runtime_get(struct pci_dev *dev); 288 void pci_config_pm_runtime_put(struct pci_dev *dev); 289 void pci_pm_power_up_and_verify_state(struct pci_dev *pci_dev); 290 void pci_pm_init(struct pci_dev *dev); 291 void pci_ea_init(struct pci_dev *dev); 292 bool pci_ea_fixed_busnrs(struct pci_dev *dev, u8 *sec, u8 *sub); 293 void pci_msi_init(struct pci_dev *dev); 294 void pci_msix_init(struct pci_dev *dev); 295 bool pci_bridge_d3_possible(struct pci_dev *dev); 296 void pci_bridge_d3_update(struct pci_dev *dev); 297 int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type); 298 void platform_pci_configure_wake(struct pci_dev *dev); 299 void platform_pci_remove_wake(struct pci_dev *dev); 300 301 static inline bool pci_bus_rrs_vendor_id(u32 l) 302 { 303 return (l & 0xffff) == PCI_VENDOR_ID_PCI_SIG; 304 } 305 306 static inline void pci_wakeup_event(struct pci_dev *dev) 307 { 308 /* Wait 100 ms before the system can be put into a sleep state. */ 309 pm_wakeup_event(&dev->dev, 100); 310 } 311 312 /** 313 * pci_bar_index_is_valid - Check whether a BAR index is within valid range 314 * @bar: BAR index 315 * 316 * Protects against overflowing &struct pci_dev.resource array. 317 * 318 * Return: true for valid index, false otherwise. 319 */ 320 static inline bool pci_bar_index_is_valid(int bar) 321 { 322 if (bar >= 0 && bar < PCI_NUM_RESOURCES) 323 return true; 324 325 return false; 326 } 327 328 static inline bool pci_has_subordinate(struct pci_dev *pci_dev) 329 { 330 return !!(pci_dev->subordinate); 331 } 332 333 static inline bool pci_power_manageable(struct pci_dev *pci_dev) 334 { 335 /* 336 * Currently we allow normal PCI devices and PCI bridges transition 337 * into D3 if their bridge_d3 is set. 338 */ 339 return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3; 340 } 341 342 static inline bool pcie_downstream_port(const struct pci_dev *dev) 343 { 344 int type = pci_pcie_type(dev); 345 346 return type == PCI_EXP_TYPE_ROOT_PORT || 347 type == PCI_EXP_TYPE_DOWNSTREAM || 348 type == PCI_EXP_TYPE_PCIE_BRIDGE; 349 } 350 351 void pci_vpd_init(struct pci_dev *dev); 352 extern const struct attribute_group pci_dev_vpd_attr_group; 353 354 /* PCI Virtual Channel */ 355 int pci_save_vc_state(struct pci_dev *dev); 356 void pci_restore_vc_state(struct pci_dev *dev); 357 void pci_allocate_vc_save_buffers(struct pci_dev *dev); 358 359 /* PCI /proc functions */ 360 #ifdef CONFIG_PROC_FS 361 int pci_proc_attach_device(struct pci_dev *dev); 362 int pci_proc_detach_device(struct pci_dev *dev); 363 int pci_proc_detach_bus(struct pci_bus *bus); 364 #else 365 static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; } 366 static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; } 367 static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; } 368 #endif 369 370 /* Functions for PCI Hotplug drivers to use */ 371 int pci_hp_add_bridge(struct pci_dev *dev); 372 bool pci_hp_spurious_link_change(struct pci_dev *pdev); 373 374 /* Lock for read/write access to pci device and bus lists */ 375 extern struct rw_semaphore pci_bus_sem; 376 extern struct mutex pci_slot_mutex; 377 378 extern raw_spinlock_t pci_lock; 379 380 extern unsigned int pci_pm_d3hot_delay; 381 382 #ifdef CONFIG_PCI_MSI 383 void pci_no_msi(void); 384 #else 385 static inline void pci_no_msi(void) { } 386 #endif 387 388 void pci_realloc_get_opt(char *); 389 390 static inline int pci_no_d1d2(struct pci_dev *dev) 391 { 392 unsigned int parent_dstates = 0; 393 394 if (dev->bus->self) 395 parent_dstates = dev->bus->self->no_d1d2; 396 return (dev->no_d1d2 || parent_dstates); 397 398 } 399 400 #ifdef HAVE_PCI_LEGACY 401 bool pci_legacy_has_sparse(struct pci_bus *bus, enum pci_mmap_state type); 402 #endif 403 404 #ifdef CONFIG_SYSFS 405 extern const struct attribute_group *pci_dev_groups[]; 406 extern const struct attribute_group *pci_dev_attr_groups[]; 407 extern const struct attribute_group *pcibus_groups[]; 408 extern const struct attribute_group *pci_bus_groups[]; 409 extern const struct attribute_group pci_doe_sysfs_group; 410 #else 411 #define pci_dev_groups NULL 412 #define pci_dev_attr_groups NULL 413 #define pcibus_groups NULL 414 #define pci_bus_groups NULL 415 #endif 416 417 extern unsigned long pci_hotplug_io_size; 418 extern unsigned long pci_hotplug_mmio_size; 419 extern unsigned long pci_hotplug_mmio_pref_size; 420 extern unsigned long pci_hotplug_bus_size; 421 422 static inline bool pci_is_cardbus_bridge(struct pci_dev *dev) 423 { 424 return dev->hdr_type == PCI_HEADER_TYPE_CARDBUS; 425 } 426 #ifdef CONFIG_CARDBUS 427 unsigned long pci_cardbus_resource_alignment(const struct resource *res); 428 int pci_bus_size_cardbus_bridge(struct pci_bus *bus, 429 struct list_head *realloc_head); 430 int pci_cardbus_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev, 431 u32 buses, int max, 432 unsigned int available_buses, int pass); 433 int pci_setup_cardbus(char *str); 434 435 #else 436 static inline unsigned long pci_cardbus_resource_alignment(const struct resource *res) 437 { 438 return 0; 439 } 440 static inline int pci_bus_size_cardbus_bridge(struct pci_bus *bus, 441 struct list_head *realloc_head) 442 { 443 return -EOPNOTSUPP; 444 } 445 static inline int pci_cardbus_scan_bridge_extend(struct pci_bus *bus, 446 struct pci_dev *dev, 447 u32 buses, int max, 448 unsigned int available_buses, 449 int pass) 450 { 451 return max; 452 } 453 static inline int pci_setup_cardbus(char *str) { return -ENOENT; } 454 #endif /* CONFIG_CARDBUS */ 455 456 /** 457 * pci_id_from_device - Obtain a pci_device_id from a PCI device 458 * @dev: the PCI device 459 * 460 * Return: a pci_device_id filled. 461 */ 462 static inline struct pci_device_id pci_id_from_device(const struct pci_dev *dev) 463 { 464 return (struct pci_device_id) { 465 .vendor = dev->vendor, 466 .device = dev->device, 467 .subvendor = dev->subsystem_vendor, 468 .subdevice = dev->subsystem_device, 469 .class = dev->class, 470 }; 471 } 472 473 /** 474 * pci_match_one_id - Tell if a PCI device ID matches a needle PCI device ID 475 * @id: single PCI device id structure to match against (needle) 476 * @dev_id: the actual ID from the PCI device 477 * 478 * ID can be retrieved from device using pci_id_from_device(). 479 * 480 * Return: the matching pci_device_id structure or %NULL if there is no match. 481 */ 482 static inline const struct pci_device_id * 483 pci_match_one_id(const struct pci_device_id *id, 484 const struct pci_device_id *dev_id) 485 { 486 if ((id->vendor == PCI_ANY_ID || id->vendor == dev_id->vendor) && 487 (id->device == PCI_ANY_ID || id->device == dev_id->device) && 488 (id->subvendor == PCI_ANY_ID || id->subvendor == dev_id->subvendor) && 489 (id->subdevice == PCI_ANY_ID || id->subdevice == dev_id->subdevice) && 490 !((id->class ^ dev_id->class) & id->class_mask)) 491 return id; 492 return NULL; 493 } 494 495 /* PCI slot sysfs helper code */ 496 #define to_pci_slot(s) container_of(s, struct pci_slot, kobj) 497 498 extern struct kset *pci_slots_kset; 499 500 struct pci_slot_attribute { 501 struct attribute attr; 502 ssize_t (*show)(struct pci_slot *, char *); 503 ssize_t (*store)(struct pci_slot *, const char *, size_t); 504 }; 505 #define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr) 506 507 enum pci_bar_type { 508 pci_bar_unknown, /* Standard PCI BAR probe */ 509 pci_bar_io, /* An I/O port BAR */ 510 pci_bar_mem32, /* A 32-bit memory BAR */ 511 pci_bar_mem64, /* A 64-bit memory BAR */ 512 }; 513 514 void devm_pci_alloc_host_bridge_release(void *data); 515 struct device *pci_get_host_bridge_device(struct pci_dev *dev); 516 void pci_put_host_bridge_device(struct device *dev); 517 518 void pci_resize_resource_set_size(struct pci_dev *dev, int resno, int size); 519 int pci_do_resource_release_and_resize(struct pci_dev *dev, int resno, int size, 520 int exclude_bars); 521 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge); 522 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align); 523 524 int pci_configure_extended_tags(struct pci_dev *dev, void *ign); 525 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl, 526 int rrs_timeout); 527 bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl, 528 int rrs_timeout); 529 530 int pci_setup_device(struct pci_dev *dev); 531 void __pci_size_stdbars(struct pci_dev *dev, int count, 532 unsigned int pos, u32 *sizes); 533 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, 534 struct resource *res, unsigned int reg, u32 *sizes); 535 void pci_configure_ari(struct pci_dev *dev); 536 537 int pci_dev_res_add_to_list(struct list_head *head, struct pci_dev *dev, 538 struct resource *res, resource_size_t add_size, 539 resource_size_t min_align); 540 void __pci_bus_size_bridges(struct pci_bus *bus, 541 struct list_head *realloc_head); 542 void __pci_bus_assign_resources(const struct pci_bus *bus, 543 struct list_head *add_list, 544 struct list_head *fail_head); 545 bool pci_bus_clip_resource(struct pci_dev *dev, int idx); 546 void pci_walk_bus_locked(struct pci_bus *top, 547 int (*cb)(struct pci_dev *, void *), 548 void *userdata); 549 550 const char *pci_resource_name(struct pci_dev *dev, unsigned int i); 551 bool pci_resource_is_optional(const struct pci_dev *dev, int resno); 552 static inline bool pci_resource_is_bridge_win(int resno) 553 { 554 return resno >= PCI_BRIDGE_RESOURCES && 555 resno <= PCI_BRIDGE_RESOURCE_END; 556 } 557 558 /** 559 * pci_resource_num - Reverse lookup resource number from device resources 560 * @dev: PCI device 561 * @res: Resource to lookup index for (MUST be a @dev's resource) 562 * 563 * Perform reverse lookup to determine the resource number for @res within 564 * @dev resource array. NOTE: The caller is responsible for ensuring @res is 565 * among @dev's resources! 566 * 567 * Returns: resource number. 568 */ 569 static inline int pci_resource_num(const struct pci_dev *dev, 570 const struct resource *res) 571 { 572 int resno = res - &dev->resource[0]; 573 574 /* Passing a resource that is not among dev's resources? */ 575 WARN_ON_ONCE(resno >= PCI_NUM_RESOURCES); 576 577 return resno; 578 } 579 580 void pbus_validate_busn(struct pci_bus *bus); 581 struct resource *pbus_select_window(struct pci_bus *bus, 582 const struct resource *res); 583 void pci_reassigndev_resource_alignment(struct pci_dev *dev); 584 void pci_disable_bridge_window(struct pci_dev *dev); 585 struct pci_bus *pci_bus_get(struct pci_bus *bus); 586 void pci_bus_put(struct pci_bus *bus); 587 588 #define PCIE_LNKCAP_SLS2SPEED(lnkcap) \ 589 ({ \ 590 u32 lnkcap_sls = (lnkcap) & PCI_EXP_LNKCAP_SLS; \ 591 \ 592 (lnkcap_sls == PCI_EXP_LNKCAP_SLS_64_0GB ? PCIE_SPEED_64_0GT : \ 593 lnkcap_sls == PCI_EXP_LNKCAP_SLS_32_0GB ? PCIE_SPEED_32_0GT : \ 594 lnkcap_sls == PCI_EXP_LNKCAP_SLS_16_0GB ? PCIE_SPEED_16_0GT : \ 595 lnkcap_sls == PCI_EXP_LNKCAP_SLS_8_0GB ? PCIE_SPEED_8_0GT : \ 596 lnkcap_sls == PCI_EXP_LNKCAP_SLS_5_0GB ? PCIE_SPEED_5_0GT : \ 597 lnkcap_sls == PCI_EXP_LNKCAP_SLS_2_5GB ? PCIE_SPEED_2_5GT : \ 598 PCI_SPEED_UNKNOWN); \ 599 }) 600 601 /* PCIe link information from Link Capabilities 2 */ 602 #define PCIE_LNKCAP2_SLS2SPEED(lnkcap2) \ 603 ((lnkcap2) & PCI_EXP_LNKCAP2_SLS_64_0GB ? PCIE_SPEED_64_0GT : \ 604 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_32_0GB ? PCIE_SPEED_32_0GT : \ 605 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_16_0GB ? PCIE_SPEED_16_0GT : \ 606 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_8_0GB ? PCIE_SPEED_8_0GT : \ 607 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_5_0GB ? PCIE_SPEED_5_0GT : \ 608 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_2_5GB ? PCIE_SPEED_2_5GT : \ 609 PCI_SPEED_UNKNOWN) 610 611 #define PCIE_LNKCTL2_TLS2SPEED(lnkctl2) \ 612 ({ \ 613 u16 lnkctl2_tls = (lnkctl2) & PCI_EXP_LNKCTL2_TLS; \ 614 \ 615 (lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_64_0GT ? PCIE_SPEED_64_0GT : \ 616 lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_32_0GT ? PCIE_SPEED_32_0GT : \ 617 lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_16_0GT ? PCIE_SPEED_16_0GT : \ 618 lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_8_0GT ? PCIE_SPEED_8_0GT : \ 619 lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_5_0GT ? PCIE_SPEED_5_0GT : \ 620 lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_2_5GT ? PCIE_SPEED_2_5GT : \ 621 PCI_SPEED_UNKNOWN); \ 622 }) 623 624 /* PCIe speed to Mb/s reduced by encoding overhead */ 625 #define PCIE_SPEED2MBS_ENC(speed) \ 626 ((speed) == PCIE_SPEED_64_0GT ? 64000*1/1 : \ 627 (speed) == PCIE_SPEED_32_0GT ? 32000*128/130 : \ 628 (speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \ 629 (speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \ 630 (speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \ 631 (speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \ 632 0) 633 634 static inline bool pcie_valid_speed(enum pci_bus_speed speed) 635 { 636 return (speed >= PCIE_SPEED_2_5GT) && (speed <= PCIE_SPEED_64_0GT); 637 } 638 639 static inline u16 pci_bus_speed2lnkctl2(enum pci_bus_speed speed) 640 { 641 static const u8 speed_conv[] = { 642 [PCIE_SPEED_2_5GT] = PCI_EXP_LNKCTL2_TLS_2_5GT, 643 [PCIE_SPEED_5_0GT] = PCI_EXP_LNKCTL2_TLS_5_0GT, 644 [PCIE_SPEED_8_0GT] = PCI_EXP_LNKCTL2_TLS_8_0GT, 645 [PCIE_SPEED_16_0GT] = PCI_EXP_LNKCTL2_TLS_16_0GT, 646 [PCIE_SPEED_32_0GT] = PCI_EXP_LNKCTL2_TLS_32_0GT, 647 [PCIE_SPEED_64_0GT] = PCI_EXP_LNKCTL2_TLS_64_0GT, 648 }; 649 650 if (WARN_ON_ONCE(!pcie_valid_speed(speed))) 651 return 0; 652 653 return speed_conv[speed]; 654 } 655 656 static inline int pcie_dev_speed_mbps(enum pci_bus_speed speed) 657 { 658 switch (speed) { 659 case PCIE_SPEED_2_5GT: 660 return 2500; 661 case PCIE_SPEED_5_0GT: 662 return 5000; 663 case PCIE_SPEED_8_0GT: 664 return 8000; 665 case PCIE_SPEED_16_0GT: 666 return 16000; 667 case PCIE_SPEED_32_0GT: 668 return 32000; 669 case PCIE_SPEED_64_0GT: 670 return 64000; 671 default: 672 break; 673 } 674 675 return -EINVAL; 676 } 677 678 u8 pcie_get_supported_speeds(struct pci_dev *dev); 679 const char *pci_speed_string(enum pci_bus_speed speed); 680 void __pcie_print_link_status(struct pci_dev *dev, bool verbose); 681 void pcie_report_downtraining(struct pci_dev *dev); 682 683 enum pcie_link_change_reason { 684 PCIE_LINK_RETRAIN, 685 PCIE_ADD_BUS, 686 PCIE_BWCTRL_ENABLE, 687 PCIE_BWCTRL_IRQ, 688 PCIE_HOTPLUG, 689 }; 690 691 static inline void __pcie_update_link_speed(struct pci_bus *bus, 692 enum pcie_link_change_reason reason, 693 u16 linksta, u16 linksta2) 694 { 695 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS]; 696 bus->flit_mode = (linksta2 & PCI_EXP_LNKSTA2_FLIT) ? 1 : 0; 697 698 trace_pcie_link_event(bus, 699 reason, 700 FIELD_GET(PCI_EXP_LNKSTA_NLW, linksta), 701 linksta & PCI_EXP_LNKSTA_LINK_STATUS_MASK); 702 } 703 704 void pcie_update_link_speed(struct pci_bus *bus, enum pcie_link_change_reason reason); 705 706 /* Single Root I/O Virtualization */ 707 struct pci_sriov { 708 int pos; /* Capability position */ 709 int nres; /* Number of resources */ 710 u32 cap; /* SR-IOV Capabilities */ 711 u16 ctrl; /* SR-IOV Control */ 712 u16 total_VFs; /* Total VFs associated with the PF */ 713 u16 initial_VFs; /* Initial VFs associated with the PF */ 714 u16 num_VFs; /* Number of VFs available */ 715 u16 offset; /* First VF Routing ID offset */ 716 u16 stride; /* Following VF stride */ 717 u16 vf_device; /* VF device ID */ 718 u32 pgsz; /* Page size for BAR alignment */ 719 u8 link; /* Function Dependency Link */ 720 u8 max_VF_buses; /* Max buses consumed by VFs */ 721 u16 driver_max_VFs; /* Max num VFs driver supports */ 722 struct pci_dev *dev; /* Lowest numbered PF */ 723 struct pci_dev *self; /* This PF */ 724 resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */ 725 u16 vf_rebar_cap; /* VF Resizable BAR capability offset */ 726 bool drivers_autoprobe; /* Auto probing of VFs by driver */ 727 }; 728 729 #ifdef CONFIG_PCI_DOE 730 void pci_doe_init(struct pci_dev *pdev); 731 void pci_doe_destroy(struct pci_dev *pdev); 732 void pci_doe_disconnected(struct pci_dev *pdev); 733 #else 734 static inline void pci_doe_init(struct pci_dev *pdev) { } 735 static inline void pci_doe_destroy(struct pci_dev *pdev) { } 736 static inline void pci_doe_disconnected(struct pci_dev *pdev) { } 737 #endif 738 739 #ifdef CONFIG_PCI_NPEM 740 void pci_npem_create(struct pci_dev *dev); 741 void pci_npem_remove(struct pci_dev *dev); 742 #else 743 static inline void pci_npem_create(struct pci_dev *dev) { } 744 static inline void pci_npem_remove(struct pci_dev *dev) { } 745 #endif 746 747 #if defined(CONFIG_PCI_DOE) && defined(CONFIG_SYSFS) 748 void pci_doe_sysfs_init(struct pci_dev *pci_dev); 749 void pci_doe_sysfs_teardown(struct pci_dev *pdev); 750 #else 751 static inline void pci_doe_sysfs_init(struct pci_dev *pdev) { } 752 static inline void pci_doe_sysfs_teardown(struct pci_dev *pdev) { } 753 #endif 754 755 #ifdef CONFIG_PCI_IDE 756 void pci_ide_init(struct pci_dev *dev); 757 void pci_ide_init_host_bridge(struct pci_host_bridge *hb); 758 void pci_ide_destroy(struct pci_dev *dev); 759 extern const struct attribute_group pci_ide_attr_group; 760 #else 761 static inline void pci_ide_init(struct pci_dev *dev) { } 762 static inline void pci_ide_init_host_bridge(struct pci_host_bridge *hb) { } 763 static inline void pci_ide_destroy(struct pci_dev *dev) { } 764 #endif 765 766 #ifdef CONFIG_PCI_TSM 767 void pci_tsm_init(struct pci_dev *pdev); 768 void pci_tsm_destroy(struct pci_dev *pdev); 769 extern const struct attribute_group pci_tsm_attr_group; 770 extern const struct attribute_group pci_tsm_auth_attr_group; 771 #else 772 static inline void pci_tsm_init(struct pci_dev *pdev) { } 773 static inline void pci_tsm_destroy(struct pci_dev *pdev) { } 774 #endif 775 776 /** 777 * pci_dev_set_io_state - Set the new error state if possible. 778 * 779 * @dev: PCI device to set new error_state 780 * @new: the state we want dev to be in 781 * 782 * If the device is experiencing perm_failure, it has to remain in that state. 783 * Any other transition is allowed. 784 * 785 * Returns true if state has been changed to the requested state. 786 */ 787 static inline bool pci_dev_set_io_state(struct pci_dev *dev, 788 pci_channel_state_t new) 789 { 790 pci_channel_state_t old; 791 792 switch (new) { 793 case pci_channel_io_perm_failure: 794 xchg(&dev->error_state, pci_channel_io_perm_failure); 795 return true; 796 case pci_channel_io_frozen: 797 old = cmpxchg(&dev->error_state, pci_channel_io_normal, 798 pci_channel_io_frozen); 799 return old != pci_channel_io_perm_failure; 800 case pci_channel_io_normal: 801 old = cmpxchg(&dev->error_state, pci_channel_io_frozen, 802 pci_channel_io_normal); 803 return old != pci_channel_io_perm_failure; 804 default: 805 return false; 806 } 807 } 808 809 static inline int pci_dev_set_disconnected(struct pci_dev *dev, void *unused) 810 { 811 pci_dev_set_io_state(dev, pci_channel_io_perm_failure); 812 pci_doe_disconnected(dev); 813 814 return 0; 815 } 816 817 /* pci_dev priv_flags */ 818 #define PCI_DEV_ADDED 0 819 #define PCI_DPC_RECOVERED 1 820 #define PCI_DPC_RECOVERING 2 821 #define PCI_DEV_REMOVED 3 822 #define PCI_LINK_CHANGED 4 823 #define PCI_LINK_CHANGING 5 824 #define PCI_LINK_LBMS_SEEN 6 825 #define PCI_DEV_ALLOW_BINDING 7 826 827 static inline void pci_dev_assign_added(struct pci_dev *dev) 828 { 829 smp_mb__before_atomic(); 830 set_bit(PCI_DEV_ADDED, &dev->priv_flags); 831 smp_mb__after_atomic(); 832 } 833 834 static inline bool pci_dev_test_and_clear_added(struct pci_dev *dev) 835 { 836 return test_and_clear_bit(PCI_DEV_ADDED, &dev->priv_flags); 837 } 838 839 static inline bool pci_dev_is_added(const struct pci_dev *dev) 840 { 841 return test_bit(PCI_DEV_ADDED, &dev->priv_flags); 842 } 843 844 static inline bool pci_dev_test_and_set_removed(struct pci_dev *dev) 845 { 846 return test_and_set_bit(PCI_DEV_REMOVED, &dev->priv_flags); 847 } 848 849 static inline void pci_dev_allow_binding(struct pci_dev *dev) 850 { 851 set_bit(PCI_DEV_ALLOW_BINDING, &dev->priv_flags); 852 } 853 854 static inline bool pci_dev_binding_disallowed(struct pci_dev *dev) 855 { 856 return !test_bit(PCI_DEV_ALLOW_BINDING, &dev->priv_flags); 857 } 858 859 #ifdef CONFIG_PCIEAER 860 #include <linux/aer.h> 861 862 #define AER_MAX_MULTI_ERR_DEVICES 5 /* Not likely to have more */ 863 864 /** 865 * struct aer_err_info - AER Error Information 866 * @dev: Devices reporting error 867 * @ratelimit_print: Flag to log or not log the devices' error. 0=NotLog/1=Log 868 * @__pad1: Padding for alignment 869 * @error_dev_num: Number of devices reporting an error 870 * @level: printk level to use in logging 871 * @id: Value from register PCI_ERR_ROOT_ERR_SRC 872 * @severity: AER severity, 0-UNCOR Non-fatal, 1-UNCOR fatal, 2-COR 873 * @root_ratelimit_print: Flag to log or not log the root's error. 0=NotLog/1=Log 874 * @multi_error_valid: If multiple errors are reported 875 * @first_error: First reported error 876 * @__pad2: Padding for alignment 877 * @is_cxl: Bus type error: 0-PCI Bus error, 1-CXL Bus error 878 * @tlp_header_valid: Indicates if TLP field contains error information 879 * @status: COR/UNCOR error status 880 * @mask: COR/UNCOR mask 881 * @anfe_status: Advisory Non-Fatal Errors, i.e. Uncorrectable Errors signaled 882 * as Correctable Errors (PCIe r7.0 sec 6.2.4.3). Only used if @severity 883 * is AER_CORRECTABLE and @status has Advisory Non-Fatal Error Status set. 884 * @tlp: Transaction packet information 885 */ 886 struct aer_err_info { 887 struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES]; 888 int ratelimit_print[AER_MAX_MULTI_ERR_DEVICES]; 889 int error_dev_num; 890 const char *level; 891 892 unsigned int id:16; 893 894 unsigned int severity:2; 895 unsigned int root_ratelimit_print:1; 896 unsigned int __pad1:4; 897 unsigned int multi_error_valid:1; 898 899 unsigned int first_error:5; 900 unsigned int __pad2:1; 901 unsigned int is_cxl:1; 902 unsigned int tlp_header_valid:1; 903 904 unsigned int status; 905 unsigned int mask; 906 u32 anfe_status; 907 struct pcie_tlp_log tlp; 908 }; 909 910 int aer_get_device_error_info(struct aer_err_info *info, int i); 911 void aer_print_error(struct aer_err_info *info, int i); 912 913 static inline const char *aer_err_bus(struct aer_err_info *info) 914 { 915 return info->is_cxl ? "CXL" : "PCIe"; 916 } 917 918 int pcie_read_tlp_log(struct pci_dev *dev, int where, int where2, 919 unsigned int tlp_len, bool flit, 920 struct pcie_tlp_log *log); 921 unsigned int aer_tlp_log_len(struct pci_dev *dev, u32 aercc); 922 void pcie_print_tlp_log(const struct pci_dev *dev, 923 const struct pcie_tlp_log *log, const char *level, 924 const char *pfx); 925 #endif /* CONFIG_PCIEAER */ 926 927 #ifdef CONFIG_PCIEPORTBUS 928 /* Cached RCEC Endpoint Association */ 929 struct rcec_ea { 930 u8 nextbusn; 931 u8 lastbusn; 932 u32 bitmap; 933 }; 934 #endif 935 936 #ifdef CONFIG_PCIE_DPC 937 void pci_save_dpc_state(struct pci_dev *dev); 938 void pci_restore_dpc_state(struct pci_dev *dev); 939 void pci_dpc_init(struct pci_dev *pdev); 940 void dpc_process_error(struct pci_dev *pdev); 941 pci_ers_result_t dpc_reset_link(struct pci_dev *pdev); 942 bool pci_dpc_recovered(struct pci_dev *pdev); 943 unsigned int dpc_tlp_log_len(struct pci_dev *dev); 944 #else 945 static inline void pci_save_dpc_state(struct pci_dev *dev) { } 946 static inline void pci_restore_dpc_state(struct pci_dev *dev) { } 947 static inline void pci_dpc_init(struct pci_dev *pdev) { } 948 static inline bool pci_dpc_recovered(struct pci_dev *pdev) { return false; } 949 #endif 950 951 #ifdef CONFIG_PCIEPORTBUS 952 void pci_rcec_init(struct pci_dev *dev); 953 void pci_rcec_exit(struct pci_dev *dev); 954 void pcie_link_rcec(struct pci_dev *rcec); 955 void pcie_walk_rcec(struct pci_dev *rcec, 956 int (*cb)(struct pci_dev *, void *), 957 void *userdata); 958 #else 959 static inline void pci_rcec_init(struct pci_dev *dev) { } 960 static inline void pci_rcec_exit(struct pci_dev *dev) { } 961 static inline void pcie_link_rcec(struct pci_dev *rcec) { } 962 static inline void pcie_walk_rcec(struct pci_dev *rcec, 963 int (*cb)(struct pci_dev *, void *), 964 void *userdata) { } 965 #endif 966 967 #ifdef CONFIG_PCI_ATS 968 /* Address Translation Service */ 969 void pci_ats_init(struct pci_dev *dev); 970 void pci_restore_ats_state(struct pci_dev *dev); 971 #else 972 static inline void pci_ats_init(struct pci_dev *d) { } 973 static inline void pci_restore_ats_state(struct pci_dev *dev) { } 974 #endif /* CONFIG_PCI_ATS */ 975 976 #ifdef CONFIG_PCI_PRI 977 void pci_pri_init(struct pci_dev *dev); 978 void pci_restore_pri_state(struct pci_dev *pdev); 979 #else 980 static inline void pci_pri_init(struct pci_dev *dev) { } 981 static inline void pci_restore_pri_state(struct pci_dev *pdev) { } 982 #endif 983 984 #ifdef CONFIG_PCI_PASID 985 void pci_pasid_init(struct pci_dev *dev); 986 void pci_restore_pasid_state(struct pci_dev *pdev); 987 #else 988 static inline void pci_pasid_init(struct pci_dev *dev) { } 989 static inline void pci_restore_pasid_state(struct pci_dev *pdev) { } 990 #endif 991 992 #ifdef CONFIG_PCI_IOV 993 int pci_iov_init(struct pci_dev *dev); 994 void pci_iov_release(struct pci_dev *dev); 995 void pci_iov_remove(struct pci_dev *dev); 996 void pci_iov_update_resource(struct pci_dev *dev, int resno); 997 resource_size_t pci_sriov_resource_alignment(const struct pci_dev *dev, 998 int resno); 999 void pci_restore_iov_state(struct pci_dev *dev); 1000 int pci_iov_bus_range(struct pci_bus *bus); 1001 void pci_iov_resource_set_size(struct pci_dev *dev, int resno, int size); 1002 bool pci_iov_is_memory_decoding_enabled(struct pci_dev *dev); 1003 static inline u16 pci_iov_vf_rebar_cap(struct pci_dev *dev) 1004 { 1005 if (!dev->is_physfn) 1006 return 0; 1007 1008 return dev->sriov->vf_rebar_cap; 1009 } 1010 static inline bool pci_resource_is_iov(int resno) 1011 { 1012 return resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END; 1013 } 1014 static inline int pci_resource_num_from_vf_bar(int resno) 1015 { 1016 return resno + PCI_IOV_RESOURCES; 1017 } 1018 static inline int pci_resource_num_to_vf_bar(int resno) 1019 { 1020 return resno - PCI_IOV_RESOURCES; 1021 } 1022 extern const struct attribute_group sriov_pf_dev_attr_group; 1023 extern const struct attribute_group sriov_vf_dev_attr_group; 1024 #else 1025 static inline int pci_iov_init(struct pci_dev *dev) 1026 { 1027 return -ENODEV; 1028 } 1029 static inline void pci_iov_release(struct pci_dev *dev) { } 1030 static inline void pci_iov_remove(struct pci_dev *dev) { } 1031 static inline void pci_iov_update_resource(struct pci_dev *dev, int resno) { } 1032 static inline resource_size_t pci_sriov_resource_alignment(const struct pci_dev *dev, 1033 int resno) 1034 { 1035 return 0; 1036 } 1037 static inline void pci_restore_iov_state(struct pci_dev *dev) { } 1038 static inline int pci_iov_bus_range(struct pci_bus *bus) 1039 { 1040 return 0; 1041 } 1042 static inline void pci_iov_resource_set_size(struct pci_dev *dev, int resno, 1043 int size) { } 1044 static inline bool pci_iov_is_memory_decoding_enabled(struct pci_dev *dev) 1045 { 1046 return false; 1047 } 1048 static inline u16 pci_iov_vf_rebar_cap(struct pci_dev *dev) 1049 { 1050 return 0; 1051 } 1052 static inline bool pci_resource_is_iov(int resno) 1053 { 1054 return false; 1055 } 1056 static inline int pci_resource_num_from_vf_bar(int resno) 1057 { 1058 WARN_ON_ONCE(1); 1059 return -ENODEV; 1060 } 1061 static inline int pci_resource_num_to_vf_bar(int resno) 1062 { 1063 WARN_ON_ONCE(1); 1064 return -ENODEV; 1065 } 1066 #endif /* CONFIG_PCI_IOV */ 1067 1068 #ifdef CONFIG_PCIE_TPH 1069 void pci_restore_tph_state(struct pci_dev *dev); 1070 void pci_save_tph_state(struct pci_dev *dev); 1071 void pci_no_tph(void); 1072 void pci_tph_init(struct pci_dev *dev); 1073 #else 1074 static inline void pci_restore_tph_state(struct pci_dev *dev) { } 1075 static inline void pci_save_tph_state(struct pci_dev *dev) { } 1076 static inline void pci_no_tph(void) { } 1077 static inline void pci_tph_init(struct pci_dev *dev) { } 1078 #endif 1079 1080 #ifdef CONFIG_PCIE_PTM 1081 void pci_ptm_init(struct pci_dev *dev); 1082 void pci_save_ptm_state(struct pci_dev *dev); 1083 void pci_restore_ptm_state(struct pci_dev *dev); 1084 void pci_suspend_ptm(struct pci_dev *dev); 1085 void pci_resume_ptm(struct pci_dev *dev); 1086 #else 1087 static inline void pci_ptm_init(struct pci_dev *dev) { } 1088 static inline void pci_save_ptm_state(struct pci_dev *dev) { } 1089 static inline void pci_restore_ptm_state(struct pci_dev *dev) { } 1090 static inline void pci_suspend_ptm(struct pci_dev *dev) { } 1091 static inline void pci_resume_ptm(struct pci_dev *dev) { } 1092 #endif 1093 1094 resource_size_t pci_resource_alignment(const struct pci_dev *dev, 1095 const struct resource *res); 1096 1097 resource_size_t pci_min_window_alignment(struct pci_bus *bus, 1098 unsigned long type); 1099 1100 void pci_acs_init(struct pci_dev *dev); 1101 void pci_enable_acs(struct pci_dev *dev); 1102 #ifdef CONFIG_PCI_QUIRKS 1103 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags); 1104 int pci_dev_specific_enable_acs(struct pci_dev *dev); 1105 int pci_dev_specific_disable_acs_redir(struct pci_dev *dev); 1106 void pci_disable_broken_acs_cap(struct pci_dev *pdev); 1107 int pcie_failed_link_retrain(struct pci_dev *dev); 1108 #else 1109 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev, 1110 u16 acs_flags) 1111 { 1112 return -ENOTTY; 1113 } 1114 static inline int pci_dev_specific_enable_acs(struct pci_dev *dev) 1115 { 1116 return -ENOTTY; 1117 } 1118 static inline int pci_dev_specific_disable_acs_redir(struct pci_dev *dev) 1119 { 1120 return -ENOTTY; 1121 } 1122 static inline void pci_disable_broken_acs_cap(struct pci_dev *dev) { } 1123 static inline int pcie_failed_link_retrain(struct pci_dev *dev) 1124 { 1125 return -ENOTTY; 1126 } 1127 #endif 1128 1129 /* PCI error reporting and recovery */ 1130 pci_ers_result_t pcie_do_recovery(struct pci_dev *dev, 1131 pci_channel_state_t state, 1132 pci_ers_result_t (*reset_subordinates)(struct pci_dev *pdev)); 1133 1134 bool pcie_wait_for_link(struct pci_dev *pdev, bool active); 1135 int pcie_retrain_link(struct pci_dev *pdev, bool use_lt); 1136 1137 /* ASPM-related functionality we need even without CONFIG_PCIEASPM */ 1138 void pci_save_ltr_state(struct pci_dev *dev); 1139 void pci_restore_ltr_state(struct pci_dev *dev); 1140 void pci_configure_aspm_l1ss(struct pci_dev *dev); 1141 void pci_save_aspm_l1ss_state(struct pci_dev *dev); 1142 void pci_restore_aspm_l1ss_state(struct pci_dev *dev); 1143 1144 #ifdef CONFIG_PCIEASPM 1145 void pcie_aspm_remove_cap(struct pci_dev *pdev, u32 lnkcap); 1146 void pcie_aspm_init_link_state(struct pci_dev *pdev); 1147 void pcie_aspm_exit_link_state(struct pci_dev *pdev); 1148 void pcie_aspm_pm_state_change(struct pci_dev *pdev, bool locked); 1149 void pcie_aspm_powersave_config_link(struct pci_dev *pdev); 1150 void pci_configure_ltr(struct pci_dev *pdev); 1151 void pci_bridge_reconfigure_ltr(struct pci_dev *pdev); 1152 void pcie_encode_t_power_on(u32 t_power_on_us, u8 *scale, u8 *value); 1153 #else 1154 static inline void pcie_aspm_remove_cap(struct pci_dev *pdev, u32 lnkcap) { } 1155 static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { } 1156 static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { } 1157 static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev, bool locked) { } 1158 static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { } 1159 static inline void pci_configure_ltr(struct pci_dev *pdev) { } 1160 static inline void pci_bridge_reconfigure_ltr(struct pci_dev *pdev) { } 1161 static inline void pcie_encode_t_power_on(u32 t_power_on_us, u8 *scale, u8 *value) 1162 { 1163 *scale = 0; 1164 *value = 0; 1165 } 1166 #endif 1167 1168 #ifdef CONFIG_PCIE_ECRC 1169 void pcie_set_ecrc_checking(struct pci_dev *dev); 1170 void pcie_ecrc_get_policy(char *str); 1171 #else 1172 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { } 1173 static inline void pcie_ecrc_get_policy(char *str) { } 1174 #endif 1175 1176 #ifdef CONFIG_PCIEPORTBUS 1177 void pcie_reset_lbms(struct pci_dev *port); 1178 #else 1179 static inline void pcie_reset_lbms(struct pci_dev *port) {} 1180 #endif 1181 1182 struct pci_dev_reset_methods { 1183 u16 vendor; 1184 u16 device; 1185 int (*reset)(struct pci_dev *dev, bool probe); 1186 }; 1187 1188 struct pci_reset_fn_method { 1189 int (*reset_fn)(struct pci_dev *pdev, bool probe); 1190 char *name; 1191 }; 1192 extern const struct pci_reset_fn_method pci_reset_fn_methods[]; 1193 1194 #ifdef CONFIG_PCI_QUIRKS 1195 int pci_dev_specific_reset(struct pci_dev *dev, bool probe); 1196 #else 1197 static inline int pci_dev_specific_reset(struct pci_dev *dev, bool probe) 1198 { 1199 return -ENOTTY; 1200 } 1201 #endif 1202 1203 #if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_PCI_ATS) 1204 bool pci_dev_specific_ats_required(struct pci_dev *dev); 1205 #else 1206 static inline bool pci_dev_specific_ats_required(struct pci_dev *dev) 1207 { 1208 return false; 1209 } 1210 #endif 1211 1212 #if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64) 1213 int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment, 1214 struct resource *res); 1215 #else 1216 static inline int acpi_get_rc_resources(struct device *dev, const char *hid, 1217 u16 segment, struct resource *res) 1218 { 1219 return -ENODEV; 1220 } 1221 #endif 1222 1223 void pci_rebar_init(struct pci_dev *pdev); 1224 void pci_restore_rebar_state(struct pci_dev *pdev); 1225 int pci_rebar_get_current_size(struct pci_dev *pdev, int bar); 1226 int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size); 1227 1228 struct device_node; 1229 1230 #define PCI_EQ_RESV 0xff 1231 1232 enum equalization_preset_type { 1233 EQ_PRESET_TYPE_8GTS, 1234 EQ_PRESET_TYPE_16GTS, 1235 EQ_PRESET_TYPE_32GTS, 1236 EQ_PRESET_TYPE_64GTS, 1237 EQ_PRESET_TYPE_MAX 1238 }; 1239 1240 struct pci_eq_presets { 1241 u16 eq_presets_8gts[MAX_NR_LANES]; 1242 u8 eq_presets_Ngts[EQ_PRESET_TYPE_MAX - 1][MAX_NR_LANES]; 1243 }; 1244 1245 #ifdef CONFIG_OF 1246 int of_get_pci_domain_nr(struct device_node *node); 1247 int of_pci_get_max_link_speed(struct device_node *node); 1248 u32 of_pci_get_slot_power_limit(struct device_node *node, 1249 u8 *slot_power_limit_value, 1250 u8 *slot_power_limit_scale); 1251 bool of_pci_preserve_config(struct device_node *node); 1252 int pci_set_of_node(struct pci_dev *dev); 1253 void pci_release_of_node(struct pci_dev *dev); 1254 void pci_set_bus_of_node(struct pci_bus *bus); 1255 void pci_release_bus_of_node(struct pci_bus *bus); 1256 1257 int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge); 1258 bool of_pci_supply_present(struct device_node *np); 1259 int of_pci_get_equalization_presets(struct device *dev, 1260 struct pci_eq_presets *presets, 1261 int num_lanes); 1262 #else 1263 static inline int 1264 of_get_pci_domain_nr(struct device_node *node) 1265 { 1266 return -1; 1267 } 1268 1269 static inline int 1270 of_pci_get_max_link_speed(struct device_node *node) 1271 { 1272 return -EINVAL; 1273 } 1274 1275 static inline u32 1276 of_pci_get_slot_power_limit(struct device_node *node, 1277 u8 *slot_power_limit_value, 1278 u8 *slot_power_limit_scale) 1279 { 1280 if (slot_power_limit_value) 1281 *slot_power_limit_value = 0; 1282 if (slot_power_limit_scale) 1283 *slot_power_limit_scale = 0; 1284 return 0; 1285 } 1286 1287 static inline bool of_pci_preserve_config(struct device_node *node) 1288 { 1289 return false; 1290 } 1291 1292 static inline int pci_set_of_node(struct pci_dev *dev) { return 0; } 1293 static inline void pci_release_of_node(struct pci_dev *dev) { } 1294 static inline void pci_set_bus_of_node(struct pci_bus *bus) { } 1295 static inline void pci_release_bus_of_node(struct pci_bus *bus) { } 1296 1297 static inline int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge) 1298 { 1299 return 0; 1300 } 1301 1302 static inline bool of_pci_supply_present(struct device_node *np) 1303 { 1304 return false; 1305 } 1306 1307 static inline int of_pci_get_equalization_presets(struct device *dev, 1308 struct pci_eq_presets *presets, 1309 int num_lanes) 1310 { 1311 presets->eq_presets_8gts[0] = PCI_EQ_RESV; 1312 for (int i = 0; i < EQ_PRESET_TYPE_MAX - 1; i++) 1313 presets->eq_presets_Ngts[i][0] = PCI_EQ_RESV; 1314 1315 return 0; 1316 } 1317 #endif /* CONFIG_OF */ 1318 1319 struct of_changeset; 1320 1321 #ifdef CONFIG_PCI_DYNAMIC_OF_NODES 1322 void of_pci_make_dev_node(struct pci_dev *pdev); 1323 void of_pci_remove_node(struct pci_dev *pdev); 1324 int of_pci_add_properties(struct pci_dev *pdev, struct of_changeset *ocs, 1325 struct device_node *np); 1326 void of_pci_make_host_bridge_node(struct pci_host_bridge *bridge); 1327 void of_pci_remove_host_bridge_node(struct pci_host_bridge *bridge); 1328 int of_pci_add_host_bridge_properties(struct pci_host_bridge *bridge, 1329 struct of_changeset *ocs, 1330 struct device_node *np); 1331 #else 1332 static inline void of_pci_make_dev_node(struct pci_dev *pdev) { } 1333 static inline void of_pci_remove_node(struct pci_dev *pdev) { } 1334 static inline void of_pci_make_host_bridge_node(struct pci_host_bridge *bridge) { } 1335 static inline void of_pci_remove_host_bridge_node(struct pci_host_bridge *bridge) { } 1336 #endif 1337 1338 #ifdef CONFIG_PCIEAER 1339 void pci_no_aer(void); 1340 void pci_aer_init(struct pci_dev *dev); 1341 void pci_aer_exit(struct pci_dev *dev); 1342 extern const struct attribute_group aer_stats_attr_group; 1343 extern const struct attribute_group aer_attr_group; 1344 void pci_aer_clear_fatal_status(struct pci_dev *dev); 1345 int pci_aer_clear_status(struct pci_dev *dev); 1346 int pci_aer_raw_clear_status(struct pci_dev *dev); 1347 void pci_save_aer_state(struct pci_dev *dev); 1348 void pci_restore_aer_state(struct pci_dev *dev); 1349 #else 1350 static inline void pci_no_aer(void) { } 1351 static inline void pci_aer_init(struct pci_dev *d) { } 1352 static inline void pci_aer_exit(struct pci_dev *d) { } 1353 static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { } 1354 static inline int pci_aer_clear_status(struct pci_dev *dev) { return -EINVAL; } 1355 static inline int pci_aer_raw_clear_status(struct pci_dev *dev) { return -EINVAL; } 1356 static inline void pci_save_aer_state(struct pci_dev *dev) { } 1357 static inline void pci_restore_aer_state(struct pci_dev *dev) { } 1358 #endif 1359 1360 #ifdef CONFIG_ACPI 1361 bool pci_acpi_preserve_config(struct pci_host_bridge *bridge); 1362 int pci_acpi_program_hp_params(struct pci_dev *dev); 1363 extern const struct attribute_group pci_dev_acpi_attr_group; 1364 void pci_set_acpi_fwnode(struct pci_dev *dev); 1365 int pci_dev_acpi_reset(struct pci_dev *dev, bool probe); 1366 bool acpi_pci_power_manageable(struct pci_dev *dev); 1367 bool acpi_pci_bridge_d3(struct pci_dev *dev); 1368 int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state); 1369 pci_power_t acpi_pci_get_power_state(struct pci_dev *dev); 1370 void acpi_pci_refresh_power_state(struct pci_dev *dev); 1371 int acpi_pci_wakeup(struct pci_dev *dev, bool enable); 1372 bool acpi_pci_need_resume(struct pci_dev *dev); 1373 pci_power_t acpi_pci_choose_state(struct pci_dev *pdev); 1374 #else 1375 static inline bool pci_acpi_preserve_config(struct pci_host_bridge *bridge) 1376 { 1377 return false; 1378 } 1379 static inline int pci_dev_acpi_reset(struct pci_dev *dev, bool probe) 1380 { 1381 return -ENOTTY; 1382 } 1383 static inline void pci_set_acpi_fwnode(struct pci_dev *dev) { } 1384 static inline int pci_acpi_program_hp_params(struct pci_dev *dev) 1385 { 1386 return -ENODEV; 1387 } 1388 static inline bool acpi_pci_power_manageable(struct pci_dev *dev) 1389 { 1390 return false; 1391 } 1392 static inline bool acpi_pci_bridge_d3(struct pci_dev *dev) 1393 { 1394 return false; 1395 } 1396 static inline int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state) 1397 { 1398 return -ENODEV; 1399 } 1400 static inline pci_power_t acpi_pci_get_power_state(struct pci_dev *dev) 1401 { 1402 return PCI_UNKNOWN; 1403 } 1404 static inline void acpi_pci_refresh_power_state(struct pci_dev *dev) { } 1405 static inline int acpi_pci_wakeup(struct pci_dev *dev, bool enable) 1406 { 1407 return -ENODEV; 1408 } 1409 static inline bool acpi_pci_need_resume(struct pci_dev *dev) 1410 { 1411 return false; 1412 } 1413 static inline pci_power_t acpi_pci_choose_state(struct pci_dev *pdev) 1414 { 1415 return PCI_POWER_ERROR; 1416 } 1417 #endif 1418 1419 #ifdef CONFIG_PCIEASPM 1420 extern const struct attribute_group aspm_ctrl_attr_group; 1421 #endif 1422 1423 #ifdef CONFIG_X86_INTEL_MID 1424 bool pci_use_mid_pm(void); 1425 int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state); 1426 pci_power_t mid_pci_get_power_state(struct pci_dev *pdev); 1427 #else 1428 static inline bool pci_use_mid_pm(void) 1429 { 1430 return false; 1431 } 1432 static inline int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state) 1433 { 1434 return -ENODEV; 1435 } 1436 static inline pci_power_t mid_pci_get_power_state(struct pci_dev *pdev) 1437 { 1438 return PCI_UNKNOWN; 1439 } 1440 #endif 1441 1442 #ifdef CONFIG_PCI_MSI 1443 int pci_msix_write_tph_tag(struct pci_dev *pdev, unsigned int index, u16 tag); 1444 #else 1445 static inline int pci_msix_write_tph_tag(struct pci_dev *pdev, unsigned int index, u16 tag) 1446 { 1447 return -ENODEV; 1448 } 1449 #endif 1450 1451 /* 1452 * Config Address for PCI Configuration Mechanism #1 1453 * 1454 * See PCI Local Bus Specification, Revision 3.0, 1455 * Section 3.2.2.3.2, Figure 3-2, p. 50. 1456 */ 1457 1458 #define PCI_CONF1_BUS_SHIFT 16 /* Bus number */ 1459 #define PCI_CONF1_DEV_SHIFT 11 /* Device number */ 1460 #define PCI_CONF1_FUNC_SHIFT 8 /* Function number */ 1461 1462 #define PCI_CONF1_BUS_MASK 0xff 1463 #define PCI_CONF1_DEV_MASK 0x1f 1464 #define PCI_CONF1_FUNC_MASK 0x7 1465 #define PCI_CONF1_REG_MASK 0xfc /* Limit aligned offset to a maximum of 256B */ 1466 1467 #define PCI_CONF1_ENABLE BIT(31) 1468 #define PCI_CONF1_BUS(x) (((x) & PCI_CONF1_BUS_MASK) << PCI_CONF1_BUS_SHIFT) 1469 #define PCI_CONF1_DEV(x) (((x) & PCI_CONF1_DEV_MASK) << PCI_CONF1_DEV_SHIFT) 1470 #define PCI_CONF1_FUNC(x) (((x) & PCI_CONF1_FUNC_MASK) << PCI_CONF1_FUNC_SHIFT) 1471 #define PCI_CONF1_REG(x) ((x) & PCI_CONF1_REG_MASK) 1472 1473 #define PCI_CONF1_ADDRESS(bus, dev, func, reg) \ 1474 (PCI_CONF1_ENABLE | \ 1475 PCI_CONF1_BUS(bus) | \ 1476 PCI_CONF1_DEV(dev) | \ 1477 PCI_CONF1_FUNC(func) | \ 1478 PCI_CONF1_REG(reg)) 1479 1480 /* 1481 * Extension of PCI Config Address for accessing extended PCIe registers 1482 * 1483 * No standardized specification, but used on lot of non-ECAM-compliant ARM SoCs 1484 * or on AMD Barcelona and new CPUs. Reserved bits [27:24] of PCI Config Address 1485 * are used for specifying additional 4 high bits of PCI Express register. 1486 */ 1487 1488 #define PCI_CONF1_EXT_REG_SHIFT 16 1489 #define PCI_CONF1_EXT_REG_MASK 0xf00 1490 #define PCI_CONF1_EXT_REG(x) (((x) & PCI_CONF1_EXT_REG_MASK) << PCI_CONF1_EXT_REG_SHIFT) 1491 1492 #define PCI_CONF1_EXT_ADDRESS(bus, dev, func, reg) \ 1493 (PCI_CONF1_ADDRESS(bus, dev, func, reg) | \ 1494 PCI_CONF1_EXT_REG(reg)) 1495 1496 #endif /* DRIVERS_PCI_H */ 1497