1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef DRIVERS_PCI_H 3 #define DRIVERS_PCI_H 4 5 #include <linux/pci.h> 6 7 struct pcie_tlp_log; 8 9 /* Number of possible devfns: 0.0 to 1f.7 inclusive */ 10 #define MAX_NR_DEVFNS 256 11 12 #define MAX_NR_LANES 16 13 14 #define PCI_FIND_CAP_TTL 48 15 16 #define PCI_VSEC_ID_INTEL_TBT 0x1234 /* Thunderbolt */ 17 18 #define PCIE_LINK_RETRAIN_TIMEOUT_MS 1000 19 20 /* 21 * Power stable to PERST# inactive. 22 * 23 * See the "Power Sequencing and Reset Signal Timings" table of the PCI Express 24 * Card Electromechanical Specification, Revision 5.1, Section 2.9.2, Symbol 25 * "T_PVPERL". 26 */ 27 #define PCIE_T_PVPERL_MS 100 28 29 /* 30 * REFCLK stable before PERST# inactive. 31 * 32 * See the "Power Sequencing and Reset Signal Timings" table of the PCI Express 33 * Card Electromechanical Specification, Revision 5.1, Section 2.9.2, Symbol 34 * "T_PERST-CLK". 35 */ 36 #define PCIE_T_PERST_CLK_US 100 37 38 /* 39 * PCIe r6.0, sec 5.3.3.2.1 <PME Synchronization> 40 * Recommends 1ms to 10ms timeout to check L2 ready. 41 */ 42 #define PCIE_PME_TO_L2_TIMEOUT_US 10000 43 44 /* 45 * PCIe r6.0, sec 6.6.1 <Conventional Reset> 46 * 47 * - "With a Downstream Port that does not support Link speeds greater 48 * than 5.0 GT/s, software must wait a minimum of 100 ms following exit 49 * from a Conventional Reset before sending a Configuration Request to 50 * the device immediately below that Port." 51 * 52 * - "With a Downstream Port that supports Link speeds greater than 53 * 5.0 GT/s, software must wait a minimum of 100 ms after Link training 54 * completes before sending a Configuration Request to the device 55 * immediately below that Port." 56 */ 57 #define PCIE_RESET_CONFIG_WAIT_MS 100 58 59 /* Parameters for the waiting for link up routine */ 60 #define PCIE_LINK_WAIT_MAX_RETRIES 10 61 #define PCIE_LINK_WAIT_SLEEP_MS 90 62 63 /* Message Routing (r[2:0]); PCIe r6.0, sec 2.2.8 */ 64 #define PCIE_MSG_TYPE_R_RC 0 65 #define PCIE_MSG_TYPE_R_ADDR 1 66 #define PCIE_MSG_TYPE_R_ID 2 67 #define PCIE_MSG_TYPE_R_BC 3 68 #define PCIE_MSG_TYPE_R_LOCAL 4 69 #define PCIE_MSG_TYPE_R_GATHER 5 70 71 /* Power Management Messages; PCIe r6.0, sec 2.2.8.2 */ 72 #define PCIE_MSG_CODE_PME_TURN_OFF 0x19 73 74 /* INTx Mechanism Messages; PCIe r6.0, sec 2.2.8.1 */ 75 #define PCIE_MSG_CODE_ASSERT_INTA 0x20 76 #define PCIE_MSG_CODE_ASSERT_INTB 0x21 77 #define PCIE_MSG_CODE_ASSERT_INTC 0x22 78 #define PCIE_MSG_CODE_ASSERT_INTD 0x23 79 #define PCIE_MSG_CODE_DEASSERT_INTA 0x24 80 #define PCIE_MSG_CODE_DEASSERT_INTB 0x25 81 #define PCIE_MSG_CODE_DEASSERT_INTC 0x26 82 #define PCIE_MSG_CODE_DEASSERT_INTD 0x27 83 84 extern const unsigned char pcie_link_speed[]; 85 extern bool pci_early_dump; 86 87 bool pcie_cap_has_lnkctl(const struct pci_dev *dev); 88 bool pcie_cap_has_lnkctl2(const struct pci_dev *dev); 89 bool pcie_cap_has_rtctl(const struct pci_dev *dev); 90 91 /* Functions internal to the PCI core code */ 92 93 #ifdef CONFIG_DMI 94 extern const struct attribute_group pci_dev_smbios_attr_group; 95 #endif 96 97 enum pci_mmap_api { 98 PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */ 99 PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */ 100 }; 101 int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai, 102 enum pci_mmap_api mmap_api); 103 104 bool pci_reset_supported(struct pci_dev *dev); 105 void pci_init_reset_methods(struct pci_dev *dev); 106 int pci_bridge_secondary_bus_reset(struct pci_dev *dev); 107 int pci_bus_error_reset(struct pci_dev *dev); 108 int __pci_reset_bus(struct pci_bus *bus); 109 110 struct pci_cap_saved_data { 111 u16 cap_nr; 112 bool cap_extended; 113 unsigned int size; 114 u32 data[]; 115 }; 116 117 struct pci_cap_saved_state { 118 struct hlist_node next; 119 struct pci_cap_saved_data cap; 120 }; 121 122 void pci_allocate_cap_save_buffers(struct pci_dev *dev); 123 void pci_free_cap_save_buffers(struct pci_dev *dev); 124 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size); 125 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, 126 u16 cap, unsigned int size); 127 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap); 128 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, 129 u16 cap); 130 131 #define PCI_PM_D2_DELAY 200 /* usec; see PCIe r4.0, sec 5.9.1 */ 132 #define PCI_PM_D3HOT_WAIT 10 /* msec */ 133 #define PCI_PM_D3COLD_WAIT 100 /* msec */ 134 135 void pci_update_current_state(struct pci_dev *dev, pci_power_t state); 136 void pci_refresh_power_state(struct pci_dev *dev); 137 int pci_power_up(struct pci_dev *dev); 138 void pci_disable_enabled_device(struct pci_dev *dev); 139 int pci_finish_runtime_suspend(struct pci_dev *dev); 140 void pcie_clear_device_status(struct pci_dev *dev); 141 void pcie_clear_root_pme_status(struct pci_dev *dev); 142 bool pci_check_pme_status(struct pci_dev *dev); 143 void pci_pme_wakeup_bus(struct pci_bus *bus); 144 void pci_pme_restore(struct pci_dev *dev); 145 bool pci_dev_need_resume(struct pci_dev *dev); 146 void pci_dev_adjust_pme(struct pci_dev *dev); 147 void pci_dev_complete_resume(struct pci_dev *pci_dev); 148 void pci_config_pm_runtime_get(struct pci_dev *dev); 149 void pci_config_pm_runtime_put(struct pci_dev *dev); 150 void pci_pm_power_up_and_verify_state(struct pci_dev *pci_dev); 151 void pci_pm_init(struct pci_dev *dev); 152 void pci_ea_init(struct pci_dev *dev); 153 void pci_msi_init(struct pci_dev *dev); 154 void pci_msix_init(struct pci_dev *dev); 155 bool pci_bridge_d3_possible(struct pci_dev *dev); 156 void pci_bridge_d3_update(struct pci_dev *dev); 157 int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type); 158 159 static inline bool pci_bus_rrs_vendor_id(u32 l) 160 { 161 return (l & 0xffff) == PCI_VENDOR_ID_PCI_SIG; 162 } 163 164 static inline void pci_wakeup_event(struct pci_dev *dev) 165 { 166 /* Wait 100 ms before the system can be put into a sleep state. */ 167 pm_wakeup_event(&dev->dev, 100); 168 } 169 170 /** 171 * pci_bar_index_is_valid - Check whether a BAR index is within valid range 172 * @bar: BAR index 173 * 174 * Protects against overflowing &struct pci_dev.resource array. 175 * 176 * Return: true for valid index, false otherwise. 177 */ 178 static inline bool pci_bar_index_is_valid(int bar) 179 { 180 if (bar >= 0 && bar < PCI_NUM_RESOURCES) 181 return true; 182 183 return false; 184 } 185 186 static inline bool pci_has_subordinate(struct pci_dev *pci_dev) 187 { 188 return !!(pci_dev->subordinate); 189 } 190 191 static inline bool pci_power_manageable(struct pci_dev *pci_dev) 192 { 193 /* 194 * Currently we allow normal PCI devices and PCI bridges transition 195 * into D3 if their bridge_d3 is set. 196 */ 197 return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3; 198 } 199 200 static inline bool pcie_downstream_port(const struct pci_dev *dev) 201 { 202 int type = pci_pcie_type(dev); 203 204 return type == PCI_EXP_TYPE_ROOT_PORT || 205 type == PCI_EXP_TYPE_DOWNSTREAM || 206 type == PCI_EXP_TYPE_PCIE_BRIDGE; 207 } 208 209 void pci_vpd_init(struct pci_dev *dev); 210 extern const struct attribute_group pci_dev_vpd_attr_group; 211 212 /* PCI Virtual Channel */ 213 int pci_save_vc_state(struct pci_dev *dev); 214 void pci_restore_vc_state(struct pci_dev *dev); 215 void pci_allocate_vc_save_buffers(struct pci_dev *dev); 216 217 /* PCI /proc functions */ 218 #ifdef CONFIG_PROC_FS 219 int pci_proc_attach_device(struct pci_dev *dev); 220 int pci_proc_detach_device(struct pci_dev *dev); 221 int pci_proc_detach_bus(struct pci_bus *bus); 222 #else 223 static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; } 224 static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; } 225 static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; } 226 #endif 227 228 /* Functions for PCI Hotplug drivers to use */ 229 int pci_hp_add_bridge(struct pci_dev *dev); 230 bool pci_hp_spurious_link_change(struct pci_dev *pdev); 231 232 #if defined(CONFIG_SYSFS) && defined(HAVE_PCI_LEGACY) 233 void pci_create_legacy_files(struct pci_bus *bus); 234 void pci_remove_legacy_files(struct pci_bus *bus); 235 #else 236 static inline void pci_create_legacy_files(struct pci_bus *bus) { } 237 static inline void pci_remove_legacy_files(struct pci_bus *bus) { } 238 #endif 239 240 /* Lock for read/write access to pci device and bus lists */ 241 extern struct rw_semaphore pci_bus_sem; 242 extern struct mutex pci_slot_mutex; 243 244 extern raw_spinlock_t pci_lock; 245 246 extern unsigned int pci_pm_d3hot_delay; 247 248 #ifdef CONFIG_PCI_MSI 249 void pci_no_msi(void); 250 #else 251 static inline void pci_no_msi(void) { } 252 #endif 253 254 void pci_realloc_get_opt(char *); 255 256 static inline int pci_no_d1d2(struct pci_dev *dev) 257 { 258 unsigned int parent_dstates = 0; 259 260 if (dev->bus->self) 261 parent_dstates = dev->bus->self->no_d1d2; 262 return (dev->no_d1d2 || parent_dstates); 263 264 } 265 266 #ifdef CONFIG_SYSFS 267 int pci_create_sysfs_dev_files(struct pci_dev *pdev); 268 void pci_remove_sysfs_dev_files(struct pci_dev *pdev); 269 extern const struct attribute_group *pci_dev_groups[]; 270 extern const struct attribute_group *pci_dev_attr_groups[]; 271 extern const struct attribute_group *pcibus_groups[]; 272 extern const struct attribute_group *pci_bus_groups[]; 273 extern const struct attribute_group pci_doe_sysfs_group; 274 #else 275 static inline int pci_create_sysfs_dev_files(struct pci_dev *pdev) { return 0; } 276 static inline void pci_remove_sysfs_dev_files(struct pci_dev *pdev) { } 277 #define pci_dev_groups NULL 278 #define pci_dev_attr_groups NULL 279 #define pcibus_groups NULL 280 #define pci_bus_groups NULL 281 #endif 282 283 extern unsigned long pci_hotplug_io_size; 284 extern unsigned long pci_hotplug_mmio_size; 285 extern unsigned long pci_hotplug_mmio_pref_size; 286 extern unsigned long pci_hotplug_bus_size; 287 extern unsigned long pci_cardbus_io_size; 288 extern unsigned long pci_cardbus_mem_size; 289 290 /** 291 * pci_match_one_device - Tell if a PCI device structure has a matching 292 * PCI device id structure 293 * @id: single PCI device id structure to match 294 * @dev: the PCI device structure to match against 295 * 296 * Returns the matching pci_device_id structure or %NULL if there is no match. 297 */ 298 static inline const struct pci_device_id * 299 pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev) 300 { 301 if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) && 302 (id->device == PCI_ANY_ID || id->device == dev->device) && 303 (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) && 304 (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) && 305 !((id->class ^ dev->class) & id->class_mask)) 306 return id; 307 return NULL; 308 } 309 310 /* PCI slot sysfs helper code */ 311 #define to_pci_slot(s) container_of(s, struct pci_slot, kobj) 312 313 extern struct kset *pci_slots_kset; 314 315 struct pci_slot_attribute { 316 struct attribute attr; 317 ssize_t (*show)(struct pci_slot *, char *); 318 ssize_t (*store)(struct pci_slot *, const char *, size_t); 319 }; 320 #define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr) 321 322 enum pci_bar_type { 323 pci_bar_unknown, /* Standard PCI BAR probe */ 324 pci_bar_io, /* An I/O port BAR */ 325 pci_bar_mem32, /* A 32-bit memory BAR */ 326 pci_bar_mem64, /* A 64-bit memory BAR */ 327 }; 328 329 struct device *pci_get_host_bridge_device(struct pci_dev *dev); 330 void pci_put_host_bridge_device(struct device *dev); 331 332 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge); 333 int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type); 334 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align); 335 336 int pci_configure_extended_tags(struct pci_dev *dev, void *ign); 337 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl, 338 int rrs_timeout); 339 bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl, 340 int rrs_timeout); 341 int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *pl, int rrs_timeout); 342 343 int pci_setup_device(struct pci_dev *dev); 344 void __pci_size_stdbars(struct pci_dev *dev, int count, 345 unsigned int pos, u32 *sizes); 346 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, 347 struct resource *res, unsigned int reg, u32 *sizes); 348 void pci_configure_ari(struct pci_dev *dev); 349 void __pci_bus_size_bridges(struct pci_bus *bus, 350 struct list_head *realloc_head); 351 void __pci_bus_assign_resources(const struct pci_bus *bus, 352 struct list_head *realloc_head, 353 struct list_head *fail_head); 354 bool pci_bus_clip_resource(struct pci_dev *dev, int idx); 355 void pci_walk_bus_locked(struct pci_bus *top, 356 int (*cb)(struct pci_dev *, void *), 357 void *userdata); 358 359 const char *pci_resource_name(struct pci_dev *dev, unsigned int i); 360 bool pci_resource_is_optional(const struct pci_dev *dev, int resno); 361 362 /** 363 * pci_resource_num - Reverse lookup resource number from device resources 364 * @dev: PCI device 365 * @res: Resource to lookup index for (MUST be a @dev's resource) 366 * 367 * Perform reverse lookup to determine the resource number for @res within 368 * @dev resource array. NOTE: The caller is responsible for ensuring @res is 369 * among @dev's resources! 370 * 371 * Returns: resource number. 372 */ 373 static inline int pci_resource_num(const struct pci_dev *dev, 374 const struct resource *res) 375 { 376 int resno = res - &dev->resource[0]; 377 378 /* Passing a resource that is not among dev's resources? */ 379 WARN_ON_ONCE(resno >= PCI_NUM_RESOURCES); 380 381 return resno; 382 } 383 384 void pci_reassigndev_resource_alignment(struct pci_dev *dev); 385 void pci_disable_bridge_window(struct pci_dev *dev); 386 struct pci_bus *pci_bus_get(struct pci_bus *bus); 387 void pci_bus_put(struct pci_bus *bus); 388 389 #define PCIE_LNKCAP_SLS2SPEED(lnkcap) \ 390 ({ \ 391 u32 lnkcap_sls = (lnkcap) & PCI_EXP_LNKCAP_SLS; \ 392 \ 393 (lnkcap_sls == PCI_EXP_LNKCAP_SLS_64_0GB ? PCIE_SPEED_64_0GT : \ 394 lnkcap_sls == PCI_EXP_LNKCAP_SLS_32_0GB ? PCIE_SPEED_32_0GT : \ 395 lnkcap_sls == PCI_EXP_LNKCAP_SLS_16_0GB ? PCIE_SPEED_16_0GT : \ 396 lnkcap_sls == PCI_EXP_LNKCAP_SLS_8_0GB ? PCIE_SPEED_8_0GT : \ 397 lnkcap_sls == PCI_EXP_LNKCAP_SLS_5_0GB ? PCIE_SPEED_5_0GT : \ 398 lnkcap_sls == PCI_EXP_LNKCAP_SLS_2_5GB ? PCIE_SPEED_2_5GT : \ 399 PCI_SPEED_UNKNOWN); \ 400 }) 401 402 /* PCIe link information from Link Capabilities 2 */ 403 #define PCIE_LNKCAP2_SLS2SPEED(lnkcap2) \ 404 ((lnkcap2) & PCI_EXP_LNKCAP2_SLS_64_0GB ? PCIE_SPEED_64_0GT : \ 405 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_32_0GB ? PCIE_SPEED_32_0GT : \ 406 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_16_0GB ? PCIE_SPEED_16_0GT : \ 407 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_8_0GB ? PCIE_SPEED_8_0GT : \ 408 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_5_0GB ? PCIE_SPEED_5_0GT : \ 409 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_2_5GB ? PCIE_SPEED_2_5GT : \ 410 PCI_SPEED_UNKNOWN) 411 412 #define PCIE_LNKCTL2_TLS2SPEED(lnkctl2) \ 413 ({ \ 414 u16 lnkctl2_tls = (lnkctl2) & PCI_EXP_LNKCTL2_TLS; \ 415 \ 416 (lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_64_0GT ? PCIE_SPEED_64_0GT : \ 417 lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_32_0GT ? PCIE_SPEED_32_0GT : \ 418 lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_16_0GT ? PCIE_SPEED_16_0GT : \ 419 lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_8_0GT ? PCIE_SPEED_8_0GT : \ 420 lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_5_0GT ? PCIE_SPEED_5_0GT : \ 421 lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_2_5GT ? PCIE_SPEED_2_5GT : \ 422 PCI_SPEED_UNKNOWN); \ 423 }) 424 425 /* PCIe speed to Mb/s reduced by encoding overhead */ 426 #define PCIE_SPEED2MBS_ENC(speed) \ 427 ((speed) == PCIE_SPEED_64_0GT ? 64000*1/1 : \ 428 (speed) == PCIE_SPEED_32_0GT ? 32000*128/130 : \ 429 (speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \ 430 (speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \ 431 (speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \ 432 (speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \ 433 0) 434 435 static inline int pcie_dev_speed_mbps(enum pci_bus_speed speed) 436 { 437 switch (speed) { 438 case PCIE_SPEED_2_5GT: 439 return 2500; 440 case PCIE_SPEED_5_0GT: 441 return 5000; 442 case PCIE_SPEED_8_0GT: 443 return 8000; 444 case PCIE_SPEED_16_0GT: 445 return 16000; 446 case PCIE_SPEED_32_0GT: 447 return 32000; 448 case PCIE_SPEED_64_0GT: 449 return 64000; 450 default: 451 break; 452 } 453 454 return -EINVAL; 455 } 456 457 u8 pcie_get_supported_speeds(struct pci_dev *dev); 458 const char *pci_speed_string(enum pci_bus_speed speed); 459 void __pcie_print_link_status(struct pci_dev *dev, bool verbose); 460 void pcie_report_downtraining(struct pci_dev *dev); 461 462 static inline void __pcie_update_link_speed(struct pci_bus *bus, u16 linksta, u16 linksta2) 463 { 464 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS]; 465 bus->flit_mode = (linksta2 & PCI_EXP_LNKSTA2_FLIT) ? 1 : 0; 466 } 467 void pcie_update_link_speed(struct pci_bus *bus); 468 469 /* Single Root I/O Virtualization */ 470 struct pci_sriov { 471 int pos; /* Capability position */ 472 int nres; /* Number of resources */ 473 u32 cap; /* SR-IOV Capabilities */ 474 u16 ctrl; /* SR-IOV Control */ 475 u16 total_VFs; /* Total VFs associated with the PF */ 476 u16 initial_VFs; /* Initial VFs associated with the PF */ 477 u16 num_VFs; /* Number of VFs available */ 478 u16 offset; /* First VF Routing ID offset */ 479 u16 stride; /* Following VF stride */ 480 u16 vf_device; /* VF device ID */ 481 u32 pgsz; /* Page size for BAR alignment */ 482 u8 link; /* Function Dependency Link */ 483 u8 max_VF_buses; /* Max buses consumed by VFs */ 484 u16 driver_max_VFs; /* Max num VFs driver supports */ 485 struct pci_dev *dev; /* Lowest numbered PF */ 486 struct pci_dev *self; /* This PF */ 487 u32 class; /* VF device */ 488 u8 hdr_type; /* VF header type */ 489 u16 subsystem_vendor; /* VF subsystem vendor */ 490 u16 subsystem_device; /* VF subsystem device */ 491 resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */ 492 u16 vf_rebar_cap; /* VF Resizable BAR capability offset */ 493 bool drivers_autoprobe; /* Auto probing of VFs by driver */ 494 }; 495 496 #ifdef CONFIG_PCI_DOE 497 void pci_doe_init(struct pci_dev *pdev); 498 void pci_doe_destroy(struct pci_dev *pdev); 499 void pci_doe_disconnected(struct pci_dev *pdev); 500 #else 501 static inline void pci_doe_init(struct pci_dev *pdev) { } 502 static inline void pci_doe_destroy(struct pci_dev *pdev) { } 503 static inline void pci_doe_disconnected(struct pci_dev *pdev) { } 504 #endif 505 506 #ifdef CONFIG_PCI_NPEM 507 void pci_npem_create(struct pci_dev *dev); 508 void pci_npem_remove(struct pci_dev *dev); 509 #else 510 static inline void pci_npem_create(struct pci_dev *dev) { } 511 static inline void pci_npem_remove(struct pci_dev *dev) { } 512 #endif 513 514 #if defined(CONFIG_PCI_DOE) && defined(CONFIG_SYSFS) 515 void pci_doe_sysfs_init(struct pci_dev *pci_dev); 516 void pci_doe_sysfs_teardown(struct pci_dev *pdev); 517 #else 518 static inline void pci_doe_sysfs_init(struct pci_dev *pdev) { } 519 static inline void pci_doe_sysfs_teardown(struct pci_dev *pdev) { } 520 #endif 521 522 /** 523 * pci_dev_set_io_state - Set the new error state if possible. 524 * 525 * @dev: PCI device to set new error_state 526 * @new: the state we want dev to be in 527 * 528 * If the device is experiencing perm_failure, it has to remain in that state. 529 * Any other transition is allowed. 530 * 531 * Returns true if state has been changed to the requested state. 532 */ 533 static inline bool pci_dev_set_io_state(struct pci_dev *dev, 534 pci_channel_state_t new) 535 { 536 pci_channel_state_t old; 537 538 switch (new) { 539 case pci_channel_io_perm_failure: 540 xchg(&dev->error_state, pci_channel_io_perm_failure); 541 return true; 542 case pci_channel_io_frozen: 543 old = cmpxchg(&dev->error_state, pci_channel_io_normal, 544 pci_channel_io_frozen); 545 return old != pci_channel_io_perm_failure; 546 case pci_channel_io_normal: 547 old = cmpxchg(&dev->error_state, pci_channel_io_frozen, 548 pci_channel_io_normal); 549 return old != pci_channel_io_perm_failure; 550 default: 551 return false; 552 } 553 } 554 555 static inline int pci_dev_set_disconnected(struct pci_dev *dev, void *unused) 556 { 557 pci_dev_set_io_state(dev, pci_channel_io_perm_failure); 558 pci_doe_disconnected(dev); 559 560 return 0; 561 } 562 563 /* pci_dev priv_flags */ 564 #define PCI_DEV_ADDED 0 565 #define PCI_DPC_RECOVERED 1 566 #define PCI_DPC_RECOVERING 2 567 #define PCI_DEV_REMOVED 3 568 #define PCI_LINK_CHANGED 4 569 #define PCI_LINK_CHANGING 5 570 #define PCI_LINK_LBMS_SEEN 6 571 #define PCI_DEV_ALLOW_BINDING 7 572 573 static inline void pci_dev_assign_added(struct pci_dev *dev) 574 { 575 smp_mb__before_atomic(); 576 set_bit(PCI_DEV_ADDED, &dev->priv_flags); 577 smp_mb__after_atomic(); 578 } 579 580 static inline bool pci_dev_test_and_clear_added(struct pci_dev *dev) 581 { 582 return test_and_clear_bit(PCI_DEV_ADDED, &dev->priv_flags); 583 } 584 585 static inline bool pci_dev_is_added(const struct pci_dev *dev) 586 { 587 return test_bit(PCI_DEV_ADDED, &dev->priv_flags); 588 } 589 590 static inline bool pci_dev_test_and_set_removed(struct pci_dev *dev) 591 { 592 return test_and_set_bit(PCI_DEV_REMOVED, &dev->priv_flags); 593 } 594 595 static inline void pci_dev_allow_binding(struct pci_dev *dev) 596 { 597 set_bit(PCI_DEV_ALLOW_BINDING, &dev->priv_flags); 598 } 599 600 static inline bool pci_dev_binding_disallowed(struct pci_dev *dev) 601 { 602 return !test_bit(PCI_DEV_ALLOW_BINDING, &dev->priv_flags); 603 } 604 605 #ifdef CONFIG_PCIEAER 606 #include <linux/aer.h> 607 608 #define AER_MAX_MULTI_ERR_DEVICES 5 /* Not likely to have more */ 609 610 struct aer_err_info { 611 struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES]; 612 int ratelimit_print[AER_MAX_MULTI_ERR_DEVICES]; 613 int error_dev_num; 614 const char *level; /* printk level */ 615 616 unsigned int id:16; 617 618 unsigned int severity:2; /* 0:NONFATAL | 1:FATAL | 2:COR */ 619 unsigned int root_ratelimit_print:1; /* 0=skip, 1=print */ 620 unsigned int __pad1:4; 621 unsigned int multi_error_valid:1; 622 623 unsigned int first_error:5; 624 unsigned int __pad2:2; 625 unsigned int tlp_header_valid:1; 626 627 unsigned int status; /* COR/UNCOR Error Status */ 628 unsigned int mask; /* COR/UNCOR Error Mask */ 629 struct pcie_tlp_log tlp; /* TLP Header */ 630 }; 631 632 int aer_get_device_error_info(struct aer_err_info *info, int i); 633 void aer_print_error(struct aer_err_info *info, int i); 634 635 int pcie_read_tlp_log(struct pci_dev *dev, int where, int where2, 636 unsigned int tlp_len, bool flit, 637 struct pcie_tlp_log *log); 638 unsigned int aer_tlp_log_len(struct pci_dev *dev, u32 aercc); 639 void pcie_print_tlp_log(const struct pci_dev *dev, 640 const struct pcie_tlp_log *log, const char *level, 641 const char *pfx); 642 #endif /* CONFIG_PCIEAER */ 643 644 #ifdef CONFIG_PCIEPORTBUS 645 /* Cached RCEC Endpoint Association */ 646 struct rcec_ea { 647 u8 nextbusn; 648 u8 lastbusn; 649 u32 bitmap; 650 }; 651 #endif 652 653 #ifdef CONFIG_PCIE_DPC 654 void pci_save_dpc_state(struct pci_dev *dev); 655 void pci_restore_dpc_state(struct pci_dev *dev); 656 void pci_dpc_init(struct pci_dev *pdev); 657 void dpc_process_error(struct pci_dev *pdev); 658 pci_ers_result_t dpc_reset_link(struct pci_dev *pdev); 659 bool pci_dpc_recovered(struct pci_dev *pdev); 660 unsigned int dpc_tlp_log_len(struct pci_dev *dev); 661 #else 662 static inline void pci_save_dpc_state(struct pci_dev *dev) { } 663 static inline void pci_restore_dpc_state(struct pci_dev *dev) { } 664 static inline void pci_dpc_init(struct pci_dev *pdev) { } 665 static inline bool pci_dpc_recovered(struct pci_dev *pdev) { return false; } 666 #endif 667 668 #ifdef CONFIG_PCIEPORTBUS 669 void pci_rcec_init(struct pci_dev *dev); 670 void pci_rcec_exit(struct pci_dev *dev); 671 void pcie_link_rcec(struct pci_dev *rcec); 672 void pcie_walk_rcec(struct pci_dev *rcec, 673 int (*cb)(struct pci_dev *, void *), 674 void *userdata); 675 #else 676 static inline void pci_rcec_init(struct pci_dev *dev) { } 677 static inline void pci_rcec_exit(struct pci_dev *dev) { } 678 static inline void pcie_link_rcec(struct pci_dev *rcec) { } 679 static inline void pcie_walk_rcec(struct pci_dev *rcec, 680 int (*cb)(struct pci_dev *, void *), 681 void *userdata) { } 682 #endif 683 684 #ifdef CONFIG_PCI_ATS 685 /* Address Translation Service */ 686 void pci_ats_init(struct pci_dev *dev); 687 void pci_restore_ats_state(struct pci_dev *dev); 688 #else 689 static inline void pci_ats_init(struct pci_dev *d) { } 690 static inline void pci_restore_ats_state(struct pci_dev *dev) { } 691 #endif /* CONFIG_PCI_ATS */ 692 693 #ifdef CONFIG_PCI_PRI 694 void pci_pri_init(struct pci_dev *dev); 695 void pci_restore_pri_state(struct pci_dev *pdev); 696 #else 697 static inline void pci_pri_init(struct pci_dev *dev) { } 698 static inline void pci_restore_pri_state(struct pci_dev *pdev) { } 699 #endif 700 701 #ifdef CONFIG_PCI_PASID 702 void pci_pasid_init(struct pci_dev *dev); 703 void pci_restore_pasid_state(struct pci_dev *pdev); 704 #else 705 static inline void pci_pasid_init(struct pci_dev *dev) { } 706 static inline void pci_restore_pasid_state(struct pci_dev *pdev) { } 707 #endif 708 709 #ifdef CONFIG_PCI_IOV 710 int pci_iov_init(struct pci_dev *dev); 711 void pci_iov_release(struct pci_dev *dev); 712 void pci_iov_remove(struct pci_dev *dev); 713 void pci_iov_update_resource(struct pci_dev *dev, int resno); 714 resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno); 715 void pci_restore_iov_state(struct pci_dev *dev); 716 int pci_iov_bus_range(struct pci_bus *bus); 717 void pci_iov_resource_set_size(struct pci_dev *dev, int resno, 718 resource_size_t size); 719 bool pci_iov_is_memory_decoding_enabled(struct pci_dev *dev); 720 static inline u16 pci_iov_vf_rebar_cap(struct pci_dev *dev) 721 { 722 if (!dev->is_physfn) 723 return 0; 724 725 return dev->sriov->vf_rebar_cap; 726 } 727 static inline bool pci_resource_is_iov(int resno) 728 { 729 return resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END; 730 } 731 static inline int pci_resource_num_from_vf_bar(int resno) 732 { 733 return resno + PCI_IOV_RESOURCES; 734 } 735 static inline int pci_resource_num_to_vf_bar(int resno) 736 { 737 return resno - PCI_IOV_RESOURCES; 738 } 739 extern const struct attribute_group sriov_pf_dev_attr_group; 740 extern const struct attribute_group sriov_vf_dev_attr_group; 741 #else 742 static inline int pci_iov_init(struct pci_dev *dev) 743 { 744 return -ENODEV; 745 } 746 static inline void pci_iov_release(struct pci_dev *dev) { } 747 static inline void pci_iov_remove(struct pci_dev *dev) { } 748 static inline void pci_iov_update_resource(struct pci_dev *dev, int resno) { } 749 static inline resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, 750 int resno) 751 { 752 return 0; 753 } 754 static inline void pci_restore_iov_state(struct pci_dev *dev) { } 755 static inline int pci_iov_bus_range(struct pci_bus *bus) 756 { 757 return 0; 758 } 759 static inline void pci_iov_resource_set_size(struct pci_dev *dev, int resno, 760 resource_size_t size) { } 761 static inline bool pci_iov_is_memory_decoding_enabled(struct pci_dev *dev) 762 { 763 return false; 764 } 765 static inline u16 pci_iov_vf_rebar_cap(struct pci_dev *dev) 766 { 767 return 0; 768 } 769 static inline bool pci_resource_is_iov(int resno) 770 { 771 return false; 772 } 773 static inline int pci_resource_num_from_vf_bar(int resno) 774 { 775 WARN_ON_ONCE(1); 776 return -ENODEV; 777 } 778 static inline int pci_resource_num_to_vf_bar(int resno) 779 { 780 WARN_ON_ONCE(1); 781 return -ENODEV; 782 } 783 #endif /* CONFIG_PCI_IOV */ 784 785 #ifdef CONFIG_PCIE_TPH 786 void pci_restore_tph_state(struct pci_dev *dev); 787 void pci_save_tph_state(struct pci_dev *dev); 788 void pci_no_tph(void); 789 void pci_tph_init(struct pci_dev *dev); 790 #else 791 static inline void pci_restore_tph_state(struct pci_dev *dev) { } 792 static inline void pci_save_tph_state(struct pci_dev *dev) { } 793 static inline void pci_no_tph(void) { } 794 static inline void pci_tph_init(struct pci_dev *dev) { } 795 #endif 796 797 #ifdef CONFIG_PCIE_PTM 798 void pci_ptm_init(struct pci_dev *dev); 799 void pci_save_ptm_state(struct pci_dev *dev); 800 void pci_restore_ptm_state(struct pci_dev *dev); 801 void pci_suspend_ptm(struct pci_dev *dev); 802 void pci_resume_ptm(struct pci_dev *dev); 803 #else 804 static inline void pci_ptm_init(struct pci_dev *dev) { } 805 static inline void pci_save_ptm_state(struct pci_dev *dev) { } 806 static inline void pci_restore_ptm_state(struct pci_dev *dev) { } 807 static inline void pci_suspend_ptm(struct pci_dev *dev) { } 808 static inline void pci_resume_ptm(struct pci_dev *dev) { } 809 #endif 810 811 unsigned long pci_cardbus_resource_alignment(struct resource *); 812 813 static inline resource_size_t pci_resource_alignment(struct pci_dev *dev, 814 struct resource *res) 815 { 816 int resno = pci_resource_num(dev, res); 817 818 if (pci_resource_is_iov(resno)) 819 return pci_sriov_resource_alignment(dev, resno); 820 if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS) 821 return pci_cardbus_resource_alignment(res); 822 return resource_alignment(res); 823 } 824 825 void pci_acs_init(struct pci_dev *dev); 826 #ifdef CONFIG_PCI_QUIRKS 827 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags); 828 int pci_dev_specific_enable_acs(struct pci_dev *dev); 829 int pci_dev_specific_disable_acs_redir(struct pci_dev *dev); 830 int pcie_failed_link_retrain(struct pci_dev *dev); 831 #else 832 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev, 833 u16 acs_flags) 834 { 835 return -ENOTTY; 836 } 837 static inline int pci_dev_specific_enable_acs(struct pci_dev *dev) 838 { 839 return -ENOTTY; 840 } 841 static inline int pci_dev_specific_disable_acs_redir(struct pci_dev *dev) 842 { 843 return -ENOTTY; 844 } 845 static inline int pcie_failed_link_retrain(struct pci_dev *dev) 846 { 847 return -ENOTTY; 848 } 849 #endif 850 851 /* PCI error reporting and recovery */ 852 pci_ers_result_t pcie_do_recovery(struct pci_dev *dev, 853 pci_channel_state_t state, 854 pci_ers_result_t (*reset_subordinates)(struct pci_dev *pdev)); 855 856 bool pcie_wait_for_link(struct pci_dev *pdev, bool active); 857 int pcie_retrain_link(struct pci_dev *pdev, bool use_lt); 858 859 /* ASPM-related functionality we need even without CONFIG_PCIEASPM */ 860 void pci_save_ltr_state(struct pci_dev *dev); 861 void pci_restore_ltr_state(struct pci_dev *dev); 862 void pci_configure_aspm_l1ss(struct pci_dev *dev); 863 void pci_save_aspm_l1ss_state(struct pci_dev *dev); 864 void pci_restore_aspm_l1ss_state(struct pci_dev *dev); 865 866 #ifdef CONFIG_PCIEASPM 867 void pcie_aspm_init_link_state(struct pci_dev *pdev); 868 void pcie_aspm_exit_link_state(struct pci_dev *pdev); 869 void pcie_aspm_pm_state_change(struct pci_dev *pdev, bool locked); 870 void pcie_aspm_powersave_config_link(struct pci_dev *pdev); 871 void pci_configure_ltr(struct pci_dev *pdev); 872 void pci_bridge_reconfigure_ltr(struct pci_dev *pdev); 873 #else 874 static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { } 875 static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { } 876 static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev, bool locked) { } 877 static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { } 878 static inline void pci_configure_ltr(struct pci_dev *pdev) { } 879 static inline void pci_bridge_reconfigure_ltr(struct pci_dev *pdev) { } 880 #endif 881 882 #ifdef CONFIG_PCIE_ECRC 883 void pcie_set_ecrc_checking(struct pci_dev *dev); 884 void pcie_ecrc_get_policy(char *str); 885 #else 886 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { } 887 static inline void pcie_ecrc_get_policy(char *str) { } 888 #endif 889 890 #ifdef CONFIG_PCIEPORTBUS 891 void pcie_reset_lbms(struct pci_dev *port); 892 #else 893 static inline void pcie_reset_lbms(struct pci_dev *port) {} 894 #endif 895 896 struct pci_dev_reset_methods { 897 u16 vendor; 898 u16 device; 899 int (*reset)(struct pci_dev *dev, bool probe); 900 }; 901 902 struct pci_reset_fn_method { 903 int (*reset_fn)(struct pci_dev *pdev, bool probe); 904 char *name; 905 }; 906 extern const struct pci_reset_fn_method pci_reset_fn_methods[]; 907 908 #ifdef CONFIG_PCI_QUIRKS 909 int pci_dev_specific_reset(struct pci_dev *dev, bool probe); 910 #else 911 static inline int pci_dev_specific_reset(struct pci_dev *dev, bool probe) 912 { 913 return -ENOTTY; 914 } 915 #endif 916 917 #if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64) 918 int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment, 919 struct resource *res); 920 #else 921 static inline int acpi_get_rc_resources(struct device *dev, const char *hid, 922 u16 segment, struct resource *res) 923 { 924 return -ENODEV; 925 } 926 #endif 927 928 void pci_rebar_init(struct pci_dev *pdev); 929 int pci_rebar_get_current_size(struct pci_dev *pdev, int bar); 930 int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size); 931 static inline u64 pci_rebar_size_to_bytes(int size) 932 { 933 return 1ULL << (size + 20); 934 } 935 936 struct device_node; 937 938 #define PCI_EQ_RESV 0xff 939 940 enum equalization_preset_type { 941 EQ_PRESET_TYPE_8GTS, 942 EQ_PRESET_TYPE_16GTS, 943 EQ_PRESET_TYPE_32GTS, 944 EQ_PRESET_TYPE_64GTS, 945 EQ_PRESET_TYPE_MAX 946 }; 947 948 struct pci_eq_presets { 949 u16 eq_presets_8gts[MAX_NR_LANES]; 950 u8 eq_presets_Ngts[EQ_PRESET_TYPE_MAX - 1][MAX_NR_LANES]; 951 }; 952 953 #ifdef CONFIG_OF 954 int of_get_pci_domain_nr(struct device_node *node); 955 int of_pci_get_max_link_speed(struct device_node *node); 956 u32 of_pci_get_slot_power_limit(struct device_node *node, 957 u8 *slot_power_limit_value, 958 u8 *slot_power_limit_scale); 959 bool of_pci_preserve_config(struct device_node *node); 960 int pci_set_of_node(struct pci_dev *dev); 961 void pci_release_of_node(struct pci_dev *dev); 962 void pci_set_bus_of_node(struct pci_bus *bus); 963 void pci_release_bus_of_node(struct pci_bus *bus); 964 965 int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge); 966 bool of_pci_supply_present(struct device_node *np); 967 int of_pci_get_equalization_presets(struct device *dev, 968 struct pci_eq_presets *presets, 969 int num_lanes); 970 #else 971 static inline int 972 of_get_pci_domain_nr(struct device_node *node) 973 { 974 return -1; 975 } 976 977 static inline int 978 of_pci_get_max_link_speed(struct device_node *node) 979 { 980 return -EINVAL; 981 } 982 983 static inline u32 984 of_pci_get_slot_power_limit(struct device_node *node, 985 u8 *slot_power_limit_value, 986 u8 *slot_power_limit_scale) 987 { 988 if (slot_power_limit_value) 989 *slot_power_limit_value = 0; 990 if (slot_power_limit_scale) 991 *slot_power_limit_scale = 0; 992 return 0; 993 } 994 995 static inline bool of_pci_preserve_config(struct device_node *node) 996 { 997 return false; 998 } 999 1000 static inline int pci_set_of_node(struct pci_dev *dev) { return 0; } 1001 static inline void pci_release_of_node(struct pci_dev *dev) { } 1002 static inline void pci_set_bus_of_node(struct pci_bus *bus) { } 1003 static inline void pci_release_bus_of_node(struct pci_bus *bus) { } 1004 1005 static inline int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge) 1006 { 1007 return 0; 1008 } 1009 1010 static inline bool of_pci_supply_present(struct device_node *np) 1011 { 1012 return false; 1013 } 1014 1015 static inline int of_pci_get_equalization_presets(struct device *dev, 1016 struct pci_eq_presets *presets, 1017 int num_lanes) 1018 { 1019 presets->eq_presets_8gts[0] = PCI_EQ_RESV; 1020 for (int i = 0; i < EQ_PRESET_TYPE_MAX - 1; i++) 1021 presets->eq_presets_Ngts[i][0] = PCI_EQ_RESV; 1022 1023 return 0; 1024 } 1025 #endif /* CONFIG_OF */ 1026 1027 struct of_changeset; 1028 1029 #ifdef CONFIG_PCI_DYNAMIC_OF_NODES 1030 void of_pci_make_dev_node(struct pci_dev *pdev); 1031 void of_pci_remove_node(struct pci_dev *pdev); 1032 int of_pci_add_properties(struct pci_dev *pdev, struct of_changeset *ocs, 1033 struct device_node *np); 1034 void of_pci_make_host_bridge_node(struct pci_host_bridge *bridge); 1035 void of_pci_remove_host_bridge_node(struct pci_host_bridge *bridge); 1036 int of_pci_add_host_bridge_properties(struct pci_host_bridge *bridge, 1037 struct of_changeset *ocs, 1038 struct device_node *np); 1039 #else 1040 static inline void of_pci_make_dev_node(struct pci_dev *pdev) { } 1041 static inline void of_pci_remove_node(struct pci_dev *pdev) { } 1042 static inline void of_pci_make_host_bridge_node(struct pci_host_bridge *bridge) { } 1043 static inline void of_pci_remove_host_bridge_node(struct pci_host_bridge *bridge) { } 1044 #endif 1045 1046 #ifdef CONFIG_PCIEAER 1047 void pci_no_aer(void); 1048 void pci_aer_init(struct pci_dev *dev); 1049 void pci_aer_exit(struct pci_dev *dev); 1050 extern const struct attribute_group aer_stats_attr_group; 1051 extern const struct attribute_group aer_attr_group; 1052 void pci_aer_clear_fatal_status(struct pci_dev *dev); 1053 int pci_aer_clear_status(struct pci_dev *dev); 1054 int pci_aer_raw_clear_status(struct pci_dev *dev); 1055 void pci_save_aer_state(struct pci_dev *dev); 1056 void pci_restore_aer_state(struct pci_dev *dev); 1057 #else 1058 static inline void pci_no_aer(void) { } 1059 static inline void pci_aer_init(struct pci_dev *d) { } 1060 static inline void pci_aer_exit(struct pci_dev *d) { } 1061 static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { } 1062 static inline int pci_aer_clear_status(struct pci_dev *dev) { return -EINVAL; } 1063 static inline int pci_aer_raw_clear_status(struct pci_dev *dev) { return -EINVAL; } 1064 static inline void pci_save_aer_state(struct pci_dev *dev) { } 1065 static inline void pci_restore_aer_state(struct pci_dev *dev) { } 1066 #endif 1067 1068 #ifdef CONFIG_ACPI 1069 bool pci_acpi_preserve_config(struct pci_host_bridge *bridge); 1070 int pci_acpi_program_hp_params(struct pci_dev *dev); 1071 extern const struct attribute_group pci_dev_acpi_attr_group; 1072 void pci_set_acpi_fwnode(struct pci_dev *dev); 1073 int pci_dev_acpi_reset(struct pci_dev *dev, bool probe); 1074 bool acpi_pci_power_manageable(struct pci_dev *dev); 1075 bool acpi_pci_bridge_d3(struct pci_dev *dev); 1076 int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state); 1077 pci_power_t acpi_pci_get_power_state(struct pci_dev *dev); 1078 void acpi_pci_refresh_power_state(struct pci_dev *dev); 1079 int acpi_pci_wakeup(struct pci_dev *dev, bool enable); 1080 bool acpi_pci_need_resume(struct pci_dev *dev); 1081 pci_power_t acpi_pci_choose_state(struct pci_dev *pdev); 1082 #else 1083 static inline bool pci_acpi_preserve_config(struct pci_host_bridge *bridge) 1084 { 1085 return false; 1086 } 1087 static inline int pci_dev_acpi_reset(struct pci_dev *dev, bool probe) 1088 { 1089 return -ENOTTY; 1090 } 1091 static inline void pci_set_acpi_fwnode(struct pci_dev *dev) { } 1092 static inline int pci_acpi_program_hp_params(struct pci_dev *dev) 1093 { 1094 return -ENODEV; 1095 } 1096 static inline bool acpi_pci_power_manageable(struct pci_dev *dev) 1097 { 1098 return false; 1099 } 1100 static inline bool acpi_pci_bridge_d3(struct pci_dev *dev) 1101 { 1102 return false; 1103 } 1104 static inline int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state) 1105 { 1106 return -ENODEV; 1107 } 1108 static inline pci_power_t acpi_pci_get_power_state(struct pci_dev *dev) 1109 { 1110 return PCI_UNKNOWN; 1111 } 1112 static inline void acpi_pci_refresh_power_state(struct pci_dev *dev) { } 1113 static inline int acpi_pci_wakeup(struct pci_dev *dev, bool enable) 1114 { 1115 return -ENODEV; 1116 } 1117 static inline bool acpi_pci_need_resume(struct pci_dev *dev) 1118 { 1119 return false; 1120 } 1121 static inline pci_power_t acpi_pci_choose_state(struct pci_dev *pdev) 1122 { 1123 return PCI_POWER_ERROR; 1124 } 1125 #endif 1126 1127 #ifdef CONFIG_PCIEASPM 1128 extern const struct attribute_group aspm_ctrl_attr_group; 1129 #endif 1130 1131 #ifdef CONFIG_X86_INTEL_MID 1132 bool pci_use_mid_pm(void); 1133 int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state); 1134 pci_power_t mid_pci_get_power_state(struct pci_dev *pdev); 1135 #else 1136 static inline bool pci_use_mid_pm(void) 1137 { 1138 return false; 1139 } 1140 static inline int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state) 1141 { 1142 return -ENODEV; 1143 } 1144 static inline pci_power_t mid_pci_get_power_state(struct pci_dev *pdev) 1145 { 1146 return PCI_UNKNOWN; 1147 } 1148 #endif 1149 1150 #ifdef CONFIG_PCI_MSI 1151 int pci_msix_write_tph_tag(struct pci_dev *pdev, unsigned int index, u16 tag); 1152 #else 1153 static inline int pci_msix_write_tph_tag(struct pci_dev *pdev, unsigned int index, u16 tag) 1154 { 1155 return -ENODEV; 1156 } 1157 #endif 1158 1159 /* 1160 * Config Address for PCI Configuration Mechanism #1 1161 * 1162 * See PCI Local Bus Specification, Revision 3.0, 1163 * Section 3.2.2.3.2, Figure 3-2, p. 50. 1164 */ 1165 1166 #define PCI_CONF1_BUS_SHIFT 16 /* Bus number */ 1167 #define PCI_CONF1_DEV_SHIFT 11 /* Device number */ 1168 #define PCI_CONF1_FUNC_SHIFT 8 /* Function number */ 1169 1170 #define PCI_CONF1_BUS_MASK 0xff 1171 #define PCI_CONF1_DEV_MASK 0x1f 1172 #define PCI_CONF1_FUNC_MASK 0x7 1173 #define PCI_CONF1_REG_MASK 0xfc /* Limit aligned offset to a maximum of 256B */ 1174 1175 #define PCI_CONF1_ENABLE BIT(31) 1176 #define PCI_CONF1_BUS(x) (((x) & PCI_CONF1_BUS_MASK) << PCI_CONF1_BUS_SHIFT) 1177 #define PCI_CONF1_DEV(x) (((x) & PCI_CONF1_DEV_MASK) << PCI_CONF1_DEV_SHIFT) 1178 #define PCI_CONF1_FUNC(x) (((x) & PCI_CONF1_FUNC_MASK) << PCI_CONF1_FUNC_SHIFT) 1179 #define PCI_CONF1_REG(x) ((x) & PCI_CONF1_REG_MASK) 1180 1181 #define PCI_CONF1_ADDRESS(bus, dev, func, reg) \ 1182 (PCI_CONF1_ENABLE | \ 1183 PCI_CONF1_BUS(bus) | \ 1184 PCI_CONF1_DEV(dev) | \ 1185 PCI_CONF1_FUNC(func) | \ 1186 PCI_CONF1_REG(reg)) 1187 1188 /* 1189 * Extension of PCI Config Address for accessing extended PCIe registers 1190 * 1191 * No standardized specification, but used on lot of non-ECAM-compliant ARM SoCs 1192 * or on AMD Barcelona and new CPUs. Reserved bits [27:24] of PCI Config Address 1193 * are used for specifying additional 4 high bits of PCI Express register. 1194 */ 1195 1196 #define PCI_CONF1_EXT_REG_SHIFT 16 1197 #define PCI_CONF1_EXT_REG_MASK 0xf00 1198 #define PCI_CONF1_EXT_REG(x) (((x) & PCI_CONF1_EXT_REG_MASK) << PCI_CONF1_EXT_REG_SHIFT) 1199 1200 #define PCI_CONF1_EXT_ADDRESS(bus, dev, func, reg) \ 1201 (PCI_CONF1_ADDRESS(bus, dev, func, reg) | \ 1202 PCI_CONF1_EXT_REG(reg)) 1203 1204 #endif /* DRIVERS_PCI_H */ 1205