1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef DRIVERS_PCI_H 3 #define DRIVERS_PCI_H 4 5 #include <linux/pci.h> 6 7 /* Number of possible devfns: 0.0 to 1f.7 inclusive */ 8 #define MAX_NR_DEVFNS 256 9 10 #define PCI_FIND_CAP_TTL 48 11 12 #define PCI_VSEC_ID_INTEL_TBT 0x1234 /* Thunderbolt */ 13 14 #define PCIE_LINK_RETRAIN_TIMEOUT_MS 1000 15 16 /* Power stable to PERST# inactive from PCIe card Electromechanical Spec */ 17 #define PCIE_T_PVPERL_MS 100 18 19 /* 20 * PCIe r6.0, sec 5.3.3.2.1 <PME Synchronization> 21 * Recommends 1ms to 10ms timeout to check L2 ready. 22 */ 23 #define PCIE_PME_TO_L2_TIMEOUT_US 10000 24 25 extern const unsigned char pcie_link_speed[]; 26 extern bool pci_early_dump; 27 28 bool pcie_cap_has_lnkctl(const struct pci_dev *dev); 29 bool pcie_cap_has_lnkctl2(const struct pci_dev *dev); 30 bool pcie_cap_has_rtctl(const struct pci_dev *dev); 31 32 /* Functions internal to the PCI core code */ 33 34 #ifdef CONFIG_DMI 35 extern const struct attribute_group pci_dev_smbios_attr_group; 36 #endif 37 38 enum pci_mmap_api { 39 PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */ 40 PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */ 41 }; 42 int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai, 43 enum pci_mmap_api mmap_api); 44 45 bool pci_reset_supported(struct pci_dev *dev); 46 void pci_init_reset_methods(struct pci_dev *dev); 47 int pci_bridge_secondary_bus_reset(struct pci_dev *dev); 48 int pci_bus_error_reset(struct pci_dev *dev); 49 50 struct pci_cap_saved_data { 51 u16 cap_nr; 52 bool cap_extended; 53 unsigned int size; 54 u32 data[]; 55 }; 56 57 struct pci_cap_saved_state { 58 struct hlist_node next; 59 struct pci_cap_saved_data cap; 60 }; 61 62 void pci_allocate_cap_save_buffers(struct pci_dev *dev); 63 void pci_free_cap_save_buffers(struct pci_dev *dev); 64 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size); 65 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, 66 u16 cap, unsigned int size); 67 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap); 68 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, 69 u16 cap); 70 71 #define PCI_PM_D2_DELAY 200 /* usec; see PCIe r4.0, sec 5.9.1 */ 72 #define PCI_PM_D3HOT_WAIT 10 /* msec */ 73 #define PCI_PM_D3COLD_WAIT 100 /* msec */ 74 75 void pci_update_current_state(struct pci_dev *dev, pci_power_t state); 76 void pci_refresh_power_state(struct pci_dev *dev); 77 int pci_power_up(struct pci_dev *dev); 78 void pci_disable_enabled_device(struct pci_dev *dev); 79 int pci_finish_runtime_suspend(struct pci_dev *dev); 80 void pcie_clear_device_status(struct pci_dev *dev); 81 void pcie_clear_root_pme_status(struct pci_dev *dev); 82 bool pci_check_pme_status(struct pci_dev *dev); 83 void pci_pme_wakeup_bus(struct pci_bus *bus); 84 int __pci_pme_wakeup(struct pci_dev *dev, void *ign); 85 void pci_pme_restore(struct pci_dev *dev); 86 bool pci_dev_need_resume(struct pci_dev *dev); 87 void pci_dev_adjust_pme(struct pci_dev *dev); 88 void pci_dev_complete_resume(struct pci_dev *pci_dev); 89 void pci_config_pm_runtime_get(struct pci_dev *dev); 90 void pci_config_pm_runtime_put(struct pci_dev *dev); 91 void pci_pm_init(struct pci_dev *dev); 92 void pci_ea_init(struct pci_dev *dev); 93 void pci_msi_init(struct pci_dev *dev); 94 void pci_msix_init(struct pci_dev *dev); 95 bool pci_bridge_d3_possible(struct pci_dev *dev); 96 void pci_bridge_d3_update(struct pci_dev *dev); 97 int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type); 98 99 static inline void pci_wakeup_event(struct pci_dev *dev) 100 { 101 /* Wait 100 ms before the system can be put into a sleep state. */ 102 pm_wakeup_event(&dev->dev, 100); 103 } 104 105 static inline bool pci_has_subordinate(struct pci_dev *pci_dev) 106 { 107 return !!(pci_dev->subordinate); 108 } 109 110 static inline bool pci_power_manageable(struct pci_dev *pci_dev) 111 { 112 /* 113 * Currently we allow normal PCI devices and PCI bridges transition 114 * into D3 if their bridge_d3 is set. 115 */ 116 return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3; 117 } 118 119 static inline bool pcie_downstream_port(const struct pci_dev *dev) 120 { 121 int type = pci_pcie_type(dev); 122 123 return type == PCI_EXP_TYPE_ROOT_PORT || 124 type == PCI_EXP_TYPE_DOWNSTREAM || 125 type == PCI_EXP_TYPE_PCIE_BRIDGE; 126 } 127 128 void pci_vpd_init(struct pci_dev *dev); 129 void pci_vpd_release(struct pci_dev *dev); 130 extern const struct attribute_group pci_dev_vpd_attr_group; 131 132 /* PCI Virtual Channel */ 133 int pci_save_vc_state(struct pci_dev *dev); 134 void pci_restore_vc_state(struct pci_dev *dev); 135 void pci_allocate_vc_save_buffers(struct pci_dev *dev); 136 137 /* PCI /proc functions */ 138 #ifdef CONFIG_PROC_FS 139 int pci_proc_attach_device(struct pci_dev *dev); 140 int pci_proc_detach_device(struct pci_dev *dev); 141 int pci_proc_detach_bus(struct pci_bus *bus); 142 #else 143 static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; } 144 static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; } 145 static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; } 146 #endif 147 148 /* Functions for PCI Hotplug drivers to use */ 149 int pci_hp_add_bridge(struct pci_dev *dev); 150 151 #if defined(CONFIG_SYSFS) && defined(HAVE_PCI_LEGACY) 152 void pci_create_legacy_files(struct pci_bus *bus); 153 void pci_remove_legacy_files(struct pci_bus *bus); 154 #else 155 static inline void pci_create_legacy_files(struct pci_bus *bus) { } 156 static inline void pci_remove_legacy_files(struct pci_bus *bus) { } 157 #endif 158 159 /* Lock for read/write access to pci device and bus lists */ 160 extern struct rw_semaphore pci_bus_sem; 161 extern struct mutex pci_slot_mutex; 162 163 extern raw_spinlock_t pci_lock; 164 165 extern unsigned int pci_pm_d3hot_delay; 166 167 #ifdef CONFIG_PCI_MSI 168 void pci_no_msi(void); 169 #else 170 static inline void pci_no_msi(void) { } 171 #endif 172 173 void pci_realloc_get_opt(char *); 174 175 static inline int pci_no_d1d2(struct pci_dev *dev) 176 { 177 unsigned int parent_dstates = 0; 178 179 if (dev->bus->self) 180 parent_dstates = dev->bus->self->no_d1d2; 181 return (dev->no_d1d2 || parent_dstates); 182 183 } 184 185 #ifdef CONFIG_SYSFS 186 int pci_create_sysfs_dev_files(struct pci_dev *pdev); 187 void pci_remove_sysfs_dev_files(struct pci_dev *pdev); 188 extern const struct attribute_group *pci_dev_groups[]; 189 extern const struct attribute_group *pci_dev_attr_groups[]; 190 extern const struct attribute_group *pcibus_groups[]; 191 extern const struct attribute_group *pci_bus_groups[]; 192 #else 193 static inline int pci_create_sysfs_dev_files(struct pci_dev *pdev) { return 0; } 194 static inline void pci_remove_sysfs_dev_files(struct pci_dev *pdev) { } 195 #define pci_dev_groups NULL 196 #define pci_dev_attr_groups NULL 197 #define pcibus_groups NULL 198 #define pci_bus_groups NULL 199 #endif 200 201 extern unsigned long pci_hotplug_io_size; 202 extern unsigned long pci_hotplug_mmio_size; 203 extern unsigned long pci_hotplug_mmio_pref_size; 204 extern unsigned long pci_hotplug_bus_size; 205 206 /** 207 * pci_match_one_device - Tell if a PCI device structure has a matching 208 * PCI device id structure 209 * @id: single PCI device id structure to match 210 * @dev: the PCI device structure to match against 211 * 212 * Returns the matching pci_device_id structure or %NULL if there is no match. 213 */ 214 static inline const struct pci_device_id * 215 pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev) 216 { 217 if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) && 218 (id->device == PCI_ANY_ID || id->device == dev->device) && 219 (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) && 220 (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) && 221 !((id->class ^ dev->class) & id->class_mask)) 222 return id; 223 return NULL; 224 } 225 226 /* PCI slot sysfs helper code */ 227 #define to_pci_slot(s) container_of(s, struct pci_slot, kobj) 228 229 extern struct kset *pci_slots_kset; 230 231 struct pci_slot_attribute { 232 struct attribute attr; 233 ssize_t (*show)(struct pci_slot *, char *); 234 ssize_t (*store)(struct pci_slot *, const char *, size_t); 235 }; 236 #define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr) 237 238 enum pci_bar_type { 239 pci_bar_unknown, /* Standard PCI BAR probe */ 240 pci_bar_io, /* An I/O port BAR */ 241 pci_bar_mem32, /* A 32-bit memory BAR */ 242 pci_bar_mem64, /* A 64-bit memory BAR */ 243 }; 244 245 struct device *pci_get_host_bridge_device(struct pci_dev *dev); 246 void pci_put_host_bridge_device(struct device *dev); 247 248 int pci_configure_extended_tags(struct pci_dev *dev, void *ign); 249 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl, 250 int crs_timeout); 251 bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl, 252 int crs_timeout); 253 int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *pl, int crs_timeout); 254 255 int pci_setup_device(struct pci_dev *dev); 256 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, 257 struct resource *res, unsigned int reg); 258 void pci_configure_ari(struct pci_dev *dev); 259 void __pci_bus_size_bridges(struct pci_bus *bus, 260 struct list_head *realloc_head); 261 void __pci_bus_assign_resources(const struct pci_bus *bus, 262 struct list_head *realloc_head, 263 struct list_head *fail_head); 264 bool pci_bus_clip_resource(struct pci_dev *dev, int idx); 265 266 const char *pci_resource_name(struct pci_dev *dev, unsigned int i); 267 268 void pci_reassigndev_resource_alignment(struct pci_dev *dev); 269 void pci_disable_bridge_window(struct pci_dev *dev); 270 struct pci_bus *pci_bus_get(struct pci_bus *bus); 271 void pci_bus_put(struct pci_bus *bus); 272 273 /* PCIe link information from Link Capabilities 2 */ 274 #define PCIE_LNKCAP2_SLS2SPEED(lnkcap2) \ 275 ((lnkcap2) & PCI_EXP_LNKCAP2_SLS_64_0GB ? PCIE_SPEED_64_0GT : \ 276 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_32_0GB ? PCIE_SPEED_32_0GT : \ 277 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_16_0GB ? PCIE_SPEED_16_0GT : \ 278 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_8_0GB ? PCIE_SPEED_8_0GT : \ 279 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_5_0GB ? PCIE_SPEED_5_0GT : \ 280 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_2_5GB ? PCIE_SPEED_2_5GT : \ 281 PCI_SPEED_UNKNOWN) 282 283 /* PCIe speed to Mb/s reduced by encoding overhead */ 284 #define PCIE_SPEED2MBS_ENC(speed) \ 285 ((speed) == PCIE_SPEED_64_0GT ? 64000*1/1 : \ 286 (speed) == PCIE_SPEED_32_0GT ? 32000*128/130 : \ 287 (speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \ 288 (speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \ 289 (speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \ 290 (speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \ 291 0) 292 293 const char *pci_speed_string(enum pci_bus_speed speed); 294 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev); 295 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev); 296 u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed, 297 enum pcie_link_width *width); 298 void __pcie_print_link_status(struct pci_dev *dev, bool verbose); 299 void pcie_report_downtraining(struct pci_dev *dev); 300 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status); 301 302 /* Single Root I/O Virtualization */ 303 struct pci_sriov { 304 int pos; /* Capability position */ 305 int nres; /* Number of resources */ 306 u32 cap; /* SR-IOV Capabilities */ 307 u16 ctrl; /* SR-IOV Control */ 308 u16 total_VFs; /* Total VFs associated with the PF */ 309 u16 initial_VFs; /* Initial VFs associated with the PF */ 310 u16 num_VFs; /* Number of VFs available */ 311 u16 offset; /* First VF Routing ID offset */ 312 u16 stride; /* Following VF stride */ 313 u16 vf_device; /* VF device ID */ 314 u32 pgsz; /* Page size for BAR alignment */ 315 u8 link; /* Function Dependency Link */ 316 u8 max_VF_buses; /* Max buses consumed by VFs */ 317 u16 driver_max_VFs; /* Max num VFs driver supports */ 318 struct pci_dev *dev; /* Lowest numbered PF */ 319 struct pci_dev *self; /* This PF */ 320 u32 class; /* VF device */ 321 u8 hdr_type; /* VF header type */ 322 u16 subsystem_vendor; /* VF subsystem vendor */ 323 u16 subsystem_device; /* VF subsystem device */ 324 resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */ 325 bool drivers_autoprobe; /* Auto probing of VFs by driver */ 326 }; 327 328 #ifdef CONFIG_PCI_DOE 329 void pci_doe_init(struct pci_dev *pdev); 330 void pci_doe_destroy(struct pci_dev *pdev); 331 void pci_doe_disconnected(struct pci_dev *pdev); 332 #else 333 static inline void pci_doe_init(struct pci_dev *pdev) { } 334 static inline void pci_doe_destroy(struct pci_dev *pdev) { } 335 static inline void pci_doe_disconnected(struct pci_dev *pdev) { } 336 #endif 337 338 /** 339 * pci_dev_set_io_state - Set the new error state if possible. 340 * 341 * @dev: PCI device to set new error_state 342 * @new: the state we want dev to be in 343 * 344 * If the device is experiencing perm_failure, it has to remain in that state. 345 * Any other transition is allowed. 346 * 347 * Returns true if state has been changed to the requested state. 348 */ 349 static inline bool pci_dev_set_io_state(struct pci_dev *dev, 350 pci_channel_state_t new) 351 { 352 pci_channel_state_t old; 353 354 switch (new) { 355 case pci_channel_io_perm_failure: 356 xchg(&dev->error_state, pci_channel_io_perm_failure); 357 return true; 358 case pci_channel_io_frozen: 359 old = cmpxchg(&dev->error_state, pci_channel_io_normal, 360 pci_channel_io_frozen); 361 return old != pci_channel_io_perm_failure; 362 case pci_channel_io_normal: 363 old = cmpxchg(&dev->error_state, pci_channel_io_frozen, 364 pci_channel_io_normal); 365 return old != pci_channel_io_perm_failure; 366 default: 367 return false; 368 } 369 } 370 371 static inline int pci_dev_set_disconnected(struct pci_dev *dev, void *unused) 372 { 373 pci_dev_set_io_state(dev, pci_channel_io_perm_failure); 374 pci_doe_disconnected(dev); 375 376 return 0; 377 } 378 379 /* pci_dev priv_flags */ 380 #define PCI_DEV_ADDED 0 381 #define PCI_DPC_RECOVERED 1 382 #define PCI_DPC_RECOVERING 2 383 384 static inline void pci_dev_assign_added(struct pci_dev *dev, bool added) 385 { 386 assign_bit(PCI_DEV_ADDED, &dev->priv_flags, added); 387 } 388 389 static inline bool pci_dev_is_added(const struct pci_dev *dev) 390 { 391 return test_bit(PCI_DEV_ADDED, &dev->priv_flags); 392 } 393 394 #ifdef CONFIG_PCIEAER 395 #include <linux/aer.h> 396 397 #define AER_MAX_MULTI_ERR_DEVICES 5 /* Not likely to have more */ 398 399 struct aer_err_info { 400 struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES]; 401 int error_dev_num; 402 403 unsigned int id:16; 404 405 unsigned int severity:2; /* 0:NONFATAL | 1:FATAL | 2:COR */ 406 unsigned int __pad1:5; 407 unsigned int multi_error_valid:1; 408 409 unsigned int first_error:5; 410 unsigned int __pad2:2; 411 unsigned int tlp_header_valid:1; 412 413 unsigned int status; /* COR/UNCOR Error Status */ 414 unsigned int mask; /* COR/UNCOR Error Mask */ 415 struct pcie_tlp_log tlp; /* TLP Header */ 416 }; 417 418 int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info); 419 void aer_print_error(struct pci_dev *dev, struct aer_err_info *info); 420 #endif /* CONFIG_PCIEAER */ 421 422 #ifdef CONFIG_PCIEPORTBUS 423 /* Cached RCEC Endpoint Association */ 424 struct rcec_ea { 425 u8 nextbusn; 426 u8 lastbusn; 427 u32 bitmap; 428 }; 429 #endif 430 431 #ifdef CONFIG_PCIE_DPC 432 void pci_save_dpc_state(struct pci_dev *dev); 433 void pci_restore_dpc_state(struct pci_dev *dev); 434 void pci_dpc_init(struct pci_dev *pdev); 435 void dpc_process_error(struct pci_dev *pdev); 436 pci_ers_result_t dpc_reset_link(struct pci_dev *pdev); 437 bool pci_dpc_recovered(struct pci_dev *pdev); 438 #else 439 static inline void pci_save_dpc_state(struct pci_dev *dev) { } 440 static inline void pci_restore_dpc_state(struct pci_dev *dev) { } 441 static inline void pci_dpc_init(struct pci_dev *pdev) { } 442 static inline bool pci_dpc_recovered(struct pci_dev *pdev) { return false; } 443 #endif 444 445 #ifdef CONFIG_PCIEPORTBUS 446 void pci_rcec_init(struct pci_dev *dev); 447 void pci_rcec_exit(struct pci_dev *dev); 448 void pcie_link_rcec(struct pci_dev *rcec); 449 void pcie_walk_rcec(struct pci_dev *rcec, 450 int (*cb)(struct pci_dev *, void *), 451 void *userdata); 452 #else 453 static inline void pci_rcec_init(struct pci_dev *dev) { } 454 static inline void pci_rcec_exit(struct pci_dev *dev) { } 455 static inline void pcie_link_rcec(struct pci_dev *rcec) { } 456 static inline void pcie_walk_rcec(struct pci_dev *rcec, 457 int (*cb)(struct pci_dev *, void *), 458 void *userdata) { } 459 #endif 460 461 #ifdef CONFIG_PCI_ATS 462 /* Address Translation Service */ 463 void pci_ats_init(struct pci_dev *dev); 464 void pci_restore_ats_state(struct pci_dev *dev); 465 #else 466 static inline void pci_ats_init(struct pci_dev *d) { } 467 static inline void pci_restore_ats_state(struct pci_dev *dev) { } 468 #endif /* CONFIG_PCI_ATS */ 469 470 #ifdef CONFIG_PCI_PRI 471 void pci_pri_init(struct pci_dev *dev); 472 void pci_restore_pri_state(struct pci_dev *pdev); 473 #else 474 static inline void pci_pri_init(struct pci_dev *dev) { } 475 static inline void pci_restore_pri_state(struct pci_dev *pdev) { } 476 #endif 477 478 #ifdef CONFIG_PCI_PASID 479 void pci_pasid_init(struct pci_dev *dev); 480 void pci_restore_pasid_state(struct pci_dev *pdev); 481 #else 482 static inline void pci_pasid_init(struct pci_dev *dev) { } 483 static inline void pci_restore_pasid_state(struct pci_dev *pdev) { } 484 #endif 485 486 #ifdef CONFIG_PCI_IOV 487 int pci_iov_init(struct pci_dev *dev); 488 void pci_iov_release(struct pci_dev *dev); 489 void pci_iov_remove(struct pci_dev *dev); 490 void pci_iov_update_resource(struct pci_dev *dev, int resno); 491 resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno); 492 void pci_restore_iov_state(struct pci_dev *dev); 493 int pci_iov_bus_range(struct pci_bus *bus); 494 extern const struct attribute_group sriov_pf_dev_attr_group; 495 extern const struct attribute_group sriov_vf_dev_attr_group; 496 #else 497 static inline int pci_iov_init(struct pci_dev *dev) 498 { 499 return -ENODEV; 500 } 501 static inline void pci_iov_release(struct pci_dev *dev) { } 502 static inline void pci_iov_remove(struct pci_dev *dev) { } 503 static inline void pci_restore_iov_state(struct pci_dev *dev) { } 504 static inline int pci_iov_bus_range(struct pci_bus *bus) 505 { 506 return 0; 507 } 508 509 #endif /* CONFIG_PCI_IOV */ 510 511 #ifdef CONFIG_PCIE_PTM 512 void pci_ptm_init(struct pci_dev *dev); 513 void pci_save_ptm_state(struct pci_dev *dev); 514 void pci_restore_ptm_state(struct pci_dev *dev); 515 void pci_suspend_ptm(struct pci_dev *dev); 516 void pci_resume_ptm(struct pci_dev *dev); 517 #else 518 static inline void pci_ptm_init(struct pci_dev *dev) { } 519 static inline void pci_save_ptm_state(struct pci_dev *dev) { } 520 static inline void pci_restore_ptm_state(struct pci_dev *dev) { } 521 static inline void pci_suspend_ptm(struct pci_dev *dev) { } 522 static inline void pci_resume_ptm(struct pci_dev *dev) { } 523 #endif 524 525 unsigned long pci_cardbus_resource_alignment(struct resource *); 526 527 static inline resource_size_t pci_resource_alignment(struct pci_dev *dev, 528 struct resource *res) 529 { 530 #ifdef CONFIG_PCI_IOV 531 int resno = res - dev->resource; 532 533 if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END) 534 return pci_sriov_resource_alignment(dev, resno); 535 #endif 536 if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS) 537 return pci_cardbus_resource_alignment(res); 538 return resource_alignment(res); 539 } 540 541 void pci_acs_init(struct pci_dev *dev); 542 #ifdef CONFIG_PCI_QUIRKS 543 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags); 544 int pci_dev_specific_enable_acs(struct pci_dev *dev); 545 int pci_dev_specific_disable_acs_redir(struct pci_dev *dev); 546 bool pcie_failed_link_retrain(struct pci_dev *dev); 547 #else 548 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev, 549 u16 acs_flags) 550 { 551 return -ENOTTY; 552 } 553 static inline int pci_dev_specific_enable_acs(struct pci_dev *dev) 554 { 555 return -ENOTTY; 556 } 557 static inline int pci_dev_specific_disable_acs_redir(struct pci_dev *dev) 558 { 559 return -ENOTTY; 560 } 561 static inline bool pcie_failed_link_retrain(struct pci_dev *dev) 562 { 563 return false; 564 } 565 #endif 566 567 /* PCI error reporting and recovery */ 568 pci_ers_result_t pcie_do_recovery(struct pci_dev *dev, 569 pci_channel_state_t state, 570 pci_ers_result_t (*reset_subordinates)(struct pci_dev *pdev)); 571 572 bool pcie_wait_for_link(struct pci_dev *pdev, bool active); 573 int pcie_retrain_link(struct pci_dev *pdev, bool use_lt); 574 575 /* ASPM-related functionality we need even without CONFIG_PCIEASPM */ 576 void pci_save_ltr_state(struct pci_dev *dev); 577 void pci_restore_ltr_state(struct pci_dev *dev); 578 void pci_configure_aspm_l1ss(struct pci_dev *dev); 579 void pci_save_aspm_l1ss_state(struct pci_dev *dev); 580 void pci_restore_aspm_l1ss_state(struct pci_dev *dev); 581 582 #ifdef CONFIG_PCIEASPM 583 void pcie_aspm_init_link_state(struct pci_dev *pdev); 584 void pcie_aspm_exit_link_state(struct pci_dev *pdev); 585 void pcie_aspm_pm_state_change(struct pci_dev *pdev, bool locked); 586 void pcie_aspm_powersave_config_link(struct pci_dev *pdev); 587 void pci_configure_ltr(struct pci_dev *pdev); 588 void pci_bridge_reconfigure_ltr(struct pci_dev *pdev); 589 #else 590 static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { } 591 static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { } 592 static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev, bool locked) { } 593 static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { } 594 static inline void pci_configure_ltr(struct pci_dev *pdev) { } 595 static inline void pci_bridge_reconfigure_ltr(struct pci_dev *pdev) { } 596 #endif 597 598 #ifdef CONFIG_PCIE_ECRC 599 void pcie_set_ecrc_checking(struct pci_dev *dev); 600 void pcie_ecrc_get_policy(char *str); 601 #else 602 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { } 603 static inline void pcie_ecrc_get_policy(char *str) { } 604 #endif 605 606 struct pci_dev_reset_methods { 607 u16 vendor; 608 u16 device; 609 int (*reset)(struct pci_dev *dev, bool probe); 610 }; 611 612 struct pci_reset_fn_method { 613 int (*reset_fn)(struct pci_dev *pdev, bool probe); 614 char *name; 615 }; 616 617 #ifdef CONFIG_PCI_QUIRKS 618 int pci_dev_specific_reset(struct pci_dev *dev, bool probe); 619 #else 620 static inline int pci_dev_specific_reset(struct pci_dev *dev, bool probe) 621 { 622 return -ENOTTY; 623 } 624 #endif 625 626 #if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64) 627 int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment, 628 struct resource *res); 629 #else 630 static inline int acpi_get_rc_resources(struct device *dev, const char *hid, 631 u16 segment, struct resource *res) 632 { 633 return -ENODEV; 634 } 635 #endif 636 637 int pci_rebar_get_current_size(struct pci_dev *pdev, int bar); 638 int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size); 639 static inline u64 pci_rebar_size_to_bytes(int size) 640 { 641 return 1ULL << (size + 20); 642 } 643 644 struct device_node; 645 646 #ifdef CONFIG_OF 647 int of_pci_parse_bus_range(struct device_node *node, struct resource *res); 648 int of_get_pci_domain_nr(struct device_node *node); 649 int of_pci_get_max_link_speed(struct device_node *node); 650 u32 of_pci_get_slot_power_limit(struct device_node *node, 651 u8 *slot_power_limit_value, 652 u8 *slot_power_limit_scale); 653 int pci_set_of_node(struct pci_dev *dev); 654 void pci_release_of_node(struct pci_dev *dev); 655 void pci_set_bus_of_node(struct pci_bus *bus); 656 void pci_release_bus_of_node(struct pci_bus *bus); 657 658 int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge); 659 660 #else 661 static inline int 662 of_pci_parse_bus_range(struct device_node *node, struct resource *res) 663 { 664 return -EINVAL; 665 } 666 667 static inline int 668 of_get_pci_domain_nr(struct device_node *node) 669 { 670 return -1; 671 } 672 673 static inline int 674 of_pci_get_max_link_speed(struct device_node *node) 675 { 676 return -EINVAL; 677 } 678 679 static inline u32 680 of_pci_get_slot_power_limit(struct device_node *node, 681 u8 *slot_power_limit_value, 682 u8 *slot_power_limit_scale) 683 { 684 if (slot_power_limit_value) 685 *slot_power_limit_value = 0; 686 if (slot_power_limit_scale) 687 *slot_power_limit_scale = 0; 688 return 0; 689 } 690 691 static inline int pci_set_of_node(struct pci_dev *dev) { return 0; } 692 static inline void pci_release_of_node(struct pci_dev *dev) { } 693 static inline void pci_set_bus_of_node(struct pci_bus *bus) { } 694 static inline void pci_release_bus_of_node(struct pci_bus *bus) { } 695 696 static inline int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge) 697 { 698 return 0; 699 } 700 701 #endif /* CONFIG_OF */ 702 703 struct of_changeset; 704 705 #ifdef CONFIG_PCI_DYNAMIC_OF_NODES 706 void of_pci_make_dev_node(struct pci_dev *pdev); 707 void of_pci_remove_node(struct pci_dev *pdev); 708 int of_pci_add_properties(struct pci_dev *pdev, struct of_changeset *ocs, 709 struct device_node *np); 710 #else 711 static inline void of_pci_make_dev_node(struct pci_dev *pdev) { } 712 static inline void of_pci_remove_node(struct pci_dev *pdev) { } 713 #endif 714 715 #ifdef CONFIG_PCIEAER 716 void pci_no_aer(void); 717 void pci_aer_init(struct pci_dev *dev); 718 void pci_aer_exit(struct pci_dev *dev); 719 extern const struct attribute_group aer_stats_attr_group; 720 void pci_aer_clear_fatal_status(struct pci_dev *dev); 721 int pci_aer_clear_status(struct pci_dev *dev); 722 int pci_aer_raw_clear_status(struct pci_dev *dev); 723 void pci_save_aer_state(struct pci_dev *dev); 724 void pci_restore_aer_state(struct pci_dev *dev); 725 #else 726 static inline void pci_no_aer(void) { } 727 static inline void pci_aer_init(struct pci_dev *d) { } 728 static inline void pci_aer_exit(struct pci_dev *d) { } 729 static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { } 730 static inline int pci_aer_clear_status(struct pci_dev *dev) { return -EINVAL; } 731 static inline int pci_aer_raw_clear_status(struct pci_dev *dev) { return -EINVAL; } 732 static inline void pci_save_aer_state(struct pci_dev *dev) { } 733 static inline void pci_restore_aer_state(struct pci_dev *dev) { } 734 #endif 735 736 #ifdef CONFIG_ACPI 737 int pci_acpi_program_hp_params(struct pci_dev *dev); 738 extern const struct attribute_group pci_dev_acpi_attr_group; 739 void pci_set_acpi_fwnode(struct pci_dev *dev); 740 int pci_dev_acpi_reset(struct pci_dev *dev, bool probe); 741 bool acpi_pci_power_manageable(struct pci_dev *dev); 742 bool acpi_pci_bridge_d3(struct pci_dev *dev); 743 int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state); 744 pci_power_t acpi_pci_get_power_state(struct pci_dev *dev); 745 void acpi_pci_refresh_power_state(struct pci_dev *dev); 746 int acpi_pci_wakeup(struct pci_dev *dev, bool enable); 747 bool acpi_pci_need_resume(struct pci_dev *dev); 748 pci_power_t acpi_pci_choose_state(struct pci_dev *pdev); 749 #else 750 static inline int pci_dev_acpi_reset(struct pci_dev *dev, bool probe) 751 { 752 return -ENOTTY; 753 } 754 static inline void pci_set_acpi_fwnode(struct pci_dev *dev) { } 755 static inline int pci_acpi_program_hp_params(struct pci_dev *dev) 756 { 757 return -ENODEV; 758 } 759 static inline bool acpi_pci_power_manageable(struct pci_dev *dev) 760 { 761 return false; 762 } 763 static inline bool acpi_pci_bridge_d3(struct pci_dev *dev) 764 { 765 return false; 766 } 767 static inline int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state) 768 { 769 return -ENODEV; 770 } 771 static inline pci_power_t acpi_pci_get_power_state(struct pci_dev *dev) 772 { 773 return PCI_UNKNOWN; 774 } 775 static inline void acpi_pci_refresh_power_state(struct pci_dev *dev) { } 776 static inline int acpi_pci_wakeup(struct pci_dev *dev, bool enable) 777 { 778 return -ENODEV; 779 } 780 static inline bool acpi_pci_need_resume(struct pci_dev *dev) 781 { 782 return false; 783 } 784 static inline pci_power_t acpi_pci_choose_state(struct pci_dev *pdev) 785 { 786 return PCI_POWER_ERROR; 787 } 788 #endif 789 790 #ifdef CONFIG_PCIEASPM 791 extern const struct attribute_group aspm_ctrl_attr_group; 792 #endif 793 794 extern const struct attribute_group pci_dev_reset_method_attr_group; 795 796 #ifdef CONFIG_X86_INTEL_MID 797 bool pci_use_mid_pm(void); 798 int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state); 799 pci_power_t mid_pci_get_power_state(struct pci_dev *pdev); 800 #else 801 static inline bool pci_use_mid_pm(void) 802 { 803 return false; 804 } 805 static inline int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state) 806 { 807 return -ENODEV; 808 } 809 static inline pci_power_t mid_pci_get_power_state(struct pci_dev *pdev) 810 { 811 return PCI_UNKNOWN; 812 } 813 #endif 814 815 /* 816 * Managed PCI resources. This manages device on/off, INTx/MSI/MSI-X 817 * on/off and BAR regions. pci_dev itself records MSI/MSI-X status, so 818 * there's no need to track it separately. pci_devres is initialized 819 * when a device is enabled using managed PCI device enable interface. 820 * 821 * TODO: Struct pci_devres and find_pci_dr() only need to be here because 822 * they're used in pci.c. Port or move these functions to devres.c and 823 * then remove them from here. 824 */ 825 struct pci_devres { 826 unsigned int enabled:1; 827 unsigned int pinned:1; 828 unsigned int orig_intx:1; 829 unsigned int restore_intx:1; 830 unsigned int mwi:1; 831 u32 region_mask; 832 }; 833 834 struct pci_devres *find_pci_dr(struct pci_dev *pdev); 835 836 /* 837 * Config Address for PCI Configuration Mechanism #1 838 * 839 * See PCI Local Bus Specification, Revision 3.0, 840 * Section 3.2.2.3.2, Figure 3-2, p. 50. 841 */ 842 843 #define PCI_CONF1_BUS_SHIFT 16 /* Bus number */ 844 #define PCI_CONF1_DEV_SHIFT 11 /* Device number */ 845 #define PCI_CONF1_FUNC_SHIFT 8 /* Function number */ 846 847 #define PCI_CONF1_BUS_MASK 0xff 848 #define PCI_CONF1_DEV_MASK 0x1f 849 #define PCI_CONF1_FUNC_MASK 0x7 850 #define PCI_CONF1_REG_MASK 0xfc /* Limit aligned offset to a maximum of 256B */ 851 852 #define PCI_CONF1_ENABLE BIT(31) 853 #define PCI_CONF1_BUS(x) (((x) & PCI_CONF1_BUS_MASK) << PCI_CONF1_BUS_SHIFT) 854 #define PCI_CONF1_DEV(x) (((x) & PCI_CONF1_DEV_MASK) << PCI_CONF1_DEV_SHIFT) 855 #define PCI_CONF1_FUNC(x) (((x) & PCI_CONF1_FUNC_MASK) << PCI_CONF1_FUNC_SHIFT) 856 #define PCI_CONF1_REG(x) ((x) & PCI_CONF1_REG_MASK) 857 858 #define PCI_CONF1_ADDRESS(bus, dev, func, reg) \ 859 (PCI_CONF1_ENABLE | \ 860 PCI_CONF1_BUS(bus) | \ 861 PCI_CONF1_DEV(dev) | \ 862 PCI_CONF1_FUNC(func) | \ 863 PCI_CONF1_REG(reg)) 864 865 /* 866 * Extension of PCI Config Address for accessing extended PCIe registers 867 * 868 * No standardized specification, but used on lot of non-ECAM-compliant ARM SoCs 869 * or on AMD Barcelona and new CPUs. Reserved bits [27:24] of PCI Config Address 870 * are used for specifying additional 4 high bits of PCI Express register. 871 */ 872 873 #define PCI_CONF1_EXT_REG_SHIFT 16 874 #define PCI_CONF1_EXT_REG_MASK 0xf00 875 #define PCI_CONF1_EXT_REG(x) (((x) & PCI_CONF1_EXT_REG_MASK) << PCI_CONF1_EXT_REG_SHIFT) 876 877 #define PCI_CONF1_EXT_ADDRESS(bus, dev, func, reg) \ 878 (PCI_CONF1_ADDRESS(bus, dev, func, reg) | \ 879 PCI_CONF1_EXT_REG(reg)) 880 881 #endif /* DRIVERS_PCI_H */ 882