1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef DRIVERS_PCI_H
3 #define DRIVERS_PCI_H
4
5 #include <linux/pci.h>
6
7 /* Number of possible devfns: 0.0 to 1f.7 inclusive */
8 #define MAX_NR_DEVFNS 256
9
10 #define PCI_FIND_CAP_TTL 48
11
12 #define PCI_VSEC_ID_INTEL_TBT 0x1234 /* Thunderbolt */
13
14 #define PCIE_LINK_RETRAIN_TIMEOUT_MS 1000
15
16 /*
17 * Power stable to PERST# inactive.
18 *
19 * See the "Power Sequencing and Reset Signal Timings" table of the PCI Express
20 * Card Electromechanical Specification, Revision 5.1, Section 2.9.2, Symbol
21 * "T_PVPERL".
22 */
23 #define PCIE_T_PVPERL_MS 100
24
25 /*
26 * REFCLK stable before PERST# inactive.
27 *
28 * See the "Power Sequencing and Reset Signal Timings" table of the PCI Express
29 * Card Electromechanical Specification, Revision 5.1, Section 2.9.2, Symbol
30 * "T_PERST-CLK".
31 */
32 #define PCIE_T_PERST_CLK_US 100
33
34 /*
35 * End of conventional reset (PERST# de-asserted) to first configuration
36 * request (device able to respond with a "Request Retry Status" completion),
37 * from PCIe r6.0, sec 6.6.1.
38 */
39 #define PCIE_T_RRS_READY_MS 100
40
41 /*
42 * PCIe r6.0, sec 5.3.3.2.1 <PME Synchronization>
43 * Recommends 1ms to 10ms timeout to check L2 ready.
44 */
45 #define PCIE_PME_TO_L2_TIMEOUT_US 10000
46
47 /*
48 * PCIe r6.0, sec 6.6.1 <Conventional Reset>
49 *
50 * - "With a Downstream Port that does not support Link speeds greater
51 * than 5.0 GT/s, software must wait a minimum of 100 ms following exit
52 * from a Conventional Reset before sending a Configuration Request to
53 * the device immediately below that Port."
54 *
55 * - "With a Downstream Port that supports Link speeds greater than
56 * 5.0 GT/s, software must wait a minimum of 100 ms after Link training
57 * completes before sending a Configuration Request to the device
58 * immediately below that Port."
59 */
60 #define PCIE_RESET_CONFIG_DEVICE_WAIT_MS 100
61
62 /* Message Routing (r[2:0]); PCIe r6.0, sec 2.2.8 */
63 #define PCIE_MSG_TYPE_R_RC 0
64 #define PCIE_MSG_TYPE_R_ADDR 1
65 #define PCIE_MSG_TYPE_R_ID 2
66 #define PCIE_MSG_TYPE_R_BC 3
67 #define PCIE_MSG_TYPE_R_LOCAL 4
68 #define PCIE_MSG_TYPE_R_GATHER 5
69
70 /* Power Management Messages; PCIe r6.0, sec 2.2.8.2 */
71 #define PCIE_MSG_CODE_PME_TURN_OFF 0x19
72
73 /* INTx Mechanism Messages; PCIe r6.0, sec 2.2.8.1 */
74 #define PCIE_MSG_CODE_ASSERT_INTA 0x20
75 #define PCIE_MSG_CODE_ASSERT_INTB 0x21
76 #define PCIE_MSG_CODE_ASSERT_INTC 0x22
77 #define PCIE_MSG_CODE_ASSERT_INTD 0x23
78 #define PCIE_MSG_CODE_DEASSERT_INTA 0x24
79 #define PCIE_MSG_CODE_DEASSERT_INTB 0x25
80 #define PCIE_MSG_CODE_DEASSERT_INTC 0x26
81 #define PCIE_MSG_CODE_DEASSERT_INTD 0x27
82
83 extern const unsigned char pcie_link_speed[];
84 extern bool pci_early_dump;
85
86 bool pcie_cap_has_lnkctl(const struct pci_dev *dev);
87 bool pcie_cap_has_lnkctl2(const struct pci_dev *dev);
88 bool pcie_cap_has_rtctl(const struct pci_dev *dev);
89
90 /* Functions internal to the PCI core code */
91
92 #ifdef CONFIG_DMI
93 extern const struct attribute_group pci_dev_smbios_attr_group;
94 #endif
95
96 enum pci_mmap_api {
97 PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */
98 PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */
99 };
100 int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai,
101 enum pci_mmap_api mmap_api);
102
103 bool pci_reset_supported(struct pci_dev *dev);
104 void pci_init_reset_methods(struct pci_dev *dev);
105 int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
106 int pci_bus_error_reset(struct pci_dev *dev);
107
108 struct pci_cap_saved_data {
109 u16 cap_nr;
110 bool cap_extended;
111 unsigned int size;
112 u32 data[];
113 };
114
115 struct pci_cap_saved_state {
116 struct hlist_node next;
117 struct pci_cap_saved_data cap;
118 };
119
120 void pci_allocate_cap_save_buffers(struct pci_dev *dev);
121 void pci_free_cap_save_buffers(struct pci_dev *dev);
122 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
123 int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
124 u16 cap, unsigned int size);
125 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
126 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
127 u16 cap);
128
129 #define PCI_PM_D2_DELAY 200 /* usec; see PCIe r4.0, sec 5.9.1 */
130 #define PCI_PM_D3HOT_WAIT 10 /* msec */
131 #define PCI_PM_D3COLD_WAIT 100 /* msec */
132
133 void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
134 void pci_refresh_power_state(struct pci_dev *dev);
135 int pci_power_up(struct pci_dev *dev);
136 void pci_disable_enabled_device(struct pci_dev *dev);
137 int pci_finish_runtime_suspend(struct pci_dev *dev);
138 void pcie_clear_device_status(struct pci_dev *dev);
139 void pcie_clear_root_pme_status(struct pci_dev *dev);
140 bool pci_check_pme_status(struct pci_dev *dev);
141 void pci_pme_wakeup_bus(struct pci_bus *bus);
142 void pci_pme_restore(struct pci_dev *dev);
143 bool pci_dev_need_resume(struct pci_dev *dev);
144 void pci_dev_adjust_pme(struct pci_dev *dev);
145 void pci_dev_complete_resume(struct pci_dev *pci_dev);
146 void pci_config_pm_runtime_get(struct pci_dev *dev);
147 void pci_config_pm_runtime_put(struct pci_dev *dev);
148 void pci_pm_init(struct pci_dev *dev);
149 void pci_ea_init(struct pci_dev *dev);
150 void pci_msi_init(struct pci_dev *dev);
151 void pci_msix_init(struct pci_dev *dev);
152 bool pci_bridge_d3_possible(struct pci_dev *dev);
153 void pci_bridge_d3_update(struct pci_dev *dev);
154 int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type);
155
pci_bus_rrs_vendor_id(u32 l)156 static inline bool pci_bus_rrs_vendor_id(u32 l)
157 {
158 return (l & 0xffff) == PCI_VENDOR_ID_PCI_SIG;
159 }
160
pci_wakeup_event(struct pci_dev * dev)161 static inline void pci_wakeup_event(struct pci_dev *dev)
162 {
163 /* Wait 100 ms before the system can be put into a sleep state. */
164 pm_wakeup_event(&dev->dev, 100);
165 }
166
pci_has_subordinate(struct pci_dev * pci_dev)167 static inline bool pci_has_subordinate(struct pci_dev *pci_dev)
168 {
169 return !!(pci_dev->subordinate);
170 }
171
pci_power_manageable(struct pci_dev * pci_dev)172 static inline bool pci_power_manageable(struct pci_dev *pci_dev)
173 {
174 /*
175 * Currently we allow normal PCI devices and PCI bridges transition
176 * into D3 if their bridge_d3 is set.
177 */
178 return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3;
179 }
180
pcie_downstream_port(const struct pci_dev * dev)181 static inline bool pcie_downstream_port(const struct pci_dev *dev)
182 {
183 int type = pci_pcie_type(dev);
184
185 return type == PCI_EXP_TYPE_ROOT_PORT ||
186 type == PCI_EXP_TYPE_DOWNSTREAM ||
187 type == PCI_EXP_TYPE_PCIE_BRIDGE;
188 }
189
190 void pci_vpd_init(struct pci_dev *dev);
191 extern const struct attribute_group pci_dev_vpd_attr_group;
192
193 /* PCI Virtual Channel */
194 int pci_save_vc_state(struct pci_dev *dev);
195 void pci_restore_vc_state(struct pci_dev *dev);
196 void pci_allocate_vc_save_buffers(struct pci_dev *dev);
197
198 /* PCI /proc functions */
199 #ifdef CONFIG_PROC_FS
200 int pci_proc_attach_device(struct pci_dev *dev);
201 int pci_proc_detach_device(struct pci_dev *dev);
202 int pci_proc_detach_bus(struct pci_bus *bus);
203 #else
pci_proc_attach_device(struct pci_dev * dev)204 static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; }
pci_proc_detach_device(struct pci_dev * dev)205 static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; }
pci_proc_detach_bus(struct pci_bus * bus)206 static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; }
207 #endif
208
209 /* Functions for PCI Hotplug drivers to use */
210 int pci_hp_add_bridge(struct pci_dev *dev);
211
212 #if defined(CONFIG_SYSFS) && defined(HAVE_PCI_LEGACY)
213 void pci_create_legacy_files(struct pci_bus *bus);
214 void pci_remove_legacy_files(struct pci_bus *bus);
215 #else
pci_create_legacy_files(struct pci_bus * bus)216 static inline void pci_create_legacy_files(struct pci_bus *bus) { }
pci_remove_legacy_files(struct pci_bus * bus)217 static inline void pci_remove_legacy_files(struct pci_bus *bus) { }
218 #endif
219
220 /* Lock for read/write access to pci device and bus lists */
221 extern struct rw_semaphore pci_bus_sem;
222 extern struct mutex pci_slot_mutex;
223
224 extern raw_spinlock_t pci_lock;
225
226 extern unsigned int pci_pm_d3hot_delay;
227
228 #ifdef CONFIG_PCI_MSI
229 void pci_no_msi(void);
230 #else
pci_no_msi(void)231 static inline void pci_no_msi(void) { }
232 #endif
233
234 void pci_realloc_get_opt(char *);
235
pci_no_d1d2(struct pci_dev * dev)236 static inline int pci_no_d1d2(struct pci_dev *dev)
237 {
238 unsigned int parent_dstates = 0;
239
240 if (dev->bus->self)
241 parent_dstates = dev->bus->self->no_d1d2;
242 return (dev->no_d1d2 || parent_dstates);
243
244 }
245
246 #ifdef CONFIG_SYSFS
247 int pci_create_sysfs_dev_files(struct pci_dev *pdev);
248 void pci_remove_sysfs_dev_files(struct pci_dev *pdev);
249 extern const struct attribute_group *pci_dev_groups[];
250 extern const struct attribute_group *pci_dev_attr_groups[];
251 extern const struct attribute_group *pcibus_groups[];
252 extern const struct attribute_group *pci_bus_groups[];
253 #else
pci_create_sysfs_dev_files(struct pci_dev * pdev)254 static inline int pci_create_sysfs_dev_files(struct pci_dev *pdev) { return 0; }
pci_remove_sysfs_dev_files(struct pci_dev * pdev)255 static inline void pci_remove_sysfs_dev_files(struct pci_dev *pdev) { }
256 #define pci_dev_groups NULL
257 #define pci_dev_attr_groups NULL
258 #define pcibus_groups NULL
259 #define pci_bus_groups NULL
260 #endif
261
262 extern unsigned long pci_hotplug_io_size;
263 extern unsigned long pci_hotplug_mmio_size;
264 extern unsigned long pci_hotplug_mmio_pref_size;
265 extern unsigned long pci_hotplug_bus_size;
266
267 /**
268 * pci_match_one_device - Tell if a PCI device structure has a matching
269 * PCI device id structure
270 * @id: single PCI device id structure to match
271 * @dev: the PCI device structure to match against
272 *
273 * Returns the matching pci_device_id structure or %NULL if there is no match.
274 */
275 static inline const struct pci_device_id *
pci_match_one_device(const struct pci_device_id * id,const struct pci_dev * dev)276 pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev)
277 {
278 if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) &&
279 (id->device == PCI_ANY_ID || id->device == dev->device) &&
280 (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) &&
281 (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) &&
282 !((id->class ^ dev->class) & id->class_mask))
283 return id;
284 return NULL;
285 }
286
287 /* PCI slot sysfs helper code */
288 #define to_pci_slot(s) container_of(s, struct pci_slot, kobj)
289
290 extern struct kset *pci_slots_kset;
291
292 struct pci_slot_attribute {
293 struct attribute attr;
294 ssize_t (*show)(struct pci_slot *, char *);
295 ssize_t (*store)(struct pci_slot *, const char *, size_t);
296 };
297 #define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr)
298
299 enum pci_bar_type {
300 pci_bar_unknown, /* Standard PCI BAR probe */
301 pci_bar_io, /* An I/O port BAR */
302 pci_bar_mem32, /* A 32-bit memory BAR */
303 pci_bar_mem64, /* A 64-bit memory BAR */
304 };
305
306 struct device *pci_get_host_bridge_device(struct pci_dev *dev);
307 void pci_put_host_bridge_device(struct device *dev);
308
309 int pci_configure_extended_tags(struct pci_dev *dev, void *ign);
310 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
311 int rrs_timeout);
312 bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
313 int rrs_timeout);
314 int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *pl, int rrs_timeout);
315
316 int pci_setup_device(struct pci_dev *dev);
317 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
318 struct resource *res, unsigned int reg);
319 void pci_configure_ari(struct pci_dev *dev);
320 void __pci_bus_size_bridges(struct pci_bus *bus,
321 struct list_head *realloc_head);
322 void __pci_bus_assign_resources(const struct pci_bus *bus,
323 struct list_head *realloc_head,
324 struct list_head *fail_head);
325 bool pci_bus_clip_resource(struct pci_dev *dev, int idx);
326
327 const char *pci_resource_name(struct pci_dev *dev, unsigned int i);
328
329 void pci_reassigndev_resource_alignment(struct pci_dev *dev);
330 void pci_disable_bridge_window(struct pci_dev *dev);
331 struct pci_bus *pci_bus_get(struct pci_bus *bus);
332 void pci_bus_put(struct pci_bus *bus);
333
334 /* PCIe link information from Link Capabilities 2 */
335 #define PCIE_LNKCAP2_SLS2SPEED(lnkcap2) \
336 ((lnkcap2) & PCI_EXP_LNKCAP2_SLS_64_0GB ? PCIE_SPEED_64_0GT : \
337 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_32_0GB ? PCIE_SPEED_32_0GT : \
338 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_16_0GB ? PCIE_SPEED_16_0GT : \
339 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_8_0GB ? PCIE_SPEED_8_0GT : \
340 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_5_0GB ? PCIE_SPEED_5_0GT : \
341 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_2_5GB ? PCIE_SPEED_2_5GT : \
342 PCI_SPEED_UNKNOWN)
343
344 /* PCIe speed to Mb/s reduced by encoding overhead */
345 #define PCIE_SPEED2MBS_ENC(speed) \
346 ((speed) == PCIE_SPEED_64_0GT ? 64000*1/1 : \
347 (speed) == PCIE_SPEED_32_0GT ? 32000*128/130 : \
348 (speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \
349 (speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \
350 (speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \
351 (speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \
352 0)
353
pcie_dev_speed_mbps(enum pci_bus_speed speed)354 static inline int pcie_dev_speed_mbps(enum pci_bus_speed speed)
355 {
356 switch (speed) {
357 case PCIE_SPEED_2_5GT:
358 return 2500;
359 case PCIE_SPEED_5_0GT:
360 return 5000;
361 case PCIE_SPEED_8_0GT:
362 return 8000;
363 case PCIE_SPEED_16_0GT:
364 return 16000;
365 case PCIE_SPEED_32_0GT:
366 return 32000;
367 case PCIE_SPEED_64_0GT:
368 return 64000;
369 default:
370 break;
371 }
372
373 return -EINVAL;
374 }
375
376 const char *pci_speed_string(enum pci_bus_speed speed);
377 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
378 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
379 void __pcie_print_link_status(struct pci_dev *dev, bool verbose);
380 void pcie_report_downtraining(struct pci_dev *dev);
381 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
382
383 /* Single Root I/O Virtualization */
384 struct pci_sriov {
385 int pos; /* Capability position */
386 int nres; /* Number of resources */
387 u32 cap; /* SR-IOV Capabilities */
388 u16 ctrl; /* SR-IOV Control */
389 u16 total_VFs; /* Total VFs associated with the PF */
390 u16 initial_VFs; /* Initial VFs associated with the PF */
391 u16 num_VFs; /* Number of VFs available */
392 u16 offset; /* First VF Routing ID offset */
393 u16 stride; /* Following VF stride */
394 u16 vf_device; /* VF device ID */
395 u32 pgsz; /* Page size for BAR alignment */
396 u8 link; /* Function Dependency Link */
397 u8 max_VF_buses; /* Max buses consumed by VFs */
398 u16 driver_max_VFs; /* Max num VFs driver supports */
399 struct pci_dev *dev; /* Lowest numbered PF */
400 struct pci_dev *self; /* This PF */
401 u32 class; /* VF device */
402 u8 hdr_type; /* VF header type */
403 u16 subsystem_vendor; /* VF subsystem vendor */
404 u16 subsystem_device; /* VF subsystem device */
405 resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */
406 bool drivers_autoprobe; /* Auto probing of VFs by driver */
407 };
408
409 #ifdef CONFIG_PCI_DOE
410 void pci_doe_init(struct pci_dev *pdev);
411 void pci_doe_destroy(struct pci_dev *pdev);
412 void pci_doe_disconnected(struct pci_dev *pdev);
413 #else
pci_doe_init(struct pci_dev * pdev)414 static inline void pci_doe_init(struct pci_dev *pdev) { }
pci_doe_destroy(struct pci_dev * pdev)415 static inline void pci_doe_destroy(struct pci_dev *pdev) { }
pci_doe_disconnected(struct pci_dev * pdev)416 static inline void pci_doe_disconnected(struct pci_dev *pdev) { }
417 #endif
418
419 #ifdef CONFIG_PCI_NPEM
420 void pci_npem_create(struct pci_dev *dev);
421 void pci_npem_remove(struct pci_dev *dev);
422 #else
pci_npem_create(struct pci_dev * dev)423 static inline void pci_npem_create(struct pci_dev *dev) { }
pci_npem_remove(struct pci_dev * dev)424 static inline void pci_npem_remove(struct pci_dev *dev) { }
425 #endif
426
427 /**
428 * pci_dev_set_io_state - Set the new error state if possible.
429 *
430 * @dev: PCI device to set new error_state
431 * @new: the state we want dev to be in
432 *
433 * If the device is experiencing perm_failure, it has to remain in that state.
434 * Any other transition is allowed.
435 *
436 * Returns true if state has been changed to the requested state.
437 */
pci_dev_set_io_state(struct pci_dev * dev,pci_channel_state_t new)438 static inline bool pci_dev_set_io_state(struct pci_dev *dev,
439 pci_channel_state_t new)
440 {
441 pci_channel_state_t old;
442
443 switch (new) {
444 case pci_channel_io_perm_failure:
445 xchg(&dev->error_state, pci_channel_io_perm_failure);
446 return true;
447 case pci_channel_io_frozen:
448 old = cmpxchg(&dev->error_state, pci_channel_io_normal,
449 pci_channel_io_frozen);
450 return old != pci_channel_io_perm_failure;
451 case pci_channel_io_normal:
452 old = cmpxchg(&dev->error_state, pci_channel_io_frozen,
453 pci_channel_io_normal);
454 return old != pci_channel_io_perm_failure;
455 default:
456 return false;
457 }
458 }
459
pci_dev_set_disconnected(struct pci_dev * dev,void * unused)460 static inline int pci_dev_set_disconnected(struct pci_dev *dev, void *unused)
461 {
462 pci_dev_set_io_state(dev, pci_channel_io_perm_failure);
463 pci_doe_disconnected(dev);
464
465 return 0;
466 }
467
468 /* pci_dev priv_flags */
469 #define PCI_DEV_ADDED 0
470 #define PCI_DPC_RECOVERED 1
471 #define PCI_DPC_RECOVERING 2
472
pci_dev_assign_added(struct pci_dev * dev,bool added)473 static inline void pci_dev_assign_added(struct pci_dev *dev, bool added)
474 {
475 assign_bit(PCI_DEV_ADDED, &dev->priv_flags, added);
476 }
477
pci_dev_is_added(const struct pci_dev * dev)478 static inline bool pci_dev_is_added(const struct pci_dev *dev)
479 {
480 return test_bit(PCI_DEV_ADDED, &dev->priv_flags);
481 }
482
483 #ifdef CONFIG_PCIEAER
484 #include <linux/aer.h>
485
486 #define AER_MAX_MULTI_ERR_DEVICES 5 /* Not likely to have more */
487
488 struct aer_err_info {
489 struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES];
490 int error_dev_num;
491
492 unsigned int id:16;
493
494 unsigned int severity:2; /* 0:NONFATAL | 1:FATAL | 2:COR */
495 unsigned int __pad1:5;
496 unsigned int multi_error_valid:1;
497
498 unsigned int first_error:5;
499 unsigned int __pad2:2;
500 unsigned int tlp_header_valid:1;
501
502 unsigned int status; /* COR/UNCOR Error Status */
503 unsigned int mask; /* COR/UNCOR Error Mask */
504 struct pcie_tlp_log tlp; /* TLP Header */
505 };
506
507 int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info);
508 void aer_print_error(struct pci_dev *dev, struct aer_err_info *info);
509 #endif /* CONFIG_PCIEAER */
510
511 #ifdef CONFIG_PCIEPORTBUS
512 /* Cached RCEC Endpoint Association */
513 struct rcec_ea {
514 u8 nextbusn;
515 u8 lastbusn;
516 u32 bitmap;
517 };
518 #endif
519
520 #ifdef CONFIG_PCIE_DPC
521 void pci_save_dpc_state(struct pci_dev *dev);
522 void pci_restore_dpc_state(struct pci_dev *dev);
523 void pci_dpc_init(struct pci_dev *pdev);
524 void dpc_process_error(struct pci_dev *pdev);
525 pci_ers_result_t dpc_reset_link(struct pci_dev *pdev);
526 bool pci_dpc_recovered(struct pci_dev *pdev);
527 #else
pci_save_dpc_state(struct pci_dev * dev)528 static inline void pci_save_dpc_state(struct pci_dev *dev) { }
pci_restore_dpc_state(struct pci_dev * dev)529 static inline void pci_restore_dpc_state(struct pci_dev *dev) { }
pci_dpc_init(struct pci_dev * pdev)530 static inline void pci_dpc_init(struct pci_dev *pdev) { }
pci_dpc_recovered(struct pci_dev * pdev)531 static inline bool pci_dpc_recovered(struct pci_dev *pdev) { return false; }
532 #endif
533
534 #ifdef CONFIG_PCIEPORTBUS
535 void pci_rcec_init(struct pci_dev *dev);
536 void pci_rcec_exit(struct pci_dev *dev);
537 void pcie_link_rcec(struct pci_dev *rcec);
538 void pcie_walk_rcec(struct pci_dev *rcec,
539 int (*cb)(struct pci_dev *, void *),
540 void *userdata);
541 #else
pci_rcec_init(struct pci_dev * dev)542 static inline void pci_rcec_init(struct pci_dev *dev) { }
pci_rcec_exit(struct pci_dev * dev)543 static inline void pci_rcec_exit(struct pci_dev *dev) { }
pcie_link_rcec(struct pci_dev * rcec)544 static inline void pcie_link_rcec(struct pci_dev *rcec) { }
pcie_walk_rcec(struct pci_dev * rcec,int (* cb)(struct pci_dev *,void *),void * userdata)545 static inline void pcie_walk_rcec(struct pci_dev *rcec,
546 int (*cb)(struct pci_dev *, void *),
547 void *userdata) { }
548 #endif
549
550 #ifdef CONFIG_PCI_ATS
551 /* Address Translation Service */
552 void pci_ats_init(struct pci_dev *dev);
553 void pci_restore_ats_state(struct pci_dev *dev);
554 #else
pci_ats_init(struct pci_dev * d)555 static inline void pci_ats_init(struct pci_dev *d) { }
pci_restore_ats_state(struct pci_dev * dev)556 static inline void pci_restore_ats_state(struct pci_dev *dev) { }
557 #endif /* CONFIG_PCI_ATS */
558
559 #ifdef CONFIG_PCI_PRI
560 void pci_pri_init(struct pci_dev *dev);
561 void pci_restore_pri_state(struct pci_dev *pdev);
562 #else
pci_pri_init(struct pci_dev * dev)563 static inline void pci_pri_init(struct pci_dev *dev) { }
pci_restore_pri_state(struct pci_dev * pdev)564 static inline void pci_restore_pri_state(struct pci_dev *pdev) { }
565 #endif
566
567 #ifdef CONFIG_PCI_PASID
568 void pci_pasid_init(struct pci_dev *dev);
569 void pci_restore_pasid_state(struct pci_dev *pdev);
570 #else
pci_pasid_init(struct pci_dev * dev)571 static inline void pci_pasid_init(struct pci_dev *dev) { }
pci_restore_pasid_state(struct pci_dev * pdev)572 static inline void pci_restore_pasid_state(struct pci_dev *pdev) { }
573 #endif
574
575 #ifdef CONFIG_PCI_IOV
576 int pci_iov_init(struct pci_dev *dev);
577 void pci_iov_release(struct pci_dev *dev);
578 void pci_iov_remove(struct pci_dev *dev);
579 void pci_iov_update_resource(struct pci_dev *dev, int resno);
580 resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno);
581 void pci_restore_iov_state(struct pci_dev *dev);
582 int pci_iov_bus_range(struct pci_bus *bus);
583 extern const struct attribute_group sriov_pf_dev_attr_group;
584 extern const struct attribute_group sriov_vf_dev_attr_group;
585 #else
pci_iov_init(struct pci_dev * dev)586 static inline int pci_iov_init(struct pci_dev *dev)
587 {
588 return -ENODEV;
589 }
pci_iov_release(struct pci_dev * dev)590 static inline void pci_iov_release(struct pci_dev *dev) { }
pci_iov_remove(struct pci_dev * dev)591 static inline void pci_iov_remove(struct pci_dev *dev) { }
pci_restore_iov_state(struct pci_dev * dev)592 static inline void pci_restore_iov_state(struct pci_dev *dev) { }
pci_iov_bus_range(struct pci_bus * bus)593 static inline int pci_iov_bus_range(struct pci_bus *bus)
594 {
595 return 0;
596 }
597
598 #endif /* CONFIG_PCI_IOV */
599
600 #ifdef CONFIG_PCIE_PTM
601 void pci_ptm_init(struct pci_dev *dev);
602 void pci_save_ptm_state(struct pci_dev *dev);
603 void pci_restore_ptm_state(struct pci_dev *dev);
604 void pci_suspend_ptm(struct pci_dev *dev);
605 void pci_resume_ptm(struct pci_dev *dev);
606 #else
pci_ptm_init(struct pci_dev * dev)607 static inline void pci_ptm_init(struct pci_dev *dev) { }
pci_save_ptm_state(struct pci_dev * dev)608 static inline void pci_save_ptm_state(struct pci_dev *dev) { }
pci_restore_ptm_state(struct pci_dev * dev)609 static inline void pci_restore_ptm_state(struct pci_dev *dev) { }
pci_suspend_ptm(struct pci_dev * dev)610 static inline void pci_suspend_ptm(struct pci_dev *dev) { }
pci_resume_ptm(struct pci_dev * dev)611 static inline void pci_resume_ptm(struct pci_dev *dev) { }
612 #endif
613
614 unsigned long pci_cardbus_resource_alignment(struct resource *);
615
pci_resource_alignment(struct pci_dev * dev,struct resource * res)616 static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
617 struct resource *res)
618 {
619 #ifdef CONFIG_PCI_IOV
620 int resno = res - dev->resource;
621
622 if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
623 return pci_sriov_resource_alignment(dev, resno);
624 #endif
625 if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS)
626 return pci_cardbus_resource_alignment(res);
627 return resource_alignment(res);
628 }
629
630 void pci_acs_init(struct pci_dev *dev);
631 #ifdef CONFIG_PCI_QUIRKS
632 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
633 int pci_dev_specific_enable_acs(struct pci_dev *dev);
634 int pci_dev_specific_disable_acs_redir(struct pci_dev *dev);
635 int pcie_failed_link_retrain(struct pci_dev *dev);
636 #else
pci_dev_specific_acs_enabled(struct pci_dev * dev,u16 acs_flags)637 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
638 u16 acs_flags)
639 {
640 return -ENOTTY;
641 }
pci_dev_specific_enable_acs(struct pci_dev * dev)642 static inline int pci_dev_specific_enable_acs(struct pci_dev *dev)
643 {
644 return -ENOTTY;
645 }
pci_dev_specific_disable_acs_redir(struct pci_dev * dev)646 static inline int pci_dev_specific_disable_acs_redir(struct pci_dev *dev)
647 {
648 return -ENOTTY;
649 }
pcie_failed_link_retrain(struct pci_dev * dev)650 static inline int pcie_failed_link_retrain(struct pci_dev *dev)
651 {
652 return -ENOTTY;
653 }
654 #endif
655
656 /* PCI error reporting and recovery */
657 pci_ers_result_t pcie_do_recovery(struct pci_dev *dev,
658 pci_channel_state_t state,
659 pci_ers_result_t (*reset_subordinates)(struct pci_dev *pdev));
660
661 bool pcie_wait_for_link(struct pci_dev *pdev, bool active);
662 int pcie_retrain_link(struct pci_dev *pdev, bool use_lt);
663
664 /* ASPM-related functionality we need even without CONFIG_PCIEASPM */
665 void pci_save_ltr_state(struct pci_dev *dev);
666 void pci_restore_ltr_state(struct pci_dev *dev);
667 void pci_configure_aspm_l1ss(struct pci_dev *dev);
668 void pci_save_aspm_l1ss_state(struct pci_dev *dev);
669 void pci_restore_aspm_l1ss_state(struct pci_dev *dev);
670
671 #ifdef CONFIG_PCIEASPM
672 void pcie_aspm_init_link_state(struct pci_dev *pdev);
673 void pcie_aspm_exit_link_state(struct pci_dev *pdev);
674 void pcie_aspm_pm_state_change(struct pci_dev *pdev, bool locked);
675 void pcie_aspm_powersave_config_link(struct pci_dev *pdev);
676 void pci_configure_ltr(struct pci_dev *pdev);
677 void pci_bridge_reconfigure_ltr(struct pci_dev *pdev);
678 #else
pcie_aspm_init_link_state(struct pci_dev * pdev)679 static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { }
pcie_aspm_exit_link_state(struct pci_dev * pdev)680 static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { }
pcie_aspm_pm_state_change(struct pci_dev * pdev,bool locked)681 static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev, bool locked) { }
pcie_aspm_powersave_config_link(struct pci_dev * pdev)682 static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { }
pci_configure_ltr(struct pci_dev * pdev)683 static inline void pci_configure_ltr(struct pci_dev *pdev) { }
pci_bridge_reconfigure_ltr(struct pci_dev * pdev)684 static inline void pci_bridge_reconfigure_ltr(struct pci_dev *pdev) { }
685 #endif
686
687 #ifdef CONFIG_PCIE_ECRC
688 void pcie_set_ecrc_checking(struct pci_dev *dev);
689 void pcie_ecrc_get_policy(char *str);
690 #else
pcie_set_ecrc_checking(struct pci_dev * dev)691 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
pcie_ecrc_get_policy(char * str)692 static inline void pcie_ecrc_get_policy(char *str) { }
693 #endif
694
695 struct pci_dev_reset_methods {
696 u16 vendor;
697 u16 device;
698 int (*reset)(struct pci_dev *dev, bool probe);
699 };
700
701 struct pci_reset_fn_method {
702 int (*reset_fn)(struct pci_dev *pdev, bool probe);
703 char *name;
704 };
705
706 #ifdef CONFIG_PCI_QUIRKS
707 int pci_dev_specific_reset(struct pci_dev *dev, bool probe);
708 #else
pci_dev_specific_reset(struct pci_dev * dev,bool probe)709 static inline int pci_dev_specific_reset(struct pci_dev *dev, bool probe)
710 {
711 return -ENOTTY;
712 }
713 #endif
714
715 #if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64)
716 int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment,
717 struct resource *res);
718 #else
acpi_get_rc_resources(struct device * dev,const char * hid,u16 segment,struct resource * res)719 static inline int acpi_get_rc_resources(struct device *dev, const char *hid,
720 u16 segment, struct resource *res)
721 {
722 return -ENODEV;
723 }
724 #endif
725
726 int pci_rebar_get_current_size(struct pci_dev *pdev, int bar);
727 int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size);
pci_rebar_size_to_bytes(int size)728 static inline u64 pci_rebar_size_to_bytes(int size)
729 {
730 return 1ULL << (size + 20);
731 }
732
733 struct device_node;
734
735 #ifdef CONFIG_OF
736 int of_pci_parse_bus_range(struct device_node *node, struct resource *res);
737 int of_get_pci_domain_nr(struct device_node *node);
738 int of_pci_get_max_link_speed(struct device_node *node);
739 u32 of_pci_get_slot_power_limit(struct device_node *node,
740 u8 *slot_power_limit_value,
741 u8 *slot_power_limit_scale);
742 bool of_pci_preserve_config(struct device_node *node);
743 int pci_set_of_node(struct pci_dev *dev);
744 void pci_release_of_node(struct pci_dev *dev);
745 void pci_set_bus_of_node(struct pci_bus *bus);
746 void pci_release_bus_of_node(struct pci_bus *bus);
747
748 int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge);
749
750 #else
751 static inline int
of_pci_parse_bus_range(struct device_node * node,struct resource * res)752 of_pci_parse_bus_range(struct device_node *node, struct resource *res)
753 {
754 return -EINVAL;
755 }
756
757 static inline int
of_get_pci_domain_nr(struct device_node * node)758 of_get_pci_domain_nr(struct device_node *node)
759 {
760 return -1;
761 }
762
763 static inline int
of_pci_get_max_link_speed(struct device_node * node)764 of_pci_get_max_link_speed(struct device_node *node)
765 {
766 return -EINVAL;
767 }
768
769 static inline u32
of_pci_get_slot_power_limit(struct device_node * node,u8 * slot_power_limit_value,u8 * slot_power_limit_scale)770 of_pci_get_slot_power_limit(struct device_node *node,
771 u8 *slot_power_limit_value,
772 u8 *slot_power_limit_scale)
773 {
774 if (slot_power_limit_value)
775 *slot_power_limit_value = 0;
776 if (slot_power_limit_scale)
777 *slot_power_limit_scale = 0;
778 return 0;
779 }
780
of_pci_preserve_config(struct device_node * node)781 static inline bool of_pci_preserve_config(struct device_node *node)
782 {
783 return false;
784 }
785
pci_set_of_node(struct pci_dev * dev)786 static inline int pci_set_of_node(struct pci_dev *dev) { return 0; }
pci_release_of_node(struct pci_dev * dev)787 static inline void pci_release_of_node(struct pci_dev *dev) { }
pci_set_bus_of_node(struct pci_bus * bus)788 static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
pci_release_bus_of_node(struct pci_bus * bus)789 static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
790
devm_of_pci_bridge_init(struct device * dev,struct pci_host_bridge * bridge)791 static inline int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge)
792 {
793 return 0;
794 }
795
796 #endif /* CONFIG_OF */
797
798 struct of_changeset;
799
800 #ifdef CONFIG_PCI_DYNAMIC_OF_NODES
801 void of_pci_make_dev_node(struct pci_dev *pdev);
802 void of_pci_remove_node(struct pci_dev *pdev);
803 int of_pci_add_properties(struct pci_dev *pdev, struct of_changeset *ocs,
804 struct device_node *np);
805 #else
of_pci_make_dev_node(struct pci_dev * pdev)806 static inline void of_pci_make_dev_node(struct pci_dev *pdev) { }
of_pci_remove_node(struct pci_dev * pdev)807 static inline void of_pci_remove_node(struct pci_dev *pdev) { }
808 #endif
809
810 #ifdef CONFIG_PCIEAER
811 void pci_no_aer(void);
812 void pci_aer_init(struct pci_dev *dev);
813 void pci_aer_exit(struct pci_dev *dev);
814 extern const struct attribute_group aer_stats_attr_group;
815 void pci_aer_clear_fatal_status(struct pci_dev *dev);
816 int pci_aer_clear_status(struct pci_dev *dev);
817 int pci_aer_raw_clear_status(struct pci_dev *dev);
818 void pci_save_aer_state(struct pci_dev *dev);
819 void pci_restore_aer_state(struct pci_dev *dev);
820 #else
pci_no_aer(void)821 static inline void pci_no_aer(void) { }
pci_aer_init(struct pci_dev * d)822 static inline void pci_aer_init(struct pci_dev *d) { }
pci_aer_exit(struct pci_dev * d)823 static inline void pci_aer_exit(struct pci_dev *d) { }
pci_aer_clear_fatal_status(struct pci_dev * dev)824 static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { }
pci_aer_clear_status(struct pci_dev * dev)825 static inline int pci_aer_clear_status(struct pci_dev *dev) { return -EINVAL; }
pci_aer_raw_clear_status(struct pci_dev * dev)826 static inline int pci_aer_raw_clear_status(struct pci_dev *dev) { return -EINVAL; }
pci_save_aer_state(struct pci_dev * dev)827 static inline void pci_save_aer_state(struct pci_dev *dev) { }
pci_restore_aer_state(struct pci_dev * dev)828 static inline void pci_restore_aer_state(struct pci_dev *dev) { }
829 #endif
830
831 #ifdef CONFIG_ACPI
832 bool pci_acpi_preserve_config(struct pci_host_bridge *bridge);
833 int pci_acpi_program_hp_params(struct pci_dev *dev);
834 extern const struct attribute_group pci_dev_acpi_attr_group;
835 void pci_set_acpi_fwnode(struct pci_dev *dev);
836 int pci_dev_acpi_reset(struct pci_dev *dev, bool probe);
837 bool acpi_pci_power_manageable(struct pci_dev *dev);
838 bool acpi_pci_bridge_d3(struct pci_dev *dev);
839 int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state);
840 pci_power_t acpi_pci_get_power_state(struct pci_dev *dev);
841 void acpi_pci_refresh_power_state(struct pci_dev *dev);
842 int acpi_pci_wakeup(struct pci_dev *dev, bool enable);
843 bool acpi_pci_need_resume(struct pci_dev *dev);
844 pci_power_t acpi_pci_choose_state(struct pci_dev *pdev);
845 #else
pci_acpi_preserve_config(struct pci_host_bridge * bridge)846 static inline bool pci_acpi_preserve_config(struct pci_host_bridge *bridge)
847 {
848 return false;
849 }
pci_dev_acpi_reset(struct pci_dev * dev,bool probe)850 static inline int pci_dev_acpi_reset(struct pci_dev *dev, bool probe)
851 {
852 return -ENOTTY;
853 }
pci_set_acpi_fwnode(struct pci_dev * dev)854 static inline void pci_set_acpi_fwnode(struct pci_dev *dev) { }
pci_acpi_program_hp_params(struct pci_dev * dev)855 static inline int pci_acpi_program_hp_params(struct pci_dev *dev)
856 {
857 return -ENODEV;
858 }
acpi_pci_power_manageable(struct pci_dev * dev)859 static inline bool acpi_pci_power_manageable(struct pci_dev *dev)
860 {
861 return false;
862 }
acpi_pci_bridge_d3(struct pci_dev * dev)863 static inline bool acpi_pci_bridge_d3(struct pci_dev *dev)
864 {
865 return false;
866 }
acpi_pci_set_power_state(struct pci_dev * dev,pci_power_t state)867 static inline int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state)
868 {
869 return -ENODEV;
870 }
acpi_pci_get_power_state(struct pci_dev * dev)871 static inline pci_power_t acpi_pci_get_power_state(struct pci_dev *dev)
872 {
873 return PCI_UNKNOWN;
874 }
acpi_pci_refresh_power_state(struct pci_dev * dev)875 static inline void acpi_pci_refresh_power_state(struct pci_dev *dev) { }
acpi_pci_wakeup(struct pci_dev * dev,bool enable)876 static inline int acpi_pci_wakeup(struct pci_dev *dev, bool enable)
877 {
878 return -ENODEV;
879 }
acpi_pci_need_resume(struct pci_dev * dev)880 static inline bool acpi_pci_need_resume(struct pci_dev *dev)
881 {
882 return false;
883 }
acpi_pci_choose_state(struct pci_dev * pdev)884 static inline pci_power_t acpi_pci_choose_state(struct pci_dev *pdev)
885 {
886 return PCI_POWER_ERROR;
887 }
888 #endif
889
890 #ifdef CONFIG_PCIEASPM
891 extern const struct attribute_group aspm_ctrl_attr_group;
892 #endif
893
894 extern const struct attribute_group pci_dev_reset_method_attr_group;
895
896 #ifdef CONFIG_X86_INTEL_MID
897 bool pci_use_mid_pm(void);
898 int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state);
899 pci_power_t mid_pci_get_power_state(struct pci_dev *pdev);
900 #else
pci_use_mid_pm(void)901 static inline bool pci_use_mid_pm(void)
902 {
903 return false;
904 }
mid_pci_set_power_state(struct pci_dev * pdev,pci_power_t state)905 static inline int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state)
906 {
907 return -ENODEV;
908 }
mid_pci_get_power_state(struct pci_dev * pdev)909 static inline pci_power_t mid_pci_get_power_state(struct pci_dev *pdev)
910 {
911 return PCI_UNKNOWN;
912 }
913 #endif
914
915 int pcim_intx(struct pci_dev *dev, int enable);
916 int pcim_request_region_exclusive(struct pci_dev *pdev, int bar,
917 const char *name);
918 void pcim_release_region(struct pci_dev *pdev, int bar);
919
920 /*
921 * Config Address for PCI Configuration Mechanism #1
922 *
923 * See PCI Local Bus Specification, Revision 3.0,
924 * Section 3.2.2.3.2, Figure 3-2, p. 50.
925 */
926
927 #define PCI_CONF1_BUS_SHIFT 16 /* Bus number */
928 #define PCI_CONF1_DEV_SHIFT 11 /* Device number */
929 #define PCI_CONF1_FUNC_SHIFT 8 /* Function number */
930
931 #define PCI_CONF1_BUS_MASK 0xff
932 #define PCI_CONF1_DEV_MASK 0x1f
933 #define PCI_CONF1_FUNC_MASK 0x7
934 #define PCI_CONF1_REG_MASK 0xfc /* Limit aligned offset to a maximum of 256B */
935
936 #define PCI_CONF1_ENABLE BIT(31)
937 #define PCI_CONF1_BUS(x) (((x) & PCI_CONF1_BUS_MASK) << PCI_CONF1_BUS_SHIFT)
938 #define PCI_CONF1_DEV(x) (((x) & PCI_CONF1_DEV_MASK) << PCI_CONF1_DEV_SHIFT)
939 #define PCI_CONF1_FUNC(x) (((x) & PCI_CONF1_FUNC_MASK) << PCI_CONF1_FUNC_SHIFT)
940 #define PCI_CONF1_REG(x) ((x) & PCI_CONF1_REG_MASK)
941
942 #define PCI_CONF1_ADDRESS(bus, dev, func, reg) \
943 (PCI_CONF1_ENABLE | \
944 PCI_CONF1_BUS(bus) | \
945 PCI_CONF1_DEV(dev) | \
946 PCI_CONF1_FUNC(func) | \
947 PCI_CONF1_REG(reg))
948
949 /*
950 * Extension of PCI Config Address for accessing extended PCIe registers
951 *
952 * No standardized specification, but used on lot of non-ECAM-compliant ARM SoCs
953 * or on AMD Barcelona and new CPUs. Reserved bits [27:24] of PCI Config Address
954 * are used for specifying additional 4 high bits of PCI Express register.
955 */
956
957 #define PCI_CONF1_EXT_REG_SHIFT 16
958 #define PCI_CONF1_EXT_REG_MASK 0xf00
959 #define PCI_CONF1_EXT_REG(x) (((x) & PCI_CONF1_EXT_REG_MASK) << PCI_CONF1_EXT_REG_SHIFT)
960
961 #define PCI_CONF1_EXT_ADDRESS(bus, dev, func, reg) \
962 (PCI_CONF1_ADDRESS(bus, dev, func, reg) | \
963 PCI_CONF1_EXT_REG(reg))
964
965 #endif /* DRIVERS_PCI_H */
966