1 /* 2 * PCI Bus Services, see include/linux/pci.h for further explanation. 3 * 4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter, 5 * David Mosberger-Tang 6 * 7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz> 8 */ 9 10 #include <linux/kernel.h> 11 #include <linux/delay.h> 12 #include <linux/init.h> 13 #include <linux/pci.h> 14 #include <linux/pm.h> 15 #include <linux/slab.h> 16 #include <linux/module.h> 17 #include <linux/spinlock.h> 18 #include <linux/string.h> 19 #include <linux/log2.h> 20 #include <linux/pci-aspm.h> 21 #include <linux/pm_wakeup.h> 22 #include <linux/interrupt.h> 23 #include <linux/device.h> 24 #include <linux/pm_runtime.h> 25 #include <asm/setup.h> 26 #include "pci.h" 27 28 const char *pci_power_names[] = { 29 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown", 30 }; 31 EXPORT_SYMBOL_GPL(pci_power_names); 32 33 int isa_dma_bridge_buggy; 34 EXPORT_SYMBOL(isa_dma_bridge_buggy); 35 36 int pci_pci_problems; 37 EXPORT_SYMBOL(pci_pci_problems); 38 39 unsigned int pci_pm_d3_delay; 40 41 static void pci_pme_list_scan(struct work_struct *work); 42 43 static LIST_HEAD(pci_pme_list); 44 static DEFINE_MUTEX(pci_pme_list_mutex); 45 static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan); 46 47 struct pci_pme_device { 48 struct list_head list; 49 struct pci_dev *dev; 50 }; 51 52 #define PME_TIMEOUT 1000 /* How long between PME checks */ 53 54 static void pci_dev_d3_sleep(struct pci_dev *dev) 55 { 56 unsigned int delay = dev->d3_delay; 57 58 if (delay < pci_pm_d3_delay) 59 delay = pci_pm_d3_delay; 60 61 msleep(delay); 62 } 63 64 #ifdef CONFIG_PCI_DOMAINS 65 int pci_domains_supported = 1; 66 #endif 67 68 #define DEFAULT_CARDBUS_IO_SIZE (256) 69 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024) 70 /* pci=cbmemsize=nnM,cbiosize=nn can override this */ 71 unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE; 72 unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE; 73 74 #define DEFAULT_HOTPLUG_IO_SIZE (256) 75 #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024) 76 /* pci=hpmemsize=nnM,hpiosize=nn can override this */ 77 unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE; 78 unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE; 79 80 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_TUNE_OFF; 81 82 /* 83 * The default CLS is used if arch didn't set CLS explicitly and not 84 * all pci devices agree on the same value. Arch can override either 85 * the dfl or actual value as it sees fit. Don't forget this is 86 * measured in 32-bit words, not bytes. 87 */ 88 u8 pci_dfl_cache_line_size __devinitdata = L1_CACHE_BYTES >> 2; 89 u8 pci_cache_line_size; 90 91 /** 92 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children 93 * @bus: pointer to PCI bus structure to search 94 * 95 * Given a PCI bus, returns the highest PCI bus number present in the set 96 * including the given PCI bus and its list of child PCI buses. 97 */ 98 unsigned char pci_bus_max_busnr(struct pci_bus* bus) 99 { 100 struct list_head *tmp; 101 unsigned char max, n; 102 103 max = bus->subordinate; 104 list_for_each(tmp, &bus->children) { 105 n = pci_bus_max_busnr(pci_bus_b(tmp)); 106 if(n > max) 107 max = n; 108 } 109 return max; 110 } 111 EXPORT_SYMBOL_GPL(pci_bus_max_busnr); 112 113 #ifdef CONFIG_HAS_IOMEM 114 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar) 115 { 116 /* 117 * Make sure the BAR is actually a memory resource, not an IO resource 118 */ 119 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { 120 WARN_ON(1); 121 return NULL; 122 } 123 return ioremap_nocache(pci_resource_start(pdev, bar), 124 pci_resource_len(pdev, bar)); 125 } 126 EXPORT_SYMBOL_GPL(pci_ioremap_bar); 127 #endif 128 129 #if 0 130 /** 131 * pci_max_busnr - returns maximum PCI bus number 132 * 133 * Returns the highest PCI bus number present in the system global list of 134 * PCI buses. 135 */ 136 unsigned char __devinit 137 pci_max_busnr(void) 138 { 139 struct pci_bus *bus = NULL; 140 unsigned char max, n; 141 142 max = 0; 143 while ((bus = pci_find_next_bus(bus)) != NULL) { 144 n = pci_bus_max_busnr(bus); 145 if(n > max) 146 max = n; 147 } 148 return max; 149 } 150 151 #endif /* 0 */ 152 153 #define PCI_FIND_CAP_TTL 48 154 155 static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn, 156 u8 pos, int cap, int *ttl) 157 { 158 u8 id; 159 160 while ((*ttl)--) { 161 pci_bus_read_config_byte(bus, devfn, pos, &pos); 162 if (pos < 0x40) 163 break; 164 pos &= ~3; 165 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID, 166 &id); 167 if (id == 0xff) 168 break; 169 if (id == cap) 170 return pos; 171 pos += PCI_CAP_LIST_NEXT; 172 } 173 return 0; 174 } 175 176 static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn, 177 u8 pos, int cap) 178 { 179 int ttl = PCI_FIND_CAP_TTL; 180 181 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl); 182 } 183 184 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap) 185 { 186 return __pci_find_next_cap(dev->bus, dev->devfn, 187 pos + PCI_CAP_LIST_NEXT, cap); 188 } 189 EXPORT_SYMBOL_GPL(pci_find_next_capability); 190 191 static int __pci_bus_find_cap_start(struct pci_bus *bus, 192 unsigned int devfn, u8 hdr_type) 193 { 194 u16 status; 195 196 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status); 197 if (!(status & PCI_STATUS_CAP_LIST)) 198 return 0; 199 200 switch (hdr_type) { 201 case PCI_HEADER_TYPE_NORMAL: 202 case PCI_HEADER_TYPE_BRIDGE: 203 return PCI_CAPABILITY_LIST; 204 case PCI_HEADER_TYPE_CARDBUS: 205 return PCI_CB_CAPABILITY_LIST; 206 default: 207 return 0; 208 } 209 210 return 0; 211 } 212 213 /** 214 * pci_find_capability - query for devices' capabilities 215 * @dev: PCI device to query 216 * @cap: capability code 217 * 218 * Tell if a device supports a given PCI capability. 219 * Returns the address of the requested capability structure within the 220 * device's PCI configuration space or 0 in case the device does not 221 * support it. Possible values for @cap: 222 * 223 * %PCI_CAP_ID_PM Power Management 224 * %PCI_CAP_ID_AGP Accelerated Graphics Port 225 * %PCI_CAP_ID_VPD Vital Product Data 226 * %PCI_CAP_ID_SLOTID Slot Identification 227 * %PCI_CAP_ID_MSI Message Signalled Interrupts 228 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap 229 * %PCI_CAP_ID_PCIX PCI-X 230 * %PCI_CAP_ID_EXP PCI Express 231 */ 232 int pci_find_capability(struct pci_dev *dev, int cap) 233 { 234 int pos; 235 236 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); 237 if (pos) 238 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap); 239 240 return pos; 241 } 242 243 /** 244 * pci_bus_find_capability - query for devices' capabilities 245 * @bus: the PCI bus to query 246 * @devfn: PCI device to query 247 * @cap: capability code 248 * 249 * Like pci_find_capability() but works for pci devices that do not have a 250 * pci_dev structure set up yet. 251 * 252 * Returns the address of the requested capability structure within the 253 * device's PCI configuration space or 0 in case the device does not 254 * support it. 255 */ 256 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap) 257 { 258 int pos; 259 u8 hdr_type; 260 261 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type); 262 263 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f); 264 if (pos) 265 pos = __pci_find_next_cap(bus, devfn, pos, cap); 266 267 return pos; 268 } 269 270 /** 271 * pci_find_ext_capability - Find an extended capability 272 * @dev: PCI device to query 273 * @cap: capability code 274 * 275 * Returns the address of the requested extended capability structure 276 * within the device's PCI configuration space or 0 if the device does 277 * not support it. Possible values for @cap: 278 * 279 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting 280 * %PCI_EXT_CAP_ID_VC Virtual Channel 281 * %PCI_EXT_CAP_ID_DSN Device Serial Number 282 * %PCI_EXT_CAP_ID_PWR Power Budgeting 283 */ 284 int pci_find_ext_capability(struct pci_dev *dev, int cap) 285 { 286 u32 header; 287 int ttl; 288 int pos = PCI_CFG_SPACE_SIZE; 289 290 /* minimum 8 bytes per capability */ 291 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; 292 293 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE) 294 return 0; 295 296 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) 297 return 0; 298 299 /* 300 * If we have no capabilities, this is indicated by cap ID, 301 * cap version and next pointer all being 0. 302 */ 303 if (header == 0) 304 return 0; 305 306 while (ttl-- > 0) { 307 if (PCI_EXT_CAP_ID(header) == cap) 308 return pos; 309 310 pos = PCI_EXT_CAP_NEXT(header); 311 if (pos < PCI_CFG_SPACE_SIZE) 312 break; 313 314 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) 315 break; 316 } 317 318 return 0; 319 } 320 EXPORT_SYMBOL_GPL(pci_find_ext_capability); 321 322 /** 323 * pci_bus_find_ext_capability - find an extended capability 324 * @bus: the PCI bus to query 325 * @devfn: PCI device to query 326 * @cap: capability code 327 * 328 * Like pci_find_ext_capability() but works for pci devices that do not have a 329 * pci_dev structure set up yet. 330 * 331 * Returns the address of the requested capability structure within the 332 * device's PCI configuration space or 0 in case the device does not 333 * support it. 334 */ 335 int pci_bus_find_ext_capability(struct pci_bus *bus, unsigned int devfn, 336 int cap) 337 { 338 u32 header; 339 int ttl; 340 int pos = PCI_CFG_SPACE_SIZE; 341 342 /* minimum 8 bytes per capability */ 343 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; 344 345 if (!pci_bus_read_config_dword(bus, devfn, pos, &header)) 346 return 0; 347 if (header == 0xffffffff || header == 0) 348 return 0; 349 350 while (ttl-- > 0) { 351 if (PCI_EXT_CAP_ID(header) == cap) 352 return pos; 353 354 pos = PCI_EXT_CAP_NEXT(header); 355 if (pos < PCI_CFG_SPACE_SIZE) 356 break; 357 358 if (!pci_bus_read_config_dword(bus, devfn, pos, &header)) 359 break; 360 } 361 362 return 0; 363 } 364 365 static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap) 366 { 367 int rc, ttl = PCI_FIND_CAP_TTL; 368 u8 cap, mask; 369 370 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST) 371 mask = HT_3BIT_CAP_MASK; 372 else 373 mask = HT_5BIT_CAP_MASK; 374 375 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos, 376 PCI_CAP_ID_HT, &ttl); 377 while (pos) { 378 rc = pci_read_config_byte(dev, pos + 3, &cap); 379 if (rc != PCIBIOS_SUCCESSFUL) 380 return 0; 381 382 if ((cap & mask) == ht_cap) 383 return pos; 384 385 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, 386 pos + PCI_CAP_LIST_NEXT, 387 PCI_CAP_ID_HT, &ttl); 388 } 389 390 return 0; 391 } 392 /** 393 * pci_find_next_ht_capability - query a device's Hypertransport capabilities 394 * @dev: PCI device to query 395 * @pos: Position from which to continue searching 396 * @ht_cap: Hypertransport capability code 397 * 398 * To be used in conjunction with pci_find_ht_capability() to search for 399 * all capabilities matching @ht_cap. @pos should always be a value returned 400 * from pci_find_ht_capability(). 401 * 402 * NB. To be 100% safe against broken PCI devices, the caller should take 403 * steps to avoid an infinite loop. 404 */ 405 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap) 406 { 407 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap); 408 } 409 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability); 410 411 /** 412 * pci_find_ht_capability - query a device's Hypertransport capabilities 413 * @dev: PCI device to query 414 * @ht_cap: Hypertransport capability code 415 * 416 * Tell if a device supports a given Hypertransport capability. 417 * Returns an address within the device's PCI configuration space 418 * or 0 in case the device does not support the request capability. 419 * The address points to the PCI capability, of type PCI_CAP_ID_HT, 420 * which has a Hypertransport capability matching @ht_cap. 421 */ 422 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap) 423 { 424 int pos; 425 426 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); 427 if (pos) 428 pos = __pci_find_next_ht_cap(dev, pos, ht_cap); 429 430 return pos; 431 } 432 EXPORT_SYMBOL_GPL(pci_find_ht_capability); 433 434 /** 435 * pci_find_parent_resource - return resource region of parent bus of given region 436 * @dev: PCI device structure contains resources to be searched 437 * @res: child resource record for which parent is sought 438 * 439 * For given resource region of given device, return the resource 440 * region of parent bus the given region is contained in or where 441 * it should be allocated from. 442 */ 443 struct resource * 444 pci_find_parent_resource(const struct pci_dev *dev, struct resource *res) 445 { 446 const struct pci_bus *bus = dev->bus; 447 int i; 448 struct resource *best = NULL, *r; 449 450 pci_bus_for_each_resource(bus, r, i) { 451 if (!r) 452 continue; 453 if (res->start && !(res->start >= r->start && res->end <= r->end)) 454 continue; /* Not contained */ 455 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM)) 456 continue; /* Wrong type */ 457 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH)) 458 return r; /* Exact match */ 459 /* We can't insert a non-prefetch resource inside a prefetchable parent .. */ 460 if (r->flags & IORESOURCE_PREFETCH) 461 continue; 462 /* .. but we can put a prefetchable resource inside a non-prefetchable one */ 463 if (!best) 464 best = r; 465 } 466 return best; 467 } 468 469 /** 470 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up) 471 * @dev: PCI device to have its BARs restored 472 * 473 * Restore the BAR values for a given device, so as to make it 474 * accessible by its driver. 475 */ 476 static void 477 pci_restore_bars(struct pci_dev *dev) 478 { 479 int i; 480 481 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) 482 pci_update_resource(dev, i); 483 } 484 485 static struct pci_platform_pm_ops *pci_platform_pm; 486 487 int pci_set_platform_pm(struct pci_platform_pm_ops *ops) 488 { 489 if (!ops->is_manageable || !ops->set_state || !ops->choose_state 490 || !ops->sleep_wake || !ops->can_wakeup) 491 return -EINVAL; 492 pci_platform_pm = ops; 493 return 0; 494 } 495 496 static inline bool platform_pci_power_manageable(struct pci_dev *dev) 497 { 498 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false; 499 } 500 501 static inline int platform_pci_set_power_state(struct pci_dev *dev, 502 pci_power_t t) 503 { 504 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS; 505 } 506 507 static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev) 508 { 509 return pci_platform_pm ? 510 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR; 511 } 512 513 static inline bool platform_pci_can_wakeup(struct pci_dev *dev) 514 { 515 return pci_platform_pm ? pci_platform_pm->can_wakeup(dev) : false; 516 } 517 518 static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable) 519 { 520 return pci_platform_pm ? 521 pci_platform_pm->sleep_wake(dev, enable) : -ENODEV; 522 } 523 524 static inline int platform_pci_run_wake(struct pci_dev *dev, bool enable) 525 { 526 return pci_platform_pm ? 527 pci_platform_pm->run_wake(dev, enable) : -ENODEV; 528 } 529 530 /** 531 * pci_raw_set_power_state - Use PCI PM registers to set the power state of 532 * given PCI device 533 * @dev: PCI device to handle. 534 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into. 535 * 536 * RETURN VALUE: 537 * -EINVAL if the requested state is invalid. 538 * -EIO if device does not support PCI PM or its PM capabilities register has a 539 * wrong version, or device doesn't support the requested state. 540 * 0 if device already is in the requested state. 541 * 0 if device's power state has been successfully changed. 542 */ 543 static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state) 544 { 545 u16 pmcsr; 546 bool need_restore = false; 547 548 /* Check if we're already there */ 549 if (dev->current_state == state) 550 return 0; 551 552 if (!dev->pm_cap) 553 return -EIO; 554 555 if (state < PCI_D0 || state > PCI_D3hot) 556 return -EINVAL; 557 558 /* Validate current state: 559 * Can enter D0 from any state, but if we can only go deeper 560 * to sleep if we're already in a low power state 561 */ 562 if (state != PCI_D0 && dev->current_state <= PCI_D3cold 563 && dev->current_state > state) { 564 dev_err(&dev->dev, "invalid power transition " 565 "(from state %d to %d)\n", dev->current_state, state); 566 return -EINVAL; 567 } 568 569 /* check if this device supports the desired state */ 570 if ((state == PCI_D1 && !dev->d1_support) 571 || (state == PCI_D2 && !dev->d2_support)) 572 return -EIO; 573 574 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); 575 576 /* If we're (effectively) in D3, force entire word to 0. 577 * This doesn't affect PME_Status, disables PME_En, and 578 * sets PowerState to 0. 579 */ 580 switch (dev->current_state) { 581 case PCI_D0: 582 case PCI_D1: 583 case PCI_D2: 584 pmcsr &= ~PCI_PM_CTRL_STATE_MASK; 585 pmcsr |= state; 586 break; 587 case PCI_D3hot: 588 case PCI_D3cold: 589 case PCI_UNKNOWN: /* Boot-up */ 590 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot 591 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET)) 592 need_restore = true; 593 /* Fall-through: force to D0 */ 594 default: 595 pmcsr = 0; 596 break; 597 } 598 599 /* enter specified state */ 600 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); 601 602 /* Mandatory power management transition delays */ 603 /* see PCI PM 1.1 5.6.1 table 18 */ 604 if (state == PCI_D3hot || dev->current_state == PCI_D3hot) 605 pci_dev_d3_sleep(dev); 606 else if (state == PCI_D2 || dev->current_state == PCI_D2) 607 udelay(PCI_PM_D2_DELAY); 608 609 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); 610 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); 611 if (dev->current_state != state && printk_ratelimit()) 612 dev_info(&dev->dev, "Refused to change power state, " 613 "currently in D%d\n", dev->current_state); 614 615 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT 616 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning 617 * from D3hot to D0 _may_ perform an internal reset, thereby 618 * going to "D0 Uninitialized" rather than "D0 Initialized". 619 * For example, at least some versions of the 3c905B and the 620 * 3c556B exhibit this behaviour. 621 * 622 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave 623 * devices in a D3hot state at boot. Consequently, we need to 624 * restore at least the BARs so that the device will be 625 * accessible to its driver. 626 */ 627 if (need_restore) 628 pci_restore_bars(dev); 629 630 if (dev->bus->self) 631 pcie_aspm_pm_state_change(dev->bus->self); 632 633 return 0; 634 } 635 636 /** 637 * pci_update_current_state - Read PCI power state of given device from its 638 * PCI PM registers and cache it 639 * @dev: PCI device to handle. 640 * @state: State to cache in case the device doesn't have the PM capability 641 */ 642 void pci_update_current_state(struct pci_dev *dev, pci_power_t state) 643 { 644 if (dev->pm_cap) { 645 u16 pmcsr; 646 647 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); 648 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); 649 } else { 650 dev->current_state = state; 651 } 652 } 653 654 /** 655 * pci_platform_power_transition - Use platform to change device power state 656 * @dev: PCI device to handle. 657 * @state: State to put the device into. 658 */ 659 static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state) 660 { 661 int error; 662 663 if (platform_pci_power_manageable(dev)) { 664 error = platform_pci_set_power_state(dev, state); 665 if (!error) 666 pci_update_current_state(dev, state); 667 } else { 668 error = -ENODEV; 669 /* Fall back to PCI_D0 if native PM is not supported */ 670 if (!dev->pm_cap) 671 dev->current_state = PCI_D0; 672 } 673 674 return error; 675 } 676 677 /** 678 * __pci_start_power_transition - Start power transition of a PCI device 679 * @dev: PCI device to handle. 680 * @state: State to put the device into. 681 */ 682 static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state) 683 { 684 if (state == PCI_D0) 685 pci_platform_power_transition(dev, PCI_D0); 686 } 687 688 /** 689 * __pci_complete_power_transition - Complete power transition of a PCI device 690 * @dev: PCI device to handle. 691 * @state: State to put the device into. 692 * 693 * This function should not be called directly by device drivers. 694 */ 695 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state) 696 { 697 return state >= PCI_D0 ? 698 pci_platform_power_transition(dev, state) : -EINVAL; 699 } 700 EXPORT_SYMBOL_GPL(__pci_complete_power_transition); 701 702 /** 703 * pci_set_power_state - Set the power state of a PCI device 704 * @dev: PCI device to handle. 705 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into. 706 * 707 * Transition a device to a new power state, using the platform firmware and/or 708 * the device's PCI PM registers. 709 * 710 * RETURN VALUE: 711 * -EINVAL if the requested state is invalid. 712 * -EIO if device does not support PCI PM or its PM capabilities register has a 713 * wrong version, or device doesn't support the requested state. 714 * 0 if device already is in the requested state. 715 * 0 if device's power state has been successfully changed. 716 */ 717 int pci_set_power_state(struct pci_dev *dev, pci_power_t state) 718 { 719 int error; 720 721 /* bound the state we're entering */ 722 if (state > PCI_D3hot) 723 state = PCI_D3hot; 724 else if (state < PCI_D0) 725 state = PCI_D0; 726 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev)) 727 /* 728 * If the device or the parent bridge do not support PCI PM, 729 * ignore the request if we're doing anything other than putting 730 * it into D0 (which would only happen on boot). 731 */ 732 return 0; 733 734 __pci_start_power_transition(dev, state); 735 736 /* This device is quirked not to be put into D3, so 737 don't put it in D3 */ 738 if (state == PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3)) 739 return 0; 740 741 error = pci_raw_set_power_state(dev, state); 742 743 if (!__pci_complete_power_transition(dev, state)) 744 error = 0; 745 /* 746 * When aspm_policy is "powersave" this call ensures 747 * that ASPM is configured. 748 */ 749 if (!error && dev->bus->self) 750 pcie_aspm_powersave_config_link(dev->bus->self); 751 752 return error; 753 } 754 755 /** 756 * pci_choose_state - Choose the power state of a PCI device 757 * @dev: PCI device to be suspended 758 * @state: target sleep state for the whole system. This is the value 759 * that is passed to suspend() function. 760 * 761 * Returns PCI power state suitable for given device and given system 762 * message. 763 */ 764 765 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state) 766 { 767 pci_power_t ret; 768 769 if (!pci_find_capability(dev, PCI_CAP_ID_PM)) 770 return PCI_D0; 771 772 ret = platform_pci_choose_state(dev); 773 if (ret != PCI_POWER_ERROR) 774 return ret; 775 776 switch (state.event) { 777 case PM_EVENT_ON: 778 return PCI_D0; 779 case PM_EVENT_FREEZE: 780 case PM_EVENT_PRETHAW: 781 /* REVISIT both freeze and pre-thaw "should" use D0 */ 782 case PM_EVENT_SUSPEND: 783 case PM_EVENT_HIBERNATE: 784 return PCI_D3hot; 785 default: 786 dev_info(&dev->dev, "unrecognized suspend event %d\n", 787 state.event); 788 BUG(); 789 } 790 return PCI_D0; 791 } 792 793 EXPORT_SYMBOL(pci_choose_state); 794 795 #define PCI_EXP_SAVE_REGS 7 796 797 #define pcie_cap_has_devctl(type, flags) 1 798 #define pcie_cap_has_lnkctl(type, flags) \ 799 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \ 800 (type == PCI_EXP_TYPE_ROOT_PORT || \ 801 type == PCI_EXP_TYPE_ENDPOINT || \ 802 type == PCI_EXP_TYPE_LEG_END)) 803 #define pcie_cap_has_sltctl(type, flags) \ 804 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \ 805 ((type == PCI_EXP_TYPE_ROOT_PORT) || \ 806 (type == PCI_EXP_TYPE_DOWNSTREAM && \ 807 (flags & PCI_EXP_FLAGS_SLOT)))) 808 #define pcie_cap_has_rtctl(type, flags) \ 809 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \ 810 (type == PCI_EXP_TYPE_ROOT_PORT || \ 811 type == PCI_EXP_TYPE_RC_EC)) 812 #define pcie_cap_has_devctl2(type, flags) \ 813 ((flags & PCI_EXP_FLAGS_VERS) > 1) 814 #define pcie_cap_has_lnkctl2(type, flags) \ 815 ((flags & PCI_EXP_FLAGS_VERS) > 1) 816 #define pcie_cap_has_sltctl2(type, flags) \ 817 ((flags & PCI_EXP_FLAGS_VERS) > 1) 818 819 static int pci_save_pcie_state(struct pci_dev *dev) 820 { 821 int pos, i = 0; 822 struct pci_cap_saved_state *save_state; 823 u16 *cap; 824 u16 flags; 825 826 pos = pci_pcie_cap(dev); 827 if (!pos) 828 return 0; 829 830 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); 831 if (!save_state) { 832 dev_err(&dev->dev, "buffer not found in %s\n", __func__); 833 return -ENOMEM; 834 } 835 cap = (u16 *)&save_state->cap.data[0]; 836 837 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags); 838 839 if (pcie_cap_has_devctl(dev->pcie_type, flags)) 840 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]); 841 if (pcie_cap_has_lnkctl(dev->pcie_type, flags)) 842 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]); 843 if (pcie_cap_has_sltctl(dev->pcie_type, flags)) 844 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]); 845 if (pcie_cap_has_rtctl(dev->pcie_type, flags)) 846 pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]); 847 if (pcie_cap_has_devctl2(dev->pcie_type, flags)) 848 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &cap[i++]); 849 if (pcie_cap_has_lnkctl2(dev->pcie_type, flags)) 850 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL2, &cap[i++]); 851 if (pcie_cap_has_sltctl2(dev->pcie_type, flags)) 852 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL2, &cap[i++]); 853 854 return 0; 855 } 856 857 static void pci_restore_pcie_state(struct pci_dev *dev) 858 { 859 int i = 0, pos; 860 struct pci_cap_saved_state *save_state; 861 u16 *cap; 862 u16 flags; 863 864 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); 865 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 866 if (!save_state || pos <= 0) 867 return; 868 cap = (u16 *)&save_state->cap.data[0]; 869 870 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags); 871 872 if (pcie_cap_has_devctl(dev->pcie_type, flags)) 873 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]); 874 if (pcie_cap_has_lnkctl(dev->pcie_type, flags)) 875 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]); 876 if (pcie_cap_has_sltctl(dev->pcie_type, flags)) 877 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]); 878 if (pcie_cap_has_rtctl(dev->pcie_type, flags)) 879 pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]); 880 if (pcie_cap_has_devctl2(dev->pcie_type, flags)) 881 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, cap[i++]); 882 if (pcie_cap_has_lnkctl2(dev->pcie_type, flags)) 883 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL2, cap[i++]); 884 if (pcie_cap_has_sltctl2(dev->pcie_type, flags)) 885 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL2, cap[i++]); 886 } 887 888 889 static int pci_save_pcix_state(struct pci_dev *dev) 890 { 891 int pos; 892 struct pci_cap_saved_state *save_state; 893 894 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); 895 if (pos <= 0) 896 return 0; 897 898 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); 899 if (!save_state) { 900 dev_err(&dev->dev, "buffer not found in %s\n", __func__); 901 return -ENOMEM; 902 } 903 904 pci_read_config_word(dev, pos + PCI_X_CMD, 905 (u16 *)save_state->cap.data); 906 907 return 0; 908 } 909 910 static void pci_restore_pcix_state(struct pci_dev *dev) 911 { 912 int i = 0, pos; 913 struct pci_cap_saved_state *save_state; 914 u16 *cap; 915 916 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); 917 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); 918 if (!save_state || pos <= 0) 919 return; 920 cap = (u16 *)&save_state->cap.data[0]; 921 922 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]); 923 } 924 925 926 /** 927 * pci_save_state - save the PCI configuration space of a device before suspending 928 * @dev: - PCI device that we're dealing with 929 */ 930 int 931 pci_save_state(struct pci_dev *dev) 932 { 933 int i; 934 /* XXX: 100% dword access ok here? */ 935 for (i = 0; i < 16; i++) 936 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]); 937 dev->state_saved = true; 938 if ((i = pci_save_pcie_state(dev)) != 0) 939 return i; 940 if ((i = pci_save_pcix_state(dev)) != 0) 941 return i; 942 return 0; 943 } 944 945 /** 946 * pci_restore_state - Restore the saved state of a PCI device 947 * @dev: - PCI device that we're dealing with 948 */ 949 void pci_restore_state(struct pci_dev *dev) 950 { 951 int i; 952 u32 val; 953 954 if (!dev->state_saved) 955 return; 956 957 /* PCI Express register must be restored first */ 958 pci_restore_pcie_state(dev); 959 960 /* 961 * The Base Address register should be programmed before the command 962 * register(s) 963 */ 964 for (i = 15; i >= 0; i--) { 965 pci_read_config_dword(dev, i * 4, &val); 966 if (val != dev->saved_config_space[i]) { 967 dev_printk(KERN_DEBUG, &dev->dev, "restoring config " 968 "space at offset %#x (was %#x, writing %#x)\n", 969 i, val, (int)dev->saved_config_space[i]); 970 pci_write_config_dword(dev,i * 4, 971 dev->saved_config_space[i]); 972 } 973 } 974 pci_restore_pcix_state(dev); 975 pci_restore_msi_state(dev); 976 pci_restore_iov_state(dev); 977 978 dev->state_saved = false; 979 } 980 981 struct pci_saved_state { 982 u32 config_space[16]; 983 struct pci_cap_saved_data cap[0]; 984 }; 985 986 /** 987 * pci_store_saved_state - Allocate and return an opaque struct containing 988 * the device saved state. 989 * @dev: PCI device that we're dealing with 990 * 991 * Rerturn NULL if no state or error. 992 */ 993 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev) 994 { 995 struct pci_saved_state *state; 996 struct pci_cap_saved_state *tmp; 997 struct pci_cap_saved_data *cap; 998 struct hlist_node *pos; 999 size_t size; 1000 1001 if (!dev->state_saved) 1002 return NULL; 1003 1004 size = sizeof(*state) + sizeof(struct pci_cap_saved_data); 1005 1006 hlist_for_each_entry(tmp, pos, &dev->saved_cap_space, next) 1007 size += sizeof(struct pci_cap_saved_data) + tmp->cap.size; 1008 1009 state = kzalloc(size, GFP_KERNEL); 1010 if (!state) 1011 return NULL; 1012 1013 memcpy(state->config_space, dev->saved_config_space, 1014 sizeof(state->config_space)); 1015 1016 cap = state->cap; 1017 hlist_for_each_entry(tmp, pos, &dev->saved_cap_space, next) { 1018 size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size; 1019 memcpy(cap, &tmp->cap, len); 1020 cap = (struct pci_cap_saved_data *)((u8 *)cap + len); 1021 } 1022 /* Empty cap_save terminates list */ 1023 1024 return state; 1025 } 1026 EXPORT_SYMBOL_GPL(pci_store_saved_state); 1027 1028 /** 1029 * pci_load_saved_state - Reload the provided save state into struct pci_dev. 1030 * @dev: PCI device that we're dealing with 1031 * @state: Saved state returned from pci_store_saved_state() 1032 */ 1033 int pci_load_saved_state(struct pci_dev *dev, struct pci_saved_state *state) 1034 { 1035 struct pci_cap_saved_data *cap; 1036 1037 dev->state_saved = false; 1038 1039 if (!state) 1040 return 0; 1041 1042 memcpy(dev->saved_config_space, state->config_space, 1043 sizeof(state->config_space)); 1044 1045 cap = state->cap; 1046 while (cap->size) { 1047 struct pci_cap_saved_state *tmp; 1048 1049 tmp = pci_find_saved_cap(dev, cap->cap_nr); 1050 if (!tmp || tmp->cap.size != cap->size) 1051 return -EINVAL; 1052 1053 memcpy(tmp->cap.data, cap->data, tmp->cap.size); 1054 cap = (struct pci_cap_saved_data *)((u8 *)cap + 1055 sizeof(struct pci_cap_saved_data) + cap->size); 1056 } 1057 1058 dev->state_saved = true; 1059 return 0; 1060 } 1061 EXPORT_SYMBOL_GPL(pci_load_saved_state); 1062 1063 /** 1064 * pci_load_and_free_saved_state - Reload the save state pointed to by state, 1065 * and free the memory allocated for it. 1066 * @dev: PCI device that we're dealing with 1067 * @state: Pointer to saved state returned from pci_store_saved_state() 1068 */ 1069 int pci_load_and_free_saved_state(struct pci_dev *dev, 1070 struct pci_saved_state **state) 1071 { 1072 int ret = pci_load_saved_state(dev, *state); 1073 kfree(*state); 1074 *state = NULL; 1075 return ret; 1076 } 1077 EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state); 1078 1079 static int do_pci_enable_device(struct pci_dev *dev, int bars) 1080 { 1081 int err; 1082 1083 err = pci_set_power_state(dev, PCI_D0); 1084 if (err < 0 && err != -EIO) 1085 return err; 1086 err = pcibios_enable_device(dev, bars); 1087 if (err < 0) 1088 return err; 1089 pci_fixup_device(pci_fixup_enable, dev); 1090 1091 return 0; 1092 } 1093 1094 /** 1095 * pci_reenable_device - Resume abandoned device 1096 * @dev: PCI device to be resumed 1097 * 1098 * Note this function is a backend of pci_default_resume and is not supposed 1099 * to be called by normal code, write proper resume handler and use it instead. 1100 */ 1101 int pci_reenable_device(struct pci_dev *dev) 1102 { 1103 if (pci_is_enabled(dev)) 1104 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1); 1105 return 0; 1106 } 1107 1108 static int __pci_enable_device_flags(struct pci_dev *dev, 1109 resource_size_t flags) 1110 { 1111 int err; 1112 int i, bars = 0; 1113 1114 /* 1115 * Power state could be unknown at this point, either due to a fresh 1116 * boot or a device removal call. So get the current power state 1117 * so that things like MSI message writing will behave as expected 1118 * (e.g. if the device really is in D0 at enable time). 1119 */ 1120 if (dev->pm_cap) { 1121 u16 pmcsr; 1122 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); 1123 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); 1124 } 1125 1126 if (atomic_add_return(1, &dev->enable_cnt) > 1) 1127 return 0; /* already enabled */ 1128 1129 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) 1130 if (dev->resource[i].flags & flags) 1131 bars |= (1 << i); 1132 1133 err = do_pci_enable_device(dev, bars); 1134 if (err < 0) 1135 atomic_dec(&dev->enable_cnt); 1136 return err; 1137 } 1138 1139 /** 1140 * pci_enable_device_io - Initialize a device for use with IO space 1141 * @dev: PCI device to be initialized 1142 * 1143 * Initialize device before it's used by a driver. Ask low-level code 1144 * to enable I/O resources. Wake up the device if it was suspended. 1145 * Beware, this function can fail. 1146 */ 1147 int pci_enable_device_io(struct pci_dev *dev) 1148 { 1149 return __pci_enable_device_flags(dev, IORESOURCE_IO); 1150 } 1151 1152 /** 1153 * pci_enable_device_mem - Initialize a device for use with Memory space 1154 * @dev: PCI device to be initialized 1155 * 1156 * Initialize device before it's used by a driver. Ask low-level code 1157 * to enable Memory resources. Wake up the device if it was suspended. 1158 * Beware, this function can fail. 1159 */ 1160 int pci_enable_device_mem(struct pci_dev *dev) 1161 { 1162 return __pci_enable_device_flags(dev, IORESOURCE_MEM); 1163 } 1164 1165 /** 1166 * pci_enable_device - Initialize device before it's used by a driver. 1167 * @dev: PCI device to be initialized 1168 * 1169 * Initialize device before it's used by a driver. Ask low-level code 1170 * to enable I/O and memory. Wake up the device if it was suspended. 1171 * Beware, this function can fail. 1172 * 1173 * Note we don't actually enable the device many times if we call 1174 * this function repeatedly (we just increment the count). 1175 */ 1176 int pci_enable_device(struct pci_dev *dev) 1177 { 1178 return __pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO); 1179 } 1180 1181 /* 1182 * Managed PCI resources. This manages device on/off, intx/msi/msix 1183 * on/off and BAR regions. pci_dev itself records msi/msix status, so 1184 * there's no need to track it separately. pci_devres is initialized 1185 * when a device is enabled using managed PCI device enable interface. 1186 */ 1187 struct pci_devres { 1188 unsigned int enabled:1; 1189 unsigned int pinned:1; 1190 unsigned int orig_intx:1; 1191 unsigned int restore_intx:1; 1192 u32 region_mask; 1193 }; 1194 1195 static void pcim_release(struct device *gendev, void *res) 1196 { 1197 struct pci_dev *dev = container_of(gendev, struct pci_dev, dev); 1198 struct pci_devres *this = res; 1199 int i; 1200 1201 if (dev->msi_enabled) 1202 pci_disable_msi(dev); 1203 if (dev->msix_enabled) 1204 pci_disable_msix(dev); 1205 1206 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) 1207 if (this->region_mask & (1 << i)) 1208 pci_release_region(dev, i); 1209 1210 if (this->restore_intx) 1211 pci_intx(dev, this->orig_intx); 1212 1213 if (this->enabled && !this->pinned) 1214 pci_disable_device(dev); 1215 } 1216 1217 static struct pci_devres * get_pci_dr(struct pci_dev *pdev) 1218 { 1219 struct pci_devres *dr, *new_dr; 1220 1221 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL); 1222 if (dr) 1223 return dr; 1224 1225 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL); 1226 if (!new_dr) 1227 return NULL; 1228 return devres_get(&pdev->dev, new_dr, NULL, NULL); 1229 } 1230 1231 static struct pci_devres * find_pci_dr(struct pci_dev *pdev) 1232 { 1233 if (pci_is_managed(pdev)) 1234 return devres_find(&pdev->dev, pcim_release, NULL, NULL); 1235 return NULL; 1236 } 1237 1238 /** 1239 * pcim_enable_device - Managed pci_enable_device() 1240 * @pdev: PCI device to be initialized 1241 * 1242 * Managed pci_enable_device(). 1243 */ 1244 int pcim_enable_device(struct pci_dev *pdev) 1245 { 1246 struct pci_devres *dr; 1247 int rc; 1248 1249 dr = get_pci_dr(pdev); 1250 if (unlikely(!dr)) 1251 return -ENOMEM; 1252 if (dr->enabled) 1253 return 0; 1254 1255 rc = pci_enable_device(pdev); 1256 if (!rc) { 1257 pdev->is_managed = 1; 1258 dr->enabled = 1; 1259 } 1260 return rc; 1261 } 1262 1263 /** 1264 * pcim_pin_device - Pin managed PCI device 1265 * @pdev: PCI device to pin 1266 * 1267 * Pin managed PCI device @pdev. Pinned device won't be disabled on 1268 * driver detach. @pdev must have been enabled with 1269 * pcim_enable_device(). 1270 */ 1271 void pcim_pin_device(struct pci_dev *pdev) 1272 { 1273 struct pci_devres *dr; 1274 1275 dr = find_pci_dr(pdev); 1276 WARN_ON(!dr || !dr->enabled); 1277 if (dr) 1278 dr->pinned = 1; 1279 } 1280 1281 /** 1282 * pcibios_disable_device - disable arch specific PCI resources for device dev 1283 * @dev: the PCI device to disable 1284 * 1285 * Disables architecture specific PCI resources for the device. This 1286 * is the default implementation. Architecture implementations can 1287 * override this. 1288 */ 1289 void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {} 1290 1291 static void do_pci_disable_device(struct pci_dev *dev) 1292 { 1293 u16 pci_command; 1294 1295 pci_read_config_word(dev, PCI_COMMAND, &pci_command); 1296 if (pci_command & PCI_COMMAND_MASTER) { 1297 pci_command &= ~PCI_COMMAND_MASTER; 1298 pci_write_config_word(dev, PCI_COMMAND, pci_command); 1299 } 1300 1301 pcibios_disable_device(dev); 1302 } 1303 1304 /** 1305 * pci_disable_enabled_device - Disable device without updating enable_cnt 1306 * @dev: PCI device to disable 1307 * 1308 * NOTE: This function is a backend of PCI power management routines and is 1309 * not supposed to be called drivers. 1310 */ 1311 void pci_disable_enabled_device(struct pci_dev *dev) 1312 { 1313 if (pci_is_enabled(dev)) 1314 do_pci_disable_device(dev); 1315 } 1316 1317 /** 1318 * pci_disable_device - Disable PCI device after use 1319 * @dev: PCI device to be disabled 1320 * 1321 * Signal to the system that the PCI device is not in use by the system 1322 * anymore. This only involves disabling PCI bus-mastering, if active. 1323 * 1324 * Note we don't actually disable the device until all callers of 1325 * pci_enable_device() have called pci_disable_device(). 1326 */ 1327 void 1328 pci_disable_device(struct pci_dev *dev) 1329 { 1330 struct pci_devres *dr; 1331 1332 dr = find_pci_dr(dev); 1333 if (dr) 1334 dr->enabled = 0; 1335 1336 if (atomic_sub_return(1, &dev->enable_cnt) != 0) 1337 return; 1338 1339 do_pci_disable_device(dev); 1340 1341 dev->is_busmaster = 0; 1342 } 1343 1344 /** 1345 * pcibios_set_pcie_reset_state - set reset state for device dev 1346 * @dev: the PCIe device reset 1347 * @state: Reset state to enter into 1348 * 1349 * 1350 * Sets the PCIe reset state for the device. This is the default 1351 * implementation. Architecture implementations can override this. 1352 */ 1353 int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev, 1354 enum pcie_reset_state state) 1355 { 1356 return -EINVAL; 1357 } 1358 1359 /** 1360 * pci_set_pcie_reset_state - set reset state for device dev 1361 * @dev: the PCIe device reset 1362 * @state: Reset state to enter into 1363 * 1364 * 1365 * Sets the PCI reset state for the device. 1366 */ 1367 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state) 1368 { 1369 return pcibios_set_pcie_reset_state(dev, state); 1370 } 1371 1372 /** 1373 * pci_check_pme_status - Check if given device has generated PME. 1374 * @dev: Device to check. 1375 * 1376 * Check the PME status of the device and if set, clear it and clear PME enable 1377 * (if set). Return 'true' if PME status and PME enable were both set or 1378 * 'false' otherwise. 1379 */ 1380 bool pci_check_pme_status(struct pci_dev *dev) 1381 { 1382 int pmcsr_pos; 1383 u16 pmcsr; 1384 bool ret = false; 1385 1386 if (!dev->pm_cap) 1387 return false; 1388 1389 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL; 1390 pci_read_config_word(dev, pmcsr_pos, &pmcsr); 1391 if (!(pmcsr & PCI_PM_CTRL_PME_STATUS)) 1392 return false; 1393 1394 /* Clear PME status. */ 1395 pmcsr |= PCI_PM_CTRL_PME_STATUS; 1396 if (pmcsr & PCI_PM_CTRL_PME_ENABLE) { 1397 /* Disable PME to avoid interrupt flood. */ 1398 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE; 1399 ret = true; 1400 } 1401 1402 pci_write_config_word(dev, pmcsr_pos, pmcsr); 1403 1404 return ret; 1405 } 1406 1407 /** 1408 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set. 1409 * @dev: Device to handle. 1410 * @pme_poll_reset: Whether or not to reset the device's pme_poll flag. 1411 * 1412 * Check if @dev has generated PME and queue a resume request for it in that 1413 * case. 1414 */ 1415 static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset) 1416 { 1417 if (pme_poll_reset && dev->pme_poll) 1418 dev->pme_poll = false; 1419 1420 if (pci_check_pme_status(dev)) { 1421 pci_wakeup_event(dev); 1422 pm_request_resume(&dev->dev); 1423 } 1424 return 0; 1425 } 1426 1427 /** 1428 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary. 1429 * @bus: Top bus of the subtree to walk. 1430 */ 1431 void pci_pme_wakeup_bus(struct pci_bus *bus) 1432 { 1433 if (bus) 1434 pci_walk_bus(bus, pci_pme_wakeup, (void *)true); 1435 } 1436 1437 /** 1438 * pci_pme_capable - check the capability of PCI device to generate PME# 1439 * @dev: PCI device to handle. 1440 * @state: PCI state from which device will issue PME#. 1441 */ 1442 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state) 1443 { 1444 if (!dev->pm_cap) 1445 return false; 1446 1447 return !!(dev->pme_support & (1 << state)); 1448 } 1449 1450 static void pci_pme_list_scan(struct work_struct *work) 1451 { 1452 struct pci_pme_device *pme_dev, *n; 1453 1454 mutex_lock(&pci_pme_list_mutex); 1455 if (!list_empty(&pci_pme_list)) { 1456 list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) { 1457 if (pme_dev->dev->pme_poll) { 1458 pci_pme_wakeup(pme_dev->dev, NULL); 1459 } else { 1460 list_del(&pme_dev->list); 1461 kfree(pme_dev); 1462 } 1463 } 1464 if (!list_empty(&pci_pme_list)) 1465 schedule_delayed_work(&pci_pme_work, 1466 msecs_to_jiffies(PME_TIMEOUT)); 1467 } 1468 mutex_unlock(&pci_pme_list_mutex); 1469 } 1470 1471 /** 1472 * pci_pme_active - enable or disable PCI device's PME# function 1473 * @dev: PCI device to handle. 1474 * @enable: 'true' to enable PME# generation; 'false' to disable it. 1475 * 1476 * The caller must verify that the device is capable of generating PME# before 1477 * calling this function with @enable equal to 'true'. 1478 */ 1479 void pci_pme_active(struct pci_dev *dev, bool enable) 1480 { 1481 u16 pmcsr; 1482 1483 if (!dev->pm_cap) 1484 return; 1485 1486 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); 1487 /* Clear PME_Status by writing 1 to it and enable PME# */ 1488 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE; 1489 if (!enable) 1490 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE; 1491 1492 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); 1493 1494 /* PCI (as opposed to PCIe) PME requires that the device have 1495 its PME# line hooked up correctly. Not all hardware vendors 1496 do this, so the PME never gets delivered and the device 1497 remains asleep. The easiest way around this is to 1498 periodically walk the list of suspended devices and check 1499 whether any have their PME flag set. The assumption is that 1500 we'll wake up often enough anyway that this won't be a huge 1501 hit, and the power savings from the devices will still be a 1502 win. */ 1503 1504 if (dev->pme_poll) { 1505 struct pci_pme_device *pme_dev; 1506 if (enable) { 1507 pme_dev = kmalloc(sizeof(struct pci_pme_device), 1508 GFP_KERNEL); 1509 if (!pme_dev) 1510 goto out; 1511 pme_dev->dev = dev; 1512 mutex_lock(&pci_pme_list_mutex); 1513 list_add(&pme_dev->list, &pci_pme_list); 1514 if (list_is_singular(&pci_pme_list)) 1515 schedule_delayed_work(&pci_pme_work, 1516 msecs_to_jiffies(PME_TIMEOUT)); 1517 mutex_unlock(&pci_pme_list_mutex); 1518 } else { 1519 mutex_lock(&pci_pme_list_mutex); 1520 list_for_each_entry(pme_dev, &pci_pme_list, list) { 1521 if (pme_dev->dev == dev) { 1522 list_del(&pme_dev->list); 1523 kfree(pme_dev); 1524 break; 1525 } 1526 } 1527 mutex_unlock(&pci_pme_list_mutex); 1528 } 1529 } 1530 1531 out: 1532 dev_printk(KERN_DEBUG, &dev->dev, "PME# %s\n", 1533 enable ? "enabled" : "disabled"); 1534 } 1535 1536 /** 1537 * __pci_enable_wake - enable PCI device as wakeup event source 1538 * @dev: PCI device affected 1539 * @state: PCI state from which device will issue wakeup events 1540 * @runtime: True if the events are to be generated at run time 1541 * @enable: True to enable event generation; false to disable 1542 * 1543 * This enables the device as a wakeup event source, or disables it. 1544 * When such events involves platform-specific hooks, those hooks are 1545 * called automatically by this routine. 1546 * 1547 * Devices with legacy power management (no standard PCI PM capabilities) 1548 * always require such platform hooks. 1549 * 1550 * RETURN VALUE: 1551 * 0 is returned on success 1552 * -EINVAL is returned if device is not supposed to wake up the system 1553 * Error code depending on the platform is returned if both the platform and 1554 * the native mechanism fail to enable the generation of wake-up events 1555 */ 1556 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, 1557 bool runtime, bool enable) 1558 { 1559 int ret = 0; 1560 1561 if (enable && !runtime && !device_may_wakeup(&dev->dev)) 1562 return -EINVAL; 1563 1564 /* Don't do the same thing twice in a row for one device. */ 1565 if (!!enable == !!dev->wakeup_prepared) 1566 return 0; 1567 1568 /* 1569 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don 1570 * Anderson we should be doing PME# wake enable followed by ACPI wake 1571 * enable. To disable wake-up we call the platform first, for symmetry. 1572 */ 1573 1574 if (enable) { 1575 int error; 1576 1577 if (pci_pme_capable(dev, state)) 1578 pci_pme_active(dev, true); 1579 else 1580 ret = 1; 1581 error = runtime ? platform_pci_run_wake(dev, true) : 1582 platform_pci_sleep_wake(dev, true); 1583 if (ret) 1584 ret = error; 1585 if (!ret) 1586 dev->wakeup_prepared = true; 1587 } else { 1588 if (runtime) 1589 platform_pci_run_wake(dev, false); 1590 else 1591 platform_pci_sleep_wake(dev, false); 1592 pci_pme_active(dev, false); 1593 dev->wakeup_prepared = false; 1594 } 1595 1596 return ret; 1597 } 1598 EXPORT_SYMBOL(__pci_enable_wake); 1599 1600 /** 1601 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold 1602 * @dev: PCI device to prepare 1603 * @enable: True to enable wake-up event generation; false to disable 1604 * 1605 * Many drivers want the device to wake up the system from D3_hot or D3_cold 1606 * and this function allows them to set that up cleanly - pci_enable_wake() 1607 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI 1608 * ordering constraints. 1609 * 1610 * This function only returns error code if the device is not capable of 1611 * generating PME# from both D3_hot and D3_cold, and the platform is unable to 1612 * enable wake-up power for it. 1613 */ 1614 int pci_wake_from_d3(struct pci_dev *dev, bool enable) 1615 { 1616 return pci_pme_capable(dev, PCI_D3cold) ? 1617 pci_enable_wake(dev, PCI_D3cold, enable) : 1618 pci_enable_wake(dev, PCI_D3hot, enable); 1619 } 1620 1621 /** 1622 * pci_target_state - find an appropriate low power state for a given PCI dev 1623 * @dev: PCI device 1624 * 1625 * Use underlying platform code to find a supported low power state for @dev. 1626 * If the platform can't manage @dev, return the deepest state from which it 1627 * can generate wake events, based on any available PME info. 1628 */ 1629 pci_power_t pci_target_state(struct pci_dev *dev) 1630 { 1631 pci_power_t target_state = PCI_D3hot; 1632 1633 if (platform_pci_power_manageable(dev)) { 1634 /* 1635 * Call the platform to choose the target state of the device 1636 * and enable wake-up from this state if supported. 1637 */ 1638 pci_power_t state = platform_pci_choose_state(dev); 1639 1640 switch (state) { 1641 case PCI_POWER_ERROR: 1642 case PCI_UNKNOWN: 1643 break; 1644 case PCI_D1: 1645 case PCI_D2: 1646 if (pci_no_d1d2(dev)) 1647 break; 1648 default: 1649 target_state = state; 1650 } 1651 } else if (!dev->pm_cap) { 1652 target_state = PCI_D0; 1653 } else if (device_may_wakeup(&dev->dev)) { 1654 /* 1655 * Find the deepest state from which the device can generate 1656 * wake-up events, make it the target state and enable device 1657 * to generate PME#. 1658 */ 1659 if (dev->pme_support) { 1660 while (target_state 1661 && !(dev->pme_support & (1 << target_state))) 1662 target_state--; 1663 } 1664 } 1665 1666 return target_state; 1667 } 1668 1669 /** 1670 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state 1671 * @dev: Device to handle. 1672 * 1673 * Choose the power state appropriate for the device depending on whether 1674 * it can wake up the system and/or is power manageable by the platform 1675 * (PCI_D3hot is the default) and put the device into that state. 1676 */ 1677 int pci_prepare_to_sleep(struct pci_dev *dev) 1678 { 1679 pci_power_t target_state = pci_target_state(dev); 1680 int error; 1681 1682 if (target_state == PCI_POWER_ERROR) 1683 return -EIO; 1684 1685 pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev)); 1686 1687 error = pci_set_power_state(dev, target_state); 1688 1689 if (error) 1690 pci_enable_wake(dev, target_state, false); 1691 1692 return error; 1693 } 1694 1695 /** 1696 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state 1697 * @dev: Device to handle. 1698 * 1699 * Disable device's system wake-up capability and put it into D0. 1700 */ 1701 int pci_back_from_sleep(struct pci_dev *dev) 1702 { 1703 pci_enable_wake(dev, PCI_D0, false); 1704 return pci_set_power_state(dev, PCI_D0); 1705 } 1706 1707 /** 1708 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend. 1709 * @dev: PCI device being suspended. 1710 * 1711 * Prepare @dev to generate wake-up events at run time and put it into a low 1712 * power state. 1713 */ 1714 int pci_finish_runtime_suspend(struct pci_dev *dev) 1715 { 1716 pci_power_t target_state = pci_target_state(dev); 1717 int error; 1718 1719 if (target_state == PCI_POWER_ERROR) 1720 return -EIO; 1721 1722 __pci_enable_wake(dev, target_state, true, pci_dev_run_wake(dev)); 1723 1724 error = pci_set_power_state(dev, target_state); 1725 1726 if (error) 1727 __pci_enable_wake(dev, target_state, true, false); 1728 1729 return error; 1730 } 1731 1732 /** 1733 * pci_dev_run_wake - Check if device can generate run-time wake-up events. 1734 * @dev: Device to check. 1735 * 1736 * Return true if the device itself is cabable of generating wake-up events 1737 * (through the platform or using the native PCIe PME) or if the device supports 1738 * PME and one of its upstream bridges can generate wake-up events. 1739 */ 1740 bool pci_dev_run_wake(struct pci_dev *dev) 1741 { 1742 struct pci_bus *bus = dev->bus; 1743 1744 if (device_run_wake(&dev->dev)) 1745 return true; 1746 1747 if (!dev->pme_support) 1748 return false; 1749 1750 while (bus->parent) { 1751 struct pci_dev *bridge = bus->self; 1752 1753 if (device_run_wake(&bridge->dev)) 1754 return true; 1755 1756 bus = bus->parent; 1757 } 1758 1759 /* We have reached the root bus. */ 1760 if (bus->bridge) 1761 return device_run_wake(bus->bridge); 1762 1763 return false; 1764 } 1765 EXPORT_SYMBOL_GPL(pci_dev_run_wake); 1766 1767 /** 1768 * pci_pm_init - Initialize PM functions of given PCI device 1769 * @dev: PCI device to handle. 1770 */ 1771 void pci_pm_init(struct pci_dev *dev) 1772 { 1773 int pm; 1774 u16 pmc; 1775 1776 pm_runtime_forbid(&dev->dev); 1777 device_enable_async_suspend(&dev->dev); 1778 dev->wakeup_prepared = false; 1779 1780 dev->pm_cap = 0; 1781 1782 /* find PCI PM capability in list */ 1783 pm = pci_find_capability(dev, PCI_CAP_ID_PM); 1784 if (!pm) 1785 return; 1786 /* Check device's ability to generate PME# */ 1787 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc); 1788 1789 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) { 1790 dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n", 1791 pmc & PCI_PM_CAP_VER_MASK); 1792 return; 1793 } 1794 1795 dev->pm_cap = pm; 1796 dev->d3_delay = PCI_PM_D3_WAIT; 1797 1798 dev->d1_support = false; 1799 dev->d2_support = false; 1800 if (!pci_no_d1d2(dev)) { 1801 if (pmc & PCI_PM_CAP_D1) 1802 dev->d1_support = true; 1803 if (pmc & PCI_PM_CAP_D2) 1804 dev->d2_support = true; 1805 1806 if (dev->d1_support || dev->d2_support) 1807 dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n", 1808 dev->d1_support ? " D1" : "", 1809 dev->d2_support ? " D2" : ""); 1810 } 1811 1812 pmc &= PCI_PM_CAP_PME_MASK; 1813 if (pmc) { 1814 dev_printk(KERN_DEBUG, &dev->dev, 1815 "PME# supported from%s%s%s%s%s\n", 1816 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "", 1817 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "", 1818 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "", 1819 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "", 1820 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : ""); 1821 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT; 1822 dev->pme_poll = true; 1823 /* 1824 * Make device's PM flags reflect the wake-up capability, but 1825 * let the user space enable it to wake up the system as needed. 1826 */ 1827 device_set_wakeup_capable(&dev->dev, true); 1828 /* Disable the PME# generation functionality */ 1829 pci_pme_active(dev, false); 1830 } else { 1831 dev->pme_support = 0; 1832 } 1833 } 1834 1835 /** 1836 * platform_pci_wakeup_init - init platform wakeup if present 1837 * @dev: PCI device 1838 * 1839 * Some devices don't have PCI PM caps but can still generate wakeup 1840 * events through platform methods (like ACPI events). If @dev supports 1841 * platform wakeup events, set the device flag to indicate as much. This 1842 * may be redundant if the device also supports PCI PM caps, but double 1843 * initialization should be safe in that case. 1844 */ 1845 void platform_pci_wakeup_init(struct pci_dev *dev) 1846 { 1847 if (!platform_pci_can_wakeup(dev)) 1848 return; 1849 1850 device_set_wakeup_capable(&dev->dev, true); 1851 platform_pci_sleep_wake(dev, false); 1852 } 1853 1854 /** 1855 * pci_add_save_buffer - allocate buffer for saving given capability registers 1856 * @dev: the PCI device 1857 * @cap: the capability to allocate the buffer for 1858 * @size: requested size of the buffer 1859 */ 1860 static int pci_add_cap_save_buffer( 1861 struct pci_dev *dev, char cap, unsigned int size) 1862 { 1863 int pos; 1864 struct pci_cap_saved_state *save_state; 1865 1866 pos = pci_find_capability(dev, cap); 1867 if (pos <= 0) 1868 return 0; 1869 1870 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL); 1871 if (!save_state) 1872 return -ENOMEM; 1873 1874 save_state->cap.cap_nr = cap; 1875 save_state->cap.size = size; 1876 pci_add_saved_cap(dev, save_state); 1877 1878 return 0; 1879 } 1880 1881 /** 1882 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities 1883 * @dev: the PCI device 1884 */ 1885 void pci_allocate_cap_save_buffers(struct pci_dev *dev) 1886 { 1887 int error; 1888 1889 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP, 1890 PCI_EXP_SAVE_REGS * sizeof(u16)); 1891 if (error) 1892 dev_err(&dev->dev, 1893 "unable to preallocate PCI Express save buffer\n"); 1894 1895 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16)); 1896 if (error) 1897 dev_err(&dev->dev, 1898 "unable to preallocate PCI-X save buffer\n"); 1899 } 1900 1901 /** 1902 * pci_enable_ari - enable ARI forwarding if hardware support it 1903 * @dev: the PCI device 1904 */ 1905 void pci_enable_ari(struct pci_dev *dev) 1906 { 1907 int pos; 1908 u32 cap; 1909 u16 flags, ctrl; 1910 struct pci_dev *bridge; 1911 1912 if (!pci_is_pcie(dev) || dev->devfn) 1913 return; 1914 1915 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI); 1916 if (!pos) 1917 return; 1918 1919 bridge = dev->bus->self; 1920 if (!bridge || !pci_is_pcie(bridge)) 1921 return; 1922 1923 pos = pci_pcie_cap(bridge); 1924 if (!pos) 1925 return; 1926 1927 /* ARI is a PCIe v2 feature */ 1928 pci_read_config_word(bridge, pos + PCI_EXP_FLAGS, &flags); 1929 if ((flags & PCI_EXP_FLAGS_VERS) < 2) 1930 return; 1931 1932 pci_read_config_dword(bridge, pos + PCI_EXP_DEVCAP2, &cap); 1933 if (!(cap & PCI_EXP_DEVCAP2_ARI)) 1934 return; 1935 1936 pci_read_config_word(bridge, pos + PCI_EXP_DEVCTL2, &ctrl); 1937 ctrl |= PCI_EXP_DEVCTL2_ARI; 1938 pci_write_config_word(bridge, pos + PCI_EXP_DEVCTL2, ctrl); 1939 1940 bridge->ari_enabled = 1; 1941 } 1942 1943 /** 1944 * pci_enable_ido - enable ID-based ordering on a device 1945 * @dev: the PCI device 1946 * @type: which types of IDO to enable 1947 * 1948 * Enable ID-based ordering on @dev. @type can contain the bits 1949 * %PCI_EXP_IDO_REQUEST and/or %PCI_EXP_IDO_COMPLETION to indicate 1950 * which types of transactions are allowed to be re-ordered. 1951 */ 1952 void pci_enable_ido(struct pci_dev *dev, unsigned long type) 1953 { 1954 int pos; 1955 u16 ctrl; 1956 1957 pos = pci_pcie_cap(dev); 1958 if (!pos) 1959 return; 1960 1961 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl); 1962 if (type & PCI_EXP_IDO_REQUEST) 1963 ctrl |= PCI_EXP_IDO_REQ_EN; 1964 if (type & PCI_EXP_IDO_COMPLETION) 1965 ctrl |= PCI_EXP_IDO_CMP_EN; 1966 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl); 1967 } 1968 EXPORT_SYMBOL(pci_enable_ido); 1969 1970 /** 1971 * pci_disable_ido - disable ID-based ordering on a device 1972 * @dev: the PCI device 1973 * @type: which types of IDO to disable 1974 */ 1975 void pci_disable_ido(struct pci_dev *dev, unsigned long type) 1976 { 1977 int pos; 1978 u16 ctrl; 1979 1980 if (!pci_is_pcie(dev)) 1981 return; 1982 1983 pos = pci_pcie_cap(dev); 1984 if (!pos) 1985 return; 1986 1987 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl); 1988 if (type & PCI_EXP_IDO_REQUEST) 1989 ctrl &= ~PCI_EXP_IDO_REQ_EN; 1990 if (type & PCI_EXP_IDO_COMPLETION) 1991 ctrl &= ~PCI_EXP_IDO_CMP_EN; 1992 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl); 1993 } 1994 EXPORT_SYMBOL(pci_disable_ido); 1995 1996 /** 1997 * pci_enable_obff - enable optimized buffer flush/fill 1998 * @dev: PCI device 1999 * @type: type of signaling to use 2000 * 2001 * Try to enable @type OBFF signaling on @dev. It will try using WAKE# 2002 * signaling if possible, falling back to message signaling only if 2003 * WAKE# isn't supported. @type should indicate whether the PCIe link 2004 * be brought out of L0s or L1 to send the message. It should be either 2005 * %PCI_EXP_OBFF_SIGNAL_ALWAYS or %PCI_OBFF_SIGNAL_L0. 2006 * 2007 * If your device can benefit from receiving all messages, even at the 2008 * power cost of bringing the link back up from a low power state, use 2009 * %PCI_EXP_OBFF_SIGNAL_ALWAYS. Otherwise, use %PCI_OBFF_SIGNAL_L0 (the 2010 * preferred type). 2011 * 2012 * RETURNS: 2013 * Zero on success, appropriate error number on failure. 2014 */ 2015 int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type type) 2016 { 2017 int pos; 2018 u32 cap; 2019 u16 ctrl; 2020 int ret; 2021 2022 if (!pci_is_pcie(dev)) 2023 return -ENOTSUPP; 2024 2025 pos = pci_pcie_cap(dev); 2026 if (!pos) 2027 return -ENOTSUPP; 2028 2029 pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP2, &cap); 2030 if (!(cap & PCI_EXP_OBFF_MASK)) 2031 return -ENOTSUPP; /* no OBFF support at all */ 2032 2033 /* Make sure the topology supports OBFF as well */ 2034 if (dev->bus) { 2035 ret = pci_enable_obff(dev->bus->self, type); 2036 if (ret) 2037 return ret; 2038 } 2039 2040 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl); 2041 if (cap & PCI_EXP_OBFF_WAKE) 2042 ctrl |= PCI_EXP_OBFF_WAKE_EN; 2043 else { 2044 switch (type) { 2045 case PCI_EXP_OBFF_SIGNAL_L0: 2046 if (!(ctrl & PCI_EXP_OBFF_WAKE_EN)) 2047 ctrl |= PCI_EXP_OBFF_MSGA_EN; 2048 break; 2049 case PCI_EXP_OBFF_SIGNAL_ALWAYS: 2050 ctrl &= ~PCI_EXP_OBFF_WAKE_EN; 2051 ctrl |= PCI_EXP_OBFF_MSGB_EN; 2052 break; 2053 default: 2054 WARN(1, "bad OBFF signal type\n"); 2055 return -ENOTSUPP; 2056 } 2057 } 2058 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl); 2059 2060 return 0; 2061 } 2062 EXPORT_SYMBOL(pci_enable_obff); 2063 2064 /** 2065 * pci_disable_obff - disable optimized buffer flush/fill 2066 * @dev: PCI device 2067 * 2068 * Disable OBFF on @dev. 2069 */ 2070 void pci_disable_obff(struct pci_dev *dev) 2071 { 2072 int pos; 2073 u16 ctrl; 2074 2075 if (!pci_is_pcie(dev)) 2076 return; 2077 2078 pos = pci_pcie_cap(dev); 2079 if (!pos) 2080 return; 2081 2082 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl); 2083 ctrl &= ~PCI_EXP_OBFF_WAKE_EN; 2084 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl); 2085 } 2086 EXPORT_SYMBOL(pci_disable_obff); 2087 2088 /** 2089 * pci_ltr_supported - check whether a device supports LTR 2090 * @dev: PCI device 2091 * 2092 * RETURNS: 2093 * True if @dev supports latency tolerance reporting, false otherwise. 2094 */ 2095 bool pci_ltr_supported(struct pci_dev *dev) 2096 { 2097 int pos; 2098 u32 cap; 2099 2100 if (!pci_is_pcie(dev)) 2101 return false; 2102 2103 pos = pci_pcie_cap(dev); 2104 if (!pos) 2105 return false; 2106 2107 pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP2, &cap); 2108 2109 return cap & PCI_EXP_DEVCAP2_LTR; 2110 } 2111 EXPORT_SYMBOL(pci_ltr_supported); 2112 2113 /** 2114 * pci_enable_ltr - enable latency tolerance reporting 2115 * @dev: PCI device 2116 * 2117 * Enable LTR on @dev if possible, which means enabling it first on 2118 * upstream ports. 2119 * 2120 * RETURNS: 2121 * Zero on success, errno on failure. 2122 */ 2123 int pci_enable_ltr(struct pci_dev *dev) 2124 { 2125 int pos; 2126 u16 ctrl; 2127 int ret; 2128 2129 if (!pci_ltr_supported(dev)) 2130 return -ENOTSUPP; 2131 2132 pos = pci_pcie_cap(dev); 2133 if (!pos) 2134 return -ENOTSUPP; 2135 2136 /* Only primary function can enable/disable LTR */ 2137 if (PCI_FUNC(dev->devfn) != 0) 2138 return -EINVAL; 2139 2140 /* Enable upstream ports first */ 2141 if (dev->bus) { 2142 ret = pci_enable_ltr(dev->bus->self); 2143 if (ret) 2144 return ret; 2145 } 2146 2147 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl); 2148 ctrl |= PCI_EXP_LTR_EN; 2149 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl); 2150 2151 return 0; 2152 } 2153 EXPORT_SYMBOL(pci_enable_ltr); 2154 2155 /** 2156 * pci_disable_ltr - disable latency tolerance reporting 2157 * @dev: PCI device 2158 */ 2159 void pci_disable_ltr(struct pci_dev *dev) 2160 { 2161 int pos; 2162 u16 ctrl; 2163 2164 if (!pci_ltr_supported(dev)) 2165 return; 2166 2167 pos = pci_pcie_cap(dev); 2168 if (!pos) 2169 return; 2170 2171 /* Only primary function can enable/disable LTR */ 2172 if (PCI_FUNC(dev->devfn) != 0) 2173 return; 2174 2175 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl); 2176 ctrl &= ~PCI_EXP_LTR_EN; 2177 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl); 2178 } 2179 EXPORT_SYMBOL(pci_disable_ltr); 2180 2181 static int __pci_ltr_scale(int *val) 2182 { 2183 int scale = 0; 2184 2185 while (*val > 1023) { 2186 *val = (*val + 31) / 32; 2187 scale++; 2188 } 2189 return scale; 2190 } 2191 2192 /** 2193 * pci_set_ltr - set LTR latency values 2194 * @dev: PCI device 2195 * @snoop_lat_ns: snoop latency in nanoseconds 2196 * @nosnoop_lat_ns: nosnoop latency in nanoseconds 2197 * 2198 * Figure out the scale and set the LTR values accordingly. 2199 */ 2200 int pci_set_ltr(struct pci_dev *dev, int snoop_lat_ns, int nosnoop_lat_ns) 2201 { 2202 int pos, ret, snoop_scale, nosnoop_scale; 2203 u16 val; 2204 2205 if (!pci_ltr_supported(dev)) 2206 return -ENOTSUPP; 2207 2208 snoop_scale = __pci_ltr_scale(&snoop_lat_ns); 2209 nosnoop_scale = __pci_ltr_scale(&nosnoop_lat_ns); 2210 2211 if (snoop_lat_ns > PCI_LTR_VALUE_MASK || 2212 nosnoop_lat_ns > PCI_LTR_VALUE_MASK) 2213 return -EINVAL; 2214 2215 if ((snoop_scale > (PCI_LTR_SCALE_MASK >> PCI_LTR_SCALE_SHIFT)) || 2216 (nosnoop_scale > (PCI_LTR_SCALE_MASK >> PCI_LTR_SCALE_SHIFT))) 2217 return -EINVAL; 2218 2219 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR); 2220 if (!pos) 2221 return -ENOTSUPP; 2222 2223 val = (snoop_scale << PCI_LTR_SCALE_SHIFT) | snoop_lat_ns; 2224 ret = pci_write_config_word(dev, pos + PCI_LTR_MAX_SNOOP_LAT, val); 2225 if (ret != 4) 2226 return -EIO; 2227 2228 val = (nosnoop_scale << PCI_LTR_SCALE_SHIFT) | nosnoop_lat_ns; 2229 ret = pci_write_config_word(dev, pos + PCI_LTR_MAX_NOSNOOP_LAT, val); 2230 if (ret != 4) 2231 return -EIO; 2232 2233 return 0; 2234 } 2235 EXPORT_SYMBOL(pci_set_ltr); 2236 2237 static int pci_acs_enable; 2238 2239 /** 2240 * pci_request_acs - ask for ACS to be enabled if supported 2241 */ 2242 void pci_request_acs(void) 2243 { 2244 pci_acs_enable = 1; 2245 } 2246 2247 /** 2248 * pci_enable_acs - enable ACS if hardware support it 2249 * @dev: the PCI device 2250 */ 2251 void pci_enable_acs(struct pci_dev *dev) 2252 { 2253 int pos; 2254 u16 cap; 2255 u16 ctrl; 2256 2257 if (!pci_acs_enable) 2258 return; 2259 2260 if (!pci_is_pcie(dev)) 2261 return; 2262 2263 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS); 2264 if (!pos) 2265 return; 2266 2267 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap); 2268 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl); 2269 2270 /* Source Validation */ 2271 ctrl |= (cap & PCI_ACS_SV); 2272 2273 /* P2P Request Redirect */ 2274 ctrl |= (cap & PCI_ACS_RR); 2275 2276 /* P2P Completion Redirect */ 2277 ctrl |= (cap & PCI_ACS_CR); 2278 2279 /* Upstream Forwarding */ 2280 ctrl |= (cap & PCI_ACS_UF); 2281 2282 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl); 2283 } 2284 2285 /** 2286 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge 2287 * @dev: the PCI device 2288 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTD, 4=INTD) 2289 * 2290 * Perform INTx swizzling for a device behind one level of bridge. This is 2291 * required by section 9.1 of the PCI-to-PCI bridge specification for devices 2292 * behind bridges on add-in cards. For devices with ARI enabled, the slot 2293 * number is always 0 (see the Implementation Note in section 2.2.8.1 of 2294 * the PCI Express Base Specification, Revision 2.1) 2295 */ 2296 u8 pci_swizzle_interrupt_pin(struct pci_dev *dev, u8 pin) 2297 { 2298 int slot; 2299 2300 if (pci_ari_enabled(dev->bus)) 2301 slot = 0; 2302 else 2303 slot = PCI_SLOT(dev->devfn); 2304 2305 return (((pin - 1) + slot) % 4) + 1; 2306 } 2307 2308 int 2309 pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge) 2310 { 2311 u8 pin; 2312 2313 pin = dev->pin; 2314 if (!pin) 2315 return -1; 2316 2317 while (!pci_is_root_bus(dev->bus)) { 2318 pin = pci_swizzle_interrupt_pin(dev, pin); 2319 dev = dev->bus->self; 2320 } 2321 *bridge = dev; 2322 return pin; 2323 } 2324 2325 /** 2326 * pci_common_swizzle - swizzle INTx all the way to root bridge 2327 * @dev: the PCI device 2328 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD) 2329 * 2330 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI 2331 * bridges all the way up to a PCI root bus. 2332 */ 2333 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp) 2334 { 2335 u8 pin = *pinp; 2336 2337 while (!pci_is_root_bus(dev->bus)) { 2338 pin = pci_swizzle_interrupt_pin(dev, pin); 2339 dev = dev->bus->self; 2340 } 2341 *pinp = pin; 2342 return PCI_SLOT(dev->devfn); 2343 } 2344 2345 /** 2346 * pci_release_region - Release a PCI bar 2347 * @pdev: PCI device whose resources were previously reserved by pci_request_region 2348 * @bar: BAR to release 2349 * 2350 * Releases the PCI I/O and memory resources previously reserved by a 2351 * successful call to pci_request_region. Call this function only 2352 * after all use of the PCI regions has ceased. 2353 */ 2354 void pci_release_region(struct pci_dev *pdev, int bar) 2355 { 2356 struct pci_devres *dr; 2357 2358 if (pci_resource_len(pdev, bar) == 0) 2359 return; 2360 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) 2361 release_region(pci_resource_start(pdev, bar), 2362 pci_resource_len(pdev, bar)); 2363 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) 2364 release_mem_region(pci_resource_start(pdev, bar), 2365 pci_resource_len(pdev, bar)); 2366 2367 dr = find_pci_dr(pdev); 2368 if (dr) 2369 dr->region_mask &= ~(1 << bar); 2370 } 2371 2372 /** 2373 * __pci_request_region - Reserved PCI I/O and memory resource 2374 * @pdev: PCI device whose resources are to be reserved 2375 * @bar: BAR to be reserved 2376 * @res_name: Name to be associated with resource. 2377 * @exclusive: whether the region access is exclusive or not 2378 * 2379 * Mark the PCI region associated with PCI device @pdev BR @bar as 2380 * being reserved by owner @res_name. Do not access any 2381 * address inside the PCI regions unless this call returns 2382 * successfully. 2383 * 2384 * If @exclusive is set, then the region is marked so that userspace 2385 * is explicitly not allowed to map the resource via /dev/mem or 2386 * sysfs MMIO access. 2387 * 2388 * Returns 0 on success, or %EBUSY on error. A warning 2389 * message is also printed on failure. 2390 */ 2391 static int __pci_request_region(struct pci_dev *pdev, int bar, const char *res_name, 2392 int exclusive) 2393 { 2394 struct pci_devres *dr; 2395 2396 if (pci_resource_len(pdev, bar) == 0) 2397 return 0; 2398 2399 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) { 2400 if (!request_region(pci_resource_start(pdev, bar), 2401 pci_resource_len(pdev, bar), res_name)) 2402 goto err_out; 2403 } 2404 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) { 2405 if (!__request_mem_region(pci_resource_start(pdev, bar), 2406 pci_resource_len(pdev, bar), res_name, 2407 exclusive)) 2408 goto err_out; 2409 } 2410 2411 dr = find_pci_dr(pdev); 2412 if (dr) 2413 dr->region_mask |= 1 << bar; 2414 2415 return 0; 2416 2417 err_out: 2418 dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar, 2419 &pdev->resource[bar]); 2420 return -EBUSY; 2421 } 2422 2423 /** 2424 * pci_request_region - Reserve PCI I/O and memory resource 2425 * @pdev: PCI device whose resources are to be reserved 2426 * @bar: BAR to be reserved 2427 * @res_name: Name to be associated with resource 2428 * 2429 * Mark the PCI region associated with PCI device @pdev BAR @bar as 2430 * being reserved by owner @res_name. Do not access any 2431 * address inside the PCI regions unless this call returns 2432 * successfully. 2433 * 2434 * Returns 0 on success, or %EBUSY on error. A warning 2435 * message is also printed on failure. 2436 */ 2437 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) 2438 { 2439 return __pci_request_region(pdev, bar, res_name, 0); 2440 } 2441 2442 /** 2443 * pci_request_region_exclusive - Reserved PCI I/O and memory resource 2444 * @pdev: PCI device whose resources are to be reserved 2445 * @bar: BAR to be reserved 2446 * @res_name: Name to be associated with resource. 2447 * 2448 * Mark the PCI region associated with PCI device @pdev BR @bar as 2449 * being reserved by owner @res_name. Do not access any 2450 * address inside the PCI regions unless this call returns 2451 * successfully. 2452 * 2453 * Returns 0 on success, or %EBUSY on error. A warning 2454 * message is also printed on failure. 2455 * 2456 * The key difference that _exclusive makes it that userspace is 2457 * explicitly not allowed to map the resource via /dev/mem or 2458 * sysfs. 2459 */ 2460 int pci_request_region_exclusive(struct pci_dev *pdev, int bar, const char *res_name) 2461 { 2462 return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE); 2463 } 2464 /** 2465 * pci_release_selected_regions - Release selected PCI I/O and memory resources 2466 * @pdev: PCI device whose resources were previously reserved 2467 * @bars: Bitmask of BARs to be released 2468 * 2469 * Release selected PCI I/O and memory resources previously reserved. 2470 * Call this function only after all use of the PCI regions has ceased. 2471 */ 2472 void pci_release_selected_regions(struct pci_dev *pdev, int bars) 2473 { 2474 int i; 2475 2476 for (i = 0; i < 6; i++) 2477 if (bars & (1 << i)) 2478 pci_release_region(pdev, i); 2479 } 2480 2481 int __pci_request_selected_regions(struct pci_dev *pdev, int bars, 2482 const char *res_name, int excl) 2483 { 2484 int i; 2485 2486 for (i = 0; i < 6; i++) 2487 if (bars & (1 << i)) 2488 if (__pci_request_region(pdev, i, res_name, excl)) 2489 goto err_out; 2490 return 0; 2491 2492 err_out: 2493 while(--i >= 0) 2494 if (bars & (1 << i)) 2495 pci_release_region(pdev, i); 2496 2497 return -EBUSY; 2498 } 2499 2500 2501 /** 2502 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources 2503 * @pdev: PCI device whose resources are to be reserved 2504 * @bars: Bitmask of BARs to be requested 2505 * @res_name: Name to be associated with resource 2506 */ 2507 int pci_request_selected_regions(struct pci_dev *pdev, int bars, 2508 const char *res_name) 2509 { 2510 return __pci_request_selected_regions(pdev, bars, res_name, 0); 2511 } 2512 2513 int pci_request_selected_regions_exclusive(struct pci_dev *pdev, 2514 int bars, const char *res_name) 2515 { 2516 return __pci_request_selected_regions(pdev, bars, res_name, 2517 IORESOURCE_EXCLUSIVE); 2518 } 2519 2520 /** 2521 * pci_release_regions - Release reserved PCI I/O and memory resources 2522 * @pdev: PCI device whose resources were previously reserved by pci_request_regions 2523 * 2524 * Releases all PCI I/O and memory resources previously reserved by a 2525 * successful call to pci_request_regions. Call this function only 2526 * after all use of the PCI regions has ceased. 2527 */ 2528 2529 void pci_release_regions(struct pci_dev *pdev) 2530 { 2531 pci_release_selected_regions(pdev, (1 << 6) - 1); 2532 } 2533 2534 /** 2535 * pci_request_regions - Reserved PCI I/O and memory resources 2536 * @pdev: PCI device whose resources are to be reserved 2537 * @res_name: Name to be associated with resource. 2538 * 2539 * Mark all PCI regions associated with PCI device @pdev as 2540 * being reserved by owner @res_name. Do not access any 2541 * address inside the PCI regions unless this call returns 2542 * successfully. 2543 * 2544 * Returns 0 on success, or %EBUSY on error. A warning 2545 * message is also printed on failure. 2546 */ 2547 int pci_request_regions(struct pci_dev *pdev, const char *res_name) 2548 { 2549 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name); 2550 } 2551 2552 /** 2553 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources 2554 * @pdev: PCI device whose resources are to be reserved 2555 * @res_name: Name to be associated with resource. 2556 * 2557 * Mark all PCI regions associated with PCI device @pdev as 2558 * being reserved by owner @res_name. Do not access any 2559 * address inside the PCI regions unless this call returns 2560 * successfully. 2561 * 2562 * pci_request_regions_exclusive() will mark the region so that 2563 * /dev/mem and the sysfs MMIO access will not be allowed. 2564 * 2565 * Returns 0 on success, or %EBUSY on error. A warning 2566 * message is also printed on failure. 2567 */ 2568 int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name) 2569 { 2570 return pci_request_selected_regions_exclusive(pdev, 2571 ((1 << 6) - 1), res_name); 2572 } 2573 2574 static void __pci_set_master(struct pci_dev *dev, bool enable) 2575 { 2576 u16 old_cmd, cmd; 2577 2578 pci_read_config_word(dev, PCI_COMMAND, &old_cmd); 2579 if (enable) 2580 cmd = old_cmd | PCI_COMMAND_MASTER; 2581 else 2582 cmd = old_cmd & ~PCI_COMMAND_MASTER; 2583 if (cmd != old_cmd) { 2584 dev_dbg(&dev->dev, "%s bus mastering\n", 2585 enable ? "enabling" : "disabling"); 2586 pci_write_config_word(dev, PCI_COMMAND, cmd); 2587 } 2588 dev->is_busmaster = enable; 2589 } 2590 2591 /** 2592 * pci_set_master - enables bus-mastering for device dev 2593 * @dev: the PCI device to enable 2594 * 2595 * Enables bus-mastering on the device and calls pcibios_set_master() 2596 * to do the needed arch specific settings. 2597 */ 2598 void pci_set_master(struct pci_dev *dev) 2599 { 2600 __pci_set_master(dev, true); 2601 pcibios_set_master(dev); 2602 } 2603 2604 /** 2605 * pci_clear_master - disables bus-mastering for device dev 2606 * @dev: the PCI device to disable 2607 */ 2608 void pci_clear_master(struct pci_dev *dev) 2609 { 2610 __pci_set_master(dev, false); 2611 } 2612 2613 /** 2614 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed 2615 * @dev: the PCI device for which MWI is to be enabled 2616 * 2617 * Helper function for pci_set_mwi. 2618 * Originally copied from drivers/net/acenic.c. 2619 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. 2620 * 2621 * RETURNS: An appropriate -ERRNO error value on error, or zero for success. 2622 */ 2623 int pci_set_cacheline_size(struct pci_dev *dev) 2624 { 2625 u8 cacheline_size; 2626 2627 if (!pci_cache_line_size) 2628 return -EINVAL; 2629 2630 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be 2631 equal to or multiple of the right value. */ 2632 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); 2633 if (cacheline_size >= pci_cache_line_size && 2634 (cacheline_size % pci_cache_line_size) == 0) 2635 return 0; 2636 2637 /* Write the correct value. */ 2638 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size); 2639 /* Read it back. */ 2640 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); 2641 if (cacheline_size == pci_cache_line_size) 2642 return 0; 2643 2644 dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not " 2645 "supported\n", pci_cache_line_size << 2); 2646 2647 return -EINVAL; 2648 } 2649 EXPORT_SYMBOL_GPL(pci_set_cacheline_size); 2650 2651 #ifdef PCI_DISABLE_MWI 2652 int pci_set_mwi(struct pci_dev *dev) 2653 { 2654 return 0; 2655 } 2656 2657 int pci_try_set_mwi(struct pci_dev *dev) 2658 { 2659 return 0; 2660 } 2661 2662 void pci_clear_mwi(struct pci_dev *dev) 2663 { 2664 } 2665 2666 #else 2667 2668 /** 2669 * pci_set_mwi - enables memory-write-invalidate PCI transaction 2670 * @dev: the PCI device for which MWI is enabled 2671 * 2672 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. 2673 * 2674 * RETURNS: An appropriate -ERRNO error value on error, or zero for success. 2675 */ 2676 int 2677 pci_set_mwi(struct pci_dev *dev) 2678 { 2679 int rc; 2680 u16 cmd; 2681 2682 rc = pci_set_cacheline_size(dev); 2683 if (rc) 2684 return rc; 2685 2686 pci_read_config_word(dev, PCI_COMMAND, &cmd); 2687 if (! (cmd & PCI_COMMAND_INVALIDATE)) { 2688 dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n"); 2689 cmd |= PCI_COMMAND_INVALIDATE; 2690 pci_write_config_word(dev, PCI_COMMAND, cmd); 2691 } 2692 2693 return 0; 2694 } 2695 2696 /** 2697 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction 2698 * @dev: the PCI device for which MWI is enabled 2699 * 2700 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. 2701 * Callers are not required to check the return value. 2702 * 2703 * RETURNS: An appropriate -ERRNO error value on error, or zero for success. 2704 */ 2705 int pci_try_set_mwi(struct pci_dev *dev) 2706 { 2707 int rc = pci_set_mwi(dev); 2708 return rc; 2709 } 2710 2711 /** 2712 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev 2713 * @dev: the PCI device to disable 2714 * 2715 * Disables PCI Memory-Write-Invalidate transaction on the device 2716 */ 2717 void 2718 pci_clear_mwi(struct pci_dev *dev) 2719 { 2720 u16 cmd; 2721 2722 pci_read_config_word(dev, PCI_COMMAND, &cmd); 2723 if (cmd & PCI_COMMAND_INVALIDATE) { 2724 cmd &= ~PCI_COMMAND_INVALIDATE; 2725 pci_write_config_word(dev, PCI_COMMAND, cmd); 2726 } 2727 } 2728 #endif /* ! PCI_DISABLE_MWI */ 2729 2730 /** 2731 * pci_intx - enables/disables PCI INTx for device dev 2732 * @pdev: the PCI device to operate on 2733 * @enable: boolean: whether to enable or disable PCI INTx 2734 * 2735 * Enables/disables PCI INTx for device dev 2736 */ 2737 void 2738 pci_intx(struct pci_dev *pdev, int enable) 2739 { 2740 u16 pci_command, new; 2741 2742 pci_read_config_word(pdev, PCI_COMMAND, &pci_command); 2743 2744 if (enable) { 2745 new = pci_command & ~PCI_COMMAND_INTX_DISABLE; 2746 } else { 2747 new = pci_command | PCI_COMMAND_INTX_DISABLE; 2748 } 2749 2750 if (new != pci_command) { 2751 struct pci_devres *dr; 2752 2753 pci_write_config_word(pdev, PCI_COMMAND, new); 2754 2755 dr = find_pci_dr(pdev); 2756 if (dr && !dr->restore_intx) { 2757 dr->restore_intx = 1; 2758 dr->orig_intx = !enable; 2759 } 2760 } 2761 } 2762 2763 /** 2764 * pci_msi_off - disables any msi or msix capabilities 2765 * @dev: the PCI device to operate on 2766 * 2767 * If you want to use msi see pci_enable_msi and friends. 2768 * This is a lower level primitive that allows us to disable 2769 * msi operation at the device level. 2770 */ 2771 void pci_msi_off(struct pci_dev *dev) 2772 { 2773 int pos; 2774 u16 control; 2775 2776 pos = pci_find_capability(dev, PCI_CAP_ID_MSI); 2777 if (pos) { 2778 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); 2779 control &= ~PCI_MSI_FLAGS_ENABLE; 2780 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); 2781 } 2782 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); 2783 if (pos) { 2784 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); 2785 control &= ~PCI_MSIX_FLAGS_ENABLE; 2786 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); 2787 } 2788 } 2789 EXPORT_SYMBOL_GPL(pci_msi_off); 2790 2791 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size) 2792 { 2793 return dma_set_max_seg_size(&dev->dev, size); 2794 } 2795 EXPORT_SYMBOL(pci_set_dma_max_seg_size); 2796 2797 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask) 2798 { 2799 return dma_set_seg_boundary(&dev->dev, mask); 2800 } 2801 EXPORT_SYMBOL(pci_set_dma_seg_boundary); 2802 2803 static int pcie_flr(struct pci_dev *dev, int probe) 2804 { 2805 int i; 2806 int pos; 2807 u32 cap; 2808 u16 status, control; 2809 2810 pos = pci_pcie_cap(dev); 2811 if (!pos) 2812 return -ENOTTY; 2813 2814 pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP, &cap); 2815 if (!(cap & PCI_EXP_DEVCAP_FLR)) 2816 return -ENOTTY; 2817 2818 if (probe) 2819 return 0; 2820 2821 /* Wait for Transaction Pending bit clean */ 2822 for (i = 0; i < 4; i++) { 2823 if (i) 2824 msleep((1 << (i - 1)) * 100); 2825 2826 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status); 2827 if (!(status & PCI_EXP_DEVSTA_TRPND)) 2828 goto clear; 2829 } 2830 2831 dev_err(&dev->dev, "transaction is not cleared; " 2832 "proceeding with reset anyway\n"); 2833 2834 clear: 2835 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &control); 2836 control |= PCI_EXP_DEVCTL_BCR_FLR; 2837 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, control); 2838 2839 msleep(100); 2840 2841 return 0; 2842 } 2843 2844 static int pci_af_flr(struct pci_dev *dev, int probe) 2845 { 2846 int i; 2847 int pos; 2848 u8 cap; 2849 u8 status; 2850 2851 pos = pci_find_capability(dev, PCI_CAP_ID_AF); 2852 if (!pos) 2853 return -ENOTTY; 2854 2855 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap); 2856 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR)) 2857 return -ENOTTY; 2858 2859 if (probe) 2860 return 0; 2861 2862 /* Wait for Transaction Pending bit clean */ 2863 for (i = 0; i < 4; i++) { 2864 if (i) 2865 msleep((1 << (i - 1)) * 100); 2866 2867 pci_read_config_byte(dev, pos + PCI_AF_STATUS, &status); 2868 if (!(status & PCI_AF_STATUS_TP)) 2869 goto clear; 2870 } 2871 2872 dev_err(&dev->dev, "transaction is not cleared; " 2873 "proceeding with reset anyway\n"); 2874 2875 clear: 2876 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR); 2877 msleep(100); 2878 2879 return 0; 2880 } 2881 2882 /** 2883 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0. 2884 * @dev: Device to reset. 2885 * @probe: If set, only check if the device can be reset this way. 2886 * 2887 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is 2888 * unset, it will be reinitialized internally when going from PCI_D3hot to 2889 * PCI_D0. If that's the case and the device is not in a low-power state 2890 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset. 2891 * 2892 * NOTE: This causes the caller to sleep for twice the device power transition 2893 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms 2894 * by devault (i.e. unless the @dev's d3_delay field has a different value). 2895 * Moreover, only devices in D0 can be reset by this function. 2896 */ 2897 static int pci_pm_reset(struct pci_dev *dev, int probe) 2898 { 2899 u16 csr; 2900 2901 if (!dev->pm_cap) 2902 return -ENOTTY; 2903 2904 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr); 2905 if (csr & PCI_PM_CTRL_NO_SOFT_RESET) 2906 return -ENOTTY; 2907 2908 if (probe) 2909 return 0; 2910 2911 if (dev->current_state != PCI_D0) 2912 return -EINVAL; 2913 2914 csr &= ~PCI_PM_CTRL_STATE_MASK; 2915 csr |= PCI_D3hot; 2916 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); 2917 pci_dev_d3_sleep(dev); 2918 2919 csr &= ~PCI_PM_CTRL_STATE_MASK; 2920 csr |= PCI_D0; 2921 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); 2922 pci_dev_d3_sleep(dev); 2923 2924 return 0; 2925 } 2926 2927 static int pci_parent_bus_reset(struct pci_dev *dev, int probe) 2928 { 2929 u16 ctrl; 2930 struct pci_dev *pdev; 2931 2932 if (pci_is_root_bus(dev->bus) || dev->subordinate || !dev->bus->self) 2933 return -ENOTTY; 2934 2935 list_for_each_entry(pdev, &dev->bus->devices, bus_list) 2936 if (pdev != dev) 2937 return -ENOTTY; 2938 2939 if (probe) 2940 return 0; 2941 2942 pci_read_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, &ctrl); 2943 ctrl |= PCI_BRIDGE_CTL_BUS_RESET; 2944 pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl); 2945 msleep(100); 2946 2947 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET; 2948 pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl); 2949 msleep(100); 2950 2951 return 0; 2952 } 2953 2954 static int pci_dev_reset(struct pci_dev *dev, int probe) 2955 { 2956 int rc; 2957 2958 might_sleep(); 2959 2960 if (!probe) { 2961 pci_block_user_cfg_access(dev); 2962 /* block PM suspend, driver probe, etc. */ 2963 device_lock(&dev->dev); 2964 } 2965 2966 rc = pci_dev_specific_reset(dev, probe); 2967 if (rc != -ENOTTY) 2968 goto done; 2969 2970 rc = pcie_flr(dev, probe); 2971 if (rc != -ENOTTY) 2972 goto done; 2973 2974 rc = pci_af_flr(dev, probe); 2975 if (rc != -ENOTTY) 2976 goto done; 2977 2978 rc = pci_pm_reset(dev, probe); 2979 if (rc != -ENOTTY) 2980 goto done; 2981 2982 rc = pci_parent_bus_reset(dev, probe); 2983 done: 2984 if (!probe) { 2985 device_unlock(&dev->dev); 2986 pci_unblock_user_cfg_access(dev); 2987 } 2988 2989 return rc; 2990 } 2991 2992 /** 2993 * __pci_reset_function - reset a PCI device function 2994 * @dev: PCI device to reset 2995 * 2996 * Some devices allow an individual function to be reset without affecting 2997 * other functions in the same device. The PCI device must be responsive 2998 * to PCI config space in order to use this function. 2999 * 3000 * The device function is presumed to be unused when this function is called. 3001 * Resetting the device will make the contents of PCI configuration space 3002 * random, so any caller of this must be prepared to reinitialise the 3003 * device including MSI, bus mastering, BARs, decoding IO and memory spaces, 3004 * etc. 3005 * 3006 * Returns 0 if the device function was successfully reset or negative if the 3007 * device doesn't support resetting a single function. 3008 */ 3009 int __pci_reset_function(struct pci_dev *dev) 3010 { 3011 return pci_dev_reset(dev, 0); 3012 } 3013 EXPORT_SYMBOL_GPL(__pci_reset_function); 3014 3015 /** 3016 * pci_probe_reset_function - check whether the device can be safely reset 3017 * @dev: PCI device to reset 3018 * 3019 * Some devices allow an individual function to be reset without affecting 3020 * other functions in the same device. The PCI device must be responsive 3021 * to PCI config space in order to use this function. 3022 * 3023 * Returns 0 if the device function can be reset or negative if the 3024 * device doesn't support resetting a single function. 3025 */ 3026 int pci_probe_reset_function(struct pci_dev *dev) 3027 { 3028 return pci_dev_reset(dev, 1); 3029 } 3030 3031 /** 3032 * pci_reset_function - quiesce and reset a PCI device function 3033 * @dev: PCI device to reset 3034 * 3035 * Some devices allow an individual function to be reset without affecting 3036 * other functions in the same device. The PCI device must be responsive 3037 * to PCI config space in order to use this function. 3038 * 3039 * This function does not just reset the PCI portion of a device, but 3040 * clears all the state associated with the device. This function differs 3041 * from __pci_reset_function in that it saves and restores device state 3042 * over the reset. 3043 * 3044 * Returns 0 if the device function was successfully reset or negative if the 3045 * device doesn't support resetting a single function. 3046 */ 3047 int pci_reset_function(struct pci_dev *dev) 3048 { 3049 int rc; 3050 3051 rc = pci_dev_reset(dev, 1); 3052 if (rc) 3053 return rc; 3054 3055 pci_save_state(dev); 3056 3057 /* 3058 * both INTx and MSI are disabled after the Interrupt Disable bit 3059 * is set and the Bus Master bit is cleared. 3060 */ 3061 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE); 3062 3063 rc = pci_dev_reset(dev, 0); 3064 3065 pci_restore_state(dev); 3066 3067 return rc; 3068 } 3069 EXPORT_SYMBOL_GPL(pci_reset_function); 3070 3071 /** 3072 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count 3073 * @dev: PCI device to query 3074 * 3075 * Returns mmrbc: maximum designed memory read count in bytes 3076 * or appropriate error value. 3077 */ 3078 int pcix_get_max_mmrbc(struct pci_dev *dev) 3079 { 3080 int cap; 3081 u32 stat; 3082 3083 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); 3084 if (!cap) 3085 return -EINVAL; 3086 3087 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat)) 3088 return -EINVAL; 3089 3090 return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21); 3091 } 3092 EXPORT_SYMBOL(pcix_get_max_mmrbc); 3093 3094 /** 3095 * pcix_get_mmrbc - get PCI-X maximum memory read byte count 3096 * @dev: PCI device to query 3097 * 3098 * Returns mmrbc: maximum memory read count in bytes 3099 * or appropriate error value. 3100 */ 3101 int pcix_get_mmrbc(struct pci_dev *dev) 3102 { 3103 int cap; 3104 u16 cmd; 3105 3106 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); 3107 if (!cap) 3108 return -EINVAL; 3109 3110 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd)) 3111 return -EINVAL; 3112 3113 return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2); 3114 } 3115 EXPORT_SYMBOL(pcix_get_mmrbc); 3116 3117 /** 3118 * pcix_set_mmrbc - set PCI-X maximum memory read byte count 3119 * @dev: PCI device to query 3120 * @mmrbc: maximum memory read count in bytes 3121 * valid values are 512, 1024, 2048, 4096 3122 * 3123 * If possible sets maximum memory read byte count, some bridges have erratas 3124 * that prevent this. 3125 */ 3126 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc) 3127 { 3128 int cap; 3129 u32 stat, v, o; 3130 u16 cmd; 3131 3132 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc)) 3133 return -EINVAL; 3134 3135 v = ffs(mmrbc) - 10; 3136 3137 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); 3138 if (!cap) 3139 return -EINVAL; 3140 3141 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat)) 3142 return -EINVAL; 3143 3144 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21) 3145 return -E2BIG; 3146 3147 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd)) 3148 return -EINVAL; 3149 3150 o = (cmd & PCI_X_CMD_MAX_READ) >> 2; 3151 if (o != v) { 3152 if (v > o && dev->bus && 3153 (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC)) 3154 return -EIO; 3155 3156 cmd &= ~PCI_X_CMD_MAX_READ; 3157 cmd |= v << 2; 3158 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd)) 3159 return -EIO; 3160 } 3161 return 0; 3162 } 3163 EXPORT_SYMBOL(pcix_set_mmrbc); 3164 3165 /** 3166 * pcie_get_readrq - get PCI Express read request size 3167 * @dev: PCI device to query 3168 * 3169 * Returns maximum memory read request in bytes 3170 * or appropriate error value. 3171 */ 3172 int pcie_get_readrq(struct pci_dev *dev) 3173 { 3174 int ret, cap; 3175 u16 ctl; 3176 3177 cap = pci_pcie_cap(dev); 3178 if (!cap) 3179 return -EINVAL; 3180 3181 ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl); 3182 if (!ret) 3183 ret = 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12); 3184 3185 return ret; 3186 } 3187 EXPORT_SYMBOL(pcie_get_readrq); 3188 3189 /** 3190 * pcie_set_readrq - set PCI Express maximum memory read request 3191 * @dev: PCI device to query 3192 * @rq: maximum memory read count in bytes 3193 * valid values are 128, 256, 512, 1024, 2048, 4096 3194 * 3195 * If possible sets maximum memory read request in bytes 3196 */ 3197 int pcie_set_readrq(struct pci_dev *dev, int rq) 3198 { 3199 int cap, err = -EINVAL; 3200 u16 ctl, v; 3201 3202 if (rq < 128 || rq > 4096 || !is_power_of_2(rq)) 3203 goto out; 3204 3205 cap = pci_pcie_cap(dev); 3206 if (!cap) 3207 goto out; 3208 3209 err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl); 3210 if (err) 3211 goto out; 3212 /* 3213 * If using the "performance" PCIe config, we clamp the 3214 * read rq size to the max packet size to prevent the 3215 * host bridge generating requests larger than we can 3216 * cope with 3217 */ 3218 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) { 3219 int mps = pcie_get_mps(dev); 3220 3221 if (mps < 0) 3222 return mps; 3223 if (mps < rq) 3224 rq = mps; 3225 } 3226 3227 v = (ffs(rq) - 8) << 12; 3228 3229 if ((ctl & PCI_EXP_DEVCTL_READRQ) != v) { 3230 ctl &= ~PCI_EXP_DEVCTL_READRQ; 3231 ctl |= v; 3232 err = pci_write_config_word(dev, cap + PCI_EXP_DEVCTL, ctl); 3233 } 3234 3235 out: 3236 return err; 3237 } 3238 EXPORT_SYMBOL(pcie_set_readrq); 3239 3240 /** 3241 * pcie_get_mps - get PCI Express maximum payload size 3242 * @dev: PCI device to query 3243 * 3244 * Returns maximum payload size in bytes 3245 * or appropriate error value. 3246 */ 3247 int pcie_get_mps(struct pci_dev *dev) 3248 { 3249 int ret, cap; 3250 u16 ctl; 3251 3252 cap = pci_pcie_cap(dev); 3253 if (!cap) 3254 return -EINVAL; 3255 3256 ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl); 3257 if (!ret) 3258 ret = 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5); 3259 3260 return ret; 3261 } 3262 3263 /** 3264 * pcie_set_mps - set PCI Express maximum payload size 3265 * @dev: PCI device to query 3266 * @mps: maximum payload size in bytes 3267 * valid values are 128, 256, 512, 1024, 2048, 4096 3268 * 3269 * If possible sets maximum payload size 3270 */ 3271 int pcie_set_mps(struct pci_dev *dev, int mps) 3272 { 3273 int cap, err = -EINVAL; 3274 u16 ctl, v; 3275 3276 if (mps < 128 || mps > 4096 || !is_power_of_2(mps)) 3277 goto out; 3278 3279 v = ffs(mps) - 8; 3280 if (v > dev->pcie_mpss) 3281 goto out; 3282 v <<= 5; 3283 3284 cap = pci_pcie_cap(dev); 3285 if (!cap) 3286 goto out; 3287 3288 err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl); 3289 if (err) 3290 goto out; 3291 3292 if ((ctl & PCI_EXP_DEVCTL_PAYLOAD) != v) { 3293 ctl &= ~PCI_EXP_DEVCTL_PAYLOAD; 3294 ctl |= v; 3295 err = pci_write_config_word(dev, cap + PCI_EXP_DEVCTL, ctl); 3296 } 3297 out: 3298 return err; 3299 } 3300 3301 /** 3302 * pci_select_bars - Make BAR mask from the type of resource 3303 * @dev: the PCI device for which BAR mask is made 3304 * @flags: resource type mask to be selected 3305 * 3306 * This helper routine makes bar mask from the type of resource. 3307 */ 3308 int pci_select_bars(struct pci_dev *dev, unsigned long flags) 3309 { 3310 int i, bars = 0; 3311 for (i = 0; i < PCI_NUM_RESOURCES; i++) 3312 if (pci_resource_flags(dev, i) & flags) 3313 bars |= (1 << i); 3314 return bars; 3315 } 3316 3317 /** 3318 * pci_resource_bar - get position of the BAR associated with a resource 3319 * @dev: the PCI device 3320 * @resno: the resource number 3321 * @type: the BAR type to be filled in 3322 * 3323 * Returns BAR position in config space, or 0 if the BAR is invalid. 3324 */ 3325 int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type) 3326 { 3327 int reg; 3328 3329 if (resno < PCI_ROM_RESOURCE) { 3330 *type = pci_bar_unknown; 3331 return PCI_BASE_ADDRESS_0 + 4 * resno; 3332 } else if (resno == PCI_ROM_RESOURCE) { 3333 *type = pci_bar_mem32; 3334 return dev->rom_base_reg; 3335 } else if (resno < PCI_BRIDGE_RESOURCES) { 3336 /* device specific resource */ 3337 reg = pci_iov_resource_bar(dev, resno, type); 3338 if (reg) 3339 return reg; 3340 } 3341 3342 dev_err(&dev->dev, "BAR %d: invalid resource\n", resno); 3343 return 0; 3344 } 3345 3346 /* Some architectures require additional programming to enable VGA */ 3347 static arch_set_vga_state_t arch_set_vga_state; 3348 3349 void __init pci_register_set_vga_state(arch_set_vga_state_t func) 3350 { 3351 arch_set_vga_state = func; /* NULL disables */ 3352 } 3353 3354 static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode, 3355 unsigned int command_bits, u32 flags) 3356 { 3357 if (arch_set_vga_state) 3358 return arch_set_vga_state(dev, decode, command_bits, 3359 flags); 3360 return 0; 3361 } 3362 3363 /** 3364 * pci_set_vga_state - set VGA decode state on device and parents if requested 3365 * @dev: the PCI device 3366 * @decode: true = enable decoding, false = disable decoding 3367 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY 3368 * @flags: traverse ancestors and change bridges 3369 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE 3370 */ 3371 int pci_set_vga_state(struct pci_dev *dev, bool decode, 3372 unsigned int command_bits, u32 flags) 3373 { 3374 struct pci_bus *bus; 3375 struct pci_dev *bridge; 3376 u16 cmd; 3377 int rc; 3378 3379 WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) & (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY))); 3380 3381 /* ARCH specific VGA enables */ 3382 rc = pci_set_vga_state_arch(dev, decode, command_bits, flags); 3383 if (rc) 3384 return rc; 3385 3386 if (flags & PCI_VGA_STATE_CHANGE_DECODES) { 3387 pci_read_config_word(dev, PCI_COMMAND, &cmd); 3388 if (decode == true) 3389 cmd |= command_bits; 3390 else 3391 cmd &= ~command_bits; 3392 pci_write_config_word(dev, PCI_COMMAND, cmd); 3393 } 3394 3395 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE)) 3396 return 0; 3397 3398 bus = dev->bus; 3399 while (bus) { 3400 bridge = bus->self; 3401 if (bridge) { 3402 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL, 3403 &cmd); 3404 if (decode == true) 3405 cmd |= PCI_BRIDGE_CTL_VGA; 3406 else 3407 cmd &= ~PCI_BRIDGE_CTL_VGA; 3408 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, 3409 cmd); 3410 } 3411 bus = bus->parent; 3412 } 3413 return 0; 3414 } 3415 3416 #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE 3417 static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0}; 3418 static DEFINE_SPINLOCK(resource_alignment_lock); 3419 3420 /** 3421 * pci_specified_resource_alignment - get resource alignment specified by user. 3422 * @dev: the PCI device to get 3423 * 3424 * RETURNS: Resource alignment if it is specified. 3425 * Zero if it is not specified. 3426 */ 3427 resource_size_t pci_specified_resource_alignment(struct pci_dev *dev) 3428 { 3429 int seg, bus, slot, func, align_order, count; 3430 resource_size_t align = 0; 3431 char *p; 3432 3433 spin_lock(&resource_alignment_lock); 3434 p = resource_alignment_param; 3435 while (*p) { 3436 count = 0; 3437 if (sscanf(p, "%d%n", &align_order, &count) == 1 && 3438 p[count] == '@') { 3439 p += count + 1; 3440 } else { 3441 align_order = -1; 3442 } 3443 if (sscanf(p, "%x:%x:%x.%x%n", 3444 &seg, &bus, &slot, &func, &count) != 4) { 3445 seg = 0; 3446 if (sscanf(p, "%x:%x.%x%n", 3447 &bus, &slot, &func, &count) != 3) { 3448 /* Invalid format */ 3449 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n", 3450 p); 3451 break; 3452 } 3453 } 3454 p += count; 3455 if (seg == pci_domain_nr(dev->bus) && 3456 bus == dev->bus->number && 3457 slot == PCI_SLOT(dev->devfn) && 3458 func == PCI_FUNC(dev->devfn)) { 3459 if (align_order == -1) { 3460 align = PAGE_SIZE; 3461 } else { 3462 align = 1 << align_order; 3463 } 3464 /* Found */ 3465 break; 3466 } 3467 if (*p != ';' && *p != ',') { 3468 /* End of param or invalid format */ 3469 break; 3470 } 3471 p++; 3472 } 3473 spin_unlock(&resource_alignment_lock); 3474 return align; 3475 } 3476 3477 /** 3478 * pci_is_reassigndev - check if specified PCI is target device to reassign 3479 * @dev: the PCI device to check 3480 * 3481 * RETURNS: non-zero for PCI device is a target device to reassign, 3482 * or zero is not. 3483 */ 3484 int pci_is_reassigndev(struct pci_dev *dev) 3485 { 3486 return (pci_specified_resource_alignment(dev) != 0); 3487 } 3488 3489 ssize_t pci_set_resource_alignment_param(const char *buf, size_t count) 3490 { 3491 if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1) 3492 count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1; 3493 spin_lock(&resource_alignment_lock); 3494 strncpy(resource_alignment_param, buf, count); 3495 resource_alignment_param[count] = '\0'; 3496 spin_unlock(&resource_alignment_lock); 3497 return count; 3498 } 3499 3500 ssize_t pci_get_resource_alignment_param(char *buf, size_t size) 3501 { 3502 size_t count; 3503 spin_lock(&resource_alignment_lock); 3504 count = snprintf(buf, size, "%s", resource_alignment_param); 3505 spin_unlock(&resource_alignment_lock); 3506 return count; 3507 } 3508 3509 static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf) 3510 { 3511 return pci_get_resource_alignment_param(buf, PAGE_SIZE); 3512 } 3513 3514 static ssize_t pci_resource_alignment_store(struct bus_type *bus, 3515 const char *buf, size_t count) 3516 { 3517 return pci_set_resource_alignment_param(buf, count); 3518 } 3519 3520 BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show, 3521 pci_resource_alignment_store); 3522 3523 static int __init pci_resource_alignment_sysfs_init(void) 3524 { 3525 return bus_create_file(&pci_bus_type, 3526 &bus_attr_resource_alignment); 3527 } 3528 3529 late_initcall(pci_resource_alignment_sysfs_init); 3530 3531 static void __devinit pci_no_domains(void) 3532 { 3533 #ifdef CONFIG_PCI_DOMAINS 3534 pci_domains_supported = 0; 3535 #endif 3536 } 3537 3538 /** 3539 * pci_ext_cfg_enabled - can we access extended PCI config space? 3540 * @dev: The PCI device of the root bridge. 3541 * 3542 * Returns 1 if we can access PCI extended config space (offsets 3543 * greater than 0xff). This is the default implementation. Architecture 3544 * implementations can override this. 3545 */ 3546 int __attribute__ ((weak)) pci_ext_cfg_avail(struct pci_dev *dev) 3547 { 3548 return 1; 3549 } 3550 3551 void __weak pci_fixup_cardbus(struct pci_bus *bus) 3552 { 3553 } 3554 EXPORT_SYMBOL(pci_fixup_cardbus); 3555 3556 static int __init pci_setup(char *str) 3557 { 3558 while (str) { 3559 char *k = strchr(str, ','); 3560 if (k) 3561 *k++ = 0; 3562 if (*str && (str = pcibios_setup(str)) && *str) { 3563 if (!strcmp(str, "nomsi")) { 3564 pci_no_msi(); 3565 } else if (!strcmp(str, "noaer")) { 3566 pci_no_aer(); 3567 } else if (!strncmp(str, "realloc", 7)) { 3568 pci_realloc(); 3569 } else if (!strcmp(str, "nodomains")) { 3570 pci_no_domains(); 3571 } else if (!strncmp(str, "cbiosize=", 9)) { 3572 pci_cardbus_io_size = memparse(str + 9, &str); 3573 } else if (!strncmp(str, "cbmemsize=", 10)) { 3574 pci_cardbus_mem_size = memparse(str + 10, &str); 3575 } else if (!strncmp(str, "resource_alignment=", 19)) { 3576 pci_set_resource_alignment_param(str + 19, 3577 strlen(str + 19)); 3578 } else if (!strncmp(str, "ecrc=", 5)) { 3579 pcie_ecrc_get_policy(str + 5); 3580 } else if (!strncmp(str, "hpiosize=", 9)) { 3581 pci_hotplug_io_size = memparse(str + 9, &str); 3582 } else if (!strncmp(str, "hpmemsize=", 10)) { 3583 pci_hotplug_mem_size = memparse(str + 10, &str); 3584 } else if (!strncmp(str, "pcie_bus_tune_off", 17)) { 3585 pcie_bus_config = PCIE_BUS_TUNE_OFF; 3586 } else if (!strncmp(str, "pcie_bus_safe", 13)) { 3587 pcie_bus_config = PCIE_BUS_SAFE; 3588 } else if (!strncmp(str, "pcie_bus_perf", 13)) { 3589 pcie_bus_config = PCIE_BUS_PERFORMANCE; 3590 } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) { 3591 pcie_bus_config = PCIE_BUS_PEER2PEER; 3592 } else { 3593 printk(KERN_ERR "PCI: Unknown option `%s'\n", 3594 str); 3595 } 3596 } 3597 str = k; 3598 } 3599 return 0; 3600 } 3601 early_param("pci", pci_setup); 3602 3603 EXPORT_SYMBOL(pci_reenable_device); 3604 EXPORT_SYMBOL(pci_enable_device_io); 3605 EXPORT_SYMBOL(pci_enable_device_mem); 3606 EXPORT_SYMBOL(pci_enable_device); 3607 EXPORT_SYMBOL(pcim_enable_device); 3608 EXPORT_SYMBOL(pcim_pin_device); 3609 EXPORT_SYMBOL(pci_disable_device); 3610 EXPORT_SYMBOL(pci_find_capability); 3611 EXPORT_SYMBOL(pci_bus_find_capability); 3612 EXPORT_SYMBOL(pci_release_regions); 3613 EXPORT_SYMBOL(pci_request_regions); 3614 EXPORT_SYMBOL(pci_request_regions_exclusive); 3615 EXPORT_SYMBOL(pci_release_region); 3616 EXPORT_SYMBOL(pci_request_region); 3617 EXPORT_SYMBOL(pci_request_region_exclusive); 3618 EXPORT_SYMBOL(pci_release_selected_regions); 3619 EXPORT_SYMBOL(pci_request_selected_regions); 3620 EXPORT_SYMBOL(pci_request_selected_regions_exclusive); 3621 EXPORT_SYMBOL(pci_set_master); 3622 EXPORT_SYMBOL(pci_clear_master); 3623 EXPORT_SYMBOL(pci_set_mwi); 3624 EXPORT_SYMBOL(pci_try_set_mwi); 3625 EXPORT_SYMBOL(pci_clear_mwi); 3626 EXPORT_SYMBOL_GPL(pci_intx); 3627 EXPORT_SYMBOL(pci_assign_resource); 3628 EXPORT_SYMBOL(pci_find_parent_resource); 3629 EXPORT_SYMBOL(pci_select_bars); 3630 3631 EXPORT_SYMBOL(pci_set_power_state); 3632 EXPORT_SYMBOL(pci_save_state); 3633 EXPORT_SYMBOL(pci_restore_state); 3634 EXPORT_SYMBOL(pci_pme_capable); 3635 EXPORT_SYMBOL(pci_pme_active); 3636 EXPORT_SYMBOL(pci_wake_from_d3); 3637 EXPORT_SYMBOL(pci_target_state); 3638 EXPORT_SYMBOL(pci_prepare_to_sleep); 3639 EXPORT_SYMBOL(pci_back_from_sleep); 3640 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state); 3641