1 /* 2 * $Id: pci.c,v 1.91 1999/01/21 13:34:01 davem Exp $ 3 * 4 * PCI Bus Services, see include/linux/pci.h for further explanation. 5 * 6 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter, 7 * David Mosberger-Tang 8 * 9 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz> 10 */ 11 12 #include <linux/kernel.h> 13 #include <linux/delay.h> 14 #include <linux/init.h> 15 #include <linux/pci.h> 16 #include <linux/module.h> 17 #include <linux/spinlock.h> 18 #include <linux/string.h> 19 #include <asm/dma.h> /* isa_dma_bridge_buggy */ 20 #include "pci.h" 21 22 23 /** 24 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children 25 * @bus: pointer to PCI bus structure to search 26 * 27 * Given a PCI bus, returns the highest PCI bus number present in the set 28 * including the given PCI bus and its list of child PCI buses. 29 */ 30 unsigned char __devinit 31 pci_bus_max_busnr(struct pci_bus* bus) 32 { 33 struct list_head *tmp; 34 unsigned char max, n; 35 36 max = bus->number; 37 list_for_each(tmp, &bus->children) { 38 n = pci_bus_max_busnr(pci_bus_b(tmp)); 39 if(n > max) 40 max = n; 41 } 42 return max; 43 } 44 45 /** 46 * pci_max_busnr - returns maximum PCI bus number 47 * 48 * Returns the highest PCI bus number present in the system global list of 49 * PCI buses. 50 */ 51 unsigned char __devinit 52 pci_max_busnr(void) 53 { 54 struct pci_bus *bus = NULL; 55 unsigned char max, n; 56 57 max = 0; 58 while ((bus = pci_find_next_bus(bus)) != NULL) { 59 n = pci_bus_max_busnr(bus); 60 if(n > max) 61 max = n; 62 } 63 return max; 64 } 65 66 static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn, u8 pos, int cap) 67 { 68 u8 id; 69 int ttl = 48; 70 71 while (ttl--) { 72 pci_bus_read_config_byte(bus, devfn, pos, &pos); 73 if (pos < 0x40) 74 break; 75 pos &= ~3; 76 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID, 77 &id); 78 if (id == 0xff) 79 break; 80 if (id == cap) 81 return pos; 82 pos += PCI_CAP_LIST_NEXT; 83 } 84 return 0; 85 } 86 87 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap) 88 { 89 return __pci_find_next_cap(dev->bus, dev->devfn, 90 pos + PCI_CAP_LIST_NEXT, cap); 91 } 92 EXPORT_SYMBOL_GPL(pci_find_next_capability); 93 94 static int __pci_bus_find_cap(struct pci_bus *bus, unsigned int devfn, u8 hdr_type, int cap) 95 { 96 u16 status; 97 u8 pos; 98 99 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status); 100 if (!(status & PCI_STATUS_CAP_LIST)) 101 return 0; 102 103 switch (hdr_type) { 104 case PCI_HEADER_TYPE_NORMAL: 105 case PCI_HEADER_TYPE_BRIDGE: 106 pos = PCI_CAPABILITY_LIST; 107 break; 108 case PCI_HEADER_TYPE_CARDBUS: 109 pos = PCI_CB_CAPABILITY_LIST; 110 break; 111 default: 112 return 0; 113 } 114 return __pci_find_next_cap(bus, devfn, pos, cap); 115 } 116 117 /** 118 * pci_find_capability - query for devices' capabilities 119 * @dev: PCI device to query 120 * @cap: capability code 121 * 122 * Tell if a device supports a given PCI capability. 123 * Returns the address of the requested capability structure within the 124 * device's PCI configuration space or 0 in case the device does not 125 * support it. Possible values for @cap: 126 * 127 * %PCI_CAP_ID_PM Power Management 128 * %PCI_CAP_ID_AGP Accelerated Graphics Port 129 * %PCI_CAP_ID_VPD Vital Product Data 130 * %PCI_CAP_ID_SLOTID Slot Identification 131 * %PCI_CAP_ID_MSI Message Signalled Interrupts 132 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap 133 * %PCI_CAP_ID_PCIX PCI-X 134 * %PCI_CAP_ID_EXP PCI Express 135 */ 136 int pci_find_capability(struct pci_dev *dev, int cap) 137 { 138 return __pci_bus_find_cap(dev->bus, dev->devfn, dev->hdr_type, cap); 139 } 140 141 /** 142 * pci_bus_find_capability - query for devices' capabilities 143 * @bus: the PCI bus to query 144 * @devfn: PCI device to query 145 * @cap: capability code 146 * 147 * Like pci_find_capability() but works for pci devices that do not have a 148 * pci_dev structure set up yet. 149 * 150 * Returns the address of the requested capability structure within the 151 * device's PCI configuration space or 0 in case the device does not 152 * support it. 153 */ 154 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap) 155 { 156 u8 hdr_type; 157 158 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type); 159 160 return __pci_bus_find_cap(bus, devfn, hdr_type & 0x7f, cap); 161 } 162 163 /** 164 * pci_find_ext_capability - Find an extended capability 165 * @dev: PCI device to query 166 * @cap: capability code 167 * 168 * Returns the address of the requested extended capability structure 169 * within the device's PCI configuration space or 0 if the device does 170 * not support it. Possible values for @cap: 171 * 172 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting 173 * %PCI_EXT_CAP_ID_VC Virtual Channel 174 * %PCI_EXT_CAP_ID_DSN Device Serial Number 175 * %PCI_EXT_CAP_ID_PWR Power Budgeting 176 */ 177 int pci_find_ext_capability(struct pci_dev *dev, int cap) 178 { 179 u32 header; 180 int ttl = 480; /* 3840 bytes, minimum 8 bytes per capability */ 181 int pos = 0x100; 182 183 if (dev->cfg_size <= 256) 184 return 0; 185 186 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) 187 return 0; 188 189 /* 190 * If we have no capabilities, this is indicated by cap ID, 191 * cap version and next pointer all being 0. 192 */ 193 if (header == 0) 194 return 0; 195 196 while (ttl-- > 0) { 197 if (PCI_EXT_CAP_ID(header) == cap) 198 return pos; 199 200 pos = PCI_EXT_CAP_NEXT(header); 201 if (pos < 0x100) 202 break; 203 204 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) 205 break; 206 } 207 208 return 0; 209 } 210 211 /** 212 * pci_find_parent_resource - return resource region of parent bus of given region 213 * @dev: PCI device structure contains resources to be searched 214 * @res: child resource record for which parent is sought 215 * 216 * For given resource region of given device, return the resource 217 * region of parent bus the given region is contained in or where 218 * it should be allocated from. 219 */ 220 struct resource * 221 pci_find_parent_resource(const struct pci_dev *dev, struct resource *res) 222 { 223 const struct pci_bus *bus = dev->bus; 224 int i; 225 struct resource *best = NULL; 226 227 for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++) { 228 struct resource *r = bus->resource[i]; 229 if (!r) 230 continue; 231 if (res->start && !(res->start >= r->start && res->end <= r->end)) 232 continue; /* Not contained */ 233 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM)) 234 continue; /* Wrong type */ 235 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH)) 236 return r; /* Exact match */ 237 if ((res->flags & IORESOURCE_PREFETCH) && !(r->flags & IORESOURCE_PREFETCH)) 238 best = r; /* Approximating prefetchable by non-prefetchable */ 239 } 240 return best; 241 } 242 243 /** 244 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up) 245 * @dev: PCI device to have its BARs restored 246 * 247 * Restore the BAR values for a given device, so as to make it 248 * accessible by its driver. 249 */ 250 void 251 pci_restore_bars(struct pci_dev *dev) 252 { 253 int i, numres; 254 255 switch (dev->hdr_type) { 256 case PCI_HEADER_TYPE_NORMAL: 257 numres = 6; 258 break; 259 case PCI_HEADER_TYPE_BRIDGE: 260 numres = 2; 261 break; 262 case PCI_HEADER_TYPE_CARDBUS: 263 numres = 1; 264 break; 265 default: 266 /* Should never get here, but just in case... */ 267 return; 268 } 269 270 for (i = 0; i < numres; i ++) 271 pci_update_resource(dev, &dev->resource[i], i); 272 } 273 274 int (*platform_pci_set_power_state)(struct pci_dev *dev, pci_power_t t); 275 276 /** 277 * pci_set_power_state - Set the power state of a PCI device 278 * @dev: PCI device to be suspended 279 * @state: PCI power state (D0, D1, D2, D3hot, D3cold) we're entering 280 * 281 * Transition a device to a new power state, using the Power Management 282 * Capabilities in the device's config space. 283 * 284 * RETURN VALUE: 285 * -EINVAL if trying to enter a lower state than we're already in. 286 * 0 if we're already in the requested state. 287 * -EIO if device does not support PCI PM. 288 * 0 if we can successfully change the power state. 289 */ 290 int 291 pci_set_power_state(struct pci_dev *dev, pci_power_t state) 292 { 293 int pm, need_restore = 0; 294 u16 pmcsr, pmc; 295 296 /* bound the state we're entering */ 297 if (state > PCI_D3hot) 298 state = PCI_D3hot; 299 300 /* Validate current state: 301 * Can enter D0 from any state, but if we can only go deeper 302 * to sleep if we're already in a low power state 303 */ 304 if (state != PCI_D0 && dev->current_state > state) 305 return -EINVAL; 306 else if (dev->current_state == state) 307 return 0; /* we're already there */ 308 309 /* find PCI PM capability in list */ 310 pm = pci_find_capability(dev, PCI_CAP_ID_PM); 311 312 /* abort if the device doesn't support PM capabilities */ 313 if (!pm) 314 return -EIO; 315 316 pci_read_config_word(dev,pm + PCI_PM_PMC,&pmc); 317 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) { 318 printk(KERN_DEBUG 319 "PCI: %s has unsupported PM cap regs version (%u)\n", 320 pci_name(dev), pmc & PCI_PM_CAP_VER_MASK); 321 return -EIO; 322 } 323 324 /* check if this device supports the desired state */ 325 if (state == PCI_D1 && !(pmc & PCI_PM_CAP_D1)) 326 return -EIO; 327 else if (state == PCI_D2 && !(pmc & PCI_PM_CAP_D2)) 328 return -EIO; 329 330 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr); 331 332 /* If we're (effectively) in D3, force entire word to 0. 333 * This doesn't affect PME_Status, disables PME_En, and 334 * sets PowerState to 0. 335 */ 336 switch (dev->current_state) { 337 case PCI_D0: 338 case PCI_D1: 339 case PCI_D2: 340 pmcsr &= ~PCI_PM_CTRL_STATE_MASK; 341 pmcsr |= state; 342 break; 343 case PCI_UNKNOWN: /* Boot-up */ 344 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot 345 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET)) 346 need_restore = 1; 347 /* Fall-through: force to D0 */ 348 default: 349 pmcsr = 0; 350 break; 351 } 352 353 /* enter specified state */ 354 pci_write_config_word(dev, pm + PCI_PM_CTRL, pmcsr); 355 356 /* Mandatory power management transition delays */ 357 /* see PCI PM 1.1 5.6.1 table 18 */ 358 if (state == PCI_D3hot || dev->current_state == PCI_D3hot) 359 msleep(10); 360 else if (state == PCI_D2 || dev->current_state == PCI_D2) 361 udelay(200); 362 363 /* 364 * Give firmware a chance to be called, such as ACPI _PRx, _PSx 365 * Firmware method after natice method ? 366 */ 367 if (platform_pci_set_power_state) 368 platform_pci_set_power_state(dev, state); 369 370 dev->current_state = state; 371 372 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT 373 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning 374 * from D3hot to D0 _may_ perform an internal reset, thereby 375 * going to "D0 Uninitialized" rather than "D0 Initialized". 376 * For example, at least some versions of the 3c905B and the 377 * 3c556B exhibit this behaviour. 378 * 379 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave 380 * devices in a D3hot state at boot. Consequently, we need to 381 * restore at least the BARs so that the device will be 382 * accessible to its driver. 383 */ 384 if (need_restore) 385 pci_restore_bars(dev); 386 387 return 0; 388 } 389 390 int (*platform_pci_choose_state)(struct pci_dev *dev, pm_message_t state); 391 392 /** 393 * pci_choose_state - Choose the power state of a PCI device 394 * @dev: PCI device to be suspended 395 * @state: target sleep state for the whole system. This is the value 396 * that is passed to suspend() function. 397 * 398 * Returns PCI power state suitable for given device and given system 399 * message. 400 */ 401 402 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state) 403 { 404 int ret; 405 406 if (!pci_find_capability(dev, PCI_CAP_ID_PM)) 407 return PCI_D0; 408 409 if (platform_pci_choose_state) { 410 ret = platform_pci_choose_state(dev, state); 411 if (ret >= 0) 412 state.event = ret; 413 } 414 415 switch (state.event) { 416 case PM_EVENT_ON: 417 return PCI_D0; 418 case PM_EVENT_FREEZE: 419 case PM_EVENT_SUSPEND: 420 return PCI_D3hot; 421 default: 422 printk("They asked me for state %d\n", state.event); 423 BUG(); 424 } 425 return PCI_D0; 426 } 427 428 EXPORT_SYMBOL(pci_choose_state); 429 430 /** 431 * pci_save_state - save the PCI configuration space of a device before suspending 432 * @dev: - PCI device that we're dealing with 433 */ 434 int 435 pci_save_state(struct pci_dev *dev) 436 { 437 int i; 438 /* XXX: 100% dword access ok here? */ 439 for (i = 0; i < 16; i++) 440 pci_read_config_dword(dev, i * 4,&dev->saved_config_space[i]); 441 return 0; 442 } 443 444 /** 445 * pci_restore_state - Restore the saved state of a PCI device 446 * @dev: - PCI device that we're dealing with 447 */ 448 int 449 pci_restore_state(struct pci_dev *dev) 450 { 451 int i; 452 453 for (i = 0; i < 16; i++) 454 pci_write_config_dword(dev,i * 4, dev->saved_config_space[i]); 455 return 0; 456 } 457 458 /** 459 * pci_enable_device_bars - Initialize some of a device for use 460 * @dev: PCI device to be initialized 461 * @bars: bitmask of BAR's that must be configured 462 * 463 * Initialize device before it's used by a driver. Ask low-level code 464 * to enable selected I/O and memory resources. Wake up the device if it 465 * was suspended. Beware, this function can fail. 466 */ 467 468 int 469 pci_enable_device_bars(struct pci_dev *dev, int bars) 470 { 471 int err; 472 473 err = pci_set_power_state(dev, PCI_D0); 474 if (err < 0 && err != -EIO) 475 return err; 476 err = pcibios_enable_device(dev, bars); 477 if (err < 0) 478 return err; 479 return 0; 480 } 481 482 /** 483 * pci_enable_device - Initialize device before it's used by a driver. 484 * @dev: PCI device to be initialized 485 * 486 * Initialize device before it's used by a driver. Ask low-level code 487 * to enable I/O and memory. Wake up the device if it was suspended. 488 * Beware, this function can fail. 489 */ 490 int 491 pci_enable_device(struct pci_dev *dev) 492 { 493 int err; 494 495 if ((err = pci_enable_device_bars(dev, (1 << PCI_NUM_RESOURCES) - 1))) 496 return err; 497 pci_fixup_device(pci_fixup_enable, dev); 498 dev->is_enabled = 1; 499 return 0; 500 } 501 502 /** 503 * pcibios_disable_device - disable arch specific PCI resources for device dev 504 * @dev: the PCI device to disable 505 * 506 * Disables architecture specific PCI resources for the device. This 507 * is the default implementation. Architecture implementations can 508 * override this. 509 */ 510 void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {} 511 512 /** 513 * pci_disable_device - Disable PCI device after use 514 * @dev: PCI device to be disabled 515 * 516 * Signal to the system that the PCI device is not in use by the system 517 * anymore. This only involves disabling PCI bus-mastering, if active. 518 */ 519 void 520 pci_disable_device(struct pci_dev *dev) 521 { 522 u16 pci_command; 523 524 pci_read_config_word(dev, PCI_COMMAND, &pci_command); 525 if (pci_command & PCI_COMMAND_MASTER) { 526 pci_command &= ~PCI_COMMAND_MASTER; 527 pci_write_config_word(dev, PCI_COMMAND, pci_command); 528 } 529 dev->is_busmaster = 0; 530 531 pcibios_disable_device(dev); 532 dev->is_enabled = 0; 533 } 534 535 /** 536 * pci_enable_wake - enable device to generate PME# when suspended 537 * @dev: - PCI device to operate on 538 * @state: - Current state of device. 539 * @enable: - Flag to enable or disable generation 540 * 541 * Set the bits in the device's PM Capabilities to generate PME# when 542 * the system is suspended. 543 * 544 * -EIO is returned if device doesn't have PM Capabilities. 545 * -EINVAL is returned if device supports it, but can't generate wake events. 546 * 0 if operation is successful. 547 * 548 */ 549 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable) 550 { 551 int pm; 552 u16 value; 553 554 /* find PCI PM capability in list */ 555 pm = pci_find_capability(dev, PCI_CAP_ID_PM); 556 557 /* If device doesn't support PM Capabilities, but request is to disable 558 * wake events, it's a nop; otherwise fail */ 559 if (!pm) 560 return enable ? -EIO : 0; 561 562 /* Check device's ability to generate PME# */ 563 pci_read_config_word(dev,pm+PCI_PM_PMC,&value); 564 565 value &= PCI_PM_CAP_PME_MASK; 566 value >>= ffs(PCI_PM_CAP_PME_MASK) - 1; /* First bit of mask */ 567 568 /* Check if it can generate PME# from requested state. */ 569 if (!value || !(value & (1 << state))) 570 return enable ? -EINVAL : 0; 571 572 pci_read_config_word(dev, pm + PCI_PM_CTRL, &value); 573 574 /* Clear PME_Status by writing 1 to it and enable PME# */ 575 value |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE; 576 577 if (!enable) 578 value &= ~PCI_PM_CTRL_PME_ENABLE; 579 580 pci_write_config_word(dev, pm + PCI_PM_CTRL, value); 581 582 return 0; 583 } 584 585 int 586 pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge) 587 { 588 u8 pin; 589 590 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); 591 if (!pin) 592 return -1; 593 pin--; 594 while (dev->bus->self) { 595 pin = (pin + PCI_SLOT(dev->devfn)) % 4; 596 dev = dev->bus->self; 597 } 598 *bridge = dev; 599 return pin; 600 } 601 602 /** 603 * pci_release_region - Release a PCI bar 604 * @pdev: PCI device whose resources were previously reserved by pci_request_region 605 * @bar: BAR to release 606 * 607 * Releases the PCI I/O and memory resources previously reserved by a 608 * successful call to pci_request_region. Call this function only 609 * after all use of the PCI regions has ceased. 610 */ 611 void pci_release_region(struct pci_dev *pdev, int bar) 612 { 613 if (pci_resource_len(pdev, bar) == 0) 614 return; 615 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) 616 release_region(pci_resource_start(pdev, bar), 617 pci_resource_len(pdev, bar)); 618 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) 619 release_mem_region(pci_resource_start(pdev, bar), 620 pci_resource_len(pdev, bar)); 621 } 622 623 /** 624 * pci_request_region - Reserved PCI I/O and memory resource 625 * @pdev: PCI device whose resources are to be reserved 626 * @bar: BAR to be reserved 627 * @res_name: Name to be associated with resource. 628 * 629 * Mark the PCI region associated with PCI device @pdev BR @bar as 630 * being reserved by owner @res_name. Do not access any 631 * address inside the PCI regions unless this call returns 632 * successfully. 633 * 634 * Returns 0 on success, or %EBUSY on error. A warning 635 * message is also printed on failure. 636 */ 637 int pci_request_region(struct pci_dev *pdev, int bar, char *res_name) 638 { 639 if (pci_resource_len(pdev, bar) == 0) 640 return 0; 641 642 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) { 643 if (!request_region(pci_resource_start(pdev, bar), 644 pci_resource_len(pdev, bar), res_name)) 645 goto err_out; 646 } 647 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) { 648 if (!request_mem_region(pci_resource_start(pdev, bar), 649 pci_resource_len(pdev, bar), res_name)) 650 goto err_out; 651 } 652 653 return 0; 654 655 err_out: 656 printk (KERN_WARNING "PCI: Unable to reserve %s region #%d:%lx@%lx for device %s\n", 657 pci_resource_flags(pdev, bar) & IORESOURCE_IO ? "I/O" : "mem", 658 bar + 1, /* PCI BAR # */ 659 pci_resource_len(pdev, bar), pci_resource_start(pdev, bar), 660 pci_name(pdev)); 661 return -EBUSY; 662 } 663 664 665 /** 666 * pci_release_regions - Release reserved PCI I/O and memory resources 667 * @pdev: PCI device whose resources were previously reserved by pci_request_regions 668 * 669 * Releases all PCI I/O and memory resources previously reserved by a 670 * successful call to pci_request_regions. Call this function only 671 * after all use of the PCI regions has ceased. 672 */ 673 674 void pci_release_regions(struct pci_dev *pdev) 675 { 676 int i; 677 678 for (i = 0; i < 6; i++) 679 pci_release_region(pdev, i); 680 } 681 682 /** 683 * pci_request_regions - Reserved PCI I/O and memory resources 684 * @pdev: PCI device whose resources are to be reserved 685 * @res_name: Name to be associated with resource. 686 * 687 * Mark all PCI regions associated with PCI device @pdev as 688 * being reserved by owner @res_name. Do not access any 689 * address inside the PCI regions unless this call returns 690 * successfully. 691 * 692 * Returns 0 on success, or %EBUSY on error. A warning 693 * message is also printed on failure. 694 */ 695 int pci_request_regions(struct pci_dev *pdev, char *res_name) 696 { 697 int i; 698 699 for (i = 0; i < 6; i++) 700 if(pci_request_region(pdev, i, res_name)) 701 goto err_out; 702 return 0; 703 704 err_out: 705 while(--i >= 0) 706 pci_release_region(pdev, i); 707 708 return -EBUSY; 709 } 710 711 /** 712 * pci_set_master - enables bus-mastering for device dev 713 * @dev: the PCI device to enable 714 * 715 * Enables bus-mastering on the device and calls pcibios_set_master() 716 * to do the needed arch specific settings. 717 */ 718 void 719 pci_set_master(struct pci_dev *dev) 720 { 721 u16 cmd; 722 723 pci_read_config_word(dev, PCI_COMMAND, &cmd); 724 if (! (cmd & PCI_COMMAND_MASTER)) { 725 pr_debug("PCI: Enabling bus mastering for device %s\n", pci_name(dev)); 726 cmd |= PCI_COMMAND_MASTER; 727 pci_write_config_word(dev, PCI_COMMAND, cmd); 728 } 729 dev->is_busmaster = 1; 730 pcibios_set_master(dev); 731 } 732 733 #ifndef HAVE_ARCH_PCI_MWI 734 /* This can be overridden by arch code. */ 735 u8 pci_cache_line_size = L1_CACHE_BYTES >> 2; 736 737 /** 738 * pci_generic_prep_mwi - helper function for pci_set_mwi 739 * @dev: the PCI device for which MWI is enabled 740 * 741 * Helper function for generic implementation of pcibios_prep_mwi 742 * function. Originally copied from drivers/net/acenic.c. 743 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. 744 * 745 * RETURNS: An appropriate -ERRNO error value on error, or zero for success. 746 */ 747 static int 748 pci_generic_prep_mwi(struct pci_dev *dev) 749 { 750 u8 cacheline_size; 751 752 if (!pci_cache_line_size) 753 return -EINVAL; /* The system doesn't support MWI. */ 754 755 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be 756 equal to or multiple of the right value. */ 757 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); 758 if (cacheline_size >= pci_cache_line_size && 759 (cacheline_size % pci_cache_line_size) == 0) 760 return 0; 761 762 /* Write the correct value. */ 763 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size); 764 /* Read it back. */ 765 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); 766 if (cacheline_size == pci_cache_line_size) 767 return 0; 768 769 printk(KERN_DEBUG "PCI: cache line size of %d is not supported " 770 "by device %s\n", pci_cache_line_size << 2, pci_name(dev)); 771 772 return -EINVAL; 773 } 774 #endif /* !HAVE_ARCH_PCI_MWI */ 775 776 /** 777 * pci_set_mwi - enables memory-write-invalidate PCI transaction 778 * @dev: the PCI device for which MWI is enabled 779 * 780 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND, 781 * and then calls @pcibios_set_mwi to do the needed arch specific 782 * operations or a generic mwi-prep function. 783 * 784 * RETURNS: An appropriate -ERRNO error value on error, or zero for success. 785 */ 786 int 787 pci_set_mwi(struct pci_dev *dev) 788 { 789 int rc; 790 u16 cmd; 791 792 #ifdef HAVE_ARCH_PCI_MWI 793 rc = pcibios_prep_mwi(dev); 794 #else 795 rc = pci_generic_prep_mwi(dev); 796 #endif 797 798 if (rc) 799 return rc; 800 801 pci_read_config_word(dev, PCI_COMMAND, &cmd); 802 if (! (cmd & PCI_COMMAND_INVALIDATE)) { 803 pr_debug("PCI: Enabling Mem-Wr-Inval for device %s\n", pci_name(dev)); 804 cmd |= PCI_COMMAND_INVALIDATE; 805 pci_write_config_word(dev, PCI_COMMAND, cmd); 806 } 807 808 return 0; 809 } 810 811 /** 812 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev 813 * @dev: the PCI device to disable 814 * 815 * Disables PCI Memory-Write-Invalidate transaction on the device 816 */ 817 void 818 pci_clear_mwi(struct pci_dev *dev) 819 { 820 u16 cmd; 821 822 pci_read_config_word(dev, PCI_COMMAND, &cmd); 823 if (cmd & PCI_COMMAND_INVALIDATE) { 824 cmd &= ~PCI_COMMAND_INVALIDATE; 825 pci_write_config_word(dev, PCI_COMMAND, cmd); 826 } 827 } 828 829 /** 830 * pci_intx - enables/disables PCI INTx for device dev 831 * @pdev: the PCI device to operate on 832 * @enable: boolean: whether to enable or disable PCI INTx 833 * 834 * Enables/disables PCI INTx for device dev 835 */ 836 void 837 pci_intx(struct pci_dev *pdev, int enable) 838 { 839 u16 pci_command, new; 840 841 pci_read_config_word(pdev, PCI_COMMAND, &pci_command); 842 843 if (enable) { 844 new = pci_command & ~PCI_COMMAND_INTX_DISABLE; 845 } else { 846 new = pci_command | PCI_COMMAND_INTX_DISABLE; 847 } 848 849 if (new != pci_command) { 850 pci_write_config_word(pdev, PCI_COMMAND, new); 851 } 852 } 853 854 #ifndef HAVE_ARCH_PCI_SET_DMA_MASK 855 /* 856 * These can be overridden by arch-specific implementations 857 */ 858 int 859 pci_set_dma_mask(struct pci_dev *dev, u64 mask) 860 { 861 if (!pci_dma_supported(dev, mask)) 862 return -EIO; 863 864 dev->dma_mask = mask; 865 866 return 0; 867 } 868 869 int 870 pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask) 871 { 872 if (!pci_dma_supported(dev, mask)) 873 return -EIO; 874 875 dev->dev.coherent_dma_mask = mask; 876 877 return 0; 878 } 879 #endif 880 881 static int __devinit pci_init(void) 882 { 883 struct pci_dev *dev = NULL; 884 885 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { 886 pci_fixup_device(pci_fixup_final, dev); 887 } 888 return 0; 889 } 890 891 static int __devinit pci_setup(char *str) 892 { 893 while (str) { 894 char *k = strchr(str, ','); 895 if (k) 896 *k++ = 0; 897 if (*str && (str = pcibios_setup(str)) && *str) { 898 /* PCI layer options should be handled here */ 899 printk(KERN_ERR "PCI: Unknown option `%s'\n", str); 900 } 901 str = k; 902 } 903 return 1; 904 } 905 906 device_initcall(pci_init); 907 908 __setup("pci=", pci_setup); 909 910 #if defined(CONFIG_ISA) || defined(CONFIG_EISA) 911 /* FIXME: Some boxes have multiple ISA bridges! */ 912 struct pci_dev *isa_bridge; 913 EXPORT_SYMBOL(isa_bridge); 914 #endif 915 916 EXPORT_SYMBOL_GPL(pci_restore_bars); 917 EXPORT_SYMBOL(pci_enable_device_bars); 918 EXPORT_SYMBOL(pci_enable_device); 919 EXPORT_SYMBOL(pci_disable_device); 920 EXPORT_SYMBOL(pci_max_busnr); 921 EXPORT_SYMBOL(pci_bus_max_busnr); 922 EXPORT_SYMBOL(pci_find_capability); 923 EXPORT_SYMBOL(pci_bus_find_capability); 924 EXPORT_SYMBOL(pci_release_regions); 925 EXPORT_SYMBOL(pci_request_regions); 926 EXPORT_SYMBOL(pci_release_region); 927 EXPORT_SYMBOL(pci_request_region); 928 EXPORT_SYMBOL(pci_set_master); 929 EXPORT_SYMBOL(pci_set_mwi); 930 EXPORT_SYMBOL(pci_clear_mwi); 931 EXPORT_SYMBOL_GPL(pci_intx); 932 EXPORT_SYMBOL(pci_set_dma_mask); 933 EXPORT_SYMBOL(pci_set_consistent_dma_mask); 934 EXPORT_SYMBOL(pci_assign_resource); 935 EXPORT_SYMBOL(pci_find_parent_resource); 936 937 EXPORT_SYMBOL(pci_set_power_state); 938 EXPORT_SYMBOL(pci_save_state); 939 EXPORT_SYMBOL(pci_restore_state); 940 EXPORT_SYMBOL(pci_enable_wake); 941 942 /* Quirk info */ 943 944 EXPORT_SYMBOL(isa_dma_bridge_buggy); 945 EXPORT_SYMBOL(pci_pci_problems); 946