1 /* 2 * PCI Bus Services, see include/linux/pci.h for further explanation. 3 * 4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter, 5 * David Mosberger-Tang 6 * 7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz> 8 */ 9 10 #include <linux/kernel.h> 11 #include <linux/delay.h> 12 #include <linux/init.h> 13 #include <linux/pci.h> 14 #include <linux/pm.h> 15 #include <linux/slab.h> 16 #include <linux/module.h> 17 #include <linux/spinlock.h> 18 #include <linux/string.h> 19 #include <linux/log2.h> 20 #include <linux/pci-aspm.h> 21 #include <linux/pm_wakeup.h> 22 #include <linux/interrupt.h> 23 #include <linux/device.h> 24 #include <linux/pm_runtime.h> 25 #include <asm-generic/pci-bridge.h> 26 #include <asm/setup.h> 27 #include "pci.h" 28 29 const char *pci_power_names[] = { 30 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown", 31 }; 32 EXPORT_SYMBOL_GPL(pci_power_names); 33 34 int isa_dma_bridge_buggy; 35 EXPORT_SYMBOL(isa_dma_bridge_buggy); 36 37 int pci_pci_problems; 38 EXPORT_SYMBOL(pci_pci_problems); 39 40 unsigned int pci_pm_d3_delay; 41 42 static void pci_pme_list_scan(struct work_struct *work); 43 44 static LIST_HEAD(pci_pme_list); 45 static DEFINE_MUTEX(pci_pme_list_mutex); 46 static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan); 47 48 struct pci_pme_device { 49 struct list_head list; 50 struct pci_dev *dev; 51 }; 52 53 #define PME_TIMEOUT 1000 /* How long between PME checks */ 54 55 static void pci_dev_d3_sleep(struct pci_dev *dev) 56 { 57 unsigned int delay = dev->d3_delay; 58 59 if (delay < pci_pm_d3_delay) 60 delay = pci_pm_d3_delay; 61 62 msleep(delay); 63 } 64 65 #ifdef CONFIG_PCI_DOMAINS 66 int pci_domains_supported = 1; 67 #endif 68 69 #define DEFAULT_CARDBUS_IO_SIZE (256) 70 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024) 71 /* pci=cbmemsize=nnM,cbiosize=nn can override this */ 72 unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE; 73 unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE; 74 75 #define DEFAULT_HOTPLUG_IO_SIZE (256) 76 #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024) 77 /* pci=hpmemsize=nnM,hpiosize=nn can override this */ 78 unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE; 79 unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE; 80 81 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_TUNE_OFF; 82 83 /* 84 * The default CLS is used if arch didn't set CLS explicitly and not 85 * all pci devices agree on the same value. Arch can override either 86 * the dfl or actual value as it sees fit. Don't forget this is 87 * measured in 32-bit words, not bytes. 88 */ 89 u8 pci_dfl_cache_line_size __devinitdata = L1_CACHE_BYTES >> 2; 90 u8 pci_cache_line_size; 91 92 /* 93 * If we set up a device for bus mastering, we need to check the latency 94 * timer as certain BIOSes forget to set it properly. 95 */ 96 unsigned int pcibios_max_latency = 255; 97 98 /* If set, the PCIe ARI capability will not be used. */ 99 static bool pcie_ari_disabled; 100 101 /** 102 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children 103 * @bus: pointer to PCI bus structure to search 104 * 105 * Given a PCI bus, returns the highest PCI bus number present in the set 106 * including the given PCI bus and its list of child PCI buses. 107 */ 108 unsigned char pci_bus_max_busnr(struct pci_bus* bus) 109 { 110 struct list_head *tmp; 111 unsigned char max, n; 112 113 max = bus->busn_res.end; 114 list_for_each(tmp, &bus->children) { 115 n = pci_bus_max_busnr(pci_bus_b(tmp)); 116 if(n > max) 117 max = n; 118 } 119 return max; 120 } 121 EXPORT_SYMBOL_GPL(pci_bus_max_busnr); 122 123 #ifdef CONFIG_HAS_IOMEM 124 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar) 125 { 126 /* 127 * Make sure the BAR is actually a memory resource, not an IO resource 128 */ 129 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { 130 WARN_ON(1); 131 return NULL; 132 } 133 return ioremap_nocache(pci_resource_start(pdev, bar), 134 pci_resource_len(pdev, bar)); 135 } 136 EXPORT_SYMBOL_GPL(pci_ioremap_bar); 137 #endif 138 139 #define PCI_FIND_CAP_TTL 48 140 141 static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn, 142 u8 pos, int cap, int *ttl) 143 { 144 u8 id; 145 146 while ((*ttl)--) { 147 pci_bus_read_config_byte(bus, devfn, pos, &pos); 148 if (pos < 0x40) 149 break; 150 pos &= ~3; 151 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID, 152 &id); 153 if (id == 0xff) 154 break; 155 if (id == cap) 156 return pos; 157 pos += PCI_CAP_LIST_NEXT; 158 } 159 return 0; 160 } 161 162 static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn, 163 u8 pos, int cap) 164 { 165 int ttl = PCI_FIND_CAP_TTL; 166 167 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl); 168 } 169 170 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap) 171 { 172 return __pci_find_next_cap(dev->bus, dev->devfn, 173 pos + PCI_CAP_LIST_NEXT, cap); 174 } 175 EXPORT_SYMBOL_GPL(pci_find_next_capability); 176 177 static int __pci_bus_find_cap_start(struct pci_bus *bus, 178 unsigned int devfn, u8 hdr_type) 179 { 180 u16 status; 181 182 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status); 183 if (!(status & PCI_STATUS_CAP_LIST)) 184 return 0; 185 186 switch (hdr_type) { 187 case PCI_HEADER_TYPE_NORMAL: 188 case PCI_HEADER_TYPE_BRIDGE: 189 return PCI_CAPABILITY_LIST; 190 case PCI_HEADER_TYPE_CARDBUS: 191 return PCI_CB_CAPABILITY_LIST; 192 default: 193 return 0; 194 } 195 196 return 0; 197 } 198 199 /** 200 * pci_find_capability - query for devices' capabilities 201 * @dev: PCI device to query 202 * @cap: capability code 203 * 204 * Tell if a device supports a given PCI capability. 205 * Returns the address of the requested capability structure within the 206 * device's PCI configuration space or 0 in case the device does not 207 * support it. Possible values for @cap: 208 * 209 * %PCI_CAP_ID_PM Power Management 210 * %PCI_CAP_ID_AGP Accelerated Graphics Port 211 * %PCI_CAP_ID_VPD Vital Product Data 212 * %PCI_CAP_ID_SLOTID Slot Identification 213 * %PCI_CAP_ID_MSI Message Signalled Interrupts 214 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap 215 * %PCI_CAP_ID_PCIX PCI-X 216 * %PCI_CAP_ID_EXP PCI Express 217 */ 218 int pci_find_capability(struct pci_dev *dev, int cap) 219 { 220 int pos; 221 222 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); 223 if (pos) 224 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap); 225 226 return pos; 227 } 228 229 /** 230 * pci_bus_find_capability - query for devices' capabilities 231 * @bus: the PCI bus to query 232 * @devfn: PCI device to query 233 * @cap: capability code 234 * 235 * Like pci_find_capability() but works for pci devices that do not have a 236 * pci_dev structure set up yet. 237 * 238 * Returns the address of the requested capability structure within the 239 * device's PCI configuration space or 0 in case the device does not 240 * support it. 241 */ 242 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap) 243 { 244 int pos; 245 u8 hdr_type; 246 247 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type); 248 249 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f); 250 if (pos) 251 pos = __pci_find_next_cap(bus, devfn, pos, cap); 252 253 return pos; 254 } 255 256 /** 257 * pci_pcie_cap2 - query for devices' PCI_CAP_ID_EXP v2 capability structure 258 * @dev: PCI device to check 259 * 260 * Like pci_pcie_cap() but also checks that the PCIe capability version is 261 * >= 2. Note that v1 capability structures could be sparse in that not 262 * all register fields were required. v2 requires the entire structure to 263 * be present size wise, while still allowing for non-implemented registers 264 * to exist but they must be hardwired to 0. 265 * 266 * Due to the differences in the versions of capability structures, one 267 * must be careful not to try and access non-existant registers that may 268 * exist in early versions - v1 - of Express devices. 269 * 270 * Returns the offset of the PCIe capability structure as long as the 271 * capability version is >= 2; otherwise 0 is returned. 272 */ 273 static int pci_pcie_cap2(struct pci_dev *dev) 274 { 275 u16 flags; 276 int pos; 277 278 pos = pci_pcie_cap(dev); 279 if (pos) { 280 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags); 281 if ((flags & PCI_EXP_FLAGS_VERS) < 2) 282 pos = 0; 283 } 284 285 return pos; 286 } 287 288 /** 289 * pci_find_ext_capability - Find an extended capability 290 * @dev: PCI device to query 291 * @cap: capability code 292 * 293 * Returns the address of the requested extended capability structure 294 * within the device's PCI configuration space or 0 if the device does 295 * not support it. Possible values for @cap: 296 * 297 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting 298 * %PCI_EXT_CAP_ID_VC Virtual Channel 299 * %PCI_EXT_CAP_ID_DSN Device Serial Number 300 * %PCI_EXT_CAP_ID_PWR Power Budgeting 301 */ 302 int pci_find_ext_capability(struct pci_dev *dev, int cap) 303 { 304 u32 header; 305 int ttl; 306 int pos = PCI_CFG_SPACE_SIZE; 307 308 /* minimum 8 bytes per capability */ 309 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; 310 311 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE) 312 return 0; 313 314 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) 315 return 0; 316 317 /* 318 * If we have no capabilities, this is indicated by cap ID, 319 * cap version and next pointer all being 0. 320 */ 321 if (header == 0) 322 return 0; 323 324 while (ttl-- > 0) { 325 if (PCI_EXT_CAP_ID(header) == cap) 326 return pos; 327 328 pos = PCI_EXT_CAP_NEXT(header); 329 if (pos < PCI_CFG_SPACE_SIZE) 330 break; 331 332 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) 333 break; 334 } 335 336 return 0; 337 } 338 EXPORT_SYMBOL_GPL(pci_find_ext_capability); 339 340 static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap) 341 { 342 int rc, ttl = PCI_FIND_CAP_TTL; 343 u8 cap, mask; 344 345 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST) 346 mask = HT_3BIT_CAP_MASK; 347 else 348 mask = HT_5BIT_CAP_MASK; 349 350 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos, 351 PCI_CAP_ID_HT, &ttl); 352 while (pos) { 353 rc = pci_read_config_byte(dev, pos + 3, &cap); 354 if (rc != PCIBIOS_SUCCESSFUL) 355 return 0; 356 357 if ((cap & mask) == ht_cap) 358 return pos; 359 360 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, 361 pos + PCI_CAP_LIST_NEXT, 362 PCI_CAP_ID_HT, &ttl); 363 } 364 365 return 0; 366 } 367 /** 368 * pci_find_next_ht_capability - query a device's Hypertransport capabilities 369 * @dev: PCI device to query 370 * @pos: Position from which to continue searching 371 * @ht_cap: Hypertransport capability code 372 * 373 * To be used in conjunction with pci_find_ht_capability() to search for 374 * all capabilities matching @ht_cap. @pos should always be a value returned 375 * from pci_find_ht_capability(). 376 * 377 * NB. To be 100% safe against broken PCI devices, the caller should take 378 * steps to avoid an infinite loop. 379 */ 380 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap) 381 { 382 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap); 383 } 384 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability); 385 386 /** 387 * pci_find_ht_capability - query a device's Hypertransport capabilities 388 * @dev: PCI device to query 389 * @ht_cap: Hypertransport capability code 390 * 391 * Tell if a device supports a given Hypertransport capability. 392 * Returns an address within the device's PCI configuration space 393 * or 0 in case the device does not support the request capability. 394 * The address points to the PCI capability, of type PCI_CAP_ID_HT, 395 * which has a Hypertransport capability matching @ht_cap. 396 */ 397 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap) 398 { 399 int pos; 400 401 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); 402 if (pos) 403 pos = __pci_find_next_ht_cap(dev, pos, ht_cap); 404 405 return pos; 406 } 407 EXPORT_SYMBOL_GPL(pci_find_ht_capability); 408 409 /** 410 * pci_find_parent_resource - return resource region of parent bus of given region 411 * @dev: PCI device structure contains resources to be searched 412 * @res: child resource record for which parent is sought 413 * 414 * For given resource region of given device, return the resource 415 * region of parent bus the given region is contained in or where 416 * it should be allocated from. 417 */ 418 struct resource * 419 pci_find_parent_resource(const struct pci_dev *dev, struct resource *res) 420 { 421 const struct pci_bus *bus = dev->bus; 422 int i; 423 struct resource *best = NULL, *r; 424 425 pci_bus_for_each_resource(bus, r, i) { 426 if (!r) 427 continue; 428 if (res->start && !(res->start >= r->start && res->end <= r->end)) 429 continue; /* Not contained */ 430 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM)) 431 continue; /* Wrong type */ 432 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH)) 433 return r; /* Exact match */ 434 /* We can't insert a non-prefetch resource inside a prefetchable parent .. */ 435 if (r->flags & IORESOURCE_PREFETCH) 436 continue; 437 /* .. but we can put a prefetchable resource inside a non-prefetchable one */ 438 if (!best) 439 best = r; 440 } 441 return best; 442 } 443 444 /** 445 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up) 446 * @dev: PCI device to have its BARs restored 447 * 448 * Restore the BAR values for a given device, so as to make it 449 * accessible by its driver. 450 */ 451 static void 452 pci_restore_bars(struct pci_dev *dev) 453 { 454 int i; 455 456 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) 457 pci_update_resource(dev, i); 458 } 459 460 static struct pci_platform_pm_ops *pci_platform_pm; 461 462 int pci_set_platform_pm(struct pci_platform_pm_ops *ops) 463 { 464 if (!ops->is_manageable || !ops->set_state || !ops->choose_state 465 || !ops->sleep_wake || !ops->can_wakeup) 466 return -EINVAL; 467 pci_platform_pm = ops; 468 return 0; 469 } 470 471 static inline bool platform_pci_power_manageable(struct pci_dev *dev) 472 { 473 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false; 474 } 475 476 static inline int platform_pci_set_power_state(struct pci_dev *dev, 477 pci_power_t t) 478 { 479 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS; 480 } 481 482 static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev) 483 { 484 return pci_platform_pm ? 485 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR; 486 } 487 488 static inline bool platform_pci_can_wakeup(struct pci_dev *dev) 489 { 490 return pci_platform_pm ? pci_platform_pm->can_wakeup(dev) : false; 491 } 492 493 static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable) 494 { 495 return pci_platform_pm ? 496 pci_platform_pm->sleep_wake(dev, enable) : -ENODEV; 497 } 498 499 static inline int platform_pci_run_wake(struct pci_dev *dev, bool enable) 500 { 501 return pci_platform_pm ? 502 pci_platform_pm->run_wake(dev, enable) : -ENODEV; 503 } 504 505 /** 506 * pci_raw_set_power_state - Use PCI PM registers to set the power state of 507 * given PCI device 508 * @dev: PCI device to handle. 509 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into. 510 * 511 * RETURN VALUE: 512 * -EINVAL if the requested state is invalid. 513 * -EIO if device does not support PCI PM or its PM capabilities register has a 514 * wrong version, or device doesn't support the requested state. 515 * 0 if device already is in the requested state. 516 * 0 if device's power state has been successfully changed. 517 */ 518 static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state) 519 { 520 u16 pmcsr; 521 bool need_restore = false; 522 523 /* Check if we're already there */ 524 if (dev->current_state == state) 525 return 0; 526 527 if (!dev->pm_cap) 528 return -EIO; 529 530 if (state < PCI_D0 || state > PCI_D3hot) 531 return -EINVAL; 532 533 /* Validate current state: 534 * Can enter D0 from any state, but if we can only go deeper 535 * to sleep if we're already in a low power state 536 */ 537 if (state != PCI_D0 && dev->current_state <= PCI_D3cold 538 && dev->current_state > state) { 539 dev_err(&dev->dev, "invalid power transition " 540 "(from state %d to %d)\n", dev->current_state, state); 541 return -EINVAL; 542 } 543 544 /* check if this device supports the desired state */ 545 if ((state == PCI_D1 && !dev->d1_support) 546 || (state == PCI_D2 && !dev->d2_support)) 547 return -EIO; 548 549 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); 550 551 /* If we're (effectively) in D3, force entire word to 0. 552 * This doesn't affect PME_Status, disables PME_En, and 553 * sets PowerState to 0. 554 */ 555 switch (dev->current_state) { 556 case PCI_D0: 557 case PCI_D1: 558 case PCI_D2: 559 pmcsr &= ~PCI_PM_CTRL_STATE_MASK; 560 pmcsr |= state; 561 break; 562 case PCI_D3hot: 563 case PCI_D3cold: 564 case PCI_UNKNOWN: /* Boot-up */ 565 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot 566 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET)) 567 need_restore = true; 568 /* Fall-through: force to D0 */ 569 default: 570 pmcsr = 0; 571 break; 572 } 573 574 /* enter specified state */ 575 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); 576 577 /* Mandatory power management transition delays */ 578 /* see PCI PM 1.1 5.6.1 table 18 */ 579 if (state == PCI_D3hot || dev->current_state == PCI_D3hot) 580 pci_dev_d3_sleep(dev); 581 else if (state == PCI_D2 || dev->current_state == PCI_D2) 582 udelay(PCI_PM_D2_DELAY); 583 584 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); 585 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); 586 if (dev->current_state != state && printk_ratelimit()) 587 dev_info(&dev->dev, "Refused to change power state, " 588 "currently in D%d\n", dev->current_state); 589 590 /* 591 * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT 592 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning 593 * from D3hot to D0 _may_ perform an internal reset, thereby 594 * going to "D0 Uninitialized" rather than "D0 Initialized". 595 * For example, at least some versions of the 3c905B and the 596 * 3c556B exhibit this behaviour. 597 * 598 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave 599 * devices in a D3hot state at boot. Consequently, we need to 600 * restore at least the BARs so that the device will be 601 * accessible to its driver. 602 */ 603 if (need_restore) 604 pci_restore_bars(dev); 605 606 if (dev->bus->self) 607 pcie_aspm_pm_state_change(dev->bus->self); 608 609 return 0; 610 } 611 612 /** 613 * pci_update_current_state - Read PCI power state of given device from its 614 * PCI PM registers and cache it 615 * @dev: PCI device to handle. 616 * @state: State to cache in case the device doesn't have the PM capability 617 */ 618 void pci_update_current_state(struct pci_dev *dev, pci_power_t state) 619 { 620 if (dev->pm_cap) { 621 u16 pmcsr; 622 623 /* 624 * Configuration space is not accessible for device in 625 * D3cold, so just keep or set D3cold for safety 626 */ 627 if (dev->current_state == PCI_D3cold) 628 return; 629 if (state == PCI_D3cold) { 630 dev->current_state = PCI_D3cold; 631 return; 632 } 633 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); 634 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); 635 } else { 636 dev->current_state = state; 637 } 638 } 639 640 /** 641 * pci_power_up - Put the given device into D0 forcibly 642 * @dev: PCI device to power up 643 */ 644 void pci_power_up(struct pci_dev *dev) 645 { 646 if (platform_pci_power_manageable(dev)) 647 platform_pci_set_power_state(dev, PCI_D0); 648 649 pci_raw_set_power_state(dev, PCI_D0); 650 pci_update_current_state(dev, PCI_D0); 651 } 652 653 /** 654 * pci_platform_power_transition - Use platform to change device power state 655 * @dev: PCI device to handle. 656 * @state: State to put the device into. 657 */ 658 static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state) 659 { 660 int error; 661 662 if (platform_pci_power_manageable(dev)) { 663 error = platform_pci_set_power_state(dev, state); 664 if (!error) 665 pci_update_current_state(dev, state); 666 /* Fall back to PCI_D0 if native PM is not supported */ 667 if (!dev->pm_cap) 668 dev->current_state = PCI_D0; 669 } else { 670 error = -ENODEV; 671 /* Fall back to PCI_D0 if native PM is not supported */ 672 if (!dev->pm_cap) 673 dev->current_state = PCI_D0; 674 } 675 676 return error; 677 } 678 679 /** 680 * __pci_start_power_transition - Start power transition of a PCI device 681 * @dev: PCI device to handle. 682 * @state: State to put the device into. 683 */ 684 static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state) 685 { 686 if (state == PCI_D0) { 687 pci_platform_power_transition(dev, PCI_D0); 688 /* 689 * Mandatory power management transition delays, see 690 * PCI Express Base Specification Revision 2.0 Section 691 * 6.6.1: Conventional Reset. Do not delay for 692 * devices powered on/off by corresponding bridge, 693 * because have already delayed for the bridge. 694 */ 695 if (dev->runtime_d3cold) { 696 msleep(dev->d3cold_delay); 697 /* 698 * When powering on a bridge from D3cold, the 699 * whole hierarchy may be powered on into 700 * D0uninitialized state, resume them to give 701 * them a chance to suspend again 702 */ 703 pci_wakeup_bus(dev->subordinate); 704 } 705 } 706 } 707 708 /** 709 * __pci_dev_set_current_state - Set current state of a PCI device 710 * @dev: Device to handle 711 * @data: pointer to state to be set 712 */ 713 static int __pci_dev_set_current_state(struct pci_dev *dev, void *data) 714 { 715 pci_power_t state = *(pci_power_t *)data; 716 717 dev->current_state = state; 718 return 0; 719 } 720 721 /** 722 * __pci_bus_set_current_state - Walk given bus and set current state of devices 723 * @bus: Top bus of the subtree to walk. 724 * @state: state to be set 725 */ 726 static void __pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state) 727 { 728 if (bus) 729 pci_walk_bus(bus, __pci_dev_set_current_state, &state); 730 } 731 732 /** 733 * __pci_complete_power_transition - Complete power transition of a PCI device 734 * @dev: PCI device to handle. 735 * @state: State to put the device into. 736 * 737 * This function should not be called directly by device drivers. 738 */ 739 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state) 740 { 741 int ret; 742 743 if (state <= PCI_D0) 744 return -EINVAL; 745 ret = pci_platform_power_transition(dev, state); 746 /* Power off the bridge may power off the whole hierarchy */ 747 if (!ret && state == PCI_D3cold) 748 __pci_bus_set_current_state(dev->subordinate, PCI_D3cold); 749 return ret; 750 } 751 EXPORT_SYMBOL_GPL(__pci_complete_power_transition); 752 753 /** 754 * pci_set_power_state - Set the power state of a PCI device 755 * @dev: PCI device to handle. 756 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into. 757 * 758 * Transition a device to a new power state, using the platform firmware and/or 759 * the device's PCI PM registers. 760 * 761 * RETURN VALUE: 762 * -EINVAL if the requested state is invalid. 763 * -EIO if device does not support PCI PM or its PM capabilities register has a 764 * wrong version, or device doesn't support the requested state. 765 * 0 if device already is in the requested state. 766 * 0 if device's power state has been successfully changed. 767 */ 768 int pci_set_power_state(struct pci_dev *dev, pci_power_t state) 769 { 770 int error; 771 772 /* bound the state we're entering */ 773 if (state > PCI_D3cold) 774 state = PCI_D3cold; 775 else if (state < PCI_D0) 776 state = PCI_D0; 777 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev)) 778 /* 779 * If the device or the parent bridge do not support PCI PM, 780 * ignore the request if we're doing anything other than putting 781 * it into D0 (which would only happen on boot). 782 */ 783 return 0; 784 785 /* Check if we're already there */ 786 if (dev->current_state == state) 787 return 0; 788 789 __pci_start_power_transition(dev, state); 790 791 /* This device is quirked not to be put into D3, so 792 don't put it in D3 */ 793 if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3)) 794 return 0; 795 796 /* 797 * To put device in D3cold, we put device into D3hot in native 798 * way, then put device into D3cold with platform ops 799 */ 800 error = pci_raw_set_power_state(dev, state > PCI_D3hot ? 801 PCI_D3hot : state); 802 803 if (!__pci_complete_power_transition(dev, state)) 804 error = 0; 805 /* 806 * When aspm_policy is "powersave" this call ensures 807 * that ASPM is configured. 808 */ 809 if (!error && dev->bus->self) 810 pcie_aspm_powersave_config_link(dev->bus->self); 811 812 return error; 813 } 814 815 /** 816 * pci_choose_state - Choose the power state of a PCI device 817 * @dev: PCI device to be suspended 818 * @state: target sleep state for the whole system. This is the value 819 * that is passed to suspend() function. 820 * 821 * Returns PCI power state suitable for given device and given system 822 * message. 823 */ 824 825 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state) 826 { 827 pci_power_t ret; 828 829 if (!pci_find_capability(dev, PCI_CAP_ID_PM)) 830 return PCI_D0; 831 832 ret = platform_pci_choose_state(dev); 833 if (ret != PCI_POWER_ERROR) 834 return ret; 835 836 switch (state.event) { 837 case PM_EVENT_ON: 838 return PCI_D0; 839 case PM_EVENT_FREEZE: 840 case PM_EVENT_PRETHAW: 841 /* REVISIT both freeze and pre-thaw "should" use D0 */ 842 case PM_EVENT_SUSPEND: 843 case PM_EVENT_HIBERNATE: 844 return PCI_D3hot; 845 default: 846 dev_info(&dev->dev, "unrecognized suspend event %d\n", 847 state.event); 848 BUG(); 849 } 850 return PCI_D0; 851 } 852 853 EXPORT_SYMBOL(pci_choose_state); 854 855 #define PCI_EXP_SAVE_REGS 7 856 857 #define pcie_cap_has_devctl(type, flags) 1 858 #define pcie_cap_has_lnkctl(type, flags) \ 859 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \ 860 (type == PCI_EXP_TYPE_ROOT_PORT || \ 861 type == PCI_EXP_TYPE_ENDPOINT || \ 862 type == PCI_EXP_TYPE_LEG_END)) 863 #define pcie_cap_has_sltctl(type, flags) \ 864 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \ 865 ((type == PCI_EXP_TYPE_ROOT_PORT) || \ 866 (type == PCI_EXP_TYPE_DOWNSTREAM && \ 867 (flags & PCI_EXP_FLAGS_SLOT)))) 868 #define pcie_cap_has_rtctl(type, flags) \ 869 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \ 870 (type == PCI_EXP_TYPE_ROOT_PORT || \ 871 type == PCI_EXP_TYPE_RC_EC)) 872 873 static struct pci_cap_saved_state *pci_find_saved_cap( 874 struct pci_dev *pci_dev, char cap) 875 { 876 struct pci_cap_saved_state *tmp; 877 struct hlist_node *pos; 878 879 hlist_for_each_entry(tmp, pos, &pci_dev->saved_cap_space, next) { 880 if (tmp->cap.cap_nr == cap) 881 return tmp; 882 } 883 return NULL; 884 } 885 886 static int pci_save_pcie_state(struct pci_dev *dev) 887 { 888 int pos, i = 0; 889 struct pci_cap_saved_state *save_state; 890 u16 *cap; 891 u16 flags; 892 893 pos = pci_pcie_cap(dev); 894 if (!pos) 895 return 0; 896 897 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); 898 if (!save_state) { 899 dev_err(&dev->dev, "buffer not found in %s\n", __func__); 900 return -ENOMEM; 901 } 902 cap = (u16 *)&save_state->cap.data[0]; 903 904 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags); 905 906 if (pcie_cap_has_devctl(dev->pcie_type, flags)) 907 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]); 908 if (pcie_cap_has_lnkctl(dev->pcie_type, flags)) 909 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]); 910 if (pcie_cap_has_sltctl(dev->pcie_type, flags)) 911 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]); 912 if (pcie_cap_has_rtctl(dev->pcie_type, flags)) 913 pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]); 914 915 pos = pci_pcie_cap2(dev); 916 if (!pos) 917 return 0; 918 919 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &cap[i++]); 920 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL2, &cap[i++]); 921 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL2, &cap[i++]); 922 return 0; 923 } 924 925 static void pci_restore_pcie_state(struct pci_dev *dev) 926 { 927 int i = 0, pos; 928 struct pci_cap_saved_state *save_state; 929 u16 *cap; 930 u16 flags; 931 932 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); 933 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 934 if (!save_state || pos <= 0) 935 return; 936 cap = (u16 *)&save_state->cap.data[0]; 937 938 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags); 939 940 if (pcie_cap_has_devctl(dev->pcie_type, flags)) 941 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]); 942 if (pcie_cap_has_lnkctl(dev->pcie_type, flags)) 943 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]); 944 if (pcie_cap_has_sltctl(dev->pcie_type, flags)) 945 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]); 946 if (pcie_cap_has_rtctl(dev->pcie_type, flags)) 947 pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]); 948 949 pos = pci_pcie_cap2(dev); 950 if (!pos) 951 return; 952 953 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, cap[i++]); 954 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL2, cap[i++]); 955 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL2, cap[i++]); 956 } 957 958 959 static int pci_save_pcix_state(struct pci_dev *dev) 960 { 961 int pos; 962 struct pci_cap_saved_state *save_state; 963 964 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); 965 if (pos <= 0) 966 return 0; 967 968 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); 969 if (!save_state) { 970 dev_err(&dev->dev, "buffer not found in %s\n", __func__); 971 return -ENOMEM; 972 } 973 974 pci_read_config_word(dev, pos + PCI_X_CMD, 975 (u16 *)save_state->cap.data); 976 977 return 0; 978 } 979 980 static void pci_restore_pcix_state(struct pci_dev *dev) 981 { 982 int i = 0, pos; 983 struct pci_cap_saved_state *save_state; 984 u16 *cap; 985 986 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); 987 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); 988 if (!save_state || pos <= 0) 989 return; 990 cap = (u16 *)&save_state->cap.data[0]; 991 992 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]); 993 } 994 995 996 /** 997 * pci_save_state - save the PCI configuration space of a device before suspending 998 * @dev: - PCI device that we're dealing with 999 */ 1000 int 1001 pci_save_state(struct pci_dev *dev) 1002 { 1003 int i; 1004 /* XXX: 100% dword access ok here? */ 1005 for (i = 0; i < 16; i++) 1006 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]); 1007 dev->state_saved = true; 1008 if ((i = pci_save_pcie_state(dev)) != 0) 1009 return i; 1010 if ((i = pci_save_pcix_state(dev)) != 0) 1011 return i; 1012 return 0; 1013 } 1014 1015 static void pci_restore_config_dword(struct pci_dev *pdev, int offset, 1016 u32 saved_val, int retry) 1017 { 1018 u32 val; 1019 1020 pci_read_config_dword(pdev, offset, &val); 1021 if (val == saved_val) 1022 return; 1023 1024 for (;;) { 1025 dev_dbg(&pdev->dev, "restoring config space at offset " 1026 "%#x (was %#x, writing %#x)\n", offset, val, saved_val); 1027 pci_write_config_dword(pdev, offset, saved_val); 1028 if (retry-- <= 0) 1029 return; 1030 1031 pci_read_config_dword(pdev, offset, &val); 1032 if (val == saved_val) 1033 return; 1034 1035 mdelay(1); 1036 } 1037 } 1038 1039 static void pci_restore_config_space_range(struct pci_dev *pdev, 1040 int start, int end, int retry) 1041 { 1042 int index; 1043 1044 for (index = end; index >= start; index--) 1045 pci_restore_config_dword(pdev, 4 * index, 1046 pdev->saved_config_space[index], 1047 retry); 1048 } 1049 1050 static void pci_restore_config_space(struct pci_dev *pdev) 1051 { 1052 if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) { 1053 pci_restore_config_space_range(pdev, 10, 15, 0); 1054 /* Restore BARs before the command register. */ 1055 pci_restore_config_space_range(pdev, 4, 9, 10); 1056 pci_restore_config_space_range(pdev, 0, 3, 0); 1057 } else { 1058 pci_restore_config_space_range(pdev, 0, 15, 0); 1059 } 1060 } 1061 1062 /** 1063 * pci_restore_state - Restore the saved state of a PCI device 1064 * @dev: - PCI device that we're dealing with 1065 */ 1066 void pci_restore_state(struct pci_dev *dev) 1067 { 1068 if (!dev->state_saved) 1069 return; 1070 1071 /* PCI Express register must be restored first */ 1072 pci_restore_pcie_state(dev); 1073 pci_restore_ats_state(dev); 1074 1075 pci_restore_config_space(dev); 1076 1077 pci_restore_pcix_state(dev); 1078 pci_restore_msi_state(dev); 1079 pci_restore_iov_state(dev); 1080 1081 dev->state_saved = false; 1082 } 1083 1084 struct pci_saved_state { 1085 u32 config_space[16]; 1086 struct pci_cap_saved_data cap[0]; 1087 }; 1088 1089 /** 1090 * pci_store_saved_state - Allocate and return an opaque struct containing 1091 * the device saved state. 1092 * @dev: PCI device that we're dealing with 1093 * 1094 * Rerturn NULL if no state or error. 1095 */ 1096 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev) 1097 { 1098 struct pci_saved_state *state; 1099 struct pci_cap_saved_state *tmp; 1100 struct pci_cap_saved_data *cap; 1101 struct hlist_node *pos; 1102 size_t size; 1103 1104 if (!dev->state_saved) 1105 return NULL; 1106 1107 size = sizeof(*state) + sizeof(struct pci_cap_saved_data); 1108 1109 hlist_for_each_entry(tmp, pos, &dev->saved_cap_space, next) 1110 size += sizeof(struct pci_cap_saved_data) + tmp->cap.size; 1111 1112 state = kzalloc(size, GFP_KERNEL); 1113 if (!state) 1114 return NULL; 1115 1116 memcpy(state->config_space, dev->saved_config_space, 1117 sizeof(state->config_space)); 1118 1119 cap = state->cap; 1120 hlist_for_each_entry(tmp, pos, &dev->saved_cap_space, next) { 1121 size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size; 1122 memcpy(cap, &tmp->cap, len); 1123 cap = (struct pci_cap_saved_data *)((u8 *)cap + len); 1124 } 1125 /* Empty cap_save terminates list */ 1126 1127 return state; 1128 } 1129 EXPORT_SYMBOL_GPL(pci_store_saved_state); 1130 1131 /** 1132 * pci_load_saved_state - Reload the provided save state into struct pci_dev. 1133 * @dev: PCI device that we're dealing with 1134 * @state: Saved state returned from pci_store_saved_state() 1135 */ 1136 int pci_load_saved_state(struct pci_dev *dev, struct pci_saved_state *state) 1137 { 1138 struct pci_cap_saved_data *cap; 1139 1140 dev->state_saved = false; 1141 1142 if (!state) 1143 return 0; 1144 1145 memcpy(dev->saved_config_space, state->config_space, 1146 sizeof(state->config_space)); 1147 1148 cap = state->cap; 1149 while (cap->size) { 1150 struct pci_cap_saved_state *tmp; 1151 1152 tmp = pci_find_saved_cap(dev, cap->cap_nr); 1153 if (!tmp || tmp->cap.size != cap->size) 1154 return -EINVAL; 1155 1156 memcpy(tmp->cap.data, cap->data, tmp->cap.size); 1157 cap = (struct pci_cap_saved_data *)((u8 *)cap + 1158 sizeof(struct pci_cap_saved_data) + cap->size); 1159 } 1160 1161 dev->state_saved = true; 1162 return 0; 1163 } 1164 EXPORT_SYMBOL_GPL(pci_load_saved_state); 1165 1166 /** 1167 * pci_load_and_free_saved_state - Reload the save state pointed to by state, 1168 * and free the memory allocated for it. 1169 * @dev: PCI device that we're dealing with 1170 * @state: Pointer to saved state returned from pci_store_saved_state() 1171 */ 1172 int pci_load_and_free_saved_state(struct pci_dev *dev, 1173 struct pci_saved_state **state) 1174 { 1175 int ret = pci_load_saved_state(dev, *state); 1176 kfree(*state); 1177 *state = NULL; 1178 return ret; 1179 } 1180 EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state); 1181 1182 static int do_pci_enable_device(struct pci_dev *dev, int bars) 1183 { 1184 int err; 1185 1186 err = pci_set_power_state(dev, PCI_D0); 1187 if (err < 0 && err != -EIO) 1188 return err; 1189 err = pcibios_enable_device(dev, bars); 1190 if (err < 0) 1191 return err; 1192 pci_fixup_device(pci_fixup_enable, dev); 1193 1194 return 0; 1195 } 1196 1197 /** 1198 * pci_reenable_device - Resume abandoned device 1199 * @dev: PCI device to be resumed 1200 * 1201 * Note this function is a backend of pci_default_resume and is not supposed 1202 * to be called by normal code, write proper resume handler and use it instead. 1203 */ 1204 int pci_reenable_device(struct pci_dev *dev) 1205 { 1206 if (pci_is_enabled(dev)) 1207 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1); 1208 return 0; 1209 } 1210 1211 static int __pci_enable_device_flags(struct pci_dev *dev, 1212 resource_size_t flags) 1213 { 1214 int err; 1215 int i, bars = 0; 1216 1217 /* 1218 * Power state could be unknown at this point, either due to a fresh 1219 * boot or a device removal call. So get the current power state 1220 * so that things like MSI message writing will behave as expected 1221 * (e.g. if the device really is in D0 at enable time). 1222 */ 1223 if (dev->pm_cap) { 1224 u16 pmcsr; 1225 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); 1226 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); 1227 } 1228 1229 if (atomic_add_return(1, &dev->enable_cnt) > 1) 1230 return 0; /* already enabled */ 1231 1232 /* only skip sriov related */ 1233 for (i = 0; i <= PCI_ROM_RESOURCE; i++) 1234 if (dev->resource[i].flags & flags) 1235 bars |= (1 << i); 1236 for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++) 1237 if (dev->resource[i].flags & flags) 1238 bars |= (1 << i); 1239 1240 err = do_pci_enable_device(dev, bars); 1241 if (err < 0) 1242 atomic_dec(&dev->enable_cnt); 1243 return err; 1244 } 1245 1246 /** 1247 * pci_enable_device_io - Initialize a device for use with IO space 1248 * @dev: PCI device to be initialized 1249 * 1250 * Initialize device before it's used by a driver. Ask low-level code 1251 * to enable I/O resources. Wake up the device if it was suspended. 1252 * Beware, this function can fail. 1253 */ 1254 int pci_enable_device_io(struct pci_dev *dev) 1255 { 1256 return __pci_enable_device_flags(dev, IORESOURCE_IO); 1257 } 1258 1259 /** 1260 * pci_enable_device_mem - Initialize a device for use with Memory space 1261 * @dev: PCI device to be initialized 1262 * 1263 * Initialize device before it's used by a driver. Ask low-level code 1264 * to enable Memory resources. Wake up the device if it was suspended. 1265 * Beware, this function can fail. 1266 */ 1267 int pci_enable_device_mem(struct pci_dev *dev) 1268 { 1269 return __pci_enable_device_flags(dev, IORESOURCE_MEM); 1270 } 1271 1272 /** 1273 * pci_enable_device - Initialize device before it's used by a driver. 1274 * @dev: PCI device to be initialized 1275 * 1276 * Initialize device before it's used by a driver. Ask low-level code 1277 * to enable I/O and memory. Wake up the device if it was suspended. 1278 * Beware, this function can fail. 1279 * 1280 * Note we don't actually enable the device many times if we call 1281 * this function repeatedly (we just increment the count). 1282 */ 1283 int pci_enable_device(struct pci_dev *dev) 1284 { 1285 return __pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO); 1286 } 1287 1288 /* 1289 * Managed PCI resources. This manages device on/off, intx/msi/msix 1290 * on/off and BAR regions. pci_dev itself records msi/msix status, so 1291 * there's no need to track it separately. pci_devres is initialized 1292 * when a device is enabled using managed PCI device enable interface. 1293 */ 1294 struct pci_devres { 1295 unsigned int enabled:1; 1296 unsigned int pinned:1; 1297 unsigned int orig_intx:1; 1298 unsigned int restore_intx:1; 1299 u32 region_mask; 1300 }; 1301 1302 static void pcim_release(struct device *gendev, void *res) 1303 { 1304 struct pci_dev *dev = container_of(gendev, struct pci_dev, dev); 1305 struct pci_devres *this = res; 1306 int i; 1307 1308 if (dev->msi_enabled) 1309 pci_disable_msi(dev); 1310 if (dev->msix_enabled) 1311 pci_disable_msix(dev); 1312 1313 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) 1314 if (this->region_mask & (1 << i)) 1315 pci_release_region(dev, i); 1316 1317 if (this->restore_intx) 1318 pci_intx(dev, this->orig_intx); 1319 1320 if (this->enabled && !this->pinned) 1321 pci_disable_device(dev); 1322 } 1323 1324 static struct pci_devres * get_pci_dr(struct pci_dev *pdev) 1325 { 1326 struct pci_devres *dr, *new_dr; 1327 1328 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL); 1329 if (dr) 1330 return dr; 1331 1332 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL); 1333 if (!new_dr) 1334 return NULL; 1335 return devres_get(&pdev->dev, new_dr, NULL, NULL); 1336 } 1337 1338 static struct pci_devres * find_pci_dr(struct pci_dev *pdev) 1339 { 1340 if (pci_is_managed(pdev)) 1341 return devres_find(&pdev->dev, pcim_release, NULL, NULL); 1342 return NULL; 1343 } 1344 1345 /** 1346 * pcim_enable_device - Managed pci_enable_device() 1347 * @pdev: PCI device to be initialized 1348 * 1349 * Managed pci_enable_device(). 1350 */ 1351 int pcim_enable_device(struct pci_dev *pdev) 1352 { 1353 struct pci_devres *dr; 1354 int rc; 1355 1356 dr = get_pci_dr(pdev); 1357 if (unlikely(!dr)) 1358 return -ENOMEM; 1359 if (dr->enabled) 1360 return 0; 1361 1362 rc = pci_enable_device(pdev); 1363 if (!rc) { 1364 pdev->is_managed = 1; 1365 dr->enabled = 1; 1366 } 1367 return rc; 1368 } 1369 1370 /** 1371 * pcim_pin_device - Pin managed PCI device 1372 * @pdev: PCI device to pin 1373 * 1374 * Pin managed PCI device @pdev. Pinned device won't be disabled on 1375 * driver detach. @pdev must have been enabled with 1376 * pcim_enable_device(). 1377 */ 1378 void pcim_pin_device(struct pci_dev *pdev) 1379 { 1380 struct pci_devres *dr; 1381 1382 dr = find_pci_dr(pdev); 1383 WARN_ON(!dr || !dr->enabled); 1384 if (dr) 1385 dr->pinned = 1; 1386 } 1387 1388 /** 1389 * pcibios_disable_device - disable arch specific PCI resources for device dev 1390 * @dev: the PCI device to disable 1391 * 1392 * Disables architecture specific PCI resources for the device. This 1393 * is the default implementation. Architecture implementations can 1394 * override this. 1395 */ 1396 void __weak pcibios_disable_device (struct pci_dev *dev) {} 1397 1398 static void do_pci_disable_device(struct pci_dev *dev) 1399 { 1400 u16 pci_command; 1401 1402 pci_read_config_word(dev, PCI_COMMAND, &pci_command); 1403 if (pci_command & PCI_COMMAND_MASTER) { 1404 pci_command &= ~PCI_COMMAND_MASTER; 1405 pci_write_config_word(dev, PCI_COMMAND, pci_command); 1406 } 1407 1408 pcibios_disable_device(dev); 1409 } 1410 1411 /** 1412 * pci_disable_enabled_device - Disable device without updating enable_cnt 1413 * @dev: PCI device to disable 1414 * 1415 * NOTE: This function is a backend of PCI power management routines and is 1416 * not supposed to be called drivers. 1417 */ 1418 void pci_disable_enabled_device(struct pci_dev *dev) 1419 { 1420 if (pci_is_enabled(dev)) 1421 do_pci_disable_device(dev); 1422 } 1423 1424 /** 1425 * pci_disable_device - Disable PCI device after use 1426 * @dev: PCI device to be disabled 1427 * 1428 * Signal to the system that the PCI device is not in use by the system 1429 * anymore. This only involves disabling PCI bus-mastering, if active. 1430 * 1431 * Note we don't actually disable the device until all callers of 1432 * pci_enable_device() have called pci_disable_device(). 1433 */ 1434 void 1435 pci_disable_device(struct pci_dev *dev) 1436 { 1437 struct pci_devres *dr; 1438 1439 dr = find_pci_dr(dev); 1440 if (dr) 1441 dr->enabled = 0; 1442 1443 if (atomic_sub_return(1, &dev->enable_cnt) != 0) 1444 return; 1445 1446 do_pci_disable_device(dev); 1447 1448 dev->is_busmaster = 0; 1449 } 1450 1451 /** 1452 * pcibios_set_pcie_reset_state - set reset state for device dev 1453 * @dev: the PCIe device reset 1454 * @state: Reset state to enter into 1455 * 1456 * 1457 * Sets the PCIe reset state for the device. This is the default 1458 * implementation. Architecture implementations can override this. 1459 */ 1460 int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev, 1461 enum pcie_reset_state state) 1462 { 1463 return -EINVAL; 1464 } 1465 1466 /** 1467 * pci_set_pcie_reset_state - set reset state for device dev 1468 * @dev: the PCIe device reset 1469 * @state: Reset state to enter into 1470 * 1471 * 1472 * Sets the PCI reset state for the device. 1473 */ 1474 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state) 1475 { 1476 return pcibios_set_pcie_reset_state(dev, state); 1477 } 1478 1479 /** 1480 * pci_check_pme_status - Check if given device has generated PME. 1481 * @dev: Device to check. 1482 * 1483 * Check the PME status of the device and if set, clear it and clear PME enable 1484 * (if set). Return 'true' if PME status and PME enable were both set or 1485 * 'false' otherwise. 1486 */ 1487 bool pci_check_pme_status(struct pci_dev *dev) 1488 { 1489 int pmcsr_pos; 1490 u16 pmcsr; 1491 bool ret = false; 1492 1493 if (!dev->pm_cap) 1494 return false; 1495 1496 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL; 1497 pci_read_config_word(dev, pmcsr_pos, &pmcsr); 1498 if (!(pmcsr & PCI_PM_CTRL_PME_STATUS)) 1499 return false; 1500 1501 /* Clear PME status. */ 1502 pmcsr |= PCI_PM_CTRL_PME_STATUS; 1503 if (pmcsr & PCI_PM_CTRL_PME_ENABLE) { 1504 /* Disable PME to avoid interrupt flood. */ 1505 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE; 1506 ret = true; 1507 } 1508 1509 pci_write_config_word(dev, pmcsr_pos, pmcsr); 1510 1511 return ret; 1512 } 1513 1514 /** 1515 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set. 1516 * @dev: Device to handle. 1517 * @pme_poll_reset: Whether or not to reset the device's pme_poll flag. 1518 * 1519 * Check if @dev has generated PME and queue a resume request for it in that 1520 * case. 1521 */ 1522 static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset) 1523 { 1524 if (pme_poll_reset && dev->pme_poll) 1525 dev->pme_poll = false; 1526 1527 if (pci_check_pme_status(dev)) { 1528 pci_wakeup_event(dev); 1529 pm_request_resume(&dev->dev); 1530 } 1531 return 0; 1532 } 1533 1534 /** 1535 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary. 1536 * @bus: Top bus of the subtree to walk. 1537 */ 1538 void pci_pme_wakeup_bus(struct pci_bus *bus) 1539 { 1540 if (bus) 1541 pci_walk_bus(bus, pci_pme_wakeup, (void *)true); 1542 } 1543 1544 /** 1545 * pci_wakeup - Wake up a PCI device 1546 * @dev: Device to handle. 1547 * @ign: ignored parameter 1548 */ 1549 static int pci_wakeup(struct pci_dev *pci_dev, void *ign) 1550 { 1551 pci_wakeup_event(pci_dev); 1552 pm_request_resume(&pci_dev->dev); 1553 return 0; 1554 } 1555 1556 /** 1557 * pci_wakeup_bus - Walk given bus and wake up devices on it 1558 * @bus: Top bus of the subtree to walk. 1559 */ 1560 void pci_wakeup_bus(struct pci_bus *bus) 1561 { 1562 if (bus) 1563 pci_walk_bus(bus, pci_wakeup, NULL); 1564 } 1565 1566 /** 1567 * pci_pme_capable - check the capability of PCI device to generate PME# 1568 * @dev: PCI device to handle. 1569 * @state: PCI state from which device will issue PME#. 1570 */ 1571 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state) 1572 { 1573 if (!dev->pm_cap) 1574 return false; 1575 1576 return !!(dev->pme_support & (1 << state)); 1577 } 1578 1579 static void pci_pme_list_scan(struct work_struct *work) 1580 { 1581 struct pci_pme_device *pme_dev, *n; 1582 1583 mutex_lock(&pci_pme_list_mutex); 1584 if (!list_empty(&pci_pme_list)) { 1585 list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) { 1586 if (pme_dev->dev->pme_poll) { 1587 struct pci_dev *bridge; 1588 1589 bridge = pme_dev->dev->bus->self; 1590 /* 1591 * If bridge is in low power state, the 1592 * configuration space of subordinate devices 1593 * may be not accessible 1594 */ 1595 if (bridge && bridge->current_state != PCI_D0) 1596 continue; 1597 pci_pme_wakeup(pme_dev->dev, NULL); 1598 } else { 1599 list_del(&pme_dev->list); 1600 kfree(pme_dev); 1601 } 1602 } 1603 if (!list_empty(&pci_pme_list)) 1604 schedule_delayed_work(&pci_pme_work, 1605 msecs_to_jiffies(PME_TIMEOUT)); 1606 } 1607 mutex_unlock(&pci_pme_list_mutex); 1608 } 1609 1610 /** 1611 * pci_pme_active - enable or disable PCI device's PME# function 1612 * @dev: PCI device to handle. 1613 * @enable: 'true' to enable PME# generation; 'false' to disable it. 1614 * 1615 * The caller must verify that the device is capable of generating PME# before 1616 * calling this function with @enable equal to 'true'. 1617 */ 1618 void pci_pme_active(struct pci_dev *dev, bool enable) 1619 { 1620 u16 pmcsr; 1621 1622 if (!dev->pm_cap) 1623 return; 1624 1625 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); 1626 /* Clear PME_Status by writing 1 to it and enable PME# */ 1627 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE; 1628 if (!enable) 1629 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE; 1630 1631 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); 1632 1633 /* PCI (as opposed to PCIe) PME requires that the device have 1634 its PME# line hooked up correctly. Not all hardware vendors 1635 do this, so the PME never gets delivered and the device 1636 remains asleep. The easiest way around this is to 1637 periodically walk the list of suspended devices and check 1638 whether any have their PME flag set. The assumption is that 1639 we'll wake up often enough anyway that this won't be a huge 1640 hit, and the power savings from the devices will still be a 1641 win. */ 1642 1643 if (dev->pme_poll) { 1644 struct pci_pme_device *pme_dev; 1645 if (enable) { 1646 pme_dev = kmalloc(sizeof(struct pci_pme_device), 1647 GFP_KERNEL); 1648 if (!pme_dev) 1649 goto out; 1650 pme_dev->dev = dev; 1651 mutex_lock(&pci_pme_list_mutex); 1652 list_add(&pme_dev->list, &pci_pme_list); 1653 if (list_is_singular(&pci_pme_list)) 1654 schedule_delayed_work(&pci_pme_work, 1655 msecs_to_jiffies(PME_TIMEOUT)); 1656 mutex_unlock(&pci_pme_list_mutex); 1657 } else { 1658 mutex_lock(&pci_pme_list_mutex); 1659 list_for_each_entry(pme_dev, &pci_pme_list, list) { 1660 if (pme_dev->dev == dev) { 1661 list_del(&pme_dev->list); 1662 kfree(pme_dev); 1663 break; 1664 } 1665 } 1666 mutex_unlock(&pci_pme_list_mutex); 1667 } 1668 } 1669 1670 out: 1671 dev_dbg(&dev->dev, "PME# %s\n", enable ? "enabled" : "disabled"); 1672 } 1673 1674 /** 1675 * __pci_enable_wake - enable PCI device as wakeup event source 1676 * @dev: PCI device affected 1677 * @state: PCI state from which device will issue wakeup events 1678 * @runtime: True if the events are to be generated at run time 1679 * @enable: True to enable event generation; false to disable 1680 * 1681 * This enables the device as a wakeup event source, or disables it. 1682 * When such events involves platform-specific hooks, those hooks are 1683 * called automatically by this routine. 1684 * 1685 * Devices with legacy power management (no standard PCI PM capabilities) 1686 * always require such platform hooks. 1687 * 1688 * RETURN VALUE: 1689 * 0 is returned on success 1690 * -EINVAL is returned if device is not supposed to wake up the system 1691 * Error code depending on the platform is returned if both the platform and 1692 * the native mechanism fail to enable the generation of wake-up events 1693 */ 1694 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, 1695 bool runtime, bool enable) 1696 { 1697 int ret = 0; 1698 1699 if (enable && !runtime && !device_may_wakeup(&dev->dev)) 1700 return -EINVAL; 1701 1702 /* Don't do the same thing twice in a row for one device. */ 1703 if (!!enable == !!dev->wakeup_prepared) 1704 return 0; 1705 1706 /* 1707 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don 1708 * Anderson we should be doing PME# wake enable followed by ACPI wake 1709 * enable. To disable wake-up we call the platform first, for symmetry. 1710 */ 1711 1712 if (enable) { 1713 int error; 1714 1715 if (pci_pme_capable(dev, state)) 1716 pci_pme_active(dev, true); 1717 else 1718 ret = 1; 1719 error = runtime ? platform_pci_run_wake(dev, true) : 1720 platform_pci_sleep_wake(dev, true); 1721 if (ret) 1722 ret = error; 1723 if (!ret) 1724 dev->wakeup_prepared = true; 1725 } else { 1726 if (runtime) 1727 platform_pci_run_wake(dev, false); 1728 else 1729 platform_pci_sleep_wake(dev, false); 1730 pci_pme_active(dev, false); 1731 dev->wakeup_prepared = false; 1732 } 1733 1734 return ret; 1735 } 1736 EXPORT_SYMBOL(__pci_enable_wake); 1737 1738 /** 1739 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold 1740 * @dev: PCI device to prepare 1741 * @enable: True to enable wake-up event generation; false to disable 1742 * 1743 * Many drivers want the device to wake up the system from D3_hot or D3_cold 1744 * and this function allows them to set that up cleanly - pci_enable_wake() 1745 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI 1746 * ordering constraints. 1747 * 1748 * This function only returns error code if the device is not capable of 1749 * generating PME# from both D3_hot and D3_cold, and the platform is unable to 1750 * enable wake-up power for it. 1751 */ 1752 int pci_wake_from_d3(struct pci_dev *dev, bool enable) 1753 { 1754 return pci_pme_capable(dev, PCI_D3cold) ? 1755 pci_enable_wake(dev, PCI_D3cold, enable) : 1756 pci_enable_wake(dev, PCI_D3hot, enable); 1757 } 1758 1759 /** 1760 * pci_target_state - find an appropriate low power state for a given PCI dev 1761 * @dev: PCI device 1762 * 1763 * Use underlying platform code to find a supported low power state for @dev. 1764 * If the platform can't manage @dev, return the deepest state from which it 1765 * can generate wake events, based on any available PME info. 1766 */ 1767 pci_power_t pci_target_state(struct pci_dev *dev) 1768 { 1769 pci_power_t target_state = PCI_D3hot; 1770 1771 if (platform_pci_power_manageable(dev)) { 1772 /* 1773 * Call the platform to choose the target state of the device 1774 * and enable wake-up from this state if supported. 1775 */ 1776 pci_power_t state = platform_pci_choose_state(dev); 1777 1778 switch (state) { 1779 case PCI_POWER_ERROR: 1780 case PCI_UNKNOWN: 1781 break; 1782 case PCI_D1: 1783 case PCI_D2: 1784 if (pci_no_d1d2(dev)) 1785 break; 1786 default: 1787 target_state = state; 1788 } 1789 } else if (!dev->pm_cap) { 1790 target_state = PCI_D0; 1791 } else if (device_may_wakeup(&dev->dev)) { 1792 /* 1793 * Find the deepest state from which the device can generate 1794 * wake-up events, make it the target state and enable device 1795 * to generate PME#. 1796 */ 1797 if (dev->pme_support) { 1798 while (target_state 1799 && !(dev->pme_support & (1 << target_state))) 1800 target_state--; 1801 } 1802 } 1803 1804 return target_state; 1805 } 1806 1807 /** 1808 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state 1809 * @dev: Device to handle. 1810 * 1811 * Choose the power state appropriate for the device depending on whether 1812 * it can wake up the system and/or is power manageable by the platform 1813 * (PCI_D3hot is the default) and put the device into that state. 1814 */ 1815 int pci_prepare_to_sleep(struct pci_dev *dev) 1816 { 1817 pci_power_t target_state = pci_target_state(dev); 1818 int error; 1819 1820 if (target_state == PCI_POWER_ERROR) 1821 return -EIO; 1822 1823 /* D3cold during system suspend/hibernate is not supported */ 1824 if (target_state > PCI_D3hot) 1825 target_state = PCI_D3hot; 1826 1827 pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev)); 1828 1829 error = pci_set_power_state(dev, target_state); 1830 1831 if (error) 1832 pci_enable_wake(dev, target_state, false); 1833 1834 return error; 1835 } 1836 1837 /** 1838 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state 1839 * @dev: Device to handle. 1840 * 1841 * Disable device's system wake-up capability and put it into D0. 1842 */ 1843 int pci_back_from_sleep(struct pci_dev *dev) 1844 { 1845 pci_enable_wake(dev, PCI_D0, false); 1846 return pci_set_power_state(dev, PCI_D0); 1847 } 1848 1849 /** 1850 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend. 1851 * @dev: PCI device being suspended. 1852 * 1853 * Prepare @dev to generate wake-up events at run time and put it into a low 1854 * power state. 1855 */ 1856 int pci_finish_runtime_suspend(struct pci_dev *dev) 1857 { 1858 pci_power_t target_state = pci_target_state(dev); 1859 int error; 1860 1861 if (target_state == PCI_POWER_ERROR) 1862 return -EIO; 1863 1864 dev->runtime_d3cold = target_state == PCI_D3cold; 1865 1866 __pci_enable_wake(dev, target_state, true, pci_dev_run_wake(dev)); 1867 1868 error = pci_set_power_state(dev, target_state); 1869 1870 if (error) { 1871 __pci_enable_wake(dev, target_state, true, false); 1872 dev->runtime_d3cold = false; 1873 } 1874 1875 return error; 1876 } 1877 1878 /** 1879 * pci_dev_run_wake - Check if device can generate run-time wake-up events. 1880 * @dev: Device to check. 1881 * 1882 * Return true if the device itself is cabable of generating wake-up events 1883 * (through the platform or using the native PCIe PME) or if the device supports 1884 * PME and one of its upstream bridges can generate wake-up events. 1885 */ 1886 bool pci_dev_run_wake(struct pci_dev *dev) 1887 { 1888 struct pci_bus *bus = dev->bus; 1889 1890 if (device_run_wake(&dev->dev)) 1891 return true; 1892 1893 if (!dev->pme_support) 1894 return false; 1895 1896 while (bus->parent) { 1897 struct pci_dev *bridge = bus->self; 1898 1899 if (device_run_wake(&bridge->dev)) 1900 return true; 1901 1902 bus = bus->parent; 1903 } 1904 1905 /* We have reached the root bus. */ 1906 if (bus->bridge) 1907 return device_run_wake(bus->bridge); 1908 1909 return false; 1910 } 1911 EXPORT_SYMBOL_GPL(pci_dev_run_wake); 1912 1913 /** 1914 * pci_pm_init - Initialize PM functions of given PCI device 1915 * @dev: PCI device to handle. 1916 */ 1917 void pci_pm_init(struct pci_dev *dev) 1918 { 1919 int pm; 1920 u16 pmc; 1921 1922 pm_runtime_forbid(&dev->dev); 1923 device_enable_async_suspend(&dev->dev); 1924 dev->wakeup_prepared = false; 1925 1926 dev->pm_cap = 0; 1927 1928 /* find PCI PM capability in list */ 1929 pm = pci_find_capability(dev, PCI_CAP_ID_PM); 1930 if (!pm) 1931 return; 1932 /* Check device's ability to generate PME# */ 1933 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc); 1934 1935 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) { 1936 dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n", 1937 pmc & PCI_PM_CAP_VER_MASK); 1938 return; 1939 } 1940 1941 dev->pm_cap = pm; 1942 dev->d3_delay = PCI_PM_D3_WAIT; 1943 dev->d3cold_delay = PCI_PM_D3COLD_WAIT; 1944 dev->d3cold_allowed = true; 1945 1946 dev->d1_support = false; 1947 dev->d2_support = false; 1948 if (!pci_no_d1d2(dev)) { 1949 if (pmc & PCI_PM_CAP_D1) 1950 dev->d1_support = true; 1951 if (pmc & PCI_PM_CAP_D2) 1952 dev->d2_support = true; 1953 1954 if (dev->d1_support || dev->d2_support) 1955 dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n", 1956 dev->d1_support ? " D1" : "", 1957 dev->d2_support ? " D2" : ""); 1958 } 1959 1960 pmc &= PCI_PM_CAP_PME_MASK; 1961 if (pmc) { 1962 dev_printk(KERN_DEBUG, &dev->dev, 1963 "PME# supported from%s%s%s%s%s\n", 1964 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "", 1965 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "", 1966 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "", 1967 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "", 1968 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : ""); 1969 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT; 1970 dev->pme_poll = true; 1971 /* 1972 * Make device's PM flags reflect the wake-up capability, but 1973 * let the user space enable it to wake up the system as needed. 1974 */ 1975 device_set_wakeup_capable(&dev->dev, true); 1976 /* Disable the PME# generation functionality */ 1977 pci_pme_active(dev, false); 1978 } else { 1979 dev->pme_support = 0; 1980 } 1981 } 1982 1983 /** 1984 * platform_pci_wakeup_init - init platform wakeup if present 1985 * @dev: PCI device 1986 * 1987 * Some devices don't have PCI PM caps but can still generate wakeup 1988 * events through platform methods (like ACPI events). If @dev supports 1989 * platform wakeup events, set the device flag to indicate as much. This 1990 * may be redundant if the device also supports PCI PM caps, but double 1991 * initialization should be safe in that case. 1992 */ 1993 void platform_pci_wakeup_init(struct pci_dev *dev) 1994 { 1995 if (!platform_pci_can_wakeup(dev)) 1996 return; 1997 1998 device_set_wakeup_capable(&dev->dev, true); 1999 platform_pci_sleep_wake(dev, false); 2000 } 2001 2002 static void pci_add_saved_cap(struct pci_dev *pci_dev, 2003 struct pci_cap_saved_state *new_cap) 2004 { 2005 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space); 2006 } 2007 2008 /** 2009 * pci_add_save_buffer - allocate buffer for saving given capability registers 2010 * @dev: the PCI device 2011 * @cap: the capability to allocate the buffer for 2012 * @size: requested size of the buffer 2013 */ 2014 static int pci_add_cap_save_buffer( 2015 struct pci_dev *dev, char cap, unsigned int size) 2016 { 2017 int pos; 2018 struct pci_cap_saved_state *save_state; 2019 2020 pos = pci_find_capability(dev, cap); 2021 if (pos <= 0) 2022 return 0; 2023 2024 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL); 2025 if (!save_state) 2026 return -ENOMEM; 2027 2028 save_state->cap.cap_nr = cap; 2029 save_state->cap.size = size; 2030 pci_add_saved_cap(dev, save_state); 2031 2032 return 0; 2033 } 2034 2035 /** 2036 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities 2037 * @dev: the PCI device 2038 */ 2039 void pci_allocate_cap_save_buffers(struct pci_dev *dev) 2040 { 2041 int error; 2042 2043 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP, 2044 PCI_EXP_SAVE_REGS * sizeof(u16)); 2045 if (error) 2046 dev_err(&dev->dev, 2047 "unable to preallocate PCI Express save buffer\n"); 2048 2049 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16)); 2050 if (error) 2051 dev_err(&dev->dev, 2052 "unable to preallocate PCI-X save buffer\n"); 2053 } 2054 2055 void pci_free_cap_save_buffers(struct pci_dev *dev) 2056 { 2057 struct pci_cap_saved_state *tmp; 2058 struct hlist_node *pos, *n; 2059 2060 hlist_for_each_entry_safe(tmp, pos, n, &dev->saved_cap_space, next) 2061 kfree(tmp); 2062 } 2063 2064 /** 2065 * pci_enable_ari - enable ARI forwarding if hardware support it 2066 * @dev: the PCI device 2067 */ 2068 void pci_enable_ari(struct pci_dev *dev) 2069 { 2070 int pos; 2071 u32 cap; 2072 u16 ctrl; 2073 struct pci_dev *bridge; 2074 2075 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn) 2076 return; 2077 2078 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI); 2079 if (!pos) 2080 return; 2081 2082 bridge = dev->bus->self; 2083 if (!bridge) 2084 return; 2085 2086 /* ARI is a PCIe cap v2 feature */ 2087 pos = pci_pcie_cap2(bridge); 2088 if (!pos) 2089 return; 2090 2091 pci_read_config_dword(bridge, pos + PCI_EXP_DEVCAP2, &cap); 2092 if (!(cap & PCI_EXP_DEVCAP2_ARI)) 2093 return; 2094 2095 pci_read_config_word(bridge, pos + PCI_EXP_DEVCTL2, &ctrl); 2096 ctrl |= PCI_EXP_DEVCTL2_ARI; 2097 pci_write_config_word(bridge, pos + PCI_EXP_DEVCTL2, ctrl); 2098 2099 bridge->ari_enabled = 1; 2100 } 2101 2102 /** 2103 * pci_enable_ido - enable ID-based Ordering on a device 2104 * @dev: the PCI device 2105 * @type: which types of IDO to enable 2106 * 2107 * Enable ID-based ordering on @dev. @type can contain the bits 2108 * %PCI_EXP_IDO_REQUEST and/or %PCI_EXP_IDO_COMPLETION to indicate 2109 * which types of transactions are allowed to be re-ordered. 2110 */ 2111 void pci_enable_ido(struct pci_dev *dev, unsigned long type) 2112 { 2113 int pos; 2114 u16 ctrl; 2115 2116 /* ID-based Ordering is a PCIe cap v2 feature */ 2117 pos = pci_pcie_cap2(dev); 2118 if (!pos) 2119 return; 2120 2121 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl); 2122 if (type & PCI_EXP_IDO_REQUEST) 2123 ctrl |= PCI_EXP_IDO_REQ_EN; 2124 if (type & PCI_EXP_IDO_COMPLETION) 2125 ctrl |= PCI_EXP_IDO_CMP_EN; 2126 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl); 2127 } 2128 EXPORT_SYMBOL(pci_enable_ido); 2129 2130 /** 2131 * pci_disable_ido - disable ID-based ordering on a device 2132 * @dev: the PCI device 2133 * @type: which types of IDO to disable 2134 */ 2135 void pci_disable_ido(struct pci_dev *dev, unsigned long type) 2136 { 2137 int pos; 2138 u16 ctrl; 2139 2140 /* ID-based Ordering is a PCIe cap v2 feature */ 2141 pos = pci_pcie_cap2(dev); 2142 if (!pos) 2143 return; 2144 2145 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl); 2146 if (type & PCI_EXP_IDO_REQUEST) 2147 ctrl &= ~PCI_EXP_IDO_REQ_EN; 2148 if (type & PCI_EXP_IDO_COMPLETION) 2149 ctrl &= ~PCI_EXP_IDO_CMP_EN; 2150 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl); 2151 } 2152 EXPORT_SYMBOL(pci_disable_ido); 2153 2154 /** 2155 * pci_enable_obff - enable optimized buffer flush/fill 2156 * @dev: PCI device 2157 * @type: type of signaling to use 2158 * 2159 * Try to enable @type OBFF signaling on @dev. It will try using WAKE# 2160 * signaling if possible, falling back to message signaling only if 2161 * WAKE# isn't supported. @type should indicate whether the PCIe link 2162 * be brought out of L0s or L1 to send the message. It should be either 2163 * %PCI_EXP_OBFF_SIGNAL_ALWAYS or %PCI_OBFF_SIGNAL_L0. 2164 * 2165 * If your device can benefit from receiving all messages, even at the 2166 * power cost of bringing the link back up from a low power state, use 2167 * %PCI_EXP_OBFF_SIGNAL_ALWAYS. Otherwise, use %PCI_OBFF_SIGNAL_L0 (the 2168 * preferred type). 2169 * 2170 * RETURNS: 2171 * Zero on success, appropriate error number on failure. 2172 */ 2173 int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type type) 2174 { 2175 int pos; 2176 u32 cap; 2177 u16 ctrl; 2178 int ret; 2179 2180 /* OBFF is a PCIe cap v2 feature */ 2181 pos = pci_pcie_cap2(dev); 2182 if (!pos) 2183 return -ENOTSUPP; 2184 2185 pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP2, &cap); 2186 if (!(cap & PCI_EXP_OBFF_MASK)) 2187 return -ENOTSUPP; /* no OBFF support at all */ 2188 2189 /* Make sure the topology supports OBFF as well */ 2190 if (dev->bus->self) { 2191 ret = pci_enable_obff(dev->bus->self, type); 2192 if (ret) 2193 return ret; 2194 } 2195 2196 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl); 2197 if (cap & PCI_EXP_OBFF_WAKE) 2198 ctrl |= PCI_EXP_OBFF_WAKE_EN; 2199 else { 2200 switch (type) { 2201 case PCI_EXP_OBFF_SIGNAL_L0: 2202 if (!(ctrl & PCI_EXP_OBFF_WAKE_EN)) 2203 ctrl |= PCI_EXP_OBFF_MSGA_EN; 2204 break; 2205 case PCI_EXP_OBFF_SIGNAL_ALWAYS: 2206 ctrl &= ~PCI_EXP_OBFF_WAKE_EN; 2207 ctrl |= PCI_EXP_OBFF_MSGB_EN; 2208 break; 2209 default: 2210 WARN(1, "bad OBFF signal type\n"); 2211 return -ENOTSUPP; 2212 } 2213 } 2214 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl); 2215 2216 return 0; 2217 } 2218 EXPORT_SYMBOL(pci_enable_obff); 2219 2220 /** 2221 * pci_disable_obff - disable optimized buffer flush/fill 2222 * @dev: PCI device 2223 * 2224 * Disable OBFF on @dev. 2225 */ 2226 void pci_disable_obff(struct pci_dev *dev) 2227 { 2228 int pos; 2229 u16 ctrl; 2230 2231 /* OBFF is a PCIe cap v2 feature */ 2232 pos = pci_pcie_cap2(dev); 2233 if (!pos) 2234 return; 2235 2236 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl); 2237 ctrl &= ~PCI_EXP_OBFF_WAKE_EN; 2238 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl); 2239 } 2240 EXPORT_SYMBOL(pci_disable_obff); 2241 2242 /** 2243 * pci_ltr_supported - check whether a device supports LTR 2244 * @dev: PCI device 2245 * 2246 * RETURNS: 2247 * True if @dev supports latency tolerance reporting, false otherwise. 2248 */ 2249 static bool pci_ltr_supported(struct pci_dev *dev) 2250 { 2251 int pos; 2252 u32 cap; 2253 2254 /* LTR is a PCIe cap v2 feature */ 2255 pos = pci_pcie_cap2(dev); 2256 if (!pos) 2257 return false; 2258 2259 pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP2, &cap); 2260 2261 return cap & PCI_EXP_DEVCAP2_LTR; 2262 } 2263 2264 /** 2265 * pci_enable_ltr - enable latency tolerance reporting 2266 * @dev: PCI device 2267 * 2268 * Enable LTR on @dev if possible, which means enabling it first on 2269 * upstream ports. 2270 * 2271 * RETURNS: 2272 * Zero on success, errno on failure. 2273 */ 2274 int pci_enable_ltr(struct pci_dev *dev) 2275 { 2276 int pos; 2277 u16 ctrl; 2278 int ret; 2279 2280 if (!pci_ltr_supported(dev)) 2281 return -ENOTSUPP; 2282 2283 /* LTR is a PCIe cap v2 feature */ 2284 pos = pci_pcie_cap2(dev); 2285 if (!pos) 2286 return -ENOTSUPP; 2287 2288 /* Only primary function can enable/disable LTR */ 2289 if (PCI_FUNC(dev->devfn) != 0) 2290 return -EINVAL; 2291 2292 /* Enable upstream ports first */ 2293 if (dev->bus->self) { 2294 ret = pci_enable_ltr(dev->bus->self); 2295 if (ret) 2296 return ret; 2297 } 2298 2299 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl); 2300 ctrl |= PCI_EXP_LTR_EN; 2301 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl); 2302 2303 return 0; 2304 } 2305 EXPORT_SYMBOL(pci_enable_ltr); 2306 2307 /** 2308 * pci_disable_ltr - disable latency tolerance reporting 2309 * @dev: PCI device 2310 */ 2311 void pci_disable_ltr(struct pci_dev *dev) 2312 { 2313 int pos; 2314 u16 ctrl; 2315 2316 if (!pci_ltr_supported(dev)) 2317 return; 2318 2319 /* LTR is a PCIe cap v2 feature */ 2320 pos = pci_pcie_cap2(dev); 2321 if (!pos) 2322 return; 2323 2324 /* Only primary function can enable/disable LTR */ 2325 if (PCI_FUNC(dev->devfn) != 0) 2326 return; 2327 2328 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl); 2329 ctrl &= ~PCI_EXP_LTR_EN; 2330 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl); 2331 } 2332 EXPORT_SYMBOL(pci_disable_ltr); 2333 2334 static int __pci_ltr_scale(int *val) 2335 { 2336 int scale = 0; 2337 2338 while (*val > 1023) { 2339 *val = (*val + 31) / 32; 2340 scale++; 2341 } 2342 return scale; 2343 } 2344 2345 /** 2346 * pci_set_ltr - set LTR latency values 2347 * @dev: PCI device 2348 * @snoop_lat_ns: snoop latency in nanoseconds 2349 * @nosnoop_lat_ns: nosnoop latency in nanoseconds 2350 * 2351 * Figure out the scale and set the LTR values accordingly. 2352 */ 2353 int pci_set_ltr(struct pci_dev *dev, int snoop_lat_ns, int nosnoop_lat_ns) 2354 { 2355 int pos, ret, snoop_scale, nosnoop_scale; 2356 u16 val; 2357 2358 if (!pci_ltr_supported(dev)) 2359 return -ENOTSUPP; 2360 2361 snoop_scale = __pci_ltr_scale(&snoop_lat_ns); 2362 nosnoop_scale = __pci_ltr_scale(&nosnoop_lat_ns); 2363 2364 if (snoop_lat_ns > PCI_LTR_VALUE_MASK || 2365 nosnoop_lat_ns > PCI_LTR_VALUE_MASK) 2366 return -EINVAL; 2367 2368 if ((snoop_scale > (PCI_LTR_SCALE_MASK >> PCI_LTR_SCALE_SHIFT)) || 2369 (nosnoop_scale > (PCI_LTR_SCALE_MASK >> PCI_LTR_SCALE_SHIFT))) 2370 return -EINVAL; 2371 2372 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR); 2373 if (!pos) 2374 return -ENOTSUPP; 2375 2376 val = (snoop_scale << PCI_LTR_SCALE_SHIFT) | snoop_lat_ns; 2377 ret = pci_write_config_word(dev, pos + PCI_LTR_MAX_SNOOP_LAT, val); 2378 if (ret != 4) 2379 return -EIO; 2380 2381 val = (nosnoop_scale << PCI_LTR_SCALE_SHIFT) | nosnoop_lat_ns; 2382 ret = pci_write_config_word(dev, pos + PCI_LTR_MAX_NOSNOOP_LAT, val); 2383 if (ret != 4) 2384 return -EIO; 2385 2386 return 0; 2387 } 2388 EXPORT_SYMBOL(pci_set_ltr); 2389 2390 static int pci_acs_enable; 2391 2392 /** 2393 * pci_request_acs - ask for ACS to be enabled if supported 2394 */ 2395 void pci_request_acs(void) 2396 { 2397 pci_acs_enable = 1; 2398 } 2399 2400 /** 2401 * pci_enable_acs - enable ACS if hardware support it 2402 * @dev: the PCI device 2403 */ 2404 void pci_enable_acs(struct pci_dev *dev) 2405 { 2406 int pos; 2407 u16 cap; 2408 u16 ctrl; 2409 2410 if (!pci_acs_enable) 2411 return; 2412 2413 if (!pci_is_pcie(dev)) 2414 return; 2415 2416 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS); 2417 if (!pos) 2418 return; 2419 2420 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap); 2421 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl); 2422 2423 /* Source Validation */ 2424 ctrl |= (cap & PCI_ACS_SV); 2425 2426 /* P2P Request Redirect */ 2427 ctrl |= (cap & PCI_ACS_RR); 2428 2429 /* P2P Completion Redirect */ 2430 ctrl |= (cap & PCI_ACS_CR); 2431 2432 /* Upstream Forwarding */ 2433 ctrl |= (cap & PCI_ACS_UF); 2434 2435 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl); 2436 } 2437 2438 /** 2439 * pci_acs_enabled - test ACS against required flags for a given device 2440 * @pdev: device to test 2441 * @acs_flags: required PCI ACS flags 2442 * 2443 * Return true if the device supports the provided flags. Automatically 2444 * filters out flags that are not implemented on multifunction devices. 2445 */ 2446 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags) 2447 { 2448 int pos, ret; 2449 u16 ctrl; 2450 2451 ret = pci_dev_specific_acs_enabled(pdev, acs_flags); 2452 if (ret >= 0) 2453 return ret > 0; 2454 2455 if (!pci_is_pcie(pdev)) 2456 return false; 2457 2458 /* Filter out flags not applicable to multifunction */ 2459 if (pdev->multifunction) 2460 acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | 2461 PCI_ACS_EC | PCI_ACS_DT); 2462 2463 if (pdev->pcie_type == PCI_EXP_TYPE_DOWNSTREAM || 2464 pdev->pcie_type == PCI_EXP_TYPE_ROOT_PORT || 2465 pdev->multifunction) { 2466 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ACS); 2467 if (!pos) 2468 return false; 2469 2470 pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl); 2471 if ((ctrl & acs_flags) != acs_flags) 2472 return false; 2473 } 2474 2475 return true; 2476 } 2477 2478 /** 2479 * pci_acs_path_enable - test ACS flags from start to end in a hierarchy 2480 * @start: starting downstream device 2481 * @end: ending upstream device or NULL to search to the root bus 2482 * @acs_flags: required flags 2483 * 2484 * Walk up a device tree from start to end testing PCI ACS support. If 2485 * any step along the way does not support the required flags, return false. 2486 */ 2487 bool pci_acs_path_enabled(struct pci_dev *start, 2488 struct pci_dev *end, u16 acs_flags) 2489 { 2490 struct pci_dev *pdev, *parent = start; 2491 2492 do { 2493 pdev = parent; 2494 2495 if (!pci_acs_enabled(pdev, acs_flags)) 2496 return false; 2497 2498 if (pci_is_root_bus(pdev->bus)) 2499 return (end == NULL); 2500 2501 parent = pdev->bus->self; 2502 } while (pdev != end); 2503 2504 return true; 2505 } 2506 2507 /** 2508 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge 2509 * @dev: the PCI device 2510 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTD, 4=INTD) 2511 * 2512 * Perform INTx swizzling for a device behind one level of bridge. This is 2513 * required by section 9.1 of the PCI-to-PCI bridge specification for devices 2514 * behind bridges on add-in cards. For devices with ARI enabled, the slot 2515 * number is always 0 (see the Implementation Note in section 2.2.8.1 of 2516 * the PCI Express Base Specification, Revision 2.1) 2517 */ 2518 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin) 2519 { 2520 int slot; 2521 2522 if (pci_ari_enabled(dev->bus)) 2523 slot = 0; 2524 else 2525 slot = PCI_SLOT(dev->devfn); 2526 2527 return (((pin - 1) + slot) % 4) + 1; 2528 } 2529 2530 int 2531 pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge) 2532 { 2533 u8 pin; 2534 2535 pin = dev->pin; 2536 if (!pin) 2537 return -1; 2538 2539 while (!pci_is_root_bus(dev->bus)) { 2540 pin = pci_swizzle_interrupt_pin(dev, pin); 2541 dev = dev->bus->self; 2542 } 2543 *bridge = dev; 2544 return pin; 2545 } 2546 2547 /** 2548 * pci_common_swizzle - swizzle INTx all the way to root bridge 2549 * @dev: the PCI device 2550 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD) 2551 * 2552 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI 2553 * bridges all the way up to a PCI root bus. 2554 */ 2555 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp) 2556 { 2557 u8 pin = *pinp; 2558 2559 while (!pci_is_root_bus(dev->bus)) { 2560 pin = pci_swizzle_interrupt_pin(dev, pin); 2561 dev = dev->bus->self; 2562 } 2563 *pinp = pin; 2564 return PCI_SLOT(dev->devfn); 2565 } 2566 2567 /** 2568 * pci_release_region - Release a PCI bar 2569 * @pdev: PCI device whose resources were previously reserved by pci_request_region 2570 * @bar: BAR to release 2571 * 2572 * Releases the PCI I/O and memory resources previously reserved by a 2573 * successful call to pci_request_region. Call this function only 2574 * after all use of the PCI regions has ceased. 2575 */ 2576 void pci_release_region(struct pci_dev *pdev, int bar) 2577 { 2578 struct pci_devres *dr; 2579 2580 if (pci_resource_len(pdev, bar) == 0) 2581 return; 2582 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) 2583 release_region(pci_resource_start(pdev, bar), 2584 pci_resource_len(pdev, bar)); 2585 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) 2586 release_mem_region(pci_resource_start(pdev, bar), 2587 pci_resource_len(pdev, bar)); 2588 2589 dr = find_pci_dr(pdev); 2590 if (dr) 2591 dr->region_mask &= ~(1 << bar); 2592 } 2593 2594 /** 2595 * __pci_request_region - Reserved PCI I/O and memory resource 2596 * @pdev: PCI device whose resources are to be reserved 2597 * @bar: BAR to be reserved 2598 * @res_name: Name to be associated with resource. 2599 * @exclusive: whether the region access is exclusive or not 2600 * 2601 * Mark the PCI region associated with PCI device @pdev BR @bar as 2602 * being reserved by owner @res_name. Do not access any 2603 * address inside the PCI regions unless this call returns 2604 * successfully. 2605 * 2606 * If @exclusive is set, then the region is marked so that userspace 2607 * is explicitly not allowed to map the resource via /dev/mem or 2608 * sysfs MMIO access. 2609 * 2610 * Returns 0 on success, or %EBUSY on error. A warning 2611 * message is also printed on failure. 2612 */ 2613 static int __pci_request_region(struct pci_dev *pdev, int bar, const char *res_name, 2614 int exclusive) 2615 { 2616 struct pci_devres *dr; 2617 2618 if (pci_resource_len(pdev, bar) == 0) 2619 return 0; 2620 2621 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) { 2622 if (!request_region(pci_resource_start(pdev, bar), 2623 pci_resource_len(pdev, bar), res_name)) 2624 goto err_out; 2625 } 2626 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) { 2627 if (!__request_mem_region(pci_resource_start(pdev, bar), 2628 pci_resource_len(pdev, bar), res_name, 2629 exclusive)) 2630 goto err_out; 2631 } 2632 2633 dr = find_pci_dr(pdev); 2634 if (dr) 2635 dr->region_mask |= 1 << bar; 2636 2637 return 0; 2638 2639 err_out: 2640 dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar, 2641 &pdev->resource[bar]); 2642 return -EBUSY; 2643 } 2644 2645 /** 2646 * pci_request_region - Reserve PCI I/O and memory resource 2647 * @pdev: PCI device whose resources are to be reserved 2648 * @bar: BAR to be reserved 2649 * @res_name: Name to be associated with resource 2650 * 2651 * Mark the PCI region associated with PCI device @pdev BAR @bar as 2652 * being reserved by owner @res_name. Do not access any 2653 * address inside the PCI regions unless this call returns 2654 * successfully. 2655 * 2656 * Returns 0 on success, or %EBUSY on error. A warning 2657 * message is also printed on failure. 2658 */ 2659 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) 2660 { 2661 return __pci_request_region(pdev, bar, res_name, 0); 2662 } 2663 2664 /** 2665 * pci_request_region_exclusive - Reserved PCI I/O and memory resource 2666 * @pdev: PCI device whose resources are to be reserved 2667 * @bar: BAR to be reserved 2668 * @res_name: Name to be associated with resource. 2669 * 2670 * Mark the PCI region associated with PCI device @pdev BR @bar as 2671 * being reserved by owner @res_name. Do not access any 2672 * address inside the PCI regions unless this call returns 2673 * successfully. 2674 * 2675 * Returns 0 on success, or %EBUSY on error. A warning 2676 * message is also printed on failure. 2677 * 2678 * The key difference that _exclusive makes it that userspace is 2679 * explicitly not allowed to map the resource via /dev/mem or 2680 * sysfs. 2681 */ 2682 int pci_request_region_exclusive(struct pci_dev *pdev, int bar, const char *res_name) 2683 { 2684 return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE); 2685 } 2686 /** 2687 * pci_release_selected_regions - Release selected PCI I/O and memory resources 2688 * @pdev: PCI device whose resources were previously reserved 2689 * @bars: Bitmask of BARs to be released 2690 * 2691 * Release selected PCI I/O and memory resources previously reserved. 2692 * Call this function only after all use of the PCI regions has ceased. 2693 */ 2694 void pci_release_selected_regions(struct pci_dev *pdev, int bars) 2695 { 2696 int i; 2697 2698 for (i = 0; i < 6; i++) 2699 if (bars & (1 << i)) 2700 pci_release_region(pdev, i); 2701 } 2702 2703 int __pci_request_selected_regions(struct pci_dev *pdev, int bars, 2704 const char *res_name, int excl) 2705 { 2706 int i; 2707 2708 for (i = 0; i < 6; i++) 2709 if (bars & (1 << i)) 2710 if (__pci_request_region(pdev, i, res_name, excl)) 2711 goto err_out; 2712 return 0; 2713 2714 err_out: 2715 while(--i >= 0) 2716 if (bars & (1 << i)) 2717 pci_release_region(pdev, i); 2718 2719 return -EBUSY; 2720 } 2721 2722 2723 /** 2724 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources 2725 * @pdev: PCI device whose resources are to be reserved 2726 * @bars: Bitmask of BARs to be requested 2727 * @res_name: Name to be associated with resource 2728 */ 2729 int pci_request_selected_regions(struct pci_dev *pdev, int bars, 2730 const char *res_name) 2731 { 2732 return __pci_request_selected_regions(pdev, bars, res_name, 0); 2733 } 2734 2735 int pci_request_selected_regions_exclusive(struct pci_dev *pdev, 2736 int bars, const char *res_name) 2737 { 2738 return __pci_request_selected_regions(pdev, bars, res_name, 2739 IORESOURCE_EXCLUSIVE); 2740 } 2741 2742 /** 2743 * pci_release_regions - Release reserved PCI I/O and memory resources 2744 * @pdev: PCI device whose resources were previously reserved by pci_request_regions 2745 * 2746 * Releases all PCI I/O and memory resources previously reserved by a 2747 * successful call to pci_request_regions. Call this function only 2748 * after all use of the PCI regions has ceased. 2749 */ 2750 2751 void pci_release_regions(struct pci_dev *pdev) 2752 { 2753 pci_release_selected_regions(pdev, (1 << 6) - 1); 2754 } 2755 2756 /** 2757 * pci_request_regions - Reserved PCI I/O and memory resources 2758 * @pdev: PCI device whose resources are to be reserved 2759 * @res_name: Name to be associated with resource. 2760 * 2761 * Mark all PCI regions associated with PCI device @pdev as 2762 * being reserved by owner @res_name. Do not access any 2763 * address inside the PCI regions unless this call returns 2764 * successfully. 2765 * 2766 * Returns 0 on success, or %EBUSY on error. A warning 2767 * message is also printed on failure. 2768 */ 2769 int pci_request_regions(struct pci_dev *pdev, const char *res_name) 2770 { 2771 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name); 2772 } 2773 2774 /** 2775 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources 2776 * @pdev: PCI device whose resources are to be reserved 2777 * @res_name: Name to be associated with resource. 2778 * 2779 * Mark all PCI regions associated with PCI device @pdev as 2780 * being reserved by owner @res_name. Do not access any 2781 * address inside the PCI regions unless this call returns 2782 * successfully. 2783 * 2784 * pci_request_regions_exclusive() will mark the region so that 2785 * /dev/mem and the sysfs MMIO access will not be allowed. 2786 * 2787 * Returns 0 on success, or %EBUSY on error. A warning 2788 * message is also printed on failure. 2789 */ 2790 int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name) 2791 { 2792 return pci_request_selected_regions_exclusive(pdev, 2793 ((1 << 6) - 1), res_name); 2794 } 2795 2796 static void __pci_set_master(struct pci_dev *dev, bool enable) 2797 { 2798 u16 old_cmd, cmd; 2799 2800 pci_read_config_word(dev, PCI_COMMAND, &old_cmd); 2801 if (enable) 2802 cmd = old_cmd | PCI_COMMAND_MASTER; 2803 else 2804 cmd = old_cmd & ~PCI_COMMAND_MASTER; 2805 if (cmd != old_cmd) { 2806 dev_dbg(&dev->dev, "%s bus mastering\n", 2807 enable ? "enabling" : "disabling"); 2808 pci_write_config_word(dev, PCI_COMMAND, cmd); 2809 } 2810 dev->is_busmaster = enable; 2811 } 2812 2813 /** 2814 * pcibios_setup - process "pci=" kernel boot arguments 2815 * @str: string used to pass in "pci=" kernel boot arguments 2816 * 2817 * Process kernel boot arguments. This is the default implementation. 2818 * Architecture specific implementations can override this as necessary. 2819 */ 2820 char * __weak __init pcibios_setup(char *str) 2821 { 2822 return str; 2823 } 2824 2825 /** 2826 * pcibios_set_master - enable PCI bus-mastering for device dev 2827 * @dev: the PCI device to enable 2828 * 2829 * Enables PCI bus-mastering for the device. This is the default 2830 * implementation. Architecture specific implementations can override 2831 * this if necessary. 2832 */ 2833 void __weak pcibios_set_master(struct pci_dev *dev) 2834 { 2835 u8 lat; 2836 2837 /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */ 2838 if (pci_is_pcie(dev)) 2839 return; 2840 2841 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat); 2842 if (lat < 16) 2843 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency; 2844 else if (lat > pcibios_max_latency) 2845 lat = pcibios_max_latency; 2846 else 2847 return; 2848 dev_printk(KERN_DEBUG, &dev->dev, "setting latency timer to %d\n", lat); 2849 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat); 2850 } 2851 2852 /** 2853 * pci_set_master - enables bus-mastering for device dev 2854 * @dev: the PCI device to enable 2855 * 2856 * Enables bus-mastering on the device and calls pcibios_set_master() 2857 * to do the needed arch specific settings. 2858 */ 2859 void pci_set_master(struct pci_dev *dev) 2860 { 2861 __pci_set_master(dev, true); 2862 pcibios_set_master(dev); 2863 } 2864 2865 /** 2866 * pci_clear_master - disables bus-mastering for device dev 2867 * @dev: the PCI device to disable 2868 */ 2869 void pci_clear_master(struct pci_dev *dev) 2870 { 2871 __pci_set_master(dev, false); 2872 } 2873 2874 /** 2875 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed 2876 * @dev: the PCI device for which MWI is to be enabled 2877 * 2878 * Helper function for pci_set_mwi. 2879 * Originally copied from drivers/net/acenic.c. 2880 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. 2881 * 2882 * RETURNS: An appropriate -ERRNO error value on error, or zero for success. 2883 */ 2884 int pci_set_cacheline_size(struct pci_dev *dev) 2885 { 2886 u8 cacheline_size; 2887 2888 if (!pci_cache_line_size) 2889 return -EINVAL; 2890 2891 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be 2892 equal to or multiple of the right value. */ 2893 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); 2894 if (cacheline_size >= pci_cache_line_size && 2895 (cacheline_size % pci_cache_line_size) == 0) 2896 return 0; 2897 2898 /* Write the correct value. */ 2899 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size); 2900 /* Read it back. */ 2901 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); 2902 if (cacheline_size == pci_cache_line_size) 2903 return 0; 2904 2905 dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not " 2906 "supported\n", pci_cache_line_size << 2); 2907 2908 return -EINVAL; 2909 } 2910 EXPORT_SYMBOL_GPL(pci_set_cacheline_size); 2911 2912 #ifdef PCI_DISABLE_MWI 2913 int pci_set_mwi(struct pci_dev *dev) 2914 { 2915 return 0; 2916 } 2917 2918 int pci_try_set_mwi(struct pci_dev *dev) 2919 { 2920 return 0; 2921 } 2922 2923 void pci_clear_mwi(struct pci_dev *dev) 2924 { 2925 } 2926 2927 #else 2928 2929 /** 2930 * pci_set_mwi - enables memory-write-invalidate PCI transaction 2931 * @dev: the PCI device for which MWI is enabled 2932 * 2933 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. 2934 * 2935 * RETURNS: An appropriate -ERRNO error value on error, or zero for success. 2936 */ 2937 int 2938 pci_set_mwi(struct pci_dev *dev) 2939 { 2940 int rc; 2941 u16 cmd; 2942 2943 rc = pci_set_cacheline_size(dev); 2944 if (rc) 2945 return rc; 2946 2947 pci_read_config_word(dev, PCI_COMMAND, &cmd); 2948 if (! (cmd & PCI_COMMAND_INVALIDATE)) { 2949 dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n"); 2950 cmd |= PCI_COMMAND_INVALIDATE; 2951 pci_write_config_word(dev, PCI_COMMAND, cmd); 2952 } 2953 2954 return 0; 2955 } 2956 2957 /** 2958 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction 2959 * @dev: the PCI device for which MWI is enabled 2960 * 2961 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. 2962 * Callers are not required to check the return value. 2963 * 2964 * RETURNS: An appropriate -ERRNO error value on error, or zero for success. 2965 */ 2966 int pci_try_set_mwi(struct pci_dev *dev) 2967 { 2968 int rc = pci_set_mwi(dev); 2969 return rc; 2970 } 2971 2972 /** 2973 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev 2974 * @dev: the PCI device to disable 2975 * 2976 * Disables PCI Memory-Write-Invalidate transaction on the device 2977 */ 2978 void 2979 pci_clear_mwi(struct pci_dev *dev) 2980 { 2981 u16 cmd; 2982 2983 pci_read_config_word(dev, PCI_COMMAND, &cmd); 2984 if (cmd & PCI_COMMAND_INVALIDATE) { 2985 cmd &= ~PCI_COMMAND_INVALIDATE; 2986 pci_write_config_word(dev, PCI_COMMAND, cmd); 2987 } 2988 } 2989 #endif /* ! PCI_DISABLE_MWI */ 2990 2991 /** 2992 * pci_intx - enables/disables PCI INTx for device dev 2993 * @pdev: the PCI device to operate on 2994 * @enable: boolean: whether to enable or disable PCI INTx 2995 * 2996 * Enables/disables PCI INTx for device dev 2997 */ 2998 void 2999 pci_intx(struct pci_dev *pdev, int enable) 3000 { 3001 u16 pci_command, new; 3002 3003 pci_read_config_word(pdev, PCI_COMMAND, &pci_command); 3004 3005 if (enable) { 3006 new = pci_command & ~PCI_COMMAND_INTX_DISABLE; 3007 } else { 3008 new = pci_command | PCI_COMMAND_INTX_DISABLE; 3009 } 3010 3011 if (new != pci_command) { 3012 struct pci_devres *dr; 3013 3014 pci_write_config_word(pdev, PCI_COMMAND, new); 3015 3016 dr = find_pci_dr(pdev); 3017 if (dr && !dr->restore_intx) { 3018 dr->restore_intx = 1; 3019 dr->orig_intx = !enable; 3020 } 3021 } 3022 } 3023 3024 /** 3025 * pci_intx_mask_supported - probe for INTx masking support 3026 * @dev: the PCI device to operate on 3027 * 3028 * Check if the device dev support INTx masking via the config space 3029 * command word. 3030 */ 3031 bool pci_intx_mask_supported(struct pci_dev *dev) 3032 { 3033 bool mask_supported = false; 3034 u16 orig, new; 3035 3036 if (dev->broken_intx_masking) 3037 return false; 3038 3039 pci_cfg_access_lock(dev); 3040 3041 pci_read_config_word(dev, PCI_COMMAND, &orig); 3042 pci_write_config_word(dev, PCI_COMMAND, 3043 orig ^ PCI_COMMAND_INTX_DISABLE); 3044 pci_read_config_word(dev, PCI_COMMAND, &new); 3045 3046 /* 3047 * There's no way to protect against hardware bugs or detect them 3048 * reliably, but as long as we know what the value should be, let's 3049 * go ahead and check it. 3050 */ 3051 if ((new ^ orig) & ~PCI_COMMAND_INTX_DISABLE) { 3052 dev_err(&dev->dev, "Command register changed from " 3053 "0x%x to 0x%x: driver or hardware bug?\n", orig, new); 3054 } else if ((new ^ orig) & PCI_COMMAND_INTX_DISABLE) { 3055 mask_supported = true; 3056 pci_write_config_word(dev, PCI_COMMAND, orig); 3057 } 3058 3059 pci_cfg_access_unlock(dev); 3060 return mask_supported; 3061 } 3062 EXPORT_SYMBOL_GPL(pci_intx_mask_supported); 3063 3064 static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask) 3065 { 3066 struct pci_bus *bus = dev->bus; 3067 bool mask_updated = true; 3068 u32 cmd_status_dword; 3069 u16 origcmd, newcmd; 3070 unsigned long flags; 3071 bool irq_pending; 3072 3073 /* 3074 * We do a single dword read to retrieve both command and status. 3075 * Document assumptions that make this possible. 3076 */ 3077 BUILD_BUG_ON(PCI_COMMAND % 4); 3078 BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS); 3079 3080 raw_spin_lock_irqsave(&pci_lock, flags); 3081 3082 bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword); 3083 3084 irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT; 3085 3086 /* 3087 * Check interrupt status register to see whether our device 3088 * triggered the interrupt (when masking) or the next IRQ is 3089 * already pending (when unmasking). 3090 */ 3091 if (mask != irq_pending) { 3092 mask_updated = false; 3093 goto done; 3094 } 3095 3096 origcmd = cmd_status_dword; 3097 newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE; 3098 if (mask) 3099 newcmd |= PCI_COMMAND_INTX_DISABLE; 3100 if (newcmd != origcmd) 3101 bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd); 3102 3103 done: 3104 raw_spin_unlock_irqrestore(&pci_lock, flags); 3105 3106 return mask_updated; 3107 } 3108 3109 /** 3110 * pci_check_and_mask_intx - mask INTx on pending interrupt 3111 * @dev: the PCI device to operate on 3112 * 3113 * Check if the device dev has its INTx line asserted, mask it and 3114 * return true in that case. False is returned if not interrupt was 3115 * pending. 3116 */ 3117 bool pci_check_and_mask_intx(struct pci_dev *dev) 3118 { 3119 return pci_check_and_set_intx_mask(dev, true); 3120 } 3121 EXPORT_SYMBOL_GPL(pci_check_and_mask_intx); 3122 3123 /** 3124 * pci_check_and_mask_intx - unmask INTx of no interrupt is pending 3125 * @dev: the PCI device to operate on 3126 * 3127 * Check if the device dev has its INTx line asserted, unmask it if not 3128 * and return true. False is returned and the mask remains active if 3129 * there was still an interrupt pending. 3130 */ 3131 bool pci_check_and_unmask_intx(struct pci_dev *dev) 3132 { 3133 return pci_check_and_set_intx_mask(dev, false); 3134 } 3135 EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx); 3136 3137 /** 3138 * pci_msi_off - disables any msi or msix capabilities 3139 * @dev: the PCI device to operate on 3140 * 3141 * If you want to use msi see pci_enable_msi and friends. 3142 * This is a lower level primitive that allows us to disable 3143 * msi operation at the device level. 3144 */ 3145 void pci_msi_off(struct pci_dev *dev) 3146 { 3147 int pos; 3148 u16 control; 3149 3150 pos = pci_find_capability(dev, PCI_CAP_ID_MSI); 3151 if (pos) { 3152 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); 3153 control &= ~PCI_MSI_FLAGS_ENABLE; 3154 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); 3155 } 3156 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); 3157 if (pos) { 3158 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); 3159 control &= ~PCI_MSIX_FLAGS_ENABLE; 3160 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); 3161 } 3162 } 3163 EXPORT_SYMBOL_GPL(pci_msi_off); 3164 3165 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size) 3166 { 3167 return dma_set_max_seg_size(&dev->dev, size); 3168 } 3169 EXPORT_SYMBOL(pci_set_dma_max_seg_size); 3170 3171 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask) 3172 { 3173 return dma_set_seg_boundary(&dev->dev, mask); 3174 } 3175 EXPORT_SYMBOL(pci_set_dma_seg_boundary); 3176 3177 static int pcie_flr(struct pci_dev *dev, int probe) 3178 { 3179 int i; 3180 int pos; 3181 u32 cap; 3182 u16 status, control; 3183 3184 pos = pci_pcie_cap(dev); 3185 if (!pos) 3186 return -ENOTTY; 3187 3188 pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP, &cap); 3189 if (!(cap & PCI_EXP_DEVCAP_FLR)) 3190 return -ENOTTY; 3191 3192 if (probe) 3193 return 0; 3194 3195 /* Wait for Transaction Pending bit clean */ 3196 for (i = 0; i < 4; i++) { 3197 if (i) 3198 msleep((1 << (i - 1)) * 100); 3199 3200 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status); 3201 if (!(status & PCI_EXP_DEVSTA_TRPND)) 3202 goto clear; 3203 } 3204 3205 dev_err(&dev->dev, "transaction is not cleared; " 3206 "proceeding with reset anyway\n"); 3207 3208 clear: 3209 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &control); 3210 control |= PCI_EXP_DEVCTL_BCR_FLR; 3211 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, control); 3212 3213 msleep(100); 3214 3215 return 0; 3216 } 3217 3218 static int pci_af_flr(struct pci_dev *dev, int probe) 3219 { 3220 int i; 3221 int pos; 3222 u8 cap; 3223 u8 status; 3224 3225 pos = pci_find_capability(dev, PCI_CAP_ID_AF); 3226 if (!pos) 3227 return -ENOTTY; 3228 3229 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap); 3230 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR)) 3231 return -ENOTTY; 3232 3233 if (probe) 3234 return 0; 3235 3236 /* Wait for Transaction Pending bit clean */ 3237 for (i = 0; i < 4; i++) { 3238 if (i) 3239 msleep((1 << (i - 1)) * 100); 3240 3241 pci_read_config_byte(dev, pos + PCI_AF_STATUS, &status); 3242 if (!(status & PCI_AF_STATUS_TP)) 3243 goto clear; 3244 } 3245 3246 dev_err(&dev->dev, "transaction is not cleared; " 3247 "proceeding with reset anyway\n"); 3248 3249 clear: 3250 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR); 3251 msleep(100); 3252 3253 return 0; 3254 } 3255 3256 /** 3257 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0. 3258 * @dev: Device to reset. 3259 * @probe: If set, only check if the device can be reset this way. 3260 * 3261 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is 3262 * unset, it will be reinitialized internally when going from PCI_D3hot to 3263 * PCI_D0. If that's the case and the device is not in a low-power state 3264 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset. 3265 * 3266 * NOTE: This causes the caller to sleep for twice the device power transition 3267 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms 3268 * by devault (i.e. unless the @dev's d3_delay field has a different value). 3269 * Moreover, only devices in D0 can be reset by this function. 3270 */ 3271 static int pci_pm_reset(struct pci_dev *dev, int probe) 3272 { 3273 u16 csr; 3274 3275 if (!dev->pm_cap) 3276 return -ENOTTY; 3277 3278 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr); 3279 if (csr & PCI_PM_CTRL_NO_SOFT_RESET) 3280 return -ENOTTY; 3281 3282 if (probe) 3283 return 0; 3284 3285 if (dev->current_state != PCI_D0) 3286 return -EINVAL; 3287 3288 csr &= ~PCI_PM_CTRL_STATE_MASK; 3289 csr |= PCI_D3hot; 3290 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); 3291 pci_dev_d3_sleep(dev); 3292 3293 csr &= ~PCI_PM_CTRL_STATE_MASK; 3294 csr |= PCI_D0; 3295 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); 3296 pci_dev_d3_sleep(dev); 3297 3298 return 0; 3299 } 3300 3301 static int pci_parent_bus_reset(struct pci_dev *dev, int probe) 3302 { 3303 u16 ctrl; 3304 struct pci_dev *pdev; 3305 3306 if (pci_is_root_bus(dev->bus) || dev->subordinate || !dev->bus->self) 3307 return -ENOTTY; 3308 3309 list_for_each_entry(pdev, &dev->bus->devices, bus_list) 3310 if (pdev != dev) 3311 return -ENOTTY; 3312 3313 if (probe) 3314 return 0; 3315 3316 pci_read_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, &ctrl); 3317 ctrl |= PCI_BRIDGE_CTL_BUS_RESET; 3318 pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl); 3319 msleep(100); 3320 3321 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET; 3322 pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl); 3323 msleep(100); 3324 3325 return 0; 3326 } 3327 3328 static int __pci_dev_reset(struct pci_dev *dev, int probe) 3329 { 3330 int rc; 3331 3332 might_sleep(); 3333 3334 rc = pci_dev_specific_reset(dev, probe); 3335 if (rc != -ENOTTY) 3336 goto done; 3337 3338 rc = pcie_flr(dev, probe); 3339 if (rc != -ENOTTY) 3340 goto done; 3341 3342 rc = pci_af_flr(dev, probe); 3343 if (rc != -ENOTTY) 3344 goto done; 3345 3346 rc = pci_pm_reset(dev, probe); 3347 if (rc != -ENOTTY) 3348 goto done; 3349 3350 rc = pci_parent_bus_reset(dev, probe); 3351 done: 3352 return rc; 3353 } 3354 3355 static int pci_dev_reset(struct pci_dev *dev, int probe) 3356 { 3357 int rc; 3358 3359 if (!probe) { 3360 pci_cfg_access_lock(dev); 3361 /* block PM suspend, driver probe, etc. */ 3362 device_lock(&dev->dev); 3363 } 3364 3365 rc = __pci_dev_reset(dev, probe); 3366 3367 if (!probe) { 3368 device_unlock(&dev->dev); 3369 pci_cfg_access_unlock(dev); 3370 } 3371 return rc; 3372 } 3373 /** 3374 * __pci_reset_function - reset a PCI device function 3375 * @dev: PCI device to reset 3376 * 3377 * Some devices allow an individual function to be reset without affecting 3378 * other functions in the same device. The PCI device must be responsive 3379 * to PCI config space in order to use this function. 3380 * 3381 * The device function is presumed to be unused when this function is called. 3382 * Resetting the device will make the contents of PCI configuration space 3383 * random, so any caller of this must be prepared to reinitialise the 3384 * device including MSI, bus mastering, BARs, decoding IO and memory spaces, 3385 * etc. 3386 * 3387 * Returns 0 if the device function was successfully reset or negative if the 3388 * device doesn't support resetting a single function. 3389 */ 3390 int __pci_reset_function(struct pci_dev *dev) 3391 { 3392 return pci_dev_reset(dev, 0); 3393 } 3394 EXPORT_SYMBOL_GPL(__pci_reset_function); 3395 3396 /** 3397 * __pci_reset_function_locked - reset a PCI device function while holding 3398 * the @dev mutex lock. 3399 * @dev: PCI device to reset 3400 * 3401 * Some devices allow an individual function to be reset without affecting 3402 * other functions in the same device. The PCI device must be responsive 3403 * to PCI config space in order to use this function. 3404 * 3405 * The device function is presumed to be unused and the caller is holding 3406 * the device mutex lock when this function is called. 3407 * Resetting the device will make the contents of PCI configuration space 3408 * random, so any caller of this must be prepared to reinitialise the 3409 * device including MSI, bus mastering, BARs, decoding IO and memory spaces, 3410 * etc. 3411 * 3412 * Returns 0 if the device function was successfully reset or negative if the 3413 * device doesn't support resetting a single function. 3414 */ 3415 int __pci_reset_function_locked(struct pci_dev *dev) 3416 { 3417 return __pci_dev_reset(dev, 0); 3418 } 3419 EXPORT_SYMBOL_GPL(__pci_reset_function_locked); 3420 3421 /** 3422 * pci_probe_reset_function - check whether the device can be safely reset 3423 * @dev: PCI device to reset 3424 * 3425 * Some devices allow an individual function to be reset without affecting 3426 * other functions in the same device. The PCI device must be responsive 3427 * to PCI config space in order to use this function. 3428 * 3429 * Returns 0 if the device function can be reset or negative if the 3430 * device doesn't support resetting a single function. 3431 */ 3432 int pci_probe_reset_function(struct pci_dev *dev) 3433 { 3434 return pci_dev_reset(dev, 1); 3435 } 3436 3437 /** 3438 * pci_reset_function - quiesce and reset a PCI device function 3439 * @dev: PCI device to reset 3440 * 3441 * Some devices allow an individual function to be reset without affecting 3442 * other functions in the same device. The PCI device must be responsive 3443 * to PCI config space in order to use this function. 3444 * 3445 * This function does not just reset the PCI portion of a device, but 3446 * clears all the state associated with the device. This function differs 3447 * from __pci_reset_function in that it saves and restores device state 3448 * over the reset. 3449 * 3450 * Returns 0 if the device function was successfully reset or negative if the 3451 * device doesn't support resetting a single function. 3452 */ 3453 int pci_reset_function(struct pci_dev *dev) 3454 { 3455 int rc; 3456 3457 rc = pci_dev_reset(dev, 1); 3458 if (rc) 3459 return rc; 3460 3461 pci_save_state(dev); 3462 3463 /* 3464 * both INTx and MSI are disabled after the Interrupt Disable bit 3465 * is set and the Bus Master bit is cleared. 3466 */ 3467 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE); 3468 3469 rc = pci_dev_reset(dev, 0); 3470 3471 pci_restore_state(dev); 3472 3473 return rc; 3474 } 3475 EXPORT_SYMBOL_GPL(pci_reset_function); 3476 3477 /** 3478 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count 3479 * @dev: PCI device to query 3480 * 3481 * Returns mmrbc: maximum designed memory read count in bytes 3482 * or appropriate error value. 3483 */ 3484 int pcix_get_max_mmrbc(struct pci_dev *dev) 3485 { 3486 int cap; 3487 u32 stat; 3488 3489 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); 3490 if (!cap) 3491 return -EINVAL; 3492 3493 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat)) 3494 return -EINVAL; 3495 3496 return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21); 3497 } 3498 EXPORT_SYMBOL(pcix_get_max_mmrbc); 3499 3500 /** 3501 * pcix_get_mmrbc - get PCI-X maximum memory read byte count 3502 * @dev: PCI device to query 3503 * 3504 * Returns mmrbc: maximum memory read count in bytes 3505 * or appropriate error value. 3506 */ 3507 int pcix_get_mmrbc(struct pci_dev *dev) 3508 { 3509 int cap; 3510 u16 cmd; 3511 3512 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); 3513 if (!cap) 3514 return -EINVAL; 3515 3516 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd)) 3517 return -EINVAL; 3518 3519 return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2); 3520 } 3521 EXPORT_SYMBOL(pcix_get_mmrbc); 3522 3523 /** 3524 * pcix_set_mmrbc - set PCI-X maximum memory read byte count 3525 * @dev: PCI device to query 3526 * @mmrbc: maximum memory read count in bytes 3527 * valid values are 512, 1024, 2048, 4096 3528 * 3529 * If possible sets maximum memory read byte count, some bridges have erratas 3530 * that prevent this. 3531 */ 3532 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc) 3533 { 3534 int cap; 3535 u32 stat, v, o; 3536 u16 cmd; 3537 3538 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc)) 3539 return -EINVAL; 3540 3541 v = ffs(mmrbc) - 10; 3542 3543 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); 3544 if (!cap) 3545 return -EINVAL; 3546 3547 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat)) 3548 return -EINVAL; 3549 3550 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21) 3551 return -E2BIG; 3552 3553 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd)) 3554 return -EINVAL; 3555 3556 o = (cmd & PCI_X_CMD_MAX_READ) >> 2; 3557 if (o != v) { 3558 if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC)) 3559 return -EIO; 3560 3561 cmd &= ~PCI_X_CMD_MAX_READ; 3562 cmd |= v << 2; 3563 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd)) 3564 return -EIO; 3565 } 3566 return 0; 3567 } 3568 EXPORT_SYMBOL(pcix_set_mmrbc); 3569 3570 /** 3571 * pcie_get_readrq - get PCI Express read request size 3572 * @dev: PCI device to query 3573 * 3574 * Returns maximum memory read request in bytes 3575 * or appropriate error value. 3576 */ 3577 int pcie_get_readrq(struct pci_dev *dev) 3578 { 3579 int ret, cap; 3580 u16 ctl; 3581 3582 cap = pci_pcie_cap(dev); 3583 if (!cap) 3584 return -EINVAL; 3585 3586 ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl); 3587 if (!ret) 3588 ret = 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12); 3589 3590 return ret; 3591 } 3592 EXPORT_SYMBOL(pcie_get_readrq); 3593 3594 /** 3595 * pcie_set_readrq - set PCI Express maximum memory read request 3596 * @dev: PCI device to query 3597 * @rq: maximum memory read count in bytes 3598 * valid values are 128, 256, 512, 1024, 2048, 4096 3599 * 3600 * If possible sets maximum memory read request in bytes 3601 */ 3602 int pcie_set_readrq(struct pci_dev *dev, int rq) 3603 { 3604 int cap, err = -EINVAL; 3605 u16 ctl, v; 3606 3607 if (rq < 128 || rq > 4096 || !is_power_of_2(rq)) 3608 goto out; 3609 3610 cap = pci_pcie_cap(dev); 3611 if (!cap) 3612 goto out; 3613 3614 err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl); 3615 if (err) 3616 goto out; 3617 /* 3618 * If using the "performance" PCIe config, we clamp the 3619 * read rq size to the max packet size to prevent the 3620 * host bridge generating requests larger than we can 3621 * cope with 3622 */ 3623 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) { 3624 int mps = pcie_get_mps(dev); 3625 3626 if (mps < 0) 3627 return mps; 3628 if (mps < rq) 3629 rq = mps; 3630 } 3631 3632 v = (ffs(rq) - 8) << 12; 3633 3634 if ((ctl & PCI_EXP_DEVCTL_READRQ) != v) { 3635 ctl &= ~PCI_EXP_DEVCTL_READRQ; 3636 ctl |= v; 3637 err = pci_write_config_word(dev, cap + PCI_EXP_DEVCTL, ctl); 3638 } 3639 3640 out: 3641 return err; 3642 } 3643 EXPORT_SYMBOL(pcie_set_readrq); 3644 3645 /** 3646 * pcie_get_mps - get PCI Express maximum payload size 3647 * @dev: PCI device to query 3648 * 3649 * Returns maximum payload size in bytes 3650 * or appropriate error value. 3651 */ 3652 int pcie_get_mps(struct pci_dev *dev) 3653 { 3654 int ret, cap; 3655 u16 ctl; 3656 3657 cap = pci_pcie_cap(dev); 3658 if (!cap) 3659 return -EINVAL; 3660 3661 ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl); 3662 if (!ret) 3663 ret = 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5); 3664 3665 return ret; 3666 } 3667 3668 /** 3669 * pcie_set_mps - set PCI Express maximum payload size 3670 * @dev: PCI device to query 3671 * @mps: maximum payload size in bytes 3672 * valid values are 128, 256, 512, 1024, 2048, 4096 3673 * 3674 * If possible sets maximum payload size 3675 */ 3676 int pcie_set_mps(struct pci_dev *dev, int mps) 3677 { 3678 int cap, err = -EINVAL; 3679 u16 ctl, v; 3680 3681 if (mps < 128 || mps > 4096 || !is_power_of_2(mps)) 3682 goto out; 3683 3684 v = ffs(mps) - 8; 3685 if (v > dev->pcie_mpss) 3686 goto out; 3687 v <<= 5; 3688 3689 cap = pci_pcie_cap(dev); 3690 if (!cap) 3691 goto out; 3692 3693 err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl); 3694 if (err) 3695 goto out; 3696 3697 if ((ctl & PCI_EXP_DEVCTL_PAYLOAD) != v) { 3698 ctl &= ~PCI_EXP_DEVCTL_PAYLOAD; 3699 ctl |= v; 3700 err = pci_write_config_word(dev, cap + PCI_EXP_DEVCTL, ctl); 3701 } 3702 out: 3703 return err; 3704 } 3705 3706 /** 3707 * pci_select_bars - Make BAR mask from the type of resource 3708 * @dev: the PCI device for which BAR mask is made 3709 * @flags: resource type mask to be selected 3710 * 3711 * This helper routine makes bar mask from the type of resource. 3712 */ 3713 int pci_select_bars(struct pci_dev *dev, unsigned long flags) 3714 { 3715 int i, bars = 0; 3716 for (i = 0; i < PCI_NUM_RESOURCES; i++) 3717 if (pci_resource_flags(dev, i) & flags) 3718 bars |= (1 << i); 3719 return bars; 3720 } 3721 3722 /** 3723 * pci_resource_bar - get position of the BAR associated with a resource 3724 * @dev: the PCI device 3725 * @resno: the resource number 3726 * @type: the BAR type to be filled in 3727 * 3728 * Returns BAR position in config space, or 0 if the BAR is invalid. 3729 */ 3730 int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type) 3731 { 3732 int reg; 3733 3734 if (resno < PCI_ROM_RESOURCE) { 3735 *type = pci_bar_unknown; 3736 return PCI_BASE_ADDRESS_0 + 4 * resno; 3737 } else if (resno == PCI_ROM_RESOURCE) { 3738 *type = pci_bar_mem32; 3739 return dev->rom_base_reg; 3740 } else if (resno < PCI_BRIDGE_RESOURCES) { 3741 /* device specific resource */ 3742 reg = pci_iov_resource_bar(dev, resno, type); 3743 if (reg) 3744 return reg; 3745 } 3746 3747 dev_err(&dev->dev, "BAR %d: invalid resource\n", resno); 3748 return 0; 3749 } 3750 3751 /* Some architectures require additional programming to enable VGA */ 3752 static arch_set_vga_state_t arch_set_vga_state; 3753 3754 void __init pci_register_set_vga_state(arch_set_vga_state_t func) 3755 { 3756 arch_set_vga_state = func; /* NULL disables */ 3757 } 3758 3759 static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode, 3760 unsigned int command_bits, u32 flags) 3761 { 3762 if (arch_set_vga_state) 3763 return arch_set_vga_state(dev, decode, command_bits, 3764 flags); 3765 return 0; 3766 } 3767 3768 /** 3769 * pci_set_vga_state - set VGA decode state on device and parents if requested 3770 * @dev: the PCI device 3771 * @decode: true = enable decoding, false = disable decoding 3772 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY 3773 * @flags: traverse ancestors and change bridges 3774 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE 3775 */ 3776 int pci_set_vga_state(struct pci_dev *dev, bool decode, 3777 unsigned int command_bits, u32 flags) 3778 { 3779 struct pci_bus *bus; 3780 struct pci_dev *bridge; 3781 u16 cmd; 3782 int rc; 3783 3784 WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) & (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY))); 3785 3786 /* ARCH specific VGA enables */ 3787 rc = pci_set_vga_state_arch(dev, decode, command_bits, flags); 3788 if (rc) 3789 return rc; 3790 3791 if (flags & PCI_VGA_STATE_CHANGE_DECODES) { 3792 pci_read_config_word(dev, PCI_COMMAND, &cmd); 3793 if (decode == true) 3794 cmd |= command_bits; 3795 else 3796 cmd &= ~command_bits; 3797 pci_write_config_word(dev, PCI_COMMAND, cmd); 3798 } 3799 3800 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE)) 3801 return 0; 3802 3803 bus = dev->bus; 3804 while (bus) { 3805 bridge = bus->self; 3806 if (bridge) { 3807 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL, 3808 &cmd); 3809 if (decode == true) 3810 cmd |= PCI_BRIDGE_CTL_VGA; 3811 else 3812 cmd &= ~PCI_BRIDGE_CTL_VGA; 3813 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, 3814 cmd); 3815 } 3816 bus = bus->parent; 3817 } 3818 return 0; 3819 } 3820 3821 #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE 3822 static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0}; 3823 static DEFINE_SPINLOCK(resource_alignment_lock); 3824 3825 /** 3826 * pci_specified_resource_alignment - get resource alignment specified by user. 3827 * @dev: the PCI device to get 3828 * 3829 * RETURNS: Resource alignment if it is specified. 3830 * Zero if it is not specified. 3831 */ 3832 resource_size_t pci_specified_resource_alignment(struct pci_dev *dev) 3833 { 3834 int seg, bus, slot, func, align_order, count; 3835 resource_size_t align = 0; 3836 char *p; 3837 3838 spin_lock(&resource_alignment_lock); 3839 p = resource_alignment_param; 3840 while (*p) { 3841 count = 0; 3842 if (sscanf(p, "%d%n", &align_order, &count) == 1 && 3843 p[count] == '@') { 3844 p += count + 1; 3845 } else { 3846 align_order = -1; 3847 } 3848 if (sscanf(p, "%x:%x:%x.%x%n", 3849 &seg, &bus, &slot, &func, &count) != 4) { 3850 seg = 0; 3851 if (sscanf(p, "%x:%x.%x%n", 3852 &bus, &slot, &func, &count) != 3) { 3853 /* Invalid format */ 3854 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n", 3855 p); 3856 break; 3857 } 3858 } 3859 p += count; 3860 if (seg == pci_domain_nr(dev->bus) && 3861 bus == dev->bus->number && 3862 slot == PCI_SLOT(dev->devfn) && 3863 func == PCI_FUNC(dev->devfn)) { 3864 if (align_order == -1) { 3865 align = PAGE_SIZE; 3866 } else { 3867 align = 1 << align_order; 3868 } 3869 /* Found */ 3870 break; 3871 } 3872 if (*p != ';' && *p != ',') { 3873 /* End of param or invalid format */ 3874 break; 3875 } 3876 p++; 3877 } 3878 spin_unlock(&resource_alignment_lock); 3879 return align; 3880 } 3881 3882 /** 3883 * pci_is_reassigndev - check if specified PCI is target device to reassign 3884 * @dev: the PCI device to check 3885 * 3886 * RETURNS: non-zero for PCI device is a target device to reassign, 3887 * or zero is not. 3888 */ 3889 int pci_is_reassigndev(struct pci_dev *dev) 3890 { 3891 return (pci_specified_resource_alignment(dev) != 0); 3892 } 3893 3894 /* 3895 * This function disables memory decoding and releases memory resources 3896 * of the device specified by kernel's boot parameter 'pci=resource_alignment='. 3897 * It also rounds up size to specified alignment. 3898 * Later on, the kernel will assign page-aligned memory resource back 3899 * to the device. 3900 */ 3901 void pci_reassigndev_resource_alignment(struct pci_dev *dev) 3902 { 3903 int i; 3904 struct resource *r; 3905 resource_size_t align, size; 3906 u16 command; 3907 3908 if (!pci_is_reassigndev(dev)) 3909 return; 3910 3911 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL && 3912 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) { 3913 dev_warn(&dev->dev, 3914 "Can't reassign resources to host bridge.\n"); 3915 return; 3916 } 3917 3918 dev_info(&dev->dev, 3919 "Disabling memory decoding and releasing memory resources.\n"); 3920 pci_read_config_word(dev, PCI_COMMAND, &command); 3921 command &= ~PCI_COMMAND_MEMORY; 3922 pci_write_config_word(dev, PCI_COMMAND, command); 3923 3924 align = pci_specified_resource_alignment(dev); 3925 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) { 3926 r = &dev->resource[i]; 3927 if (!(r->flags & IORESOURCE_MEM)) 3928 continue; 3929 size = resource_size(r); 3930 if (size < align) { 3931 size = align; 3932 dev_info(&dev->dev, 3933 "Rounding up size of resource #%d to %#llx.\n", 3934 i, (unsigned long long)size); 3935 } 3936 r->end = size - 1; 3937 r->start = 0; 3938 } 3939 /* Need to disable bridge's resource window, 3940 * to enable the kernel to reassign new resource 3941 * window later on. 3942 */ 3943 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE && 3944 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { 3945 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) { 3946 r = &dev->resource[i]; 3947 if (!(r->flags & IORESOURCE_MEM)) 3948 continue; 3949 r->end = resource_size(r) - 1; 3950 r->start = 0; 3951 } 3952 pci_disable_bridge_window(dev); 3953 } 3954 } 3955 3956 ssize_t pci_set_resource_alignment_param(const char *buf, size_t count) 3957 { 3958 if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1) 3959 count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1; 3960 spin_lock(&resource_alignment_lock); 3961 strncpy(resource_alignment_param, buf, count); 3962 resource_alignment_param[count] = '\0'; 3963 spin_unlock(&resource_alignment_lock); 3964 return count; 3965 } 3966 3967 ssize_t pci_get_resource_alignment_param(char *buf, size_t size) 3968 { 3969 size_t count; 3970 spin_lock(&resource_alignment_lock); 3971 count = snprintf(buf, size, "%s", resource_alignment_param); 3972 spin_unlock(&resource_alignment_lock); 3973 return count; 3974 } 3975 3976 static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf) 3977 { 3978 return pci_get_resource_alignment_param(buf, PAGE_SIZE); 3979 } 3980 3981 static ssize_t pci_resource_alignment_store(struct bus_type *bus, 3982 const char *buf, size_t count) 3983 { 3984 return pci_set_resource_alignment_param(buf, count); 3985 } 3986 3987 BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show, 3988 pci_resource_alignment_store); 3989 3990 static int __init pci_resource_alignment_sysfs_init(void) 3991 { 3992 return bus_create_file(&pci_bus_type, 3993 &bus_attr_resource_alignment); 3994 } 3995 3996 late_initcall(pci_resource_alignment_sysfs_init); 3997 3998 static void __devinit pci_no_domains(void) 3999 { 4000 #ifdef CONFIG_PCI_DOMAINS 4001 pci_domains_supported = 0; 4002 #endif 4003 } 4004 4005 /** 4006 * pci_ext_cfg_enabled - can we access extended PCI config space? 4007 * @dev: The PCI device of the root bridge. 4008 * 4009 * Returns 1 if we can access PCI extended config space (offsets 4010 * greater than 0xff). This is the default implementation. Architecture 4011 * implementations can override this. 4012 */ 4013 int __weak pci_ext_cfg_avail(struct pci_dev *dev) 4014 { 4015 return 1; 4016 } 4017 4018 void __weak pci_fixup_cardbus(struct pci_bus *bus) 4019 { 4020 } 4021 EXPORT_SYMBOL(pci_fixup_cardbus); 4022 4023 static int __init pci_setup(char *str) 4024 { 4025 while (str) { 4026 char *k = strchr(str, ','); 4027 if (k) 4028 *k++ = 0; 4029 if (*str && (str = pcibios_setup(str)) && *str) { 4030 if (!strcmp(str, "nomsi")) { 4031 pci_no_msi(); 4032 } else if (!strcmp(str, "noaer")) { 4033 pci_no_aer(); 4034 } else if (!strncmp(str, "realloc=", 8)) { 4035 pci_realloc_get_opt(str + 8); 4036 } else if (!strncmp(str, "realloc", 7)) { 4037 pci_realloc_get_opt("on"); 4038 } else if (!strcmp(str, "nodomains")) { 4039 pci_no_domains(); 4040 } else if (!strncmp(str, "noari", 5)) { 4041 pcie_ari_disabled = true; 4042 } else if (!strncmp(str, "cbiosize=", 9)) { 4043 pci_cardbus_io_size = memparse(str + 9, &str); 4044 } else if (!strncmp(str, "cbmemsize=", 10)) { 4045 pci_cardbus_mem_size = memparse(str + 10, &str); 4046 } else if (!strncmp(str, "resource_alignment=", 19)) { 4047 pci_set_resource_alignment_param(str + 19, 4048 strlen(str + 19)); 4049 } else if (!strncmp(str, "ecrc=", 5)) { 4050 pcie_ecrc_get_policy(str + 5); 4051 } else if (!strncmp(str, "hpiosize=", 9)) { 4052 pci_hotplug_io_size = memparse(str + 9, &str); 4053 } else if (!strncmp(str, "hpmemsize=", 10)) { 4054 pci_hotplug_mem_size = memparse(str + 10, &str); 4055 } else if (!strncmp(str, "pcie_bus_tune_off", 17)) { 4056 pcie_bus_config = PCIE_BUS_TUNE_OFF; 4057 } else if (!strncmp(str, "pcie_bus_safe", 13)) { 4058 pcie_bus_config = PCIE_BUS_SAFE; 4059 } else if (!strncmp(str, "pcie_bus_perf", 13)) { 4060 pcie_bus_config = PCIE_BUS_PERFORMANCE; 4061 } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) { 4062 pcie_bus_config = PCIE_BUS_PEER2PEER; 4063 } else if (!strncmp(str, "pcie_scan_all", 13)) { 4064 pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS); 4065 } else { 4066 printk(KERN_ERR "PCI: Unknown option `%s'\n", 4067 str); 4068 } 4069 } 4070 str = k; 4071 } 4072 return 0; 4073 } 4074 early_param("pci", pci_setup); 4075 4076 EXPORT_SYMBOL(pci_reenable_device); 4077 EXPORT_SYMBOL(pci_enable_device_io); 4078 EXPORT_SYMBOL(pci_enable_device_mem); 4079 EXPORT_SYMBOL(pci_enable_device); 4080 EXPORT_SYMBOL(pcim_enable_device); 4081 EXPORT_SYMBOL(pcim_pin_device); 4082 EXPORT_SYMBOL(pci_disable_device); 4083 EXPORT_SYMBOL(pci_find_capability); 4084 EXPORT_SYMBOL(pci_bus_find_capability); 4085 EXPORT_SYMBOL(pci_release_regions); 4086 EXPORT_SYMBOL(pci_request_regions); 4087 EXPORT_SYMBOL(pci_request_regions_exclusive); 4088 EXPORT_SYMBOL(pci_release_region); 4089 EXPORT_SYMBOL(pci_request_region); 4090 EXPORT_SYMBOL(pci_request_region_exclusive); 4091 EXPORT_SYMBOL(pci_release_selected_regions); 4092 EXPORT_SYMBOL(pci_request_selected_regions); 4093 EXPORT_SYMBOL(pci_request_selected_regions_exclusive); 4094 EXPORT_SYMBOL(pci_set_master); 4095 EXPORT_SYMBOL(pci_clear_master); 4096 EXPORT_SYMBOL(pci_set_mwi); 4097 EXPORT_SYMBOL(pci_try_set_mwi); 4098 EXPORT_SYMBOL(pci_clear_mwi); 4099 EXPORT_SYMBOL_GPL(pci_intx); 4100 EXPORT_SYMBOL(pci_assign_resource); 4101 EXPORT_SYMBOL(pci_find_parent_resource); 4102 EXPORT_SYMBOL(pci_select_bars); 4103 4104 EXPORT_SYMBOL(pci_set_power_state); 4105 EXPORT_SYMBOL(pci_save_state); 4106 EXPORT_SYMBOL(pci_restore_state); 4107 EXPORT_SYMBOL(pci_pme_capable); 4108 EXPORT_SYMBOL(pci_pme_active); 4109 EXPORT_SYMBOL(pci_wake_from_d3); 4110 EXPORT_SYMBOL(pci_target_state); 4111 EXPORT_SYMBOL(pci_prepare_to_sleep); 4112 EXPORT_SYMBOL(pci_back_from_sleep); 4113 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state); 4114