1 /* 2 * $Id: pci.c,v 1.91 1999/01/21 13:34:01 davem Exp $ 3 * 4 * PCI Bus Services, see include/linux/pci.h for further explanation. 5 * 6 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter, 7 * David Mosberger-Tang 8 * 9 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz> 10 */ 11 12 #include <linux/kernel.h> 13 #include <linux/delay.h> 14 #include <linux/init.h> 15 #include <linux/pci.h> 16 #include <linux/module.h> 17 #include <linux/spinlock.h> 18 #include <linux/string.h> 19 #include <asm/dma.h> /* isa_dma_bridge_buggy */ 20 #include "pci.h" 21 22 23 /** 24 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children 25 * @bus: pointer to PCI bus structure to search 26 * 27 * Given a PCI bus, returns the highest PCI bus number present in the set 28 * including the given PCI bus and its list of child PCI buses. 29 */ 30 unsigned char __devinit 31 pci_bus_max_busnr(struct pci_bus* bus) 32 { 33 struct list_head *tmp; 34 unsigned char max, n; 35 36 max = bus->number; 37 list_for_each(tmp, &bus->children) { 38 n = pci_bus_max_busnr(pci_bus_b(tmp)); 39 if(n > max) 40 max = n; 41 } 42 return max; 43 } 44 45 /** 46 * pci_max_busnr - returns maximum PCI bus number 47 * 48 * Returns the highest PCI bus number present in the system global list of 49 * PCI buses. 50 */ 51 unsigned char __devinit 52 pci_max_busnr(void) 53 { 54 struct pci_bus *bus = NULL; 55 unsigned char max, n; 56 57 max = 0; 58 while ((bus = pci_find_next_bus(bus)) != NULL) { 59 n = pci_bus_max_busnr(bus); 60 if(n > max) 61 max = n; 62 } 63 return max; 64 } 65 66 static int __pci_bus_find_cap(struct pci_bus *bus, unsigned int devfn, u8 hdr_type, int cap) 67 { 68 u16 status; 69 u8 pos, id; 70 int ttl = 48; 71 72 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status); 73 if (!(status & PCI_STATUS_CAP_LIST)) 74 return 0; 75 76 switch (hdr_type) { 77 case PCI_HEADER_TYPE_NORMAL: 78 case PCI_HEADER_TYPE_BRIDGE: 79 pci_bus_read_config_byte(bus, devfn, PCI_CAPABILITY_LIST, &pos); 80 break; 81 case PCI_HEADER_TYPE_CARDBUS: 82 pci_bus_read_config_byte(bus, devfn, PCI_CB_CAPABILITY_LIST, &pos); 83 break; 84 default: 85 return 0; 86 } 87 while (ttl-- && pos >= 0x40) { 88 pos &= ~3; 89 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID, &id); 90 if (id == 0xff) 91 break; 92 if (id == cap) 93 return pos; 94 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_NEXT, &pos); 95 } 96 return 0; 97 } 98 99 /** 100 * pci_find_capability - query for devices' capabilities 101 * @dev: PCI device to query 102 * @cap: capability code 103 * 104 * Tell if a device supports a given PCI capability. 105 * Returns the address of the requested capability structure within the 106 * device's PCI configuration space or 0 in case the device does not 107 * support it. Possible values for @cap: 108 * 109 * %PCI_CAP_ID_PM Power Management 110 * %PCI_CAP_ID_AGP Accelerated Graphics Port 111 * %PCI_CAP_ID_VPD Vital Product Data 112 * %PCI_CAP_ID_SLOTID Slot Identification 113 * %PCI_CAP_ID_MSI Message Signalled Interrupts 114 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap 115 * %PCI_CAP_ID_PCIX PCI-X 116 * %PCI_CAP_ID_EXP PCI Express 117 */ 118 int pci_find_capability(struct pci_dev *dev, int cap) 119 { 120 return __pci_bus_find_cap(dev->bus, dev->devfn, dev->hdr_type, cap); 121 } 122 123 /** 124 * pci_bus_find_capability - query for devices' capabilities 125 * @bus: the PCI bus to query 126 * @devfn: PCI device to query 127 * @cap: capability code 128 * 129 * Like pci_find_capability() but works for pci devices that do not have a 130 * pci_dev structure set up yet. 131 * 132 * Returns the address of the requested capability structure within the 133 * device's PCI configuration space or 0 in case the device does not 134 * support it. 135 */ 136 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap) 137 { 138 u8 hdr_type; 139 140 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type); 141 142 return __pci_bus_find_cap(bus, devfn, hdr_type & 0x7f, cap); 143 } 144 145 /** 146 * pci_find_ext_capability - Find an extended capability 147 * @dev: PCI device to query 148 * @cap: capability code 149 * 150 * Returns the address of the requested extended capability structure 151 * within the device's PCI configuration space or 0 if the device does 152 * not support it. Possible values for @cap: 153 * 154 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting 155 * %PCI_EXT_CAP_ID_VC Virtual Channel 156 * %PCI_EXT_CAP_ID_DSN Device Serial Number 157 * %PCI_EXT_CAP_ID_PWR Power Budgeting 158 */ 159 int pci_find_ext_capability(struct pci_dev *dev, int cap) 160 { 161 u32 header; 162 int ttl = 480; /* 3840 bytes, minimum 8 bytes per capability */ 163 int pos = 0x100; 164 165 if (dev->cfg_size <= 256) 166 return 0; 167 168 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) 169 return 0; 170 171 /* 172 * If we have no capabilities, this is indicated by cap ID, 173 * cap version and next pointer all being 0. 174 */ 175 if (header == 0) 176 return 0; 177 178 while (ttl-- > 0) { 179 if (PCI_EXT_CAP_ID(header) == cap) 180 return pos; 181 182 pos = PCI_EXT_CAP_NEXT(header); 183 if (pos < 0x100) 184 break; 185 186 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) 187 break; 188 } 189 190 return 0; 191 } 192 193 /** 194 * pci_find_parent_resource - return resource region of parent bus of given region 195 * @dev: PCI device structure contains resources to be searched 196 * @res: child resource record for which parent is sought 197 * 198 * For given resource region of given device, return the resource 199 * region of parent bus the given region is contained in or where 200 * it should be allocated from. 201 */ 202 struct resource * 203 pci_find_parent_resource(const struct pci_dev *dev, struct resource *res) 204 { 205 const struct pci_bus *bus = dev->bus; 206 int i; 207 struct resource *best = NULL; 208 209 for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++) { 210 struct resource *r = bus->resource[i]; 211 if (!r) 212 continue; 213 if (res->start && !(res->start >= r->start && res->end <= r->end)) 214 continue; /* Not contained */ 215 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM)) 216 continue; /* Wrong type */ 217 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH)) 218 return r; /* Exact match */ 219 if ((res->flags & IORESOURCE_PREFETCH) && !(r->flags & IORESOURCE_PREFETCH)) 220 best = r; /* Approximating prefetchable by non-prefetchable */ 221 } 222 return best; 223 } 224 225 /** 226 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up) 227 * @dev: PCI device to have its BARs restored 228 * 229 * Restore the BAR values for a given device, so as to make it 230 * accessible by its driver. 231 */ 232 void 233 pci_restore_bars(struct pci_dev *dev) 234 { 235 int i, numres; 236 237 switch (dev->hdr_type) { 238 case PCI_HEADER_TYPE_NORMAL: 239 numres = 6; 240 break; 241 case PCI_HEADER_TYPE_BRIDGE: 242 numres = 2; 243 break; 244 case PCI_HEADER_TYPE_CARDBUS: 245 numres = 1; 246 break; 247 default: 248 /* Should never get here, but just in case... */ 249 return; 250 } 251 252 for (i = 0; i < numres; i ++) 253 pci_update_resource(dev, &dev->resource[i], i); 254 } 255 256 int (*platform_pci_set_power_state)(struct pci_dev *dev, pci_power_t t); 257 258 /** 259 * pci_set_power_state - Set the power state of a PCI device 260 * @dev: PCI device to be suspended 261 * @state: PCI power state (D0, D1, D2, D3hot, D3cold) we're entering 262 * 263 * Transition a device to a new power state, using the Power Management 264 * Capabilities in the device's config space. 265 * 266 * RETURN VALUE: 267 * -EINVAL if trying to enter a lower state than we're already in. 268 * 0 if we're already in the requested state. 269 * -EIO if device does not support PCI PM. 270 * 0 if we can successfully change the power state. 271 */ 272 int 273 pci_set_power_state(struct pci_dev *dev, pci_power_t state) 274 { 275 int pm, need_restore = 0; 276 u16 pmcsr, pmc; 277 278 /* bound the state we're entering */ 279 if (state > PCI_D3hot) 280 state = PCI_D3hot; 281 282 /* Validate current state: 283 * Can enter D0 from any state, but if we can only go deeper 284 * to sleep if we're already in a low power state 285 */ 286 if (state != PCI_D0 && dev->current_state > state) 287 return -EINVAL; 288 else if (dev->current_state == state) 289 return 0; /* we're already there */ 290 291 /* find PCI PM capability in list */ 292 pm = pci_find_capability(dev, PCI_CAP_ID_PM); 293 294 /* abort if the device doesn't support PM capabilities */ 295 if (!pm) 296 return -EIO; 297 298 pci_read_config_word(dev,pm + PCI_PM_PMC,&pmc); 299 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) { 300 printk(KERN_DEBUG 301 "PCI: %s has unsupported PM cap regs version (%u)\n", 302 pci_name(dev), pmc & PCI_PM_CAP_VER_MASK); 303 return -EIO; 304 } 305 306 /* check if this device supports the desired state */ 307 if (state == PCI_D1 && !(pmc & PCI_PM_CAP_D1)) 308 return -EIO; 309 else if (state == PCI_D2 && !(pmc & PCI_PM_CAP_D2)) 310 return -EIO; 311 312 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr); 313 314 /* If we're (effectively) in D3, force entire word to 0. 315 * This doesn't affect PME_Status, disables PME_En, and 316 * sets PowerState to 0. 317 */ 318 switch (dev->current_state) { 319 case PCI_D0: 320 case PCI_D1: 321 case PCI_D2: 322 pmcsr &= ~PCI_PM_CTRL_STATE_MASK; 323 pmcsr |= state; 324 break; 325 case PCI_UNKNOWN: /* Boot-up */ 326 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot 327 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET)) 328 need_restore = 1; 329 /* Fall-through: force to D0 */ 330 default: 331 pmcsr = 0; 332 break; 333 } 334 335 /* enter specified state */ 336 pci_write_config_word(dev, pm + PCI_PM_CTRL, pmcsr); 337 338 /* Mandatory power management transition delays */ 339 /* see PCI PM 1.1 5.6.1 table 18 */ 340 if (state == PCI_D3hot || dev->current_state == PCI_D3hot) 341 msleep(10); 342 else if (state == PCI_D2 || dev->current_state == PCI_D2) 343 udelay(200); 344 345 /* 346 * Give firmware a chance to be called, such as ACPI _PRx, _PSx 347 * Firmware method after natice method ? 348 */ 349 if (platform_pci_set_power_state) 350 platform_pci_set_power_state(dev, state); 351 352 dev->current_state = state; 353 354 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT 355 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning 356 * from D3hot to D0 _may_ perform an internal reset, thereby 357 * going to "D0 Uninitialized" rather than "D0 Initialized". 358 * For example, at least some versions of the 3c905B and the 359 * 3c556B exhibit this behaviour. 360 * 361 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave 362 * devices in a D3hot state at boot. Consequently, we need to 363 * restore at least the BARs so that the device will be 364 * accessible to its driver. 365 */ 366 if (need_restore) 367 pci_restore_bars(dev); 368 369 return 0; 370 } 371 372 int (*platform_pci_choose_state)(struct pci_dev *dev, pm_message_t state); 373 374 /** 375 * pci_choose_state - Choose the power state of a PCI device 376 * @dev: PCI device to be suspended 377 * @state: target sleep state for the whole system. This is the value 378 * that is passed to suspend() function. 379 * 380 * Returns PCI power state suitable for given device and given system 381 * message. 382 */ 383 384 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state) 385 { 386 int ret; 387 388 if (!pci_find_capability(dev, PCI_CAP_ID_PM)) 389 return PCI_D0; 390 391 if (platform_pci_choose_state) { 392 ret = platform_pci_choose_state(dev, state); 393 if (ret >= 0) 394 state.event = ret; 395 } 396 397 switch (state.event) { 398 case PM_EVENT_ON: 399 return PCI_D0; 400 case PM_EVENT_FREEZE: 401 case PM_EVENT_SUSPEND: 402 return PCI_D3hot; 403 default: 404 printk("They asked me for state %d\n", state.event); 405 BUG(); 406 } 407 return PCI_D0; 408 } 409 410 EXPORT_SYMBOL(pci_choose_state); 411 412 /** 413 * pci_save_state - save the PCI configuration space of a device before suspending 414 * @dev: - PCI device that we're dealing with 415 */ 416 int 417 pci_save_state(struct pci_dev *dev) 418 { 419 int i; 420 /* XXX: 100% dword access ok here? */ 421 for (i = 0; i < 16; i++) 422 pci_read_config_dword(dev, i * 4,&dev->saved_config_space[i]); 423 return 0; 424 } 425 426 /** 427 * pci_restore_state - Restore the saved state of a PCI device 428 * @dev: - PCI device that we're dealing with 429 */ 430 int 431 pci_restore_state(struct pci_dev *dev) 432 { 433 int i; 434 435 for (i = 0; i < 16; i++) 436 pci_write_config_dword(dev,i * 4, dev->saved_config_space[i]); 437 return 0; 438 } 439 440 /** 441 * pci_enable_device_bars - Initialize some of a device for use 442 * @dev: PCI device to be initialized 443 * @bars: bitmask of BAR's that must be configured 444 * 445 * Initialize device before it's used by a driver. Ask low-level code 446 * to enable selected I/O and memory resources. Wake up the device if it 447 * was suspended. Beware, this function can fail. 448 */ 449 450 int 451 pci_enable_device_bars(struct pci_dev *dev, int bars) 452 { 453 int err; 454 455 err = pci_set_power_state(dev, PCI_D0); 456 if (err < 0 && err != -EIO) 457 return err; 458 err = pcibios_enable_device(dev, bars); 459 if (err < 0) 460 return err; 461 return 0; 462 } 463 464 /** 465 * pci_enable_device - Initialize device before it's used by a driver. 466 * @dev: PCI device to be initialized 467 * 468 * Initialize device before it's used by a driver. Ask low-level code 469 * to enable I/O and memory. Wake up the device if it was suspended. 470 * Beware, this function can fail. 471 */ 472 int 473 pci_enable_device(struct pci_dev *dev) 474 { 475 int err; 476 477 if ((err = pci_enable_device_bars(dev, (1 << PCI_NUM_RESOURCES) - 1))) 478 return err; 479 pci_fixup_device(pci_fixup_enable, dev); 480 dev->is_enabled = 1; 481 return 0; 482 } 483 484 /** 485 * pcibios_disable_device - disable arch specific PCI resources for device dev 486 * @dev: the PCI device to disable 487 * 488 * Disables architecture specific PCI resources for the device. This 489 * is the default implementation. Architecture implementations can 490 * override this. 491 */ 492 void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {} 493 494 /** 495 * pci_disable_device - Disable PCI device after use 496 * @dev: PCI device to be disabled 497 * 498 * Signal to the system that the PCI device is not in use by the system 499 * anymore. This only involves disabling PCI bus-mastering, if active. 500 */ 501 void 502 pci_disable_device(struct pci_dev *dev) 503 { 504 u16 pci_command; 505 506 pci_read_config_word(dev, PCI_COMMAND, &pci_command); 507 if (pci_command & PCI_COMMAND_MASTER) { 508 pci_command &= ~PCI_COMMAND_MASTER; 509 pci_write_config_word(dev, PCI_COMMAND, pci_command); 510 } 511 dev->is_busmaster = 0; 512 513 pcibios_disable_device(dev); 514 dev->is_enabled = 0; 515 } 516 517 /** 518 * pci_enable_wake - enable device to generate PME# when suspended 519 * @dev: - PCI device to operate on 520 * @state: - Current state of device. 521 * @enable: - Flag to enable or disable generation 522 * 523 * Set the bits in the device's PM Capabilities to generate PME# when 524 * the system is suspended. 525 * 526 * -EIO is returned if device doesn't have PM Capabilities. 527 * -EINVAL is returned if device supports it, but can't generate wake events. 528 * 0 if operation is successful. 529 * 530 */ 531 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable) 532 { 533 int pm; 534 u16 value; 535 536 /* find PCI PM capability in list */ 537 pm = pci_find_capability(dev, PCI_CAP_ID_PM); 538 539 /* If device doesn't support PM Capabilities, but request is to disable 540 * wake events, it's a nop; otherwise fail */ 541 if (!pm) 542 return enable ? -EIO : 0; 543 544 /* Check device's ability to generate PME# */ 545 pci_read_config_word(dev,pm+PCI_PM_PMC,&value); 546 547 value &= PCI_PM_CAP_PME_MASK; 548 value >>= ffs(PCI_PM_CAP_PME_MASK) - 1; /* First bit of mask */ 549 550 /* Check if it can generate PME# from requested state. */ 551 if (!value || !(value & (1 << state))) 552 return enable ? -EINVAL : 0; 553 554 pci_read_config_word(dev, pm + PCI_PM_CTRL, &value); 555 556 /* Clear PME_Status by writing 1 to it and enable PME# */ 557 value |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE; 558 559 if (!enable) 560 value &= ~PCI_PM_CTRL_PME_ENABLE; 561 562 pci_write_config_word(dev, pm + PCI_PM_CTRL, value); 563 564 return 0; 565 } 566 567 int 568 pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge) 569 { 570 u8 pin; 571 572 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); 573 if (!pin) 574 return -1; 575 pin--; 576 while (dev->bus->self) { 577 pin = (pin + PCI_SLOT(dev->devfn)) % 4; 578 dev = dev->bus->self; 579 } 580 *bridge = dev; 581 return pin; 582 } 583 584 /** 585 * pci_release_region - Release a PCI bar 586 * @pdev: PCI device whose resources were previously reserved by pci_request_region 587 * @bar: BAR to release 588 * 589 * Releases the PCI I/O and memory resources previously reserved by a 590 * successful call to pci_request_region. Call this function only 591 * after all use of the PCI regions has ceased. 592 */ 593 void pci_release_region(struct pci_dev *pdev, int bar) 594 { 595 if (pci_resource_len(pdev, bar) == 0) 596 return; 597 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) 598 release_region(pci_resource_start(pdev, bar), 599 pci_resource_len(pdev, bar)); 600 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) 601 release_mem_region(pci_resource_start(pdev, bar), 602 pci_resource_len(pdev, bar)); 603 } 604 605 /** 606 * pci_request_region - Reserved PCI I/O and memory resource 607 * @pdev: PCI device whose resources are to be reserved 608 * @bar: BAR to be reserved 609 * @res_name: Name to be associated with resource. 610 * 611 * Mark the PCI region associated with PCI device @pdev BR @bar as 612 * being reserved by owner @res_name. Do not access any 613 * address inside the PCI regions unless this call returns 614 * successfully. 615 * 616 * Returns 0 on success, or %EBUSY on error. A warning 617 * message is also printed on failure. 618 */ 619 int pci_request_region(struct pci_dev *pdev, int bar, char *res_name) 620 { 621 if (pci_resource_len(pdev, bar) == 0) 622 return 0; 623 624 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) { 625 if (!request_region(pci_resource_start(pdev, bar), 626 pci_resource_len(pdev, bar), res_name)) 627 goto err_out; 628 } 629 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) { 630 if (!request_mem_region(pci_resource_start(pdev, bar), 631 pci_resource_len(pdev, bar), res_name)) 632 goto err_out; 633 } 634 635 return 0; 636 637 err_out: 638 printk (KERN_WARNING "PCI: Unable to reserve %s region #%d:%lx@%lx for device %s\n", 639 pci_resource_flags(pdev, bar) & IORESOURCE_IO ? "I/O" : "mem", 640 bar + 1, /* PCI BAR # */ 641 pci_resource_len(pdev, bar), pci_resource_start(pdev, bar), 642 pci_name(pdev)); 643 return -EBUSY; 644 } 645 646 647 /** 648 * pci_release_regions - Release reserved PCI I/O and memory resources 649 * @pdev: PCI device whose resources were previously reserved by pci_request_regions 650 * 651 * Releases all PCI I/O and memory resources previously reserved by a 652 * successful call to pci_request_regions. Call this function only 653 * after all use of the PCI regions has ceased. 654 */ 655 656 void pci_release_regions(struct pci_dev *pdev) 657 { 658 int i; 659 660 for (i = 0; i < 6; i++) 661 pci_release_region(pdev, i); 662 } 663 664 /** 665 * pci_request_regions - Reserved PCI I/O and memory resources 666 * @pdev: PCI device whose resources are to be reserved 667 * @res_name: Name to be associated with resource. 668 * 669 * Mark all PCI regions associated with PCI device @pdev as 670 * being reserved by owner @res_name. Do not access any 671 * address inside the PCI regions unless this call returns 672 * successfully. 673 * 674 * Returns 0 on success, or %EBUSY on error. A warning 675 * message is also printed on failure. 676 */ 677 int pci_request_regions(struct pci_dev *pdev, char *res_name) 678 { 679 int i; 680 681 for (i = 0; i < 6; i++) 682 if(pci_request_region(pdev, i, res_name)) 683 goto err_out; 684 return 0; 685 686 err_out: 687 while(--i >= 0) 688 pci_release_region(pdev, i); 689 690 return -EBUSY; 691 } 692 693 /** 694 * pci_set_master - enables bus-mastering for device dev 695 * @dev: the PCI device to enable 696 * 697 * Enables bus-mastering on the device and calls pcibios_set_master() 698 * to do the needed arch specific settings. 699 */ 700 void 701 pci_set_master(struct pci_dev *dev) 702 { 703 u16 cmd; 704 705 pci_read_config_word(dev, PCI_COMMAND, &cmd); 706 if (! (cmd & PCI_COMMAND_MASTER)) { 707 pr_debug("PCI: Enabling bus mastering for device %s\n", pci_name(dev)); 708 cmd |= PCI_COMMAND_MASTER; 709 pci_write_config_word(dev, PCI_COMMAND, cmd); 710 } 711 dev->is_busmaster = 1; 712 pcibios_set_master(dev); 713 } 714 715 #ifndef HAVE_ARCH_PCI_MWI 716 /* This can be overridden by arch code. */ 717 u8 pci_cache_line_size = L1_CACHE_BYTES >> 2; 718 719 /** 720 * pci_generic_prep_mwi - helper function for pci_set_mwi 721 * @dev: the PCI device for which MWI is enabled 722 * 723 * Helper function for generic implementation of pcibios_prep_mwi 724 * function. Originally copied from drivers/net/acenic.c. 725 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. 726 * 727 * RETURNS: An appropriate -ERRNO error value on error, or zero for success. 728 */ 729 static int 730 pci_generic_prep_mwi(struct pci_dev *dev) 731 { 732 u8 cacheline_size; 733 734 if (!pci_cache_line_size) 735 return -EINVAL; /* The system doesn't support MWI. */ 736 737 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be 738 equal to or multiple of the right value. */ 739 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); 740 if (cacheline_size >= pci_cache_line_size && 741 (cacheline_size % pci_cache_line_size) == 0) 742 return 0; 743 744 /* Write the correct value. */ 745 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size); 746 /* Read it back. */ 747 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); 748 if (cacheline_size == pci_cache_line_size) 749 return 0; 750 751 printk(KERN_DEBUG "PCI: cache line size of %d is not supported " 752 "by device %s\n", pci_cache_line_size << 2, pci_name(dev)); 753 754 return -EINVAL; 755 } 756 #endif /* !HAVE_ARCH_PCI_MWI */ 757 758 /** 759 * pci_set_mwi - enables memory-write-invalidate PCI transaction 760 * @dev: the PCI device for which MWI is enabled 761 * 762 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND, 763 * and then calls @pcibios_set_mwi to do the needed arch specific 764 * operations or a generic mwi-prep function. 765 * 766 * RETURNS: An appropriate -ERRNO error value on error, or zero for success. 767 */ 768 int 769 pci_set_mwi(struct pci_dev *dev) 770 { 771 int rc; 772 u16 cmd; 773 774 #ifdef HAVE_ARCH_PCI_MWI 775 rc = pcibios_prep_mwi(dev); 776 #else 777 rc = pci_generic_prep_mwi(dev); 778 #endif 779 780 if (rc) 781 return rc; 782 783 pci_read_config_word(dev, PCI_COMMAND, &cmd); 784 if (! (cmd & PCI_COMMAND_INVALIDATE)) { 785 pr_debug("PCI: Enabling Mem-Wr-Inval for device %s\n", pci_name(dev)); 786 cmd |= PCI_COMMAND_INVALIDATE; 787 pci_write_config_word(dev, PCI_COMMAND, cmd); 788 } 789 790 return 0; 791 } 792 793 /** 794 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev 795 * @dev: the PCI device to disable 796 * 797 * Disables PCI Memory-Write-Invalidate transaction on the device 798 */ 799 void 800 pci_clear_mwi(struct pci_dev *dev) 801 { 802 u16 cmd; 803 804 pci_read_config_word(dev, PCI_COMMAND, &cmd); 805 if (cmd & PCI_COMMAND_INVALIDATE) { 806 cmd &= ~PCI_COMMAND_INVALIDATE; 807 pci_write_config_word(dev, PCI_COMMAND, cmd); 808 } 809 } 810 811 /** 812 * pci_intx - enables/disables PCI INTx for device dev 813 * @pdev: the PCI device to operate on 814 * @enable: boolean: whether to enable or disable PCI INTx 815 * 816 * Enables/disables PCI INTx for device dev 817 */ 818 void 819 pci_intx(struct pci_dev *pdev, int enable) 820 { 821 u16 pci_command, new; 822 823 pci_read_config_word(pdev, PCI_COMMAND, &pci_command); 824 825 if (enable) { 826 new = pci_command & ~PCI_COMMAND_INTX_DISABLE; 827 } else { 828 new = pci_command | PCI_COMMAND_INTX_DISABLE; 829 } 830 831 if (new != pci_command) { 832 pci_write_config_word(pdev, PCI_COMMAND, new); 833 } 834 } 835 836 #ifndef HAVE_ARCH_PCI_SET_DMA_MASK 837 /* 838 * These can be overridden by arch-specific implementations 839 */ 840 int 841 pci_set_dma_mask(struct pci_dev *dev, u64 mask) 842 { 843 if (!pci_dma_supported(dev, mask)) 844 return -EIO; 845 846 dev->dma_mask = mask; 847 848 return 0; 849 } 850 851 int 852 pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask) 853 { 854 if (!pci_dma_supported(dev, mask)) 855 return -EIO; 856 857 dev->dev.coherent_dma_mask = mask; 858 859 return 0; 860 } 861 #endif 862 863 static int __devinit pci_init(void) 864 { 865 struct pci_dev *dev = NULL; 866 867 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { 868 pci_fixup_device(pci_fixup_final, dev); 869 } 870 return 0; 871 } 872 873 static int __devinit pci_setup(char *str) 874 { 875 while (str) { 876 char *k = strchr(str, ','); 877 if (k) 878 *k++ = 0; 879 if (*str && (str = pcibios_setup(str)) && *str) { 880 /* PCI layer options should be handled here */ 881 printk(KERN_ERR "PCI: Unknown option `%s'\n", str); 882 } 883 str = k; 884 } 885 return 1; 886 } 887 888 device_initcall(pci_init); 889 890 __setup("pci=", pci_setup); 891 892 #if defined(CONFIG_ISA) || defined(CONFIG_EISA) 893 /* FIXME: Some boxes have multiple ISA bridges! */ 894 struct pci_dev *isa_bridge; 895 EXPORT_SYMBOL(isa_bridge); 896 #endif 897 898 EXPORT_SYMBOL_GPL(pci_restore_bars); 899 EXPORT_SYMBOL(pci_enable_device_bars); 900 EXPORT_SYMBOL(pci_enable_device); 901 EXPORT_SYMBOL(pci_disable_device); 902 EXPORT_SYMBOL(pci_max_busnr); 903 EXPORT_SYMBOL(pci_bus_max_busnr); 904 EXPORT_SYMBOL(pci_find_capability); 905 EXPORT_SYMBOL(pci_bus_find_capability); 906 EXPORT_SYMBOL(pci_release_regions); 907 EXPORT_SYMBOL(pci_request_regions); 908 EXPORT_SYMBOL(pci_release_region); 909 EXPORT_SYMBOL(pci_request_region); 910 EXPORT_SYMBOL(pci_set_master); 911 EXPORT_SYMBOL(pci_set_mwi); 912 EXPORT_SYMBOL(pci_clear_mwi); 913 EXPORT_SYMBOL_GPL(pci_intx); 914 EXPORT_SYMBOL(pci_set_dma_mask); 915 EXPORT_SYMBOL(pci_set_consistent_dma_mask); 916 EXPORT_SYMBOL(pci_assign_resource); 917 EXPORT_SYMBOL(pci_find_parent_resource); 918 919 EXPORT_SYMBOL(pci_set_power_state); 920 EXPORT_SYMBOL(pci_save_state); 921 EXPORT_SYMBOL(pci_restore_state); 922 EXPORT_SYMBOL(pci_enable_wake); 923 924 /* Quirk info */ 925 926 EXPORT_SYMBOL(isa_dma_bridge_buggy); 927 EXPORT_SYMBOL(pci_pci_problems); 928