1 /* 2 * $Id: pci.c,v 1.91 1999/01/21 13:34:01 davem Exp $ 3 * 4 * PCI Bus Services, see include/linux/pci.h for further explanation. 5 * 6 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter, 7 * David Mosberger-Tang 8 * 9 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz> 10 */ 11 12 #include <linux/kernel.h> 13 #include <linux/delay.h> 14 #include <linux/init.h> 15 #include <linux/pci.h> 16 #include <linux/module.h> 17 #include <linux/spinlock.h> 18 #include <linux/string.h> 19 #include <asm/dma.h> /* isa_dma_bridge_buggy */ 20 #include "pci.h" 21 22 23 /** 24 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children 25 * @bus: pointer to PCI bus structure to search 26 * 27 * Given a PCI bus, returns the highest PCI bus number present in the set 28 * including the given PCI bus and its list of child PCI buses. 29 */ 30 unsigned char __devinit 31 pci_bus_max_busnr(struct pci_bus* bus) 32 { 33 struct list_head *tmp; 34 unsigned char max, n; 35 36 max = bus->subordinate; 37 list_for_each(tmp, &bus->children) { 38 n = pci_bus_max_busnr(pci_bus_b(tmp)); 39 if(n > max) 40 max = n; 41 } 42 return max; 43 } 44 EXPORT_SYMBOL_GPL(pci_bus_max_busnr); 45 46 #if 0 47 /** 48 * pci_max_busnr - returns maximum PCI bus number 49 * 50 * Returns the highest PCI bus number present in the system global list of 51 * PCI buses. 52 */ 53 unsigned char __devinit 54 pci_max_busnr(void) 55 { 56 struct pci_bus *bus = NULL; 57 unsigned char max, n; 58 59 max = 0; 60 while ((bus = pci_find_next_bus(bus)) != NULL) { 61 n = pci_bus_max_busnr(bus); 62 if(n > max) 63 max = n; 64 } 65 return max; 66 } 67 68 #endif /* 0 */ 69 70 static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn, u8 pos, int cap) 71 { 72 u8 id; 73 int ttl = 48; 74 75 while (ttl--) { 76 pci_bus_read_config_byte(bus, devfn, pos, &pos); 77 if (pos < 0x40) 78 break; 79 pos &= ~3; 80 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID, 81 &id); 82 if (id == 0xff) 83 break; 84 if (id == cap) 85 return pos; 86 pos += PCI_CAP_LIST_NEXT; 87 } 88 return 0; 89 } 90 91 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap) 92 { 93 return __pci_find_next_cap(dev->bus, dev->devfn, 94 pos + PCI_CAP_LIST_NEXT, cap); 95 } 96 EXPORT_SYMBOL_GPL(pci_find_next_capability); 97 98 static int __pci_bus_find_cap(struct pci_bus *bus, unsigned int devfn, u8 hdr_type, int cap) 99 { 100 u16 status; 101 u8 pos; 102 103 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status); 104 if (!(status & PCI_STATUS_CAP_LIST)) 105 return 0; 106 107 switch (hdr_type) { 108 case PCI_HEADER_TYPE_NORMAL: 109 case PCI_HEADER_TYPE_BRIDGE: 110 pos = PCI_CAPABILITY_LIST; 111 break; 112 case PCI_HEADER_TYPE_CARDBUS: 113 pos = PCI_CB_CAPABILITY_LIST; 114 break; 115 default: 116 return 0; 117 } 118 return __pci_find_next_cap(bus, devfn, pos, cap); 119 } 120 121 /** 122 * pci_find_capability - query for devices' capabilities 123 * @dev: PCI device to query 124 * @cap: capability code 125 * 126 * Tell if a device supports a given PCI capability. 127 * Returns the address of the requested capability structure within the 128 * device's PCI configuration space or 0 in case the device does not 129 * support it. Possible values for @cap: 130 * 131 * %PCI_CAP_ID_PM Power Management 132 * %PCI_CAP_ID_AGP Accelerated Graphics Port 133 * %PCI_CAP_ID_VPD Vital Product Data 134 * %PCI_CAP_ID_SLOTID Slot Identification 135 * %PCI_CAP_ID_MSI Message Signalled Interrupts 136 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap 137 * %PCI_CAP_ID_PCIX PCI-X 138 * %PCI_CAP_ID_EXP PCI Express 139 */ 140 int pci_find_capability(struct pci_dev *dev, int cap) 141 { 142 return __pci_bus_find_cap(dev->bus, dev->devfn, dev->hdr_type, cap); 143 } 144 145 /** 146 * pci_bus_find_capability - query for devices' capabilities 147 * @bus: the PCI bus to query 148 * @devfn: PCI device to query 149 * @cap: capability code 150 * 151 * Like pci_find_capability() but works for pci devices that do not have a 152 * pci_dev structure set up yet. 153 * 154 * Returns the address of the requested capability structure within the 155 * device's PCI configuration space or 0 in case the device does not 156 * support it. 157 */ 158 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap) 159 { 160 u8 hdr_type; 161 162 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type); 163 164 return __pci_bus_find_cap(bus, devfn, hdr_type & 0x7f, cap); 165 } 166 167 #if 0 168 /** 169 * pci_find_ext_capability - Find an extended capability 170 * @dev: PCI device to query 171 * @cap: capability code 172 * 173 * Returns the address of the requested extended capability structure 174 * within the device's PCI configuration space or 0 if the device does 175 * not support it. Possible values for @cap: 176 * 177 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting 178 * %PCI_EXT_CAP_ID_VC Virtual Channel 179 * %PCI_EXT_CAP_ID_DSN Device Serial Number 180 * %PCI_EXT_CAP_ID_PWR Power Budgeting 181 */ 182 int pci_find_ext_capability(struct pci_dev *dev, int cap) 183 { 184 u32 header; 185 int ttl = 480; /* 3840 bytes, minimum 8 bytes per capability */ 186 int pos = 0x100; 187 188 if (dev->cfg_size <= 256) 189 return 0; 190 191 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) 192 return 0; 193 194 /* 195 * If we have no capabilities, this is indicated by cap ID, 196 * cap version and next pointer all being 0. 197 */ 198 if (header == 0) 199 return 0; 200 201 while (ttl-- > 0) { 202 if (PCI_EXT_CAP_ID(header) == cap) 203 return pos; 204 205 pos = PCI_EXT_CAP_NEXT(header); 206 if (pos < 0x100) 207 break; 208 209 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) 210 break; 211 } 212 213 return 0; 214 } 215 #endif /* 0 */ 216 217 /** 218 * pci_find_parent_resource - return resource region of parent bus of given region 219 * @dev: PCI device structure contains resources to be searched 220 * @res: child resource record for which parent is sought 221 * 222 * For given resource region of given device, return the resource 223 * region of parent bus the given region is contained in or where 224 * it should be allocated from. 225 */ 226 struct resource * 227 pci_find_parent_resource(const struct pci_dev *dev, struct resource *res) 228 { 229 const struct pci_bus *bus = dev->bus; 230 int i; 231 struct resource *best = NULL; 232 233 for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++) { 234 struct resource *r = bus->resource[i]; 235 if (!r) 236 continue; 237 if (res->start && !(res->start >= r->start && res->end <= r->end)) 238 continue; /* Not contained */ 239 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM)) 240 continue; /* Wrong type */ 241 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH)) 242 return r; /* Exact match */ 243 if ((res->flags & IORESOURCE_PREFETCH) && !(r->flags & IORESOURCE_PREFETCH)) 244 best = r; /* Approximating prefetchable by non-prefetchable */ 245 } 246 return best; 247 } 248 249 /** 250 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up) 251 * @dev: PCI device to have its BARs restored 252 * 253 * Restore the BAR values for a given device, so as to make it 254 * accessible by its driver. 255 */ 256 void 257 pci_restore_bars(struct pci_dev *dev) 258 { 259 int i, numres; 260 261 switch (dev->hdr_type) { 262 case PCI_HEADER_TYPE_NORMAL: 263 numres = 6; 264 break; 265 case PCI_HEADER_TYPE_BRIDGE: 266 numres = 2; 267 break; 268 case PCI_HEADER_TYPE_CARDBUS: 269 numres = 1; 270 break; 271 default: 272 /* Should never get here, but just in case... */ 273 return; 274 } 275 276 for (i = 0; i < numres; i ++) 277 pci_update_resource(dev, &dev->resource[i], i); 278 } 279 280 int (*platform_pci_set_power_state)(struct pci_dev *dev, pci_power_t t); 281 282 /** 283 * pci_set_power_state - Set the power state of a PCI device 284 * @dev: PCI device to be suspended 285 * @state: PCI power state (D0, D1, D2, D3hot, D3cold) we're entering 286 * 287 * Transition a device to a new power state, using the Power Management 288 * Capabilities in the device's config space. 289 * 290 * RETURN VALUE: 291 * -EINVAL if trying to enter a lower state than we're already in. 292 * 0 if we're already in the requested state. 293 * -EIO if device does not support PCI PM. 294 * 0 if we can successfully change the power state. 295 */ 296 int 297 pci_set_power_state(struct pci_dev *dev, pci_power_t state) 298 { 299 int pm, need_restore = 0; 300 u16 pmcsr, pmc; 301 302 /* bound the state we're entering */ 303 if (state > PCI_D3hot) 304 state = PCI_D3hot; 305 306 /* Validate current state: 307 * Can enter D0 from any state, but if we can only go deeper 308 * to sleep if we're already in a low power state 309 */ 310 if (state != PCI_D0 && dev->current_state > state) { 311 printk(KERN_ERR "%s(): %s: state=%d, current state=%d\n", 312 __FUNCTION__, pci_name(dev), state, dev->current_state); 313 return -EINVAL; 314 } else if (dev->current_state == state) 315 return 0; /* we're already there */ 316 317 /* find PCI PM capability in list */ 318 pm = pci_find_capability(dev, PCI_CAP_ID_PM); 319 320 /* abort if the device doesn't support PM capabilities */ 321 if (!pm) 322 return -EIO; 323 324 pci_read_config_word(dev,pm + PCI_PM_PMC,&pmc); 325 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) { 326 printk(KERN_DEBUG 327 "PCI: %s has unsupported PM cap regs version (%u)\n", 328 pci_name(dev), pmc & PCI_PM_CAP_VER_MASK); 329 return -EIO; 330 } 331 332 /* check if this device supports the desired state */ 333 if (state == PCI_D1 && !(pmc & PCI_PM_CAP_D1)) 334 return -EIO; 335 else if (state == PCI_D2 && !(pmc & PCI_PM_CAP_D2)) 336 return -EIO; 337 338 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr); 339 340 /* If we're (effectively) in D3, force entire word to 0. 341 * This doesn't affect PME_Status, disables PME_En, and 342 * sets PowerState to 0. 343 */ 344 switch (dev->current_state) { 345 case PCI_D0: 346 case PCI_D1: 347 case PCI_D2: 348 pmcsr &= ~PCI_PM_CTRL_STATE_MASK; 349 pmcsr |= state; 350 break; 351 case PCI_UNKNOWN: /* Boot-up */ 352 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot 353 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET)) 354 need_restore = 1; 355 /* Fall-through: force to D0 */ 356 default: 357 pmcsr = 0; 358 break; 359 } 360 361 /* enter specified state */ 362 pci_write_config_word(dev, pm + PCI_PM_CTRL, pmcsr); 363 364 /* Mandatory power management transition delays */ 365 /* see PCI PM 1.1 5.6.1 table 18 */ 366 if (state == PCI_D3hot || dev->current_state == PCI_D3hot) 367 msleep(10); 368 else if (state == PCI_D2 || dev->current_state == PCI_D2) 369 udelay(200); 370 371 /* 372 * Give firmware a chance to be called, such as ACPI _PRx, _PSx 373 * Firmware method after natice method ? 374 */ 375 if (platform_pci_set_power_state) 376 platform_pci_set_power_state(dev, state); 377 378 dev->current_state = state; 379 380 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT 381 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning 382 * from D3hot to D0 _may_ perform an internal reset, thereby 383 * going to "D0 Uninitialized" rather than "D0 Initialized". 384 * For example, at least some versions of the 3c905B and the 385 * 3c556B exhibit this behaviour. 386 * 387 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave 388 * devices in a D3hot state at boot. Consequently, we need to 389 * restore at least the BARs so that the device will be 390 * accessible to its driver. 391 */ 392 if (need_restore) 393 pci_restore_bars(dev); 394 395 return 0; 396 } 397 398 int (*platform_pci_choose_state)(struct pci_dev *dev, pm_message_t state); 399 400 /** 401 * pci_choose_state - Choose the power state of a PCI device 402 * @dev: PCI device to be suspended 403 * @state: target sleep state for the whole system. This is the value 404 * that is passed to suspend() function. 405 * 406 * Returns PCI power state suitable for given device and given system 407 * message. 408 */ 409 410 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state) 411 { 412 int ret; 413 414 if (!pci_find_capability(dev, PCI_CAP_ID_PM)) 415 return PCI_D0; 416 417 if (platform_pci_choose_state) { 418 ret = platform_pci_choose_state(dev, state); 419 if (ret >= 0) 420 state.event = ret; 421 } 422 423 switch (state.event) { 424 case PM_EVENT_ON: 425 return PCI_D0; 426 case PM_EVENT_FREEZE: 427 case PM_EVENT_SUSPEND: 428 return PCI_D3hot; 429 default: 430 printk("They asked me for state %d\n", state.event); 431 BUG(); 432 } 433 return PCI_D0; 434 } 435 436 EXPORT_SYMBOL(pci_choose_state); 437 438 /** 439 * pci_save_state - save the PCI configuration space of a device before suspending 440 * @dev: - PCI device that we're dealing with 441 */ 442 int 443 pci_save_state(struct pci_dev *dev) 444 { 445 int i; 446 /* XXX: 100% dword access ok here? */ 447 for (i = 0; i < 16; i++) 448 pci_read_config_dword(dev, i * 4,&dev->saved_config_space[i]); 449 if ((i = pci_save_msi_state(dev)) != 0) 450 return i; 451 if ((i = pci_save_msix_state(dev)) != 0) 452 return i; 453 return 0; 454 } 455 456 /** 457 * pci_restore_state - Restore the saved state of a PCI device 458 * @dev: - PCI device that we're dealing with 459 */ 460 int 461 pci_restore_state(struct pci_dev *dev) 462 { 463 int i; 464 465 for (i = 0; i < 16; i++) 466 pci_write_config_dword(dev,i * 4, dev->saved_config_space[i]); 467 pci_restore_msi_state(dev); 468 pci_restore_msix_state(dev); 469 return 0; 470 } 471 472 /** 473 * pci_enable_device_bars - Initialize some of a device for use 474 * @dev: PCI device to be initialized 475 * @bars: bitmask of BAR's that must be configured 476 * 477 * Initialize device before it's used by a driver. Ask low-level code 478 * to enable selected I/O and memory resources. Wake up the device if it 479 * was suspended. Beware, this function can fail. 480 */ 481 482 int 483 pci_enable_device_bars(struct pci_dev *dev, int bars) 484 { 485 int err; 486 487 err = pci_set_power_state(dev, PCI_D0); 488 if (err < 0 && err != -EIO) 489 return err; 490 err = pcibios_enable_device(dev, bars); 491 if (err < 0) 492 return err; 493 return 0; 494 } 495 496 /** 497 * pci_enable_device - Initialize device before it's used by a driver. 498 * @dev: PCI device to be initialized 499 * 500 * Initialize device before it's used by a driver. Ask low-level code 501 * to enable I/O and memory. Wake up the device if it was suspended. 502 * Beware, this function can fail. 503 */ 504 int 505 pci_enable_device(struct pci_dev *dev) 506 { 507 int err = pci_enable_device_bars(dev, (1 << PCI_NUM_RESOURCES) - 1); 508 if (err) 509 return err; 510 pci_fixup_device(pci_fixup_enable, dev); 511 dev->is_enabled = 1; 512 return 0; 513 } 514 515 /** 516 * pcibios_disable_device - disable arch specific PCI resources for device dev 517 * @dev: the PCI device to disable 518 * 519 * Disables architecture specific PCI resources for the device. This 520 * is the default implementation. Architecture implementations can 521 * override this. 522 */ 523 void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {} 524 525 /** 526 * pci_disable_device - Disable PCI device after use 527 * @dev: PCI device to be disabled 528 * 529 * Signal to the system that the PCI device is not in use by the system 530 * anymore. This only involves disabling PCI bus-mastering, if active. 531 */ 532 void 533 pci_disable_device(struct pci_dev *dev) 534 { 535 u16 pci_command; 536 537 pci_read_config_word(dev, PCI_COMMAND, &pci_command); 538 if (pci_command & PCI_COMMAND_MASTER) { 539 pci_command &= ~PCI_COMMAND_MASTER; 540 pci_write_config_word(dev, PCI_COMMAND, pci_command); 541 } 542 dev->is_busmaster = 0; 543 544 pcibios_disable_device(dev); 545 dev->is_enabled = 0; 546 } 547 548 /** 549 * pci_enable_wake - enable device to generate PME# when suspended 550 * @dev: - PCI device to operate on 551 * @state: - Current state of device. 552 * @enable: - Flag to enable or disable generation 553 * 554 * Set the bits in the device's PM Capabilities to generate PME# when 555 * the system is suspended. 556 * 557 * -EIO is returned if device doesn't have PM Capabilities. 558 * -EINVAL is returned if device supports it, but can't generate wake events. 559 * 0 if operation is successful. 560 * 561 */ 562 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable) 563 { 564 int pm; 565 u16 value; 566 567 /* find PCI PM capability in list */ 568 pm = pci_find_capability(dev, PCI_CAP_ID_PM); 569 570 /* If device doesn't support PM Capabilities, but request is to disable 571 * wake events, it's a nop; otherwise fail */ 572 if (!pm) 573 return enable ? -EIO : 0; 574 575 /* Check device's ability to generate PME# */ 576 pci_read_config_word(dev,pm+PCI_PM_PMC,&value); 577 578 value &= PCI_PM_CAP_PME_MASK; 579 value >>= ffs(PCI_PM_CAP_PME_MASK) - 1; /* First bit of mask */ 580 581 /* Check if it can generate PME# from requested state. */ 582 if (!value || !(value & (1 << state))) 583 return enable ? -EINVAL : 0; 584 585 pci_read_config_word(dev, pm + PCI_PM_CTRL, &value); 586 587 /* Clear PME_Status by writing 1 to it and enable PME# */ 588 value |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE; 589 590 if (!enable) 591 value &= ~PCI_PM_CTRL_PME_ENABLE; 592 593 pci_write_config_word(dev, pm + PCI_PM_CTRL, value); 594 595 return 0; 596 } 597 598 int 599 pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge) 600 { 601 u8 pin; 602 603 pin = dev->pin; 604 if (!pin) 605 return -1; 606 pin--; 607 while (dev->bus->self) { 608 pin = (pin + PCI_SLOT(dev->devfn)) % 4; 609 dev = dev->bus->self; 610 } 611 *bridge = dev; 612 return pin; 613 } 614 615 /** 616 * pci_release_region - Release a PCI bar 617 * @pdev: PCI device whose resources were previously reserved by pci_request_region 618 * @bar: BAR to release 619 * 620 * Releases the PCI I/O and memory resources previously reserved by a 621 * successful call to pci_request_region. Call this function only 622 * after all use of the PCI regions has ceased. 623 */ 624 void pci_release_region(struct pci_dev *pdev, int bar) 625 { 626 if (pci_resource_len(pdev, bar) == 0) 627 return; 628 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) 629 release_region(pci_resource_start(pdev, bar), 630 pci_resource_len(pdev, bar)); 631 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) 632 release_mem_region(pci_resource_start(pdev, bar), 633 pci_resource_len(pdev, bar)); 634 } 635 636 /** 637 * pci_request_region - Reserved PCI I/O and memory resource 638 * @pdev: PCI device whose resources are to be reserved 639 * @bar: BAR to be reserved 640 * @res_name: Name to be associated with resource. 641 * 642 * Mark the PCI region associated with PCI device @pdev BR @bar as 643 * being reserved by owner @res_name. Do not access any 644 * address inside the PCI regions unless this call returns 645 * successfully. 646 * 647 * Returns 0 on success, or %EBUSY on error. A warning 648 * message is also printed on failure. 649 */ 650 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) 651 { 652 if (pci_resource_len(pdev, bar) == 0) 653 return 0; 654 655 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) { 656 if (!request_region(pci_resource_start(pdev, bar), 657 pci_resource_len(pdev, bar), res_name)) 658 goto err_out; 659 } 660 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) { 661 if (!request_mem_region(pci_resource_start(pdev, bar), 662 pci_resource_len(pdev, bar), res_name)) 663 goto err_out; 664 } 665 666 return 0; 667 668 err_out: 669 printk (KERN_WARNING "PCI: Unable to reserve %s region #%d:%lx@%lx for device %s\n", 670 pci_resource_flags(pdev, bar) & IORESOURCE_IO ? "I/O" : "mem", 671 bar + 1, /* PCI BAR # */ 672 pci_resource_len(pdev, bar), pci_resource_start(pdev, bar), 673 pci_name(pdev)); 674 return -EBUSY; 675 } 676 677 678 /** 679 * pci_release_regions - Release reserved PCI I/O and memory resources 680 * @pdev: PCI device whose resources were previously reserved by pci_request_regions 681 * 682 * Releases all PCI I/O and memory resources previously reserved by a 683 * successful call to pci_request_regions. Call this function only 684 * after all use of the PCI regions has ceased. 685 */ 686 687 void pci_release_regions(struct pci_dev *pdev) 688 { 689 int i; 690 691 for (i = 0; i < 6; i++) 692 pci_release_region(pdev, i); 693 } 694 695 /** 696 * pci_request_regions - Reserved PCI I/O and memory resources 697 * @pdev: PCI device whose resources are to be reserved 698 * @res_name: Name to be associated with resource. 699 * 700 * Mark all PCI regions associated with PCI device @pdev as 701 * being reserved by owner @res_name. Do not access any 702 * address inside the PCI regions unless this call returns 703 * successfully. 704 * 705 * Returns 0 on success, or %EBUSY on error. A warning 706 * message is also printed on failure. 707 */ 708 int pci_request_regions(struct pci_dev *pdev, const char *res_name) 709 { 710 int i; 711 712 for (i = 0; i < 6; i++) 713 if(pci_request_region(pdev, i, res_name)) 714 goto err_out; 715 return 0; 716 717 err_out: 718 while(--i >= 0) 719 pci_release_region(pdev, i); 720 721 return -EBUSY; 722 } 723 724 /** 725 * pci_set_master - enables bus-mastering for device dev 726 * @dev: the PCI device to enable 727 * 728 * Enables bus-mastering on the device and calls pcibios_set_master() 729 * to do the needed arch specific settings. 730 */ 731 void 732 pci_set_master(struct pci_dev *dev) 733 { 734 u16 cmd; 735 736 pci_read_config_word(dev, PCI_COMMAND, &cmd); 737 if (! (cmd & PCI_COMMAND_MASTER)) { 738 pr_debug("PCI: Enabling bus mastering for device %s\n", pci_name(dev)); 739 cmd |= PCI_COMMAND_MASTER; 740 pci_write_config_word(dev, PCI_COMMAND, cmd); 741 } 742 dev->is_busmaster = 1; 743 pcibios_set_master(dev); 744 } 745 746 #ifndef HAVE_ARCH_PCI_MWI 747 /* This can be overridden by arch code. */ 748 u8 pci_cache_line_size = L1_CACHE_BYTES >> 2; 749 750 /** 751 * pci_generic_prep_mwi - helper function for pci_set_mwi 752 * @dev: the PCI device for which MWI is enabled 753 * 754 * Helper function for generic implementation of pcibios_prep_mwi 755 * function. Originally copied from drivers/net/acenic.c. 756 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. 757 * 758 * RETURNS: An appropriate -ERRNO error value on error, or zero for success. 759 */ 760 static int 761 pci_generic_prep_mwi(struct pci_dev *dev) 762 { 763 u8 cacheline_size; 764 765 if (!pci_cache_line_size) 766 return -EINVAL; /* The system doesn't support MWI. */ 767 768 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be 769 equal to or multiple of the right value. */ 770 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); 771 if (cacheline_size >= pci_cache_line_size && 772 (cacheline_size % pci_cache_line_size) == 0) 773 return 0; 774 775 /* Write the correct value. */ 776 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size); 777 /* Read it back. */ 778 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); 779 if (cacheline_size == pci_cache_line_size) 780 return 0; 781 782 printk(KERN_DEBUG "PCI: cache line size of %d is not supported " 783 "by device %s\n", pci_cache_line_size << 2, pci_name(dev)); 784 785 return -EINVAL; 786 } 787 #endif /* !HAVE_ARCH_PCI_MWI */ 788 789 /** 790 * pci_set_mwi - enables memory-write-invalidate PCI transaction 791 * @dev: the PCI device for which MWI is enabled 792 * 793 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND, 794 * and then calls @pcibios_set_mwi to do the needed arch specific 795 * operations or a generic mwi-prep function. 796 * 797 * RETURNS: An appropriate -ERRNO error value on error, or zero for success. 798 */ 799 int 800 pci_set_mwi(struct pci_dev *dev) 801 { 802 int rc; 803 u16 cmd; 804 805 #ifdef HAVE_ARCH_PCI_MWI 806 rc = pcibios_prep_mwi(dev); 807 #else 808 rc = pci_generic_prep_mwi(dev); 809 #endif 810 811 if (rc) 812 return rc; 813 814 pci_read_config_word(dev, PCI_COMMAND, &cmd); 815 if (! (cmd & PCI_COMMAND_INVALIDATE)) { 816 pr_debug("PCI: Enabling Mem-Wr-Inval for device %s\n", pci_name(dev)); 817 cmd |= PCI_COMMAND_INVALIDATE; 818 pci_write_config_word(dev, PCI_COMMAND, cmd); 819 } 820 821 return 0; 822 } 823 824 /** 825 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev 826 * @dev: the PCI device to disable 827 * 828 * Disables PCI Memory-Write-Invalidate transaction on the device 829 */ 830 void 831 pci_clear_mwi(struct pci_dev *dev) 832 { 833 u16 cmd; 834 835 pci_read_config_word(dev, PCI_COMMAND, &cmd); 836 if (cmd & PCI_COMMAND_INVALIDATE) { 837 cmd &= ~PCI_COMMAND_INVALIDATE; 838 pci_write_config_word(dev, PCI_COMMAND, cmd); 839 } 840 } 841 842 /** 843 * pci_intx - enables/disables PCI INTx for device dev 844 * @pdev: the PCI device to operate on 845 * @enable: boolean: whether to enable or disable PCI INTx 846 * 847 * Enables/disables PCI INTx for device dev 848 */ 849 void 850 pci_intx(struct pci_dev *pdev, int enable) 851 { 852 u16 pci_command, new; 853 854 pci_read_config_word(pdev, PCI_COMMAND, &pci_command); 855 856 if (enable) { 857 new = pci_command & ~PCI_COMMAND_INTX_DISABLE; 858 } else { 859 new = pci_command | PCI_COMMAND_INTX_DISABLE; 860 } 861 862 if (new != pci_command) { 863 pci_write_config_word(pdev, PCI_COMMAND, new); 864 } 865 } 866 867 #ifndef HAVE_ARCH_PCI_SET_DMA_MASK 868 /* 869 * These can be overridden by arch-specific implementations 870 */ 871 int 872 pci_set_dma_mask(struct pci_dev *dev, u64 mask) 873 { 874 if (!pci_dma_supported(dev, mask)) 875 return -EIO; 876 877 dev->dma_mask = mask; 878 879 return 0; 880 } 881 882 int 883 pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask) 884 { 885 if (!pci_dma_supported(dev, mask)) 886 return -EIO; 887 888 dev->dev.coherent_dma_mask = mask; 889 890 return 0; 891 } 892 #endif 893 894 static int __devinit pci_init(void) 895 { 896 struct pci_dev *dev = NULL; 897 898 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { 899 pci_fixup_device(pci_fixup_final, dev); 900 } 901 return 0; 902 } 903 904 static int __devinit pci_setup(char *str) 905 { 906 while (str) { 907 char *k = strchr(str, ','); 908 if (k) 909 *k++ = 0; 910 if (*str && (str = pcibios_setup(str)) && *str) { 911 if (!strcmp(str, "nomsi")) { 912 pci_no_msi(); 913 } else { 914 printk(KERN_ERR "PCI: Unknown option `%s'\n", 915 str); 916 } 917 } 918 str = k; 919 } 920 return 1; 921 } 922 923 device_initcall(pci_init); 924 925 __setup("pci=", pci_setup); 926 927 #if defined(CONFIG_ISA) || defined(CONFIG_EISA) 928 /* FIXME: Some boxes have multiple ISA bridges! */ 929 struct pci_dev *isa_bridge; 930 EXPORT_SYMBOL(isa_bridge); 931 #endif 932 933 EXPORT_SYMBOL_GPL(pci_restore_bars); 934 EXPORT_SYMBOL(pci_enable_device_bars); 935 EXPORT_SYMBOL(pci_enable_device); 936 EXPORT_SYMBOL(pci_disable_device); 937 EXPORT_SYMBOL(pci_find_capability); 938 EXPORT_SYMBOL(pci_bus_find_capability); 939 EXPORT_SYMBOL(pci_release_regions); 940 EXPORT_SYMBOL(pci_request_regions); 941 EXPORT_SYMBOL(pci_release_region); 942 EXPORT_SYMBOL(pci_request_region); 943 EXPORT_SYMBOL(pci_set_master); 944 EXPORT_SYMBOL(pci_set_mwi); 945 EXPORT_SYMBOL(pci_clear_mwi); 946 EXPORT_SYMBOL_GPL(pci_intx); 947 EXPORT_SYMBOL(pci_set_dma_mask); 948 EXPORT_SYMBOL(pci_set_consistent_dma_mask); 949 EXPORT_SYMBOL(pci_assign_resource); 950 EXPORT_SYMBOL(pci_find_parent_resource); 951 952 EXPORT_SYMBOL(pci_set_power_state); 953 EXPORT_SYMBOL(pci_save_state); 954 EXPORT_SYMBOL(pci_restore_state); 955 EXPORT_SYMBOL(pci_enable_wake); 956 957 /* Quirk info */ 958 959 EXPORT_SYMBOL(isa_dma_bridge_buggy); 960 EXPORT_SYMBOL(pci_pci_problems); 961