1 /* 2 * $Id: pci.c,v 1.91 1999/01/21 13:34:01 davem Exp $ 3 * 4 * PCI Bus Services, see include/linux/pci.h for further explanation. 5 * 6 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter, 7 * David Mosberger-Tang 8 * 9 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz> 10 */ 11 12 #include <linux/kernel.h> 13 #include <linux/delay.h> 14 #include <linux/init.h> 15 #include <linux/pci.h> 16 #include <linux/module.h> 17 #include <linux/spinlock.h> 18 #include <asm/dma.h> /* isa_dma_bridge_buggy */ 19 #include "pci.h" 20 21 22 /** 23 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children 24 * @bus: pointer to PCI bus structure to search 25 * 26 * Given a PCI bus, returns the highest PCI bus number present in the set 27 * including the given PCI bus and its list of child PCI buses. 28 */ 29 unsigned char __devinit 30 pci_bus_max_busnr(struct pci_bus* bus) 31 { 32 struct list_head *tmp; 33 unsigned char max, n; 34 35 max = bus->number; 36 list_for_each(tmp, &bus->children) { 37 n = pci_bus_max_busnr(pci_bus_b(tmp)); 38 if(n > max) 39 max = n; 40 } 41 return max; 42 } 43 44 /** 45 * pci_max_busnr - returns maximum PCI bus number 46 * 47 * Returns the highest PCI bus number present in the system global list of 48 * PCI buses. 49 */ 50 unsigned char __devinit 51 pci_max_busnr(void) 52 { 53 struct pci_bus *bus = NULL; 54 unsigned char max, n; 55 56 max = 0; 57 while ((bus = pci_find_next_bus(bus)) != NULL) { 58 n = pci_bus_max_busnr(bus); 59 if(n > max) 60 max = n; 61 } 62 return max; 63 } 64 65 static int __pci_bus_find_cap(struct pci_bus *bus, unsigned int devfn, u8 hdr_type, int cap) 66 { 67 u16 status; 68 u8 pos, id; 69 int ttl = 48; 70 71 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status); 72 if (!(status & PCI_STATUS_CAP_LIST)) 73 return 0; 74 75 switch (hdr_type) { 76 case PCI_HEADER_TYPE_NORMAL: 77 case PCI_HEADER_TYPE_BRIDGE: 78 pci_bus_read_config_byte(bus, devfn, PCI_CAPABILITY_LIST, &pos); 79 break; 80 case PCI_HEADER_TYPE_CARDBUS: 81 pci_bus_read_config_byte(bus, devfn, PCI_CB_CAPABILITY_LIST, &pos); 82 break; 83 default: 84 return 0; 85 } 86 while (ttl-- && pos >= 0x40) { 87 pos &= ~3; 88 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID, &id); 89 if (id == 0xff) 90 break; 91 if (id == cap) 92 return pos; 93 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_NEXT, &pos); 94 } 95 return 0; 96 } 97 98 /** 99 * pci_find_capability - query for devices' capabilities 100 * @dev: PCI device to query 101 * @cap: capability code 102 * 103 * Tell if a device supports a given PCI capability. 104 * Returns the address of the requested capability structure within the 105 * device's PCI configuration space or 0 in case the device does not 106 * support it. Possible values for @cap: 107 * 108 * %PCI_CAP_ID_PM Power Management 109 * %PCI_CAP_ID_AGP Accelerated Graphics Port 110 * %PCI_CAP_ID_VPD Vital Product Data 111 * %PCI_CAP_ID_SLOTID Slot Identification 112 * %PCI_CAP_ID_MSI Message Signalled Interrupts 113 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap 114 * %PCI_CAP_ID_PCIX PCI-X 115 * %PCI_CAP_ID_EXP PCI Express 116 */ 117 int pci_find_capability(struct pci_dev *dev, int cap) 118 { 119 return __pci_bus_find_cap(dev->bus, dev->devfn, dev->hdr_type, cap); 120 } 121 122 /** 123 * pci_bus_find_capability - query for devices' capabilities 124 * @bus: the PCI bus to query 125 * @devfn: PCI device to query 126 * @cap: capability code 127 * 128 * Like pci_find_capability() but works for pci devices that do not have a 129 * pci_dev structure set up yet. 130 * 131 * Returns the address of the requested capability structure within the 132 * device's PCI configuration space or 0 in case the device does not 133 * support it. 134 */ 135 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap) 136 { 137 u8 hdr_type; 138 139 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type); 140 141 return __pci_bus_find_cap(bus, devfn, hdr_type & 0x7f, cap); 142 } 143 144 /** 145 * pci_find_ext_capability - Find an extended capability 146 * @dev: PCI device to query 147 * @cap: capability code 148 * 149 * Returns the address of the requested extended capability structure 150 * within the device's PCI configuration space or 0 if the device does 151 * not support it. Possible values for @cap: 152 * 153 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting 154 * %PCI_EXT_CAP_ID_VC Virtual Channel 155 * %PCI_EXT_CAP_ID_DSN Device Serial Number 156 * %PCI_EXT_CAP_ID_PWR Power Budgeting 157 */ 158 int pci_find_ext_capability(struct pci_dev *dev, int cap) 159 { 160 u32 header; 161 int ttl = 480; /* 3840 bytes, minimum 8 bytes per capability */ 162 int pos = 0x100; 163 164 if (dev->cfg_size <= 256) 165 return 0; 166 167 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) 168 return 0; 169 170 /* 171 * If we have no capabilities, this is indicated by cap ID, 172 * cap version and next pointer all being 0. 173 */ 174 if (header == 0) 175 return 0; 176 177 while (ttl-- > 0) { 178 if (PCI_EXT_CAP_ID(header) == cap) 179 return pos; 180 181 pos = PCI_EXT_CAP_NEXT(header); 182 if (pos < 0x100) 183 break; 184 185 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) 186 break; 187 } 188 189 return 0; 190 } 191 192 /** 193 * pci_find_parent_resource - return resource region of parent bus of given region 194 * @dev: PCI device structure contains resources to be searched 195 * @res: child resource record for which parent is sought 196 * 197 * For given resource region of given device, return the resource 198 * region of parent bus the given region is contained in or where 199 * it should be allocated from. 200 */ 201 struct resource * 202 pci_find_parent_resource(const struct pci_dev *dev, struct resource *res) 203 { 204 const struct pci_bus *bus = dev->bus; 205 int i; 206 struct resource *best = NULL; 207 208 for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++) { 209 struct resource *r = bus->resource[i]; 210 if (!r) 211 continue; 212 if (res->start && !(res->start >= r->start && res->end <= r->end)) 213 continue; /* Not contained */ 214 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM)) 215 continue; /* Wrong type */ 216 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH)) 217 return r; /* Exact match */ 218 if ((res->flags & IORESOURCE_PREFETCH) && !(r->flags & IORESOURCE_PREFETCH)) 219 best = r; /* Approximating prefetchable by non-prefetchable */ 220 } 221 return best; 222 } 223 224 /** 225 * pci_set_power_state - Set the power state of a PCI device 226 * @dev: PCI device to be suspended 227 * @state: PCI power state (D0, D1, D2, D3hot, D3cold) we're entering 228 * 229 * Transition a device to a new power state, using the Power Management 230 * Capabilities in the device's config space. 231 * 232 * RETURN VALUE: 233 * -EINVAL if trying to enter a lower state than we're already in. 234 * 0 if we're already in the requested state. 235 * -EIO if device does not support PCI PM. 236 * 0 if we can successfully change the power state. 237 */ 238 239 int 240 pci_set_power_state(struct pci_dev *dev, pci_power_t state) 241 { 242 int pm; 243 u16 pmcsr, pmc; 244 245 /* bound the state we're entering */ 246 if (state > PCI_D3hot) 247 state = PCI_D3hot; 248 249 /* Validate current state: 250 * Can enter D0 from any state, but if we can only go deeper 251 * to sleep if we're already in a low power state 252 */ 253 if (state != PCI_D0 && dev->current_state > state) 254 return -EINVAL; 255 else if (dev->current_state == state) 256 return 0; /* we're already there */ 257 258 /* find PCI PM capability in list */ 259 pm = pci_find_capability(dev, PCI_CAP_ID_PM); 260 261 /* abort if the device doesn't support PM capabilities */ 262 if (!pm) 263 return -EIO; 264 265 pci_read_config_word(dev,pm + PCI_PM_PMC,&pmc); 266 if ((pmc & PCI_PM_CAP_VER_MASK) > 2) { 267 printk(KERN_DEBUG 268 "PCI: %s has unsupported PM cap regs version (%u)\n", 269 pci_name(dev), pmc & PCI_PM_CAP_VER_MASK); 270 return -EIO; 271 } 272 273 /* check if this device supports the desired state */ 274 if (state == PCI_D1 || state == PCI_D2) { 275 if (state == PCI_D1 && !(pmc & PCI_PM_CAP_D1)) 276 return -EIO; 277 else if (state == PCI_D2 && !(pmc & PCI_PM_CAP_D2)) 278 return -EIO; 279 } 280 281 /* If we're in D3, force entire word to 0. 282 * This doesn't affect PME_Status, disables PME_En, and 283 * sets PowerState to 0. 284 */ 285 if (dev->current_state >= PCI_D3hot) 286 pmcsr = 0; 287 else { 288 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr); 289 pmcsr &= ~PCI_PM_CTRL_STATE_MASK; 290 pmcsr |= state; 291 } 292 293 /* enter specified state */ 294 pci_write_config_word(dev, pm + PCI_PM_CTRL, pmcsr); 295 296 /* Mandatory power management transition delays */ 297 /* see PCI PM 1.1 5.6.1 table 18 */ 298 if (state == PCI_D3hot || dev->current_state == PCI_D3hot) 299 msleep(10); 300 else if (state == PCI_D2 || dev->current_state == PCI_D2) 301 udelay(200); 302 dev->current_state = state; 303 304 return 0; 305 } 306 307 /** 308 * pci_choose_state - Choose the power state of a PCI device 309 * @dev: PCI device to be suspended 310 * @state: target sleep state for the whole system. This is the value 311 * that is passed to suspend() function. 312 * 313 * Returns PCI power state suitable for given device and given system 314 * message. 315 */ 316 317 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state) 318 { 319 if (!pci_find_capability(dev, PCI_CAP_ID_PM)) 320 return PCI_D0; 321 322 switch (state) { 323 case 0: return PCI_D0; 324 case 3: return PCI_D3hot; 325 default: 326 printk("They asked me for state %d\n", state); 327 BUG(); 328 } 329 return PCI_D0; 330 } 331 332 EXPORT_SYMBOL(pci_choose_state); 333 334 /** 335 * pci_save_state - save the PCI configuration space of a device before suspending 336 * @dev: - PCI device that we're dealing with 337 * @buffer: - buffer to hold config space context 338 * 339 * @buffer must be large enough to hold the entire PCI 2.2 config space 340 * (>= 64 bytes). 341 */ 342 int 343 pci_save_state(struct pci_dev *dev) 344 { 345 int i; 346 /* XXX: 100% dword access ok here? */ 347 for (i = 0; i < 16; i++) 348 pci_read_config_dword(dev, i * 4,&dev->saved_config_space[i]); 349 return 0; 350 } 351 352 /** 353 * pci_restore_state - Restore the saved state of a PCI device 354 * @dev: - PCI device that we're dealing with 355 * @buffer: - saved PCI config space 356 * 357 */ 358 int 359 pci_restore_state(struct pci_dev *dev) 360 { 361 int i; 362 363 for (i = 0; i < 16; i++) 364 pci_write_config_dword(dev,i * 4, dev->saved_config_space[i]); 365 return 0; 366 } 367 368 /** 369 * pci_enable_device_bars - Initialize some of a device for use 370 * @dev: PCI device to be initialized 371 * @bars: bitmask of BAR's that must be configured 372 * 373 * Initialize device before it's used by a driver. Ask low-level code 374 * to enable selected I/O and memory resources. Wake up the device if it 375 * was suspended. Beware, this function can fail. 376 */ 377 378 int 379 pci_enable_device_bars(struct pci_dev *dev, int bars) 380 { 381 int err; 382 383 pci_set_power_state(dev, PCI_D0); 384 if ((err = pcibios_enable_device(dev, bars)) < 0) 385 return err; 386 return 0; 387 } 388 389 /** 390 * pci_enable_device - Initialize device before it's used by a driver. 391 * @dev: PCI device to be initialized 392 * 393 * Initialize device before it's used by a driver. Ask low-level code 394 * to enable I/O and memory. Wake up the device if it was suspended. 395 * Beware, this function can fail. 396 */ 397 int 398 pci_enable_device(struct pci_dev *dev) 399 { 400 int err; 401 402 if ((err = pci_enable_device_bars(dev, (1 << PCI_NUM_RESOURCES) - 1))) 403 return err; 404 pci_fixup_device(pci_fixup_enable, dev); 405 dev->is_enabled = 1; 406 return 0; 407 } 408 409 /** 410 * pcibios_disable_device - disable arch specific PCI resources for device dev 411 * @dev: the PCI device to disable 412 * 413 * Disables architecture specific PCI resources for the device. This 414 * is the default implementation. Architecture implementations can 415 * override this. 416 */ 417 void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {} 418 419 /** 420 * pci_disable_device - Disable PCI device after use 421 * @dev: PCI device to be disabled 422 * 423 * Signal to the system that the PCI device is not in use by the system 424 * anymore. This only involves disabling PCI bus-mastering, if active. 425 */ 426 void 427 pci_disable_device(struct pci_dev *dev) 428 { 429 u16 pci_command; 430 431 pci_read_config_word(dev, PCI_COMMAND, &pci_command); 432 if (pci_command & PCI_COMMAND_MASTER) { 433 pci_command &= ~PCI_COMMAND_MASTER; 434 pci_write_config_word(dev, PCI_COMMAND, pci_command); 435 } 436 dev->is_busmaster = 0; 437 438 pcibios_disable_device(dev); 439 dev->is_enabled = 0; 440 } 441 442 /** 443 * pci_enable_wake - enable device to generate PME# when suspended 444 * @dev: - PCI device to operate on 445 * @state: - Current state of device. 446 * @enable: - Flag to enable or disable generation 447 * 448 * Set the bits in the device's PM Capabilities to generate PME# when 449 * the system is suspended. 450 * 451 * -EIO is returned if device doesn't have PM Capabilities. 452 * -EINVAL is returned if device supports it, but can't generate wake events. 453 * 0 if operation is successful. 454 * 455 */ 456 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable) 457 { 458 int pm; 459 u16 value; 460 461 /* find PCI PM capability in list */ 462 pm = pci_find_capability(dev, PCI_CAP_ID_PM); 463 464 /* If device doesn't support PM Capabilities, but request is to disable 465 * wake events, it's a nop; otherwise fail */ 466 if (!pm) 467 return enable ? -EIO : 0; 468 469 /* Check device's ability to generate PME# */ 470 pci_read_config_word(dev,pm+PCI_PM_PMC,&value); 471 472 value &= PCI_PM_CAP_PME_MASK; 473 value >>= ffs(PCI_PM_CAP_PME_MASK) - 1; /* First bit of mask */ 474 475 /* Check if it can generate PME# from requested state. */ 476 if (!value || !(value & (1 << state))) 477 return enable ? -EINVAL : 0; 478 479 pci_read_config_word(dev, pm + PCI_PM_CTRL, &value); 480 481 /* Clear PME_Status by writing 1 to it and enable PME# */ 482 value |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE; 483 484 if (!enable) 485 value &= ~PCI_PM_CTRL_PME_ENABLE; 486 487 pci_write_config_word(dev, pm + PCI_PM_CTRL, value); 488 489 return 0; 490 } 491 492 int 493 pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge) 494 { 495 u8 pin; 496 497 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); 498 if (!pin) 499 return -1; 500 pin--; 501 while (dev->bus->self) { 502 pin = (pin + PCI_SLOT(dev->devfn)) % 4; 503 dev = dev->bus->self; 504 } 505 *bridge = dev; 506 return pin; 507 } 508 509 /** 510 * pci_release_region - Release a PCI bar 511 * @pdev: PCI device whose resources were previously reserved by pci_request_region 512 * @bar: BAR to release 513 * 514 * Releases the PCI I/O and memory resources previously reserved by a 515 * successful call to pci_request_region. Call this function only 516 * after all use of the PCI regions has ceased. 517 */ 518 void pci_release_region(struct pci_dev *pdev, int bar) 519 { 520 if (pci_resource_len(pdev, bar) == 0) 521 return; 522 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) 523 release_region(pci_resource_start(pdev, bar), 524 pci_resource_len(pdev, bar)); 525 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) 526 release_mem_region(pci_resource_start(pdev, bar), 527 pci_resource_len(pdev, bar)); 528 } 529 530 /** 531 * pci_request_region - Reserved PCI I/O and memory resource 532 * @pdev: PCI device whose resources are to be reserved 533 * @bar: BAR to be reserved 534 * @res_name: Name to be associated with resource. 535 * 536 * Mark the PCI region associated with PCI device @pdev BR @bar as 537 * being reserved by owner @res_name. Do not access any 538 * address inside the PCI regions unless this call returns 539 * successfully. 540 * 541 * Returns 0 on success, or %EBUSY on error. A warning 542 * message is also printed on failure. 543 */ 544 int pci_request_region(struct pci_dev *pdev, int bar, char *res_name) 545 { 546 if (pci_resource_len(pdev, bar) == 0) 547 return 0; 548 549 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) { 550 if (!request_region(pci_resource_start(pdev, bar), 551 pci_resource_len(pdev, bar), res_name)) 552 goto err_out; 553 } 554 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) { 555 if (!request_mem_region(pci_resource_start(pdev, bar), 556 pci_resource_len(pdev, bar), res_name)) 557 goto err_out; 558 } 559 560 return 0; 561 562 err_out: 563 printk (KERN_WARNING "PCI: Unable to reserve %s region #%d:%lx@%lx for device %s\n", 564 pci_resource_flags(pdev, bar) & IORESOURCE_IO ? "I/O" : "mem", 565 bar + 1, /* PCI BAR # */ 566 pci_resource_len(pdev, bar), pci_resource_start(pdev, bar), 567 pci_name(pdev)); 568 return -EBUSY; 569 } 570 571 572 /** 573 * pci_release_regions - Release reserved PCI I/O and memory resources 574 * @pdev: PCI device whose resources were previously reserved by pci_request_regions 575 * 576 * Releases all PCI I/O and memory resources previously reserved by a 577 * successful call to pci_request_regions. Call this function only 578 * after all use of the PCI regions has ceased. 579 */ 580 581 void pci_release_regions(struct pci_dev *pdev) 582 { 583 int i; 584 585 for (i = 0; i < 6; i++) 586 pci_release_region(pdev, i); 587 } 588 589 /** 590 * pci_request_regions - Reserved PCI I/O and memory resources 591 * @pdev: PCI device whose resources are to be reserved 592 * @res_name: Name to be associated with resource. 593 * 594 * Mark all PCI regions associated with PCI device @pdev as 595 * being reserved by owner @res_name. Do not access any 596 * address inside the PCI regions unless this call returns 597 * successfully. 598 * 599 * Returns 0 on success, or %EBUSY on error. A warning 600 * message is also printed on failure. 601 */ 602 int pci_request_regions(struct pci_dev *pdev, char *res_name) 603 { 604 int i; 605 606 for (i = 0; i < 6; i++) 607 if(pci_request_region(pdev, i, res_name)) 608 goto err_out; 609 return 0; 610 611 err_out: 612 while(--i >= 0) 613 pci_release_region(pdev, i); 614 615 return -EBUSY; 616 } 617 618 /** 619 * pci_set_master - enables bus-mastering for device dev 620 * @dev: the PCI device to enable 621 * 622 * Enables bus-mastering on the device and calls pcibios_set_master() 623 * to do the needed arch specific settings. 624 */ 625 void 626 pci_set_master(struct pci_dev *dev) 627 { 628 u16 cmd; 629 630 pci_read_config_word(dev, PCI_COMMAND, &cmd); 631 if (! (cmd & PCI_COMMAND_MASTER)) { 632 pr_debug("PCI: Enabling bus mastering for device %s\n", pci_name(dev)); 633 cmd |= PCI_COMMAND_MASTER; 634 pci_write_config_word(dev, PCI_COMMAND, cmd); 635 } 636 dev->is_busmaster = 1; 637 pcibios_set_master(dev); 638 } 639 640 #ifndef HAVE_ARCH_PCI_MWI 641 /* This can be overridden by arch code. */ 642 u8 pci_cache_line_size = L1_CACHE_BYTES >> 2; 643 644 /** 645 * pci_generic_prep_mwi - helper function for pci_set_mwi 646 * @dev: the PCI device for which MWI is enabled 647 * 648 * Helper function for generic implementation of pcibios_prep_mwi 649 * function. Originally copied from drivers/net/acenic.c. 650 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. 651 * 652 * RETURNS: An appropriate -ERRNO error value on error, or zero for success. 653 */ 654 static int 655 pci_generic_prep_mwi(struct pci_dev *dev) 656 { 657 u8 cacheline_size; 658 659 if (!pci_cache_line_size) 660 return -EINVAL; /* The system doesn't support MWI. */ 661 662 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be 663 equal to or multiple of the right value. */ 664 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); 665 if (cacheline_size >= pci_cache_line_size && 666 (cacheline_size % pci_cache_line_size) == 0) 667 return 0; 668 669 /* Write the correct value. */ 670 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size); 671 /* Read it back. */ 672 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); 673 if (cacheline_size == pci_cache_line_size) 674 return 0; 675 676 printk(KERN_DEBUG "PCI: cache line size of %d is not supported " 677 "by device %s\n", pci_cache_line_size << 2, pci_name(dev)); 678 679 return -EINVAL; 680 } 681 #endif /* !HAVE_ARCH_PCI_MWI */ 682 683 /** 684 * pci_set_mwi - enables memory-write-invalidate PCI transaction 685 * @dev: the PCI device for which MWI is enabled 686 * 687 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND, 688 * and then calls @pcibios_set_mwi to do the needed arch specific 689 * operations or a generic mwi-prep function. 690 * 691 * RETURNS: An appropriate -ERRNO error value on error, or zero for success. 692 */ 693 int 694 pci_set_mwi(struct pci_dev *dev) 695 { 696 int rc; 697 u16 cmd; 698 699 #ifdef HAVE_ARCH_PCI_MWI 700 rc = pcibios_prep_mwi(dev); 701 #else 702 rc = pci_generic_prep_mwi(dev); 703 #endif 704 705 if (rc) 706 return rc; 707 708 pci_read_config_word(dev, PCI_COMMAND, &cmd); 709 if (! (cmd & PCI_COMMAND_INVALIDATE)) { 710 pr_debug("PCI: Enabling Mem-Wr-Inval for device %s\n", pci_name(dev)); 711 cmd |= PCI_COMMAND_INVALIDATE; 712 pci_write_config_word(dev, PCI_COMMAND, cmd); 713 } 714 715 return 0; 716 } 717 718 /** 719 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev 720 * @dev: the PCI device to disable 721 * 722 * Disables PCI Memory-Write-Invalidate transaction on the device 723 */ 724 void 725 pci_clear_mwi(struct pci_dev *dev) 726 { 727 u16 cmd; 728 729 pci_read_config_word(dev, PCI_COMMAND, &cmd); 730 if (cmd & PCI_COMMAND_INVALIDATE) { 731 cmd &= ~PCI_COMMAND_INVALIDATE; 732 pci_write_config_word(dev, PCI_COMMAND, cmd); 733 } 734 } 735 736 #ifndef HAVE_ARCH_PCI_SET_DMA_MASK 737 /* 738 * These can be overridden by arch-specific implementations 739 */ 740 int 741 pci_set_dma_mask(struct pci_dev *dev, u64 mask) 742 { 743 if (!pci_dma_supported(dev, mask)) 744 return -EIO; 745 746 dev->dma_mask = mask; 747 748 return 0; 749 } 750 751 int 752 pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask) 753 { 754 if (!pci_dma_supported(dev, mask)) 755 return -EIO; 756 757 dev->dev.coherent_dma_mask = mask; 758 759 return 0; 760 } 761 #endif 762 763 static int __devinit pci_init(void) 764 { 765 struct pci_dev *dev = NULL; 766 767 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { 768 pci_fixup_device(pci_fixup_final, dev); 769 } 770 return 0; 771 } 772 773 static int __devinit pci_setup(char *str) 774 { 775 while (str) { 776 char *k = strchr(str, ','); 777 if (k) 778 *k++ = 0; 779 if (*str && (str = pcibios_setup(str)) && *str) { 780 /* PCI layer options should be handled here */ 781 printk(KERN_ERR "PCI: Unknown option `%s'\n", str); 782 } 783 str = k; 784 } 785 return 1; 786 } 787 788 device_initcall(pci_init); 789 790 __setup("pci=", pci_setup); 791 792 #if defined(CONFIG_ISA) || defined(CONFIG_EISA) 793 /* FIXME: Some boxes have multiple ISA bridges! */ 794 struct pci_dev *isa_bridge; 795 EXPORT_SYMBOL(isa_bridge); 796 #endif 797 798 EXPORT_SYMBOL(pci_enable_device_bars); 799 EXPORT_SYMBOL(pci_enable_device); 800 EXPORT_SYMBOL(pci_disable_device); 801 EXPORT_SYMBOL(pci_max_busnr); 802 EXPORT_SYMBOL(pci_bus_max_busnr); 803 EXPORT_SYMBOL(pci_find_capability); 804 EXPORT_SYMBOL(pci_bus_find_capability); 805 EXPORT_SYMBOL(pci_release_regions); 806 EXPORT_SYMBOL(pci_request_regions); 807 EXPORT_SYMBOL(pci_release_region); 808 EXPORT_SYMBOL(pci_request_region); 809 EXPORT_SYMBOL(pci_set_master); 810 EXPORT_SYMBOL(pci_set_mwi); 811 EXPORT_SYMBOL(pci_clear_mwi); 812 EXPORT_SYMBOL(pci_set_dma_mask); 813 EXPORT_SYMBOL(pci_set_consistent_dma_mask); 814 EXPORT_SYMBOL(pci_assign_resource); 815 EXPORT_SYMBOL(pci_find_parent_resource); 816 817 EXPORT_SYMBOL(pci_set_power_state); 818 EXPORT_SYMBOL(pci_save_state); 819 EXPORT_SYMBOL(pci_restore_state); 820 EXPORT_SYMBOL(pci_enable_wake); 821 822 /* Quirk info */ 823 824 EXPORT_SYMBOL(isa_dma_bridge_buggy); 825 EXPORT_SYMBOL(pci_pci_problems); 826