1 /* 2 * PCI Bus Services, see include/linux/pci.h for further explanation. 3 * 4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter, 5 * David Mosberger-Tang 6 * 7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz> 8 */ 9 10 #include <linux/acpi.h> 11 #include <linux/kernel.h> 12 #include <linux/delay.h> 13 #include <linux/dmi.h> 14 #include <linux/init.h> 15 #include <linux/of.h> 16 #include <linux/of_pci.h> 17 #include <linux/pci.h> 18 #include <linux/pm.h> 19 #include <linux/slab.h> 20 #include <linux/module.h> 21 #include <linux/spinlock.h> 22 #include <linux/string.h> 23 #include <linux/log2.h> 24 #include <linux/pci-aspm.h> 25 #include <linux/pm_wakeup.h> 26 #include <linux/interrupt.h> 27 #include <linux/device.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/pci_hotplug.h> 30 #include <linux/vmalloc.h> 31 #include <linux/pci-ats.h> 32 #include <asm/setup.h> 33 #include <asm/dma.h> 34 #include <linux/aer.h> 35 #include "pci.h" 36 37 const char *pci_power_names[] = { 38 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown", 39 }; 40 EXPORT_SYMBOL_GPL(pci_power_names); 41 42 int isa_dma_bridge_buggy; 43 EXPORT_SYMBOL(isa_dma_bridge_buggy); 44 45 int pci_pci_problems; 46 EXPORT_SYMBOL(pci_pci_problems); 47 48 unsigned int pci_pm_d3_delay; 49 50 static void pci_pme_list_scan(struct work_struct *work); 51 52 static LIST_HEAD(pci_pme_list); 53 static DEFINE_MUTEX(pci_pme_list_mutex); 54 static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan); 55 static DEFINE_MUTEX(pci_bridge_mutex); 56 57 struct pci_pme_device { 58 struct list_head list; 59 struct pci_dev *dev; 60 }; 61 62 #define PME_TIMEOUT 1000 /* How long between PME checks */ 63 64 static void pci_dev_d3_sleep(struct pci_dev *dev) 65 { 66 unsigned int delay = dev->d3_delay; 67 68 if (delay < pci_pm_d3_delay) 69 delay = pci_pm_d3_delay; 70 71 if (delay) 72 msleep(delay); 73 } 74 75 #ifdef CONFIG_PCI_DOMAINS 76 int pci_domains_supported = 1; 77 #endif 78 79 #define DEFAULT_CARDBUS_IO_SIZE (256) 80 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024) 81 /* pci=cbmemsize=nnM,cbiosize=nn can override this */ 82 unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE; 83 unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE; 84 85 #define DEFAULT_HOTPLUG_IO_SIZE (256) 86 #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024) 87 /* pci=hpmemsize=nnM,hpiosize=nn can override this */ 88 unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE; 89 unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE; 90 91 #define DEFAULT_HOTPLUG_BUS_SIZE 1 92 unsigned long pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE; 93 94 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_DEFAULT; 95 96 /* 97 * The default CLS is used if arch didn't set CLS explicitly and not 98 * all pci devices agree on the same value. Arch can override either 99 * the dfl or actual value as it sees fit. Don't forget this is 100 * measured in 32-bit words, not bytes. 101 */ 102 u8 pci_dfl_cache_line_size = L1_CACHE_BYTES >> 2; 103 u8 pci_cache_line_size; 104 105 /* 106 * If we set up a device for bus mastering, we need to check the latency 107 * timer as certain BIOSes forget to set it properly. 108 */ 109 unsigned int pcibios_max_latency = 255; 110 111 /* If set, the PCIe ARI capability will not be used. */ 112 static bool pcie_ari_disabled; 113 114 /* Disable bridge_d3 for all PCIe ports */ 115 static bool pci_bridge_d3_disable; 116 /* Force bridge_d3 for all PCIe ports */ 117 static bool pci_bridge_d3_force; 118 119 static int __init pcie_port_pm_setup(char *str) 120 { 121 if (!strcmp(str, "off")) 122 pci_bridge_d3_disable = true; 123 else if (!strcmp(str, "force")) 124 pci_bridge_d3_force = true; 125 return 1; 126 } 127 __setup("pcie_port_pm=", pcie_port_pm_setup); 128 129 /** 130 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children 131 * @bus: pointer to PCI bus structure to search 132 * 133 * Given a PCI bus, returns the highest PCI bus number present in the set 134 * including the given PCI bus and its list of child PCI buses. 135 */ 136 unsigned char pci_bus_max_busnr(struct pci_bus *bus) 137 { 138 struct pci_bus *tmp; 139 unsigned char max, n; 140 141 max = bus->busn_res.end; 142 list_for_each_entry(tmp, &bus->children, node) { 143 n = pci_bus_max_busnr(tmp); 144 if (n > max) 145 max = n; 146 } 147 return max; 148 } 149 EXPORT_SYMBOL_GPL(pci_bus_max_busnr); 150 151 #ifdef CONFIG_HAS_IOMEM 152 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar) 153 { 154 struct resource *res = &pdev->resource[bar]; 155 156 /* 157 * Make sure the BAR is actually a memory resource, not an IO resource 158 */ 159 if (res->flags & IORESOURCE_UNSET || !(res->flags & IORESOURCE_MEM)) { 160 dev_warn(&pdev->dev, "can't ioremap BAR %d: %pR\n", bar, res); 161 return NULL; 162 } 163 return ioremap_nocache(res->start, resource_size(res)); 164 } 165 EXPORT_SYMBOL_GPL(pci_ioremap_bar); 166 167 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar) 168 { 169 /* 170 * Make sure the BAR is actually a memory resource, not an IO resource 171 */ 172 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { 173 WARN_ON(1); 174 return NULL; 175 } 176 return ioremap_wc(pci_resource_start(pdev, bar), 177 pci_resource_len(pdev, bar)); 178 } 179 EXPORT_SYMBOL_GPL(pci_ioremap_wc_bar); 180 #endif 181 182 183 static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn, 184 u8 pos, int cap, int *ttl) 185 { 186 u8 id; 187 u16 ent; 188 189 pci_bus_read_config_byte(bus, devfn, pos, &pos); 190 191 while ((*ttl)--) { 192 if (pos < 0x40) 193 break; 194 pos &= ~3; 195 pci_bus_read_config_word(bus, devfn, pos, &ent); 196 197 id = ent & 0xff; 198 if (id == 0xff) 199 break; 200 if (id == cap) 201 return pos; 202 pos = (ent >> 8); 203 } 204 return 0; 205 } 206 207 static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn, 208 u8 pos, int cap) 209 { 210 int ttl = PCI_FIND_CAP_TTL; 211 212 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl); 213 } 214 215 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap) 216 { 217 return __pci_find_next_cap(dev->bus, dev->devfn, 218 pos + PCI_CAP_LIST_NEXT, cap); 219 } 220 EXPORT_SYMBOL_GPL(pci_find_next_capability); 221 222 static int __pci_bus_find_cap_start(struct pci_bus *bus, 223 unsigned int devfn, u8 hdr_type) 224 { 225 u16 status; 226 227 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status); 228 if (!(status & PCI_STATUS_CAP_LIST)) 229 return 0; 230 231 switch (hdr_type) { 232 case PCI_HEADER_TYPE_NORMAL: 233 case PCI_HEADER_TYPE_BRIDGE: 234 return PCI_CAPABILITY_LIST; 235 case PCI_HEADER_TYPE_CARDBUS: 236 return PCI_CB_CAPABILITY_LIST; 237 } 238 239 return 0; 240 } 241 242 /** 243 * pci_find_capability - query for devices' capabilities 244 * @dev: PCI device to query 245 * @cap: capability code 246 * 247 * Tell if a device supports a given PCI capability. 248 * Returns the address of the requested capability structure within the 249 * device's PCI configuration space or 0 in case the device does not 250 * support it. Possible values for @cap: 251 * 252 * %PCI_CAP_ID_PM Power Management 253 * %PCI_CAP_ID_AGP Accelerated Graphics Port 254 * %PCI_CAP_ID_VPD Vital Product Data 255 * %PCI_CAP_ID_SLOTID Slot Identification 256 * %PCI_CAP_ID_MSI Message Signalled Interrupts 257 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap 258 * %PCI_CAP_ID_PCIX PCI-X 259 * %PCI_CAP_ID_EXP PCI Express 260 */ 261 int pci_find_capability(struct pci_dev *dev, int cap) 262 { 263 int pos; 264 265 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); 266 if (pos) 267 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap); 268 269 return pos; 270 } 271 EXPORT_SYMBOL(pci_find_capability); 272 273 /** 274 * pci_bus_find_capability - query for devices' capabilities 275 * @bus: the PCI bus to query 276 * @devfn: PCI device to query 277 * @cap: capability code 278 * 279 * Like pci_find_capability() but works for pci devices that do not have a 280 * pci_dev structure set up yet. 281 * 282 * Returns the address of the requested capability structure within the 283 * device's PCI configuration space or 0 in case the device does not 284 * support it. 285 */ 286 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap) 287 { 288 int pos; 289 u8 hdr_type; 290 291 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type); 292 293 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f); 294 if (pos) 295 pos = __pci_find_next_cap(bus, devfn, pos, cap); 296 297 return pos; 298 } 299 EXPORT_SYMBOL(pci_bus_find_capability); 300 301 /** 302 * pci_find_next_ext_capability - Find an extended capability 303 * @dev: PCI device to query 304 * @start: address at which to start looking (0 to start at beginning of list) 305 * @cap: capability code 306 * 307 * Returns the address of the next matching extended capability structure 308 * within the device's PCI configuration space or 0 if the device does 309 * not support it. Some capabilities can occur several times, e.g., the 310 * vendor-specific capability, and this provides a way to find them all. 311 */ 312 int pci_find_next_ext_capability(struct pci_dev *dev, int start, int cap) 313 { 314 u32 header; 315 int ttl; 316 int pos = PCI_CFG_SPACE_SIZE; 317 318 /* minimum 8 bytes per capability */ 319 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; 320 321 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE) 322 return 0; 323 324 if (start) 325 pos = start; 326 327 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) 328 return 0; 329 330 /* 331 * If we have no capabilities, this is indicated by cap ID, 332 * cap version and next pointer all being 0. 333 */ 334 if (header == 0) 335 return 0; 336 337 while (ttl-- > 0) { 338 if (PCI_EXT_CAP_ID(header) == cap && pos != start) 339 return pos; 340 341 pos = PCI_EXT_CAP_NEXT(header); 342 if (pos < PCI_CFG_SPACE_SIZE) 343 break; 344 345 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) 346 break; 347 } 348 349 return 0; 350 } 351 EXPORT_SYMBOL_GPL(pci_find_next_ext_capability); 352 353 /** 354 * pci_find_ext_capability - Find an extended capability 355 * @dev: PCI device to query 356 * @cap: capability code 357 * 358 * Returns the address of the requested extended capability structure 359 * within the device's PCI configuration space or 0 if the device does 360 * not support it. Possible values for @cap: 361 * 362 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting 363 * %PCI_EXT_CAP_ID_VC Virtual Channel 364 * %PCI_EXT_CAP_ID_DSN Device Serial Number 365 * %PCI_EXT_CAP_ID_PWR Power Budgeting 366 */ 367 int pci_find_ext_capability(struct pci_dev *dev, int cap) 368 { 369 return pci_find_next_ext_capability(dev, 0, cap); 370 } 371 EXPORT_SYMBOL_GPL(pci_find_ext_capability); 372 373 static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap) 374 { 375 int rc, ttl = PCI_FIND_CAP_TTL; 376 u8 cap, mask; 377 378 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST) 379 mask = HT_3BIT_CAP_MASK; 380 else 381 mask = HT_5BIT_CAP_MASK; 382 383 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos, 384 PCI_CAP_ID_HT, &ttl); 385 while (pos) { 386 rc = pci_read_config_byte(dev, pos + 3, &cap); 387 if (rc != PCIBIOS_SUCCESSFUL) 388 return 0; 389 390 if ((cap & mask) == ht_cap) 391 return pos; 392 393 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, 394 pos + PCI_CAP_LIST_NEXT, 395 PCI_CAP_ID_HT, &ttl); 396 } 397 398 return 0; 399 } 400 /** 401 * pci_find_next_ht_capability - query a device's Hypertransport capabilities 402 * @dev: PCI device to query 403 * @pos: Position from which to continue searching 404 * @ht_cap: Hypertransport capability code 405 * 406 * To be used in conjunction with pci_find_ht_capability() to search for 407 * all capabilities matching @ht_cap. @pos should always be a value returned 408 * from pci_find_ht_capability(). 409 * 410 * NB. To be 100% safe against broken PCI devices, the caller should take 411 * steps to avoid an infinite loop. 412 */ 413 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap) 414 { 415 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap); 416 } 417 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability); 418 419 /** 420 * pci_find_ht_capability - query a device's Hypertransport capabilities 421 * @dev: PCI device to query 422 * @ht_cap: Hypertransport capability code 423 * 424 * Tell if a device supports a given Hypertransport capability. 425 * Returns an address within the device's PCI configuration space 426 * or 0 in case the device does not support the request capability. 427 * The address points to the PCI capability, of type PCI_CAP_ID_HT, 428 * which has a Hypertransport capability matching @ht_cap. 429 */ 430 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap) 431 { 432 int pos; 433 434 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); 435 if (pos) 436 pos = __pci_find_next_ht_cap(dev, pos, ht_cap); 437 438 return pos; 439 } 440 EXPORT_SYMBOL_GPL(pci_find_ht_capability); 441 442 /** 443 * pci_find_parent_resource - return resource region of parent bus of given region 444 * @dev: PCI device structure contains resources to be searched 445 * @res: child resource record for which parent is sought 446 * 447 * For given resource region of given device, return the resource 448 * region of parent bus the given region is contained in. 449 */ 450 struct resource *pci_find_parent_resource(const struct pci_dev *dev, 451 struct resource *res) 452 { 453 const struct pci_bus *bus = dev->bus; 454 struct resource *r; 455 int i; 456 457 pci_bus_for_each_resource(bus, r, i) { 458 if (!r) 459 continue; 460 if (resource_contains(r, res)) { 461 462 /* 463 * If the window is prefetchable but the BAR is 464 * not, the allocator made a mistake. 465 */ 466 if (r->flags & IORESOURCE_PREFETCH && 467 !(res->flags & IORESOURCE_PREFETCH)) 468 return NULL; 469 470 /* 471 * If we're below a transparent bridge, there may 472 * be both a positively-decoded aperture and a 473 * subtractively-decoded region that contain the BAR. 474 * We want the positively-decoded one, so this depends 475 * on pci_bus_for_each_resource() giving us those 476 * first. 477 */ 478 return r; 479 } 480 } 481 return NULL; 482 } 483 EXPORT_SYMBOL(pci_find_parent_resource); 484 485 /** 486 * pci_find_resource - Return matching PCI device resource 487 * @dev: PCI device to query 488 * @res: Resource to look for 489 * 490 * Goes over standard PCI resources (BARs) and checks if the given resource 491 * is partially or fully contained in any of them. In that case the 492 * matching resource is returned, %NULL otherwise. 493 */ 494 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res) 495 { 496 int i; 497 498 for (i = 0; i < PCI_ROM_RESOURCE; i++) { 499 struct resource *r = &dev->resource[i]; 500 501 if (r->start && resource_contains(r, res)) 502 return r; 503 } 504 505 return NULL; 506 } 507 EXPORT_SYMBOL(pci_find_resource); 508 509 /** 510 * pci_find_pcie_root_port - return PCIe Root Port 511 * @dev: PCI device to query 512 * 513 * Traverse up the parent chain and return the PCIe Root Port PCI Device 514 * for a given PCI Device. 515 */ 516 struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev) 517 { 518 struct pci_dev *bridge, *highest_pcie_bridge = dev; 519 520 bridge = pci_upstream_bridge(dev); 521 while (bridge && pci_is_pcie(bridge)) { 522 highest_pcie_bridge = bridge; 523 bridge = pci_upstream_bridge(bridge); 524 } 525 526 if (pci_pcie_type(highest_pcie_bridge) != PCI_EXP_TYPE_ROOT_PORT) 527 return NULL; 528 529 return highest_pcie_bridge; 530 } 531 EXPORT_SYMBOL(pci_find_pcie_root_port); 532 533 /** 534 * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos 535 * @dev: the PCI device to operate on 536 * @pos: config space offset of status word 537 * @mask: mask of bit(s) to care about in status word 538 * 539 * Return 1 when mask bit(s) in status word clear, 0 otherwise. 540 */ 541 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask) 542 { 543 int i; 544 545 /* Wait for Transaction Pending bit clean */ 546 for (i = 0; i < 4; i++) { 547 u16 status; 548 if (i) 549 msleep((1 << (i - 1)) * 100); 550 551 pci_read_config_word(dev, pos, &status); 552 if (!(status & mask)) 553 return 1; 554 } 555 556 return 0; 557 } 558 559 /** 560 * pci_restore_bars - restore a device's BAR values (e.g. after wake-up) 561 * @dev: PCI device to have its BARs restored 562 * 563 * Restore the BAR values for a given device, so as to make it 564 * accessible by its driver. 565 */ 566 static void pci_restore_bars(struct pci_dev *dev) 567 { 568 int i; 569 570 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) 571 pci_update_resource(dev, i); 572 } 573 574 static const struct pci_platform_pm_ops *pci_platform_pm; 575 576 int pci_set_platform_pm(const struct pci_platform_pm_ops *ops) 577 { 578 if (!ops->is_manageable || !ops->set_state || !ops->get_state || 579 !ops->choose_state || !ops->set_wakeup || !ops->need_resume) 580 return -EINVAL; 581 pci_platform_pm = ops; 582 return 0; 583 } 584 585 static inline bool platform_pci_power_manageable(struct pci_dev *dev) 586 { 587 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false; 588 } 589 590 static inline int platform_pci_set_power_state(struct pci_dev *dev, 591 pci_power_t t) 592 { 593 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS; 594 } 595 596 static inline pci_power_t platform_pci_get_power_state(struct pci_dev *dev) 597 { 598 return pci_platform_pm ? pci_platform_pm->get_state(dev) : PCI_UNKNOWN; 599 } 600 601 static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev) 602 { 603 return pci_platform_pm ? 604 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR; 605 } 606 607 static inline int platform_pci_set_wakeup(struct pci_dev *dev, bool enable) 608 { 609 return pci_platform_pm ? 610 pci_platform_pm->set_wakeup(dev, enable) : -ENODEV; 611 } 612 613 static inline bool platform_pci_need_resume(struct pci_dev *dev) 614 { 615 return pci_platform_pm ? pci_platform_pm->need_resume(dev) : false; 616 } 617 618 /** 619 * pci_raw_set_power_state - Use PCI PM registers to set the power state of 620 * given PCI device 621 * @dev: PCI device to handle. 622 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into. 623 * 624 * RETURN VALUE: 625 * -EINVAL if the requested state is invalid. 626 * -EIO if device does not support PCI PM or its PM capabilities register has a 627 * wrong version, or device doesn't support the requested state. 628 * 0 if device already is in the requested state. 629 * 0 if device's power state has been successfully changed. 630 */ 631 static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state) 632 { 633 u16 pmcsr; 634 bool need_restore = false; 635 636 /* Check if we're already there */ 637 if (dev->current_state == state) 638 return 0; 639 640 if (!dev->pm_cap) 641 return -EIO; 642 643 if (state < PCI_D0 || state > PCI_D3hot) 644 return -EINVAL; 645 646 /* Validate current state: 647 * Can enter D0 from any state, but if we can only go deeper 648 * to sleep if we're already in a low power state 649 */ 650 if (state != PCI_D0 && dev->current_state <= PCI_D3cold 651 && dev->current_state > state) { 652 dev_err(&dev->dev, "invalid power transition (from state %d to %d)\n", 653 dev->current_state, state); 654 return -EINVAL; 655 } 656 657 /* check if this device supports the desired state */ 658 if ((state == PCI_D1 && !dev->d1_support) 659 || (state == PCI_D2 && !dev->d2_support)) 660 return -EIO; 661 662 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); 663 664 /* If we're (effectively) in D3, force entire word to 0. 665 * This doesn't affect PME_Status, disables PME_En, and 666 * sets PowerState to 0. 667 */ 668 switch (dev->current_state) { 669 case PCI_D0: 670 case PCI_D1: 671 case PCI_D2: 672 pmcsr &= ~PCI_PM_CTRL_STATE_MASK; 673 pmcsr |= state; 674 break; 675 case PCI_D3hot: 676 case PCI_D3cold: 677 case PCI_UNKNOWN: /* Boot-up */ 678 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot 679 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET)) 680 need_restore = true; 681 /* Fall-through: force to D0 */ 682 default: 683 pmcsr = 0; 684 break; 685 } 686 687 /* enter specified state */ 688 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); 689 690 /* Mandatory power management transition delays */ 691 /* see PCI PM 1.1 5.6.1 table 18 */ 692 if (state == PCI_D3hot || dev->current_state == PCI_D3hot) 693 pci_dev_d3_sleep(dev); 694 else if (state == PCI_D2 || dev->current_state == PCI_D2) 695 udelay(PCI_PM_D2_DELAY); 696 697 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); 698 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); 699 if (dev->current_state != state && printk_ratelimit()) 700 dev_info(&dev->dev, "Refused to change power state, currently in D%d\n", 701 dev->current_state); 702 703 /* 704 * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT 705 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning 706 * from D3hot to D0 _may_ perform an internal reset, thereby 707 * going to "D0 Uninitialized" rather than "D0 Initialized". 708 * For example, at least some versions of the 3c905B and the 709 * 3c556B exhibit this behaviour. 710 * 711 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave 712 * devices in a D3hot state at boot. Consequently, we need to 713 * restore at least the BARs so that the device will be 714 * accessible to its driver. 715 */ 716 if (need_restore) 717 pci_restore_bars(dev); 718 719 if (dev->bus->self) 720 pcie_aspm_pm_state_change(dev->bus->self); 721 722 return 0; 723 } 724 725 /** 726 * pci_update_current_state - Read power state of given device and cache it 727 * @dev: PCI device to handle. 728 * @state: State to cache in case the device doesn't have the PM capability 729 * 730 * The power state is read from the PMCSR register, which however is 731 * inaccessible in D3cold. The platform firmware is therefore queried first 732 * to detect accessibility of the register. In case the platform firmware 733 * reports an incorrect state or the device isn't power manageable by the 734 * platform at all, we try to detect D3cold by testing accessibility of the 735 * vendor ID in config space. 736 */ 737 void pci_update_current_state(struct pci_dev *dev, pci_power_t state) 738 { 739 if (platform_pci_get_power_state(dev) == PCI_D3cold || 740 !pci_device_is_present(dev)) { 741 dev->current_state = PCI_D3cold; 742 } else if (dev->pm_cap) { 743 u16 pmcsr; 744 745 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); 746 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); 747 } else { 748 dev->current_state = state; 749 } 750 } 751 752 /** 753 * pci_power_up - Put the given device into D0 forcibly 754 * @dev: PCI device to power up 755 */ 756 void pci_power_up(struct pci_dev *dev) 757 { 758 if (platform_pci_power_manageable(dev)) 759 platform_pci_set_power_state(dev, PCI_D0); 760 761 pci_raw_set_power_state(dev, PCI_D0); 762 pci_update_current_state(dev, PCI_D0); 763 } 764 765 /** 766 * pci_platform_power_transition - Use platform to change device power state 767 * @dev: PCI device to handle. 768 * @state: State to put the device into. 769 */ 770 static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state) 771 { 772 int error; 773 774 if (platform_pci_power_manageable(dev)) { 775 error = platform_pci_set_power_state(dev, state); 776 if (!error) 777 pci_update_current_state(dev, state); 778 } else 779 error = -ENODEV; 780 781 if (error && !dev->pm_cap) /* Fall back to PCI_D0 */ 782 dev->current_state = PCI_D0; 783 784 return error; 785 } 786 787 /** 788 * pci_wakeup - Wake up a PCI device 789 * @pci_dev: Device to handle. 790 * @ign: ignored parameter 791 */ 792 static int pci_wakeup(struct pci_dev *pci_dev, void *ign) 793 { 794 pci_wakeup_event(pci_dev); 795 pm_request_resume(&pci_dev->dev); 796 return 0; 797 } 798 799 /** 800 * pci_wakeup_bus - Walk given bus and wake up devices on it 801 * @bus: Top bus of the subtree to walk. 802 */ 803 static void pci_wakeup_bus(struct pci_bus *bus) 804 { 805 if (bus) 806 pci_walk_bus(bus, pci_wakeup, NULL); 807 } 808 809 /** 810 * __pci_start_power_transition - Start power transition of a PCI device 811 * @dev: PCI device to handle. 812 * @state: State to put the device into. 813 */ 814 static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state) 815 { 816 if (state == PCI_D0) { 817 pci_platform_power_transition(dev, PCI_D0); 818 /* 819 * Mandatory power management transition delays, see 820 * PCI Express Base Specification Revision 2.0 Section 821 * 6.6.1: Conventional Reset. Do not delay for 822 * devices powered on/off by corresponding bridge, 823 * because have already delayed for the bridge. 824 */ 825 if (dev->runtime_d3cold) { 826 if (dev->d3cold_delay) 827 msleep(dev->d3cold_delay); 828 /* 829 * When powering on a bridge from D3cold, the 830 * whole hierarchy may be powered on into 831 * D0uninitialized state, resume them to give 832 * them a chance to suspend again 833 */ 834 pci_wakeup_bus(dev->subordinate); 835 } 836 } 837 } 838 839 /** 840 * __pci_dev_set_current_state - Set current state of a PCI device 841 * @dev: Device to handle 842 * @data: pointer to state to be set 843 */ 844 static int __pci_dev_set_current_state(struct pci_dev *dev, void *data) 845 { 846 pci_power_t state = *(pci_power_t *)data; 847 848 dev->current_state = state; 849 return 0; 850 } 851 852 /** 853 * __pci_bus_set_current_state - Walk given bus and set current state of devices 854 * @bus: Top bus of the subtree to walk. 855 * @state: state to be set 856 */ 857 static void __pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state) 858 { 859 if (bus) 860 pci_walk_bus(bus, __pci_dev_set_current_state, &state); 861 } 862 863 /** 864 * __pci_complete_power_transition - Complete power transition of a PCI device 865 * @dev: PCI device to handle. 866 * @state: State to put the device into. 867 * 868 * This function should not be called directly by device drivers. 869 */ 870 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state) 871 { 872 int ret; 873 874 if (state <= PCI_D0) 875 return -EINVAL; 876 ret = pci_platform_power_transition(dev, state); 877 /* Power off the bridge may power off the whole hierarchy */ 878 if (!ret && state == PCI_D3cold) 879 __pci_bus_set_current_state(dev->subordinate, PCI_D3cold); 880 return ret; 881 } 882 EXPORT_SYMBOL_GPL(__pci_complete_power_transition); 883 884 /** 885 * pci_set_power_state - Set the power state of a PCI device 886 * @dev: PCI device to handle. 887 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into. 888 * 889 * Transition a device to a new power state, using the platform firmware and/or 890 * the device's PCI PM registers. 891 * 892 * RETURN VALUE: 893 * -EINVAL if the requested state is invalid. 894 * -EIO if device does not support PCI PM or its PM capabilities register has a 895 * wrong version, or device doesn't support the requested state. 896 * 0 if the transition is to D1 or D2 but D1 and D2 are not supported. 897 * 0 if device already is in the requested state. 898 * 0 if the transition is to D3 but D3 is not supported. 899 * 0 if device's power state has been successfully changed. 900 */ 901 int pci_set_power_state(struct pci_dev *dev, pci_power_t state) 902 { 903 int error; 904 905 /* bound the state we're entering */ 906 if (state > PCI_D3cold) 907 state = PCI_D3cold; 908 else if (state < PCI_D0) 909 state = PCI_D0; 910 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev)) 911 /* 912 * If the device or the parent bridge do not support PCI PM, 913 * ignore the request if we're doing anything other than putting 914 * it into D0 (which would only happen on boot). 915 */ 916 return 0; 917 918 /* Check if we're already there */ 919 if (dev->current_state == state) 920 return 0; 921 922 __pci_start_power_transition(dev, state); 923 924 /* This device is quirked not to be put into D3, so 925 don't put it in D3 */ 926 if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3)) 927 return 0; 928 929 /* 930 * To put device in D3cold, we put device into D3hot in native 931 * way, then put device into D3cold with platform ops 932 */ 933 error = pci_raw_set_power_state(dev, state > PCI_D3hot ? 934 PCI_D3hot : state); 935 936 if (!__pci_complete_power_transition(dev, state)) 937 error = 0; 938 939 return error; 940 } 941 EXPORT_SYMBOL(pci_set_power_state); 942 943 /** 944 * pci_choose_state - Choose the power state of a PCI device 945 * @dev: PCI device to be suspended 946 * @state: target sleep state for the whole system. This is the value 947 * that is passed to suspend() function. 948 * 949 * Returns PCI power state suitable for given device and given system 950 * message. 951 */ 952 953 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state) 954 { 955 pci_power_t ret; 956 957 if (!dev->pm_cap) 958 return PCI_D0; 959 960 ret = platform_pci_choose_state(dev); 961 if (ret != PCI_POWER_ERROR) 962 return ret; 963 964 switch (state.event) { 965 case PM_EVENT_ON: 966 return PCI_D0; 967 case PM_EVENT_FREEZE: 968 case PM_EVENT_PRETHAW: 969 /* REVISIT both freeze and pre-thaw "should" use D0 */ 970 case PM_EVENT_SUSPEND: 971 case PM_EVENT_HIBERNATE: 972 return PCI_D3hot; 973 default: 974 dev_info(&dev->dev, "unrecognized suspend event %d\n", 975 state.event); 976 BUG(); 977 } 978 return PCI_D0; 979 } 980 EXPORT_SYMBOL(pci_choose_state); 981 982 #define PCI_EXP_SAVE_REGS 7 983 984 static struct pci_cap_saved_state *_pci_find_saved_cap(struct pci_dev *pci_dev, 985 u16 cap, bool extended) 986 { 987 struct pci_cap_saved_state *tmp; 988 989 hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) { 990 if (tmp->cap.cap_extended == extended && tmp->cap.cap_nr == cap) 991 return tmp; 992 } 993 return NULL; 994 } 995 996 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap) 997 { 998 return _pci_find_saved_cap(dev, cap, false); 999 } 1000 1001 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, u16 cap) 1002 { 1003 return _pci_find_saved_cap(dev, cap, true); 1004 } 1005 1006 static int pci_save_pcie_state(struct pci_dev *dev) 1007 { 1008 int i = 0; 1009 struct pci_cap_saved_state *save_state; 1010 u16 *cap; 1011 1012 if (!pci_is_pcie(dev)) 1013 return 0; 1014 1015 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); 1016 if (!save_state) { 1017 dev_err(&dev->dev, "buffer not found in %s\n", __func__); 1018 return -ENOMEM; 1019 } 1020 1021 cap = (u16 *)&save_state->cap.data[0]; 1022 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]); 1023 pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]); 1024 pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]); 1025 pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]); 1026 pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]); 1027 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]); 1028 pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]); 1029 1030 return 0; 1031 } 1032 1033 static void pci_restore_pcie_state(struct pci_dev *dev) 1034 { 1035 int i = 0; 1036 struct pci_cap_saved_state *save_state; 1037 u16 *cap; 1038 1039 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); 1040 if (!save_state) 1041 return; 1042 1043 cap = (u16 *)&save_state->cap.data[0]; 1044 pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]); 1045 pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]); 1046 pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]); 1047 pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]); 1048 pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]); 1049 pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]); 1050 pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]); 1051 } 1052 1053 1054 static int pci_save_pcix_state(struct pci_dev *dev) 1055 { 1056 int pos; 1057 struct pci_cap_saved_state *save_state; 1058 1059 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); 1060 if (!pos) 1061 return 0; 1062 1063 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); 1064 if (!save_state) { 1065 dev_err(&dev->dev, "buffer not found in %s\n", __func__); 1066 return -ENOMEM; 1067 } 1068 1069 pci_read_config_word(dev, pos + PCI_X_CMD, 1070 (u16 *)save_state->cap.data); 1071 1072 return 0; 1073 } 1074 1075 static void pci_restore_pcix_state(struct pci_dev *dev) 1076 { 1077 int i = 0, pos; 1078 struct pci_cap_saved_state *save_state; 1079 u16 *cap; 1080 1081 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); 1082 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); 1083 if (!save_state || !pos) 1084 return; 1085 cap = (u16 *)&save_state->cap.data[0]; 1086 1087 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]); 1088 } 1089 1090 1091 /** 1092 * pci_save_state - save the PCI configuration space of a device before suspending 1093 * @dev: - PCI device that we're dealing with 1094 */ 1095 int pci_save_state(struct pci_dev *dev) 1096 { 1097 int i; 1098 /* XXX: 100% dword access ok here? */ 1099 for (i = 0; i < 16; i++) 1100 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]); 1101 dev->state_saved = true; 1102 1103 i = pci_save_pcie_state(dev); 1104 if (i != 0) 1105 return i; 1106 1107 i = pci_save_pcix_state(dev); 1108 if (i != 0) 1109 return i; 1110 1111 return pci_save_vc_state(dev); 1112 } 1113 EXPORT_SYMBOL(pci_save_state); 1114 1115 static void pci_restore_config_dword(struct pci_dev *pdev, int offset, 1116 u32 saved_val, int retry) 1117 { 1118 u32 val; 1119 1120 pci_read_config_dword(pdev, offset, &val); 1121 if (val == saved_val) 1122 return; 1123 1124 for (;;) { 1125 dev_dbg(&pdev->dev, "restoring config space at offset %#x (was %#x, writing %#x)\n", 1126 offset, val, saved_val); 1127 pci_write_config_dword(pdev, offset, saved_val); 1128 if (retry-- <= 0) 1129 return; 1130 1131 pci_read_config_dword(pdev, offset, &val); 1132 if (val == saved_val) 1133 return; 1134 1135 mdelay(1); 1136 } 1137 } 1138 1139 static void pci_restore_config_space_range(struct pci_dev *pdev, 1140 int start, int end, int retry) 1141 { 1142 int index; 1143 1144 for (index = end; index >= start; index--) 1145 pci_restore_config_dword(pdev, 4 * index, 1146 pdev->saved_config_space[index], 1147 retry); 1148 } 1149 1150 static void pci_restore_config_space(struct pci_dev *pdev) 1151 { 1152 if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) { 1153 pci_restore_config_space_range(pdev, 10, 15, 0); 1154 /* Restore BARs before the command register. */ 1155 pci_restore_config_space_range(pdev, 4, 9, 10); 1156 pci_restore_config_space_range(pdev, 0, 3, 0); 1157 } else { 1158 pci_restore_config_space_range(pdev, 0, 15, 0); 1159 } 1160 } 1161 1162 /** 1163 * pci_restore_state - Restore the saved state of a PCI device 1164 * @dev: - PCI device that we're dealing with 1165 */ 1166 void pci_restore_state(struct pci_dev *dev) 1167 { 1168 if (!dev->state_saved) 1169 return; 1170 1171 /* PCI Express register must be restored first */ 1172 pci_restore_pcie_state(dev); 1173 pci_restore_pasid_state(dev); 1174 pci_restore_pri_state(dev); 1175 pci_restore_ats_state(dev); 1176 pci_restore_vc_state(dev); 1177 1178 pci_cleanup_aer_error_status_regs(dev); 1179 1180 pci_restore_config_space(dev); 1181 1182 pci_restore_pcix_state(dev); 1183 pci_restore_msi_state(dev); 1184 1185 /* Restore ACS and IOV configuration state */ 1186 pci_enable_acs(dev); 1187 pci_restore_iov_state(dev); 1188 1189 dev->state_saved = false; 1190 } 1191 EXPORT_SYMBOL(pci_restore_state); 1192 1193 struct pci_saved_state { 1194 u32 config_space[16]; 1195 struct pci_cap_saved_data cap[0]; 1196 }; 1197 1198 /** 1199 * pci_store_saved_state - Allocate and return an opaque struct containing 1200 * the device saved state. 1201 * @dev: PCI device that we're dealing with 1202 * 1203 * Return NULL if no state or error. 1204 */ 1205 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev) 1206 { 1207 struct pci_saved_state *state; 1208 struct pci_cap_saved_state *tmp; 1209 struct pci_cap_saved_data *cap; 1210 size_t size; 1211 1212 if (!dev->state_saved) 1213 return NULL; 1214 1215 size = sizeof(*state) + sizeof(struct pci_cap_saved_data); 1216 1217 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) 1218 size += sizeof(struct pci_cap_saved_data) + tmp->cap.size; 1219 1220 state = kzalloc(size, GFP_KERNEL); 1221 if (!state) 1222 return NULL; 1223 1224 memcpy(state->config_space, dev->saved_config_space, 1225 sizeof(state->config_space)); 1226 1227 cap = state->cap; 1228 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) { 1229 size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size; 1230 memcpy(cap, &tmp->cap, len); 1231 cap = (struct pci_cap_saved_data *)((u8 *)cap + len); 1232 } 1233 /* Empty cap_save terminates list */ 1234 1235 return state; 1236 } 1237 EXPORT_SYMBOL_GPL(pci_store_saved_state); 1238 1239 /** 1240 * pci_load_saved_state - Reload the provided save state into struct pci_dev. 1241 * @dev: PCI device that we're dealing with 1242 * @state: Saved state returned from pci_store_saved_state() 1243 */ 1244 int pci_load_saved_state(struct pci_dev *dev, 1245 struct pci_saved_state *state) 1246 { 1247 struct pci_cap_saved_data *cap; 1248 1249 dev->state_saved = false; 1250 1251 if (!state) 1252 return 0; 1253 1254 memcpy(dev->saved_config_space, state->config_space, 1255 sizeof(state->config_space)); 1256 1257 cap = state->cap; 1258 while (cap->size) { 1259 struct pci_cap_saved_state *tmp; 1260 1261 tmp = _pci_find_saved_cap(dev, cap->cap_nr, cap->cap_extended); 1262 if (!tmp || tmp->cap.size != cap->size) 1263 return -EINVAL; 1264 1265 memcpy(tmp->cap.data, cap->data, tmp->cap.size); 1266 cap = (struct pci_cap_saved_data *)((u8 *)cap + 1267 sizeof(struct pci_cap_saved_data) + cap->size); 1268 } 1269 1270 dev->state_saved = true; 1271 return 0; 1272 } 1273 EXPORT_SYMBOL_GPL(pci_load_saved_state); 1274 1275 /** 1276 * pci_load_and_free_saved_state - Reload the save state pointed to by state, 1277 * and free the memory allocated for it. 1278 * @dev: PCI device that we're dealing with 1279 * @state: Pointer to saved state returned from pci_store_saved_state() 1280 */ 1281 int pci_load_and_free_saved_state(struct pci_dev *dev, 1282 struct pci_saved_state **state) 1283 { 1284 int ret = pci_load_saved_state(dev, *state); 1285 kfree(*state); 1286 *state = NULL; 1287 return ret; 1288 } 1289 EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state); 1290 1291 int __weak pcibios_enable_device(struct pci_dev *dev, int bars) 1292 { 1293 return pci_enable_resources(dev, bars); 1294 } 1295 1296 static int do_pci_enable_device(struct pci_dev *dev, int bars) 1297 { 1298 int err; 1299 struct pci_dev *bridge; 1300 u16 cmd; 1301 u8 pin; 1302 1303 err = pci_set_power_state(dev, PCI_D0); 1304 if (err < 0 && err != -EIO) 1305 return err; 1306 1307 bridge = pci_upstream_bridge(dev); 1308 if (bridge) 1309 pcie_aspm_powersave_config_link(bridge); 1310 1311 err = pcibios_enable_device(dev, bars); 1312 if (err < 0) 1313 return err; 1314 pci_fixup_device(pci_fixup_enable, dev); 1315 1316 if (dev->msi_enabled || dev->msix_enabled) 1317 return 0; 1318 1319 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); 1320 if (pin) { 1321 pci_read_config_word(dev, PCI_COMMAND, &cmd); 1322 if (cmd & PCI_COMMAND_INTX_DISABLE) 1323 pci_write_config_word(dev, PCI_COMMAND, 1324 cmd & ~PCI_COMMAND_INTX_DISABLE); 1325 } 1326 1327 return 0; 1328 } 1329 1330 /** 1331 * pci_reenable_device - Resume abandoned device 1332 * @dev: PCI device to be resumed 1333 * 1334 * Note this function is a backend of pci_default_resume and is not supposed 1335 * to be called by normal code, write proper resume handler and use it instead. 1336 */ 1337 int pci_reenable_device(struct pci_dev *dev) 1338 { 1339 if (pci_is_enabled(dev)) 1340 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1); 1341 return 0; 1342 } 1343 EXPORT_SYMBOL(pci_reenable_device); 1344 1345 static void pci_enable_bridge(struct pci_dev *dev) 1346 { 1347 struct pci_dev *bridge; 1348 int retval; 1349 1350 bridge = pci_upstream_bridge(dev); 1351 if (bridge) 1352 pci_enable_bridge(bridge); 1353 1354 /* 1355 * Hold pci_bridge_mutex to prevent a race when enabling two 1356 * devices below the bridge simultaneously. The race may cause a 1357 * PCI_COMMAND_MEMORY update to be lost (see changelog). 1358 */ 1359 mutex_lock(&pci_bridge_mutex); 1360 if (pci_is_enabled(dev)) { 1361 if (!dev->is_busmaster) 1362 pci_set_master(dev); 1363 goto end; 1364 } 1365 1366 retval = pci_enable_device(dev); 1367 if (retval) 1368 dev_err(&dev->dev, "Error enabling bridge (%d), continuing\n", 1369 retval); 1370 pci_set_master(dev); 1371 end: 1372 mutex_unlock(&pci_bridge_mutex); 1373 } 1374 1375 static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags) 1376 { 1377 struct pci_dev *bridge; 1378 int err; 1379 int i, bars = 0; 1380 1381 /* 1382 * Power state could be unknown at this point, either due to a fresh 1383 * boot or a device removal call. So get the current power state 1384 * so that things like MSI message writing will behave as expected 1385 * (e.g. if the device really is in D0 at enable time). 1386 */ 1387 if (dev->pm_cap) { 1388 u16 pmcsr; 1389 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); 1390 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); 1391 } 1392 1393 if (atomic_inc_return(&dev->enable_cnt) > 1) 1394 return 0; /* already enabled */ 1395 1396 bridge = pci_upstream_bridge(dev); 1397 if (bridge && !pci_is_enabled(bridge)) 1398 pci_enable_bridge(bridge); 1399 1400 /* only skip sriov related */ 1401 for (i = 0; i <= PCI_ROM_RESOURCE; i++) 1402 if (dev->resource[i].flags & flags) 1403 bars |= (1 << i); 1404 for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++) 1405 if (dev->resource[i].flags & flags) 1406 bars |= (1 << i); 1407 1408 err = do_pci_enable_device(dev, bars); 1409 if (err < 0) 1410 atomic_dec(&dev->enable_cnt); 1411 return err; 1412 } 1413 1414 /** 1415 * pci_enable_device_io - Initialize a device for use with IO space 1416 * @dev: PCI device to be initialized 1417 * 1418 * Initialize device before it's used by a driver. Ask low-level code 1419 * to enable I/O resources. Wake up the device if it was suspended. 1420 * Beware, this function can fail. 1421 */ 1422 int pci_enable_device_io(struct pci_dev *dev) 1423 { 1424 return pci_enable_device_flags(dev, IORESOURCE_IO); 1425 } 1426 EXPORT_SYMBOL(pci_enable_device_io); 1427 1428 /** 1429 * pci_enable_device_mem - Initialize a device for use with Memory space 1430 * @dev: PCI device to be initialized 1431 * 1432 * Initialize device before it's used by a driver. Ask low-level code 1433 * to enable Memory resources. Wake up the device if it was suspended. 1434 * Beware, this function can fail. 1435 */ 1436 int pci_enable_device_mem(struct pci_dev *dev) 1437 { 1438 return pci_enable_device_flags(dev, IORESOURCE_MEM); 1439 } 1440 EXPORT_SYMBOL(pci_enable_device_mem); 1441 1442 /** 1443 * pci_enable_device - Initialize device before it's used by a driver. 1444 * @dev: PCI device to be initialized 1445 * 1446 * Initialize device before it's used by a driver. Ask low-level code 1447 * to enable I/O and memory. Wake up the device if it was suspended. 1448 * Beware, this function can fail. 1449 * 1450 * Note we don't actually enable the device many times if we call 1451 * this function repeatedly (we just increment the count). 1452 */ 1453 int pci_enable_device(struct pci_dev *dev) 1454 { 1455 return pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO); 1456 } 1457 EXPORT_SYMBOL(pci_enable_device); 1458 1459 /* 1460 * Managed PCI resources. This manages device on/off, intx/msi/msix 1461 * on/off and BAR regions. pci_dev itself records msi/msix status, so 1462 * there's no need to track it separately. pci_devres is initialized 1463 * when a device is enabled using managed PCI device enable interface. 1464 */ 1465 struct pci_devres { 1466 unsigned int enabled:1; 1467 unsigned int pinned:1; 1468 unsigned int orig_intx:1; 1469 unsigned int restore_intx:1; 1470 u32 region_mask; 1471 }; 1472 1473 static void pcim_release(struct device *gendev, void *res) 1474 { 1475 struct pci_dev *dev = to_pci_dev(gendev); 1476 struct pci_devres *this = res; 1477 int i; 1478 1479 if (dev->msi_enabled) 1480 pci_disable_msi(dev); 1481 if (dev->msix_enabled) 1482 pci_disable_msix(dev); 1483 1484 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) 1485 if (this->region_mask & (1 << i)) 1486 pci_release_region(dev, i); 1487 1488 if (this->restore_intx) 1489 pci_intx(dev, this->orig_intx); 1490 1491 if (this->enabled && !this->pinned) 1492 pci_disable_device(dev); 1493 } 1494 1495 static struct pci_devres *get_pci_dr(struct pci_dev *pdev) 1496 { 1497 struct pci_devres *dr, *new_dr; 1498 1499 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL); 1500 if (dr) 1501 return dr; 1502 1503 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL); 1504 if (!new_dr) 1505 return NULL; 1506 return devres_get(&pdev->dev, new_dr, NULL, NULL); 1507 } 1508 1509 static struct pci_devres *find_pci_dr(struct pci_dev *pdev) 1510 { 1511 if (pci_is_managed(pdev)) 1512 return devres_find(&pdev->dev, pcim_release, NULL, NULL); 1513 return NULL; 1514 } 1515 1516 /** 1517 * pcim_enable_device - Managed pci_enable_device() 1518 * @pdev: PCI device to be initialized 1519 * 1520 * Managed pci_enable_device(). 1521 */ 1522 int pcim_enable_device(struct pci_dev *pdev) 1523 { 1524 struct pci_devres *dr; 1525 int rc; 1526 1527 dr = get_pci_dr(pdev); 1528 if (unlikely(!dr)) 1529 return -ENOMEM; 1530 if (dr->enabled) 1531 return 0; 1532 1533 rc = pci_enable_device(pdev); 1534 if (!rc) { 1535 pdev->is_managed = 1; 1536 dr->enabled = 1; 1537 } 1538 return rc; 1539 } 1540 EXPORT_SYMBOL(pcim_enable_device); 1541 1542 /** 1543 * pcim_pin_device - Pin managed PCI device 1544 * @pdev: PCI device to pin 1545 * 1546 * Pin managed PCI device @pdev. Pinned device won't be disabled on 1547 * driver detach. @pdev must have been enabled with 1548 * pcim_enable_device(). 1549 */ 1550 void pcim_pin_device(struct pci_dev *pdev) 1551 { 1552 struct pci_devres *dr; 1553 1554 dr = find_pci_dr(pdev); 1555 WARN_ON(!dr || !dr->enabled); 1556 if (dr) 1557 dr->pinned = 1; 1558 } 1559 EXPORT_SYMBOL(pcim_pin_device); 1560 1561 /* 1562 * pcibios_add_device - provide arch specific hooks when adding device dev 1563 * @dev: the PCI device being added 1564 * 1565 * Permits the platform to provide architecture specific functionality when 1566 * devices are added. This is the default implementation. Architecture 1567 * implementations can override this. 1568 */ 1569 int __weak pcibios_add_device(struct pci_dev *dev) 1570 { 1571 return 0; 1572 } 1573 1574 /** 1575 * pcibios_release_device - provide arch specific hooks when releasing device dev 1576 * @dev: the PCI device being released 1577 * 1578 * Permits the platform to provide architecture specific functionality when 1579 * devices are released. This is the default implementation. Architecture 1580 * implementations can override this. 1581 */ 1582 void __weak pcibios_release_device(struct pci_dev *dev) {} 1583 1584 /** 1585 * pcibios_disable_device - disable arch specific PCI resources for device dev 1586 * @dev: the PCI device to disable 1587 * 1588 * Disables architecture specific PCI resources for the device. This 1589 * is the default implementation. Architecture implementations can 1590 * override this. 1591 */ 1592 void __weak pcibios_disable_device(struct pci_dev *dev) {} 1593 1594 /** 1595 * pcibios_penalize_isa_irq - penalize an ISA IRQ 1596 * @irq: ISA IRQ to penalize 1597 * @active: IRQ active or not 1598 * 1599 * Permits the platform to provide architecture-specific functionality when 1600 * penalizing ISA IRQs. This is the default implementation. Architecture 1601 * implementations can override this. 1602 */ 1603 void __weak pcibios_penalize_isa_irq(int irq, int active) {} 1604 1605 static void do_pci_disable_device(struct pci_dev *dev) 1606 { 1607 u16 pci_command; 1608 1609 pci_read_config_word(dev, PCI_COMMAND, &pci_command); 1610 if (pci_command & PCI_COMMAND_MASTER) { 1611 pci_command &= ~PCI_COMMAND_MASTER; 1612 pci_write_config_word(dev, PCI_COMMAND, pci_command); 1613 } 1614 1615 pcibios_disable_device(dev); 1616 } 1617 1618 /** 1619 * pci_disable_enabled_device - Disable device without updating enable_cnt 1620 * @dev: PCI device to disable 1621 * 1622 * NOTE: This function is a backend of PCI power management routines and is 1623 * not supposed to be called drivers. 1624 */ 1625 void pci_disable_enabled_device(struct pci_dev *dev) 1626 { 1627 if (pci_is_enabled(dev)) 1628 do_pci_disable_device(dev); 1629 } 1630 1631 /** 1632 * pci_disable_device - Disable PCI device after use 1633 * @dev: PCI device to be disabled 1634 * 1635 * Signal to the system that the PCI device is not in use by the system 1636 * anymore. This only involves disabling PCI bus-mastering, if active. 1637 * 1638 * Note we don't actually disable the device until all callers of 1639 * pci_enable_device() have called pci_disable_device(). 1640 */ 1641 void pci_disable_device(struct pci_dev *dev) 1642 { 1643 struct pci_devres *dr; 1644 1645 dr = find_pci_dr(dev); 1646 if (dr) 1647 dr->enabled = 0; 1648 1649 dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0, 1650 "disabling already-disabled device"); 1651 1652 if (atomic_dec_return(&dev->enable_cnt) != 0) 1653 return; 1654 1655 do_pci_disable_device(dev); 1656 1657 dev->is_busmaster = 0; 1658 } 1659 EXPORT_SYMBOL(pci_disable_device); 1660 1661 /** 1662 * pcibios_set_pcie_reset_state - set reset state for device dev 1663 * @dev: the PCIe device reset 1664 * @state: Reset state to enter into 1665 * 1666 * 1667 * Sets the PCIe reset state for the device. This is the default 1668 * implementation. Architecture implementations can override this. 1669 */ 1670 int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev, 1671 enum pcie_reset_state state) 1672 { 1673 return -EINVAL; 1674 } 1675 1676 /** 1677 * pci_set_pcie_reset_state - set reset state for device dev 1678 * @dev: the PCIe device reset 1679 * @state: Reset state to enter into 1680 * 1681 * 1682 * Sets the PCI reset state for the device. 1683 */ 1684 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state) 1685 { 1686 return pcibios_set_pcie_reset_state(dev, state); 1687 } 1688 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state); 1689 1690 /** 1691 * pci_check_pme_status - Check if given device has generated PME. 1692 * @dev: Device to check. 1693 * 1694 * Check the PME status of the device and if set, clear it and clear PME enable 1695 * (if set). Return 'true' if PME status and PME enable were both set or 1696 * 'false' otherwise. 1697 */ 1698 bool pci_check_pme_status(struct pci_dev *dev) 1699 { 1700 int pmcsr_pos; 1701 u16 pmcsr; 1702 bool ret = false; 1703 1704 if (!dev->pm_cap) 1705 return false; 1706 1707 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL; 1708 pci_read_config_word(dev, pmcsr_pos, &pmcsr); 1709 if (!(pmcsr & PCI_PM_CTRL_PME_STATUS)) 1710 return false; 1711 1712 /* Clear PME status. */ 1713 pmcsr |= PCI_PM_CTRL_PME_STATUS; 1714 if (pmcsr & PCI_PM_CTRL_PME_ENABLE) { 1715 /* Disable PME to avoid interrupt flood. */ 1716 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE; 1717 ret = true; 1718 } 1719 1720 pci_write_config_word(dev, pmcsr_pos, pmcsr); 1721 1722 return ret; 1723 } 1724 1725 /** 1726 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set. 1727 * @dev: Device to handle. 1728 * @pme_poll_reset: Whether or not to reset the device's pme_poll flag. 1729 * 1730 * Check if @dev has generated PME and queue a resume request for it in that 1731 * case. 1732 */ 1733 static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset) 1734 { 1735 if (pme_poll_reset && dev->pme_poll) 1736 dev->pme_poll = false; 1737 1738 if (pci_check_pme_status(dev)) { 1739 pci_wakeup_event(dev); 1740 pm_request_resume(&dev->dev); 1741 } 1742 return 0; 1743 } 1744 1745 /** 1746 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary. 1747 * @bus: Top bus of the subtree to walk. 1748 */ 1749 void pci_pme_wakeup_bus(struct pci_bus *bus) 1750 { 1751 if (bus) 1752 pci_walk_bus(bus, pci_pme_wakeup, (void *)true); 1753 } 1754 1755 1756 /** 1757 * pci_pme_capable - check the capability of PCI device to generate PME# 1758 * @dev: PCI device to handle. 1759 * @state: PCI state from which device will issue PME#. 1760 */ 1761 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state) 1762 { 1763 if (!dev->pm_cap) 1764 return false; 1765 1766 return !!(dev->pme_support & (1 << state)); 1767 } 1768 EXPORT_SYMBOL(pci_pme_capable); 1769 1770 static void pci_pme_list_scan(struct work_struct *work) 1771 { 1772 struct pci_pme_device *pme_dev, *n; 1773 1774 mutex_lock(&pci_pme_list_mutex); 1775 list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) { 1776 if (pme_dev->dev->pme_poll) { 1777 struct pci_dev *bridge; 1778 1779 bridge = pme_dev->dev->bus->self; 1780 /* 1781 * If bridge is in low power state, the 1782 * configuration space of subordinate devices 1783 * may be not accessible 1784 */ 1785 if (bridge && bridge->current_state != PCI_D0) 1786 continue; 1787 pci_pme_wakeup(pme_dev->dev, NULL); 1788 } else { 1789 list_del(&pme_dev->list); 1790 kfree(pme_dev); 1791 } 1792 } 1793 if (!list_empty(&pci_pme_list)) 1794 queue_delayed_work(system_freezable_wq, &pci_pme_work, 1795 msecs_to_jiffies(PME_TIMEOUT)); 1796 mutex_unlock(&pci_pme_list_mutex); 1797 } 1798 1799 static void __pci_pme_active(struct pci_dev *dev, bool enable) 1800 { 1801 u16 pmcsr; 1802 1803 if (!dev->pme_support) 1804 return; 1805 1806 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); 1807 /* Clear PME_Status by writing 1 to it and enable PME# */ 1808 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE; 1809 if (!enable) 1810 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE; 1811 1812 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); 1813 } 1814 1815 /** 1816 * pci_pme_restore - Restore PME configuration after config space restore. 1817 * @dev: PCI device to update. 1818 */ 1819 void pci_pme_restore(struct pci_dev *dev) 1820 { 1821 u16 pmcsr; 1822 1823 if (!dev->pme_support) 1824 return; 1825 1826 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); 1827 if (dev->wakeup_prepared) { 1828 pmcsr |= PCI_PM_CTRL_PME_ENABLE; 1829 pmcsr &= ~PCI_PM_CTRL_PME_STATUS; 1830 } else { 1831 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE; 1832 pmcsr |= PCI_PM_CTRL_PME_STATUS; 1833 } 1834 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); 1835 } 1836 1837 /** 1838 * pci_pme_active - enable or disable PCI device's PME# function 1839 * @dev: PCI device to handle. 1840 * @enable: 'true' to enable PME# generation; 'false' to disable it. 1841 * 1842 * The caller must verify that the device is capable of generating PME# before 1843 * calling this function with @enable equal to 'true'. 1844 */ 1845 void pci_pme_active(struct pci_dev *dev, bool enable) 1846 { 1847 __pci_pme_active(dev, enable); 1848 1849 /* 1850 * PCI (as opposed to PCIe) PME requires that the device have 1851 * its PME# line hooked up correctly. Not all hardware vendors 1852 * do this, so the PME never gets delivered and the device 1853 * remains asleep. The easiest way around this is to 1854 * periodically walk the list of suspended devices and check 1855 * whether any have their PME flag set. The assumption is that 1856 * we'll wake up often enough anyway that this won't be a huge 1857 * hit, and the power savings from the devices will still be a 1858 * win. 1859 * 1860 * Although PCIe uses in-band PME message instead of PME# line 1861 * to report PME, PME does not work for some PCIe devices in 1862 * reality. For example, there are devices that set their PME 1863 * status bits, but don't really bother to send a PME message; 1864 * there are PCI Express Root Ports that don't bother to 1865 * trigger interrupts when they receive PME messages from the 1866 * devices below. So PME poll is used for PCIe devices too. 1867 */ 1868 1869 if (dev->pme_poll) { 1870 struct pci_pme_device *pme_dev; 1871 if (enable) { 1872 pme_dev = kmalloc(sizeof(struct pci_pme_device), 1873 GFP_KERNEL); 1874 if (!pme_dev) { 1875 dev_warn(&dev->dev, "can't enable PME#\n"); 1876 return; 1877 } 1878 pme_dev->dev = dev; 1879 mutex_lock(&pci_pme_list_mutex); 1880 list_add(&pme_dev->list, &pci_pme_list); 1881 if (list_is_singular(&pci_pme_list)) 1882 queue_delayed_work(system_freezable_wq, 1883 &pci_pme_work, 1884 msecs_to_jiffies(PME_TIMEOUT)); 1885 mutex_unlock(&pci_pme_list_mutex); 1886 } else { 1887 mutex_lock(&pci_pme_list_mutex); 1888 list_for_each_entry(pme_dev, &pci_pme_list, list) { 1889 if (pme_dev->dev == dev) { 1890 list_del(&pme_dev->list); 1891 kfree(pme_dev); 1892 break; 1893 } 1894 } 1895 mutex_unlock(&pci_pme_list_mutex); 1896 } 1897 } 1898 1899 dev_dbg(&dev->dev, "PME# %s\n", enable ? "enabled" : "disabled"); 1900 } 1901 EXPORT_SYMBOL(pci_pme_active); 1902 1903 /** 1904 * pci_enable_wake - enable PCI device as wakeup event source 1905 * @dev: PCI device affected 1906 * @state: PCI state from which device will issue wakeup events 1907 * @enable: True to enable event generation; false to disable 1908 * 1909 * This enables the device as a wakeup event source, or disables it. 1910 * When such events involves platform-specific hooks, those hooks are 1911 * called automatically by this routine. 1912 * 1913 * Devices with legacy power management (no standard PCI PM capabilities) 1914 * always require such platform hooks. 1915 * 1916 * RETURN VALUE: 1917 * 0 is returned on success 1918 * -EINVAL is returned if device is not supposed to wake up the system 1919 * Error code depending on the platform is returned if both the platform and 1920 * the native mechanism fail to enable the generation of wake-up events 1921 */ 1922 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable) 1923 { 1924 int ret = 0; 1925 1926 /* 1927 * Bridges can only signal wakeup on behalf of subordinate devices, 1928 * but that is set up elsewhere, so skip them. 1929 */ 1930 if (pci_has_subordinate(dev)) 1931 return 0; 1932 1933 /* Don't do the same thing twice in a row for one device. */ 1934 if (!!enable == !!dev->wakeup_prepared) 1935 return 0; 1936 1937 /* 1938 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don 1939 * Anderson we should be doing PME# wake enable followed by ACPI wake 1940 * enable. To disable wake-up we call the platform first, for symmetry. 1941 */ 1942 1943 if (enable) { 1944 int error; 1945 1946 if (pci_pme_capable(dev, state)) 1947 pci_pme_active(dev, true); 1948 else 1949 ret = 1; 1950 error = platform_pci_set_wakeup(dev, true); 1951 if (ret) 1952 ret = error; 1953 if (!ret) 1954 dev->wakeup_prepared = true; 1955 } else { 1956 platform_pci_set_wakeup(dev, false); 1957 pci_pme_active(dev, false); 1958 dev->wakeup_prepared = false; 1959 } 1960 1961 return ret; 1962 } 1963 EXPORT_SYMBOL(pci_enable_wake); 1964 1965 /** 1966 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold 1967 * @dev: PCI device to prepare 1968 * @enable: True to enable wake-up event generation; false to disable 1969 * 1970 * Many drivers want the device to wake up the system from D3_hot or D3_cold 1971 * and this function allows them to set that up cleanly - pci_enable_wake() 1972 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI 1973 * ordering constraints. 1974 * 1975 * This function only returns error code if the device is not capable of 1976 * generating PME# from both D3_hot and D3_cold, and the platform is unable to 1977 * enable wake-up power for it. 1978 */ 1979 int pci_wake_from_d3(struct pci_dev *dev, bool enable) 1980 { 1981 return pci_pme_capable(dev, PCI_D3cold) ? 1982 pci_enable_wake(dev, PCI_D3cold, enable) : 1983 pci_enable_wake(dev, PCI_D3hot, enable); 1984 } 1985 EXPORT_SYMBOL(pci_wake_from_d3); 1986 1987 /** 1988 * pci_target_state - find an appropriate low power state for a given PCI dev 1989 * @dev: PCI device 1990 * @wakeup: Whether or not wakeup functionality will be enabled for the device. 1991 * 1992 * Use underlying platform code to find a supported low power state for @dev. 1993 * If the platform can't manage @dev, return the deepest state from which it 1994 * can generate wake events, based on any available PME info. 1995 */ 1996 static pci_power_t pci_target_state(struct pci_dev *dev, bool wakeup) 1997 { 1998 pci_power_t target_state = PCI_D3hot; 1999 2000 if (platform_pci_power_manageable(dev)) { 2001 /* 2002 * Call the platform to choose the target state of the device 2003 * and enable wake-up from this state if supported. 2004 */ 2005 pci_power_t state = platform_pci_choose_state(dev); 2006 2007 switch (state) { 2008 case PCI_POWER_ERROR: 2009 case PCI_UNKNOWN: 2010 break; 2011 case PCI_D1: 2012 case PCI_D2: 2013 if (pci_no_d1d2(dev)) 2014 break; 2015 default: 2016 target_state = state; 2017 } 2018 2019 return target_state; 2020 } 2021 2022 if (!dev->pm_cap) 2023 target_state = PCI_D0; 2024 2025 /* 2026 * If the device is in D3cold even though it's not power-manageable by 2027 * the platform, it may have been powered down by non-standard means. 2028 * Best to let it slumber. 2029 */ 2030 if (dev->current_state == PCI_D3cold) 2031 target_state = PCI_D3cold; 2032 2033 if (wakeup) { 2034 /* 2035 * Find the deepest state from which the device can generate 2036 * wake-up events, make it the target state and enable device 2037 * to generate PME#. 2038 */ 2039 if (dev->pme_support) { 2040 while (target_state 2041 && !(dev->pme_support & (1 << target_state))) 2042 target_state--; 2043 } 2044 } 2045 2046 return target_state; 2047 } 2048 2049 /** 2050 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state 2051 * @dev: Device to handle. 2052 * 2053 * Choose the power state appropriate for the device depending on whether 2054 * it can wake up the system and/or is power manageable by the platform 2055 * (PCI_D3hot is the default) and put the device into that state. 2056 */ 2057 int pci_prepare_to_sleep(struct pci_dev *dev) 2058 { 2059 bool wakeup = device_may_wakeup(&dev->dev); 2060 pci_power_t target_state = pci_target_state(dev, wakeup); 2061 int error; 2062 2063 if (target_state == PCI_POWER_ERROR) 2064 return -EIO; 2065 2066 pci_enable_wake(dev, target_state, wakeup); 2067 2068 error = pci_set_power_state(dev, target_state); 2069 2070 if (error) 2071 pci_enable_wake(dev, target_state, false); 2072 2073 return error; 2074 } 2075 EXPORT_SYMBOL(pci_prepare_to_sleep); 2076 2077 /** 2078 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state 2079 * @dev: Device to handle. 2080 * 2081 * Disable device's system wake-up capability and put it into D0. 2082 */ 2083 int pci_back_from_sleep(struct pci_dev *dev) 2084 { 2085 pci_enable_wake(dev, PCI_D0, false); 2086 return pci_set_power_state(dev, PCI_D0); 2087 } 2088 EXPORT_SYMBOL(pci_back_from_sleep); 2089 2090 /** 2091 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend. 2092 * @dev: PCI device being suspended. 2093 * 2094 * Prepare @dev to generate wake-up events at run time and put it into a low 2095 * power state. 2096 */ 2097 int pci_finish_runtime_suspend(struct pci_dev *dev) 2098 { 2099 pci_power_t target_state; 2100 int error; 2101 2102 target_state = pci_target_state(dev, device_can_wakeup(&dev->dev)); 2103 if (target_state == PCI_POWER_ERROR) 2104 return -EIO; 2105 2106 dev->runtime_d3cold = target_state == PCI_D3cold; 2107 2108 pci_enable_wake(dev, target_state, pci_dev_run_wake(dev)); 2109 2110 error = pci_set_power_state(dev, target_state); 2111 2112 if (error) { 2113 pci_enable_wake(dev, target_state, false); 2114 dev->runtime_d3cold = false; 2115 } 2116 2117 return error; 2118 } 2119 2120 /** 2121 * pci_dev_run_wake - Check if device can generate run-time wake-up events. 2122 * @dev: Device to check. 2123 * 2124 * Return true if the device itself is capable of generating wake-up events 2125 * (through the platform or using the native PCIe PME) or if the device supports 2126 * PME and one of its upstream bridges can generate wake-up events. 2127 */ 2128 bool pci_dev_run_wake(struct pci_dev *dev) 2129 { 2130 struct pci_bus *bus = dev->bus; 2131 2132 if (device_can_wakeup(&dev->dev)) 2133 return true; 2134 2135 if (!dev->pme_support) 2136 return false; 2137 2138 /* PME-capable in principle, but not from the target power state */ 2139 if (!pci_pme_capable(dev, pci_target_state(dev, false))) 2140 return false; 2141 2142 while (bus->parent) { 2143 struct pci_dev *bridge = bus->self; 2144 2145 if (device_can_wakeup(&bridge->dev)) 2146 return true; 2147 2148 bus = bus->parent; 2149 } 2150 2151 /* We have reached the root bus. */ 2152 if (bus->bridge) 2153 return device_can_wakeup(bus->bridge); 2154 2155 return false; 2156 } 2157 EXPORT_SYMBOL_GPL(pci_dev_run_wake); 2158 2159 /** 2160 * pci_dev_keep_suspended - Check if the device can stay in the suspended state. 2161 * @pci_dev: Device to check. 2162 * 2163 * Return 'true' if the device is runtime-suspended, it doesn't have to be 2164 * reconfigured due to wakeup settings difference between system and runtime 2165 * suspend and the current power state of it is suitable for the upcoming 2166 * (system) transition. 2167 * 2168 * If the device is not configured for system wakeup, disable PME for it before 2169 * returning 'true' to prevent it from waking up the system unnecessarily. 2170 */ 2171 bool pci_dev_keep_suspended(struct pci_dev *pci_dev) 2172 { 2173 struct device *dev = &pci_dev->dev; 2174 bool wakeup = device_may_wakeup(dev); 2175 2176 if (!pm_runtime_suspended(dev) 2177 || pci_target_state(pci_dev, wakeup) != pci_dev->current_state 2178 || platform_pci_need_resume(pci_dev) 2179 || (pci_dev->dev_flags & PCI_DEV_FLAGS_NEEDS_RESUME)) 2180 return false; 2181 2182 /* 2183 * At this point the device is good to go unless it's been configured 2184 * to generate PME at the runtime suspend time, but it is not supposed 2185 * to wake up the system. In that case, simply disable PME for it 2186 * (it will have to be re-enabled on exit from system resume). 2187 * 2188 * If the device's power state is D3cold and the platform check above 2189 * hasn't triggered, the device's configuration is suitable and we don't 2190 * need to manipulate it at all. 2191 */ 2192 spin_lock_irq(&dev->power.lock); 2193 2194 if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold && 2195 !wakeup) 2196 __pci_pme_active(pci_dev, false); 2197 2198 spin_unlock_irq(&dev->power.lock); 2199 return true; 2200 } 2201 2202 /** 2203 * pci_dev_complete_resume - Finalize resume from system sleep for a device. 2204 * @pci_dev: Device to handle. 2205 * 2206 * If the device is runtime suspended and wakeup-capable, enable PME for it as 2207 * it might have been disabled during the prepare phase of system suspend if 2208 * the device was not configured for system wakeup. 2209 */ 2210 void pci_dev_complete_resume(struct pci_dev *pci_dev) 2211 { 2212 struct device *dev = &pci_dev->dev; 2213 2214 if (!pci_dev_run_wake(pci_dev)) 2215 return; 2216 2217 spin_lock_irq(&dev->power.lock); 2218 2219 if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold) 2220 __pci_pme_active(pci_dev, true); 2221 2222 spin_unlock_irq(&dev->power.lock); 2223 } 2224 2225 void pci_config_pm_runtime_get(struct pci_dev *pdev) 2226 { 2227 struct device *dev = &pdev->dev; 2228 struct device *parent = dev->parent; 2229 2230 if (parent) 2231 pm_runtime_get_sync(parent); 2232 pm_runtime_get_noresume(dev); 2233 /* 2234 * pdev->current_state is set to PCI_D3cold during suspending, 2235 * so wait until suspending completes 2236 */ 2237 pm_runtime_barrier(dev); 2238 /* 2239 * Only need to resume devices in D3cold, because config 2240 * registers are still accessible for devices suspended but 2241 * not in D3cold. 2242 */ 2243 if (pdev->current_state == PCI_D3cold) 2244 pm_runtime_resume(dev); 2245 } 2246 2247 void pci_config_pm_runtime_put(struct pci_dev *pdev) 2248 { 2249 struct device *dev = &pdev->dev; 2250 struct device *parent = dev->parent; 2251 2252 pm_runtime_put(dev); 2253 if (parent) 2254 pm_runtime_put_sync(parent); 2255 } 2256 2257 /** 2258 * pci_bridge_d3_possible - Is it possible to put the bridge into D3 2259 * @bridge: Bridge to check 2260 * 2261 * This function checks if it is possible to move the bridge to D3. 2262 * Currently we only allow D3 for recent enough PCIe ports. 2263 */ 2264 bool pci_bridge_d3_possible(struct pci_dev *bridge) 2265 { 2266 unsigned int year; 2267 2268 if (!pci_is_pcie(bridge)) 2269 return false; 2270 2271 switch (pci_pcie_type(bridge)) { 2272 case PCI_EXP_TYPE_ROOT_PORT: 2273 case PCI_EXP_TYPE_UPSTREAM: 2274 case PCI_EXP_TYPE_DOWNSTREAM: 2275 if (pci_bridge_d3_disable) 2276 return false; 2277 2278 /* 2279 * Hotplug interrupts cannot be delivered if the link is down, 2280 * so parents of a hotplug port must stay awake. In addition, 2281 * hotplug ports handled by firmware in System Management Mode 2282 * may not be put into D3 by the OS (Thunderbolt on non-Macs). 2283 * For simplicity, disallow in general for now. 2284 */ 2285 if (bridge->is_hotplug_bridge) 2286 return false; 2287 2288 if (pci_bridge_d3_force) 2289 return true; 2290 2291 /* 2292 * It should be safe to put PCIe ports from 2015 or newer 2293 * to D3. 2294 */ 2295 if (dmi_get_date(DMI_BIOS_DATE, &year, NULL, NULL) && 2296 year >= 2015) { 2297 return true; 2298 } 2299 break; 2300 } 2301 2302 return false; 2303 } 2304 2305 static int pci_dev_check_d3cold(struct pci_dev *dev, void *data) 2306 { 2307 bool *d3cold_ok = data; 2308 2309 if (/* The device needs to be allowed to go D3cold ... */ 2310 dev->no_d3cold || !dev->d3cold_allowed || 2311 2312 /* ... and if it is wakeup capable to do so from D3cold. */ 2313 (device_may_wakeup(&dev->dev) && 2314 !pci_pme_capable(dev, PCI_D3cold)) || 2315 2316 /* If it is a bridge it must be allowed to go to D3. */ 2317 !pci_power_manageable(dev)) 2318 2319 *d3cold_ok = false; 2320 2321 return !*d3cold_ok; 2322 } 2323 2324 /* 2325 * pci_bridge_d3_update - Update bridge D3 capabilities 2326 * @dev: PCI device which is changed 2327 * 2328 * Update upstream bridge PM capabilities accordingly depending on if the 2329 * device PM configuration was changed or the device is being removed. The 2330 * change is also propagated upstream. 2331 */ 2332 void pci_bridge_d3_update(struct pci_dev *dev) 2333 { 2334 bool remove = !device_is_registered(&dev->dev); 2335 struct pci_dev *bridge; 2336 bool d3cold_ok = true; 2337 2338 bridge = pci_upstream_bridge(dev); 2339 if (!bridge || !pci_bridge_d3_possible(bridge)) 2340 return; 2341 2342 /* 2343 * If D3 is currently allowed for the bridge, removing one of its 2344 * children won't change that. 2345 */ 2346 if (remove && bridge->bridge_d3) 2347 return; 2348 2349 /* 2350 * If D3 is currently allowed for the bridge and a child is added or 2351 * changed, disallowance of D3 can only be caused by that child, so 2352 * we only need to check that single device, not any of its siblings. 2353 * 2354 * If D3 is currently not allowed for the bridge, checking the device 2355 * first may allow us to skip checking its siblings. 2356 */ 2357 if (!remove) 2358 pci_dev_check_d3cold(dev, &d3cold_ok); 2359 2360 /* 2361 * If D3 is currently not allowed for the bridge, this may be caused 2362 * either by the device being changed/removed or any of its siblings, 2363 * so we need to go through all children to find out if one of them 2364 * continues to block D3. 2365 */ 2366 if (d3cold_ok && !bridge->bridge_d3) 2367 pci_walk_bus(bridge->subordinate, pci_dev_check_d3cold, 2368 &d3cold_ok); 2369 2370 if (bridge->bridge_d3 != d3cold_ok) { 2371 bridge->bridge_d3 = d3cold_ok; 2372 /* Propagate change to upstream bridges */ 2373 pci_bridge_d3_update(bridge); 2374 } 2375 } 2376 2377 /** 2378 * pci_d3cold_enable - Enable D3cold for device 2379 * @dev: PCI device to handle 2380 * 2381 * This function can be used in drivers to enable D3cold from the device 2382 * they handle. It also updates upstream PCI bridge PM capabilities 2383 * accordingly. 2384 */ 2385 void pci_d3cold_enable(struct pci_dev *dev) 2386 { 2387 if (dev->no_d3cold) { 2388 dev->no_d3cold = false; 2389 pci_bridge_d3_update(dev); 2390 } 2391 } 2392 EXPORT_SYMBOL_GPL(pci_d3cold_enable); 2393 2394 /** 2395 * pci_d3cold_disable - Disable D3cold for device 2396 * @dev: PCI device to handle 2397 * 2398 * This function can be used in drivers to disable D3cold from the device 2399 * they handle. It also updates upstream PCI bridge PM capabilities 2400 * accordingly. 2401 */ 2402 void pci_d3cold_disable(struct pci_dev *dev) 2403 { 2404 if (!dev->no_d3cold) { 2405 dev->no_d3cold = true; 2406 pci_bridge_d3_update(dev); 2407 } 2408 } 2409 EXPORT_SYMBOL_GPL(pci_d3cold_disable); 2410 2411 /** 2412 * pci_pm_init - Initialize PM functions of given PCI device 2413 * @dev: PCI device to handle. 2414 */ 2415 void pci_pm_init(struct pci_dev *dev) 2416 { 2417 int pm; 2418 u16 pmc; 2419 2420 pm_runtime_forbid(&dev->dev); 2421 pm_runtime_set_active(&dev->dev); 2422 pm_runtime_enable(&dev->dev); 2423 device_enable_async_suspend(&dev->dev); 2424 dev->wakeup_prepared = false; 2425 2426 dev->pm_cap = 0; 2427 dev->pme_support = 0; 2428 2429 /* find PCI PM capability in list */ 2430 pm = pci_find_capability(dev, PCI_CAP_ID_PM); 2431 if (!pm) 2432 return; 2433 /* Check device's ability to generate PME# */ 2434 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc); 2435 2436 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) { 2437 dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n", 2438 pmc & PCI_PM_CAP_VER_MASK); 2439 return; 2440 } 2441 2442 dev->pm_cap = pm; 2443 dev->d3_delay = PCI_PM_D3_WAIT; 2444 dev->d3cold_delay = PCI_PM_D3COLD_WAIT; 2445 dev->bridge_d3 = pci_bridge_d3_possible(dev); 2446 dev->d3cold_allowed = true; 2447 2448 dev->d1_support = false; 2449 dev->d2_support = false; 2450 if (!pci_no_d1d2(dev)) { 2451 if (pmc & PCI_PM_CAP_D1) 2452 dev->d1_support = true; 2453 if (pmc & PCI_PM_CAP_D2) 2454 dev->d2_support = true; 2455 2456 if (dev->d1_support || dev->d2_support) 2457 dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n", 2458 dev->d1_support ? " D1" : "", 2459 dev->d2_support ? " D2" : ""); 2460 } 2461 2462 pmc &= PCI_PM_CAP_PME_MASK; 2463 if (pmc) { 2464 dev_printk(KERN_DEBUG, &dev->dev, 2465 "PME# supported from%s%s%s%s%s\n", 2466 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "", 2467 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "", 2468 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "", 2469 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "", 2470 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : ""); 2471 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT; 2472 dev->pme_poll = true; 2473 /* 2474 * Make device's PM flags reflect the wake-up capability, but 2475 * let the user space enable it to wake up the system as needed. 2476 */ 2477 device_set_wakeup_capable(&dev->dev, true); 2478 /* Disable the PME# generation functionality */ 2479 pci_pme_active(dev, false); 2480 } 2481 } 2482 2483 static unsigned long pci_ea_flags(struct pci_dev *dev, u8 prop) 2484 { 2485 unsigned long flags = IORESOURCE_PCI_FIXED | IORESOURCE_PCI_EA_BEI; 2486 2487 switch (prop) { 2488 case PCI_EA_P_MEM: 2489 case PCI_EA_P_VF_MEM: 2490 flags |= IORESOURCE_MEM; 2491 break; 2492 case PCI_EA_P_MEM_PREFETCH: 2493 case PCI_EA_P_VF_MEM_PREFETCH: 2494 flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH; 2495 break; 2496 case PCI_EA_P_IO: 2497 flags |= IORESOURCE_IO; 2498 break; 2499 default: 2500 return 0; 2501 } 2502 2503 return flags; 2504 } 2505 2506 static struct resource *pci_ea_get_resource(struct pci_dev *dev, u8 bei, 2507 u8 prop) 2508 { 2509 if (bei <= PCI_EA_BEI_BAR5 && prop <= PCI_EA_P_IO) 2510 return &dev->resource[bei]; 2511 #ifdef CONFIG_PCI_IOV 2512 else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5 && 2513 (prop == PCI_EA_P_VF_MEM || prop == PCI_EA_P_VF_MEM_PREFETCH)) 2514 return &dev->resource[PCI_IOV_RESOURCES + 2515 bei - PCI_EA_BEI_VF_BAR0]; 2516 #endif 2517 else if (bei == PCI_EA_BEI_ROM) 2518 return &dev->resource[PCI_ROM_RESOURCE]; 2519 else 2520 return NULL; 2521 } 2522 2523 /* Read an Enhanced Allocation (EA) entry */ 2524 static int pci_ea_read(struct pci_dev *dev, int offset) 2525 { 2526 struct resource *res; 2527 int ent_size, ent_offset = offset; 2528 resource_size_t start, end; 2529 unsigned long flags; 2530 u32 dw0, bei, base, max_offset; 2531 u8 prop; 2532 bool support_64 = (sizeof(resource_size_t) >= 8); 2533 2534 pci_read_config_dword(dev, ent_offset, &dw0); 2535 ent_offset += 4; 2536 2537 /* Entry size field indicates DWORDs after 1st */ 2538 ent_size = ((dw0 & PCI_EA_ES) + 1) << 2; 2539 2540 if (!(dw0 & PCI_EA_ENABLE)) /* Entry not enabled */ 2541 goto out; 2542 2543 bei = (dw0 & PCI_EA_BEI) >> 4; 2544 prop = (dw0 & PCI_EA_PP) >> 8; 2545 2546 /* 2547 * If the Property is in the reserved range, try the Secondary 2548 * Property instead. 2549 */ 2550 if (prop > PCI_EA_P_BRIDGE_IO && prop < PCI_EA_P_MEM_RESERVED) 2551 prop = (dw0 & PCI_EA_SP) >> 16; 2552 if (prop > PCI_EA_P_BRIDGE_IO) 2553 goto out; 2554 2555 res = pci_ea_get_resource(dev, bei, prop); 2556 if (!res) { 2557 dev_err(&dev->dev, "Unsupported EA entry BEI: %u\n", bei); 2558 goto out; 2559 } 2560 2561 flags = pci_ea_flags(dev, prop); 2562 if (!flags) { 2563 dev_err(&dev->dev, "Unsupported EA properties: %#x\n", prop); 2564 goto out; 2565 } 2566 2567 /* Read Base */ 2568 pci_read_config_dword(dev, ent_offset, &base); 2569 start = (base & PCI_EA_FIELD_MASK); 2570 ent_offset += 4; 2571 2572 /* Read MaxOffset */ 2573 pci_read_config_dword(dev, ent_offset, &max_offset); 2574 ent_offset += 4; 2575 2576 /* Read Base MSBs (if 64-bit entry) */ 2577 if (base & PCI_EA_IS_64) { 2578 u32 base_upper; 2579 2580 pci_read_config_dword(dev, ent_offset, &base_upper); 2581 ent_offset += 4; 2582 2583 flags |= IORESOURCE_MEM_64; 2584 2585 /* entry starts above 32-bit boundary, can't use */ 2586 if (!support_64 && base_upper) 2587 goto out; 2588 2589 if (support_64) 2590 start |= ((u64)base_upper << 32); 2591 } 2592 2593 end = start + (max_offset | 0x03); 2594 2595 /* Read MaxOffset MSBs (if 64-bit entry) */ 2596 if (max_offset & PCI_EA_IS_64) { 2597 u32 max_offset_upper; 2598 2599 pci_read_config_dword(dev, ent_offset, &max_offset_upper); 2600 ent_offset += 4; 2601 2602 flags |= IORESOURCE_MEM_64; 2603 2604 /* entry too big, can't use */ 2605 if (!support_64 && max_offset_upper) 2606 goto out; 2607 2608 if (support_64) 2609 end += ((u64)max_offset_upper << 32); 2610 } 2611 2612 if (end < start) { 2613 dev_err(&dev->dev, "EA Entry crosses address boundary\n"); 2614 goto out; 2615 } 2616 2617 if (ent_size != ent_offset - offset) { 2618 dev_err(&dev->dev, 2619 "EA Entry Size (%d) does not match length read (%d)\n", 2620 ent_size, ent_offset - offset); 2621 goto out; 2622 } 2623 2624 res->name = pci_name(dev); 2625 res->start = start; 2626 res->end = end; 2627 res->flags = flags; 2628 2629 if (bei <= PCI_EA_BEI_BAR5) 2630 dev_printk(KERN_DEBUG, &dev->dev, "BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n", 2631 bei, res, prop); 2632 else if (bei == PCI_EA_BEI_ROM) 2633 dev_printk(KERN_DEBUG, &dev->dev, "ROM: %pR (from Enhanced Allocation, properties %#02x)\n", 2634 res, prop); 2635 else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5) 2636 dev_printk(KERN_DEBUG, &dev->dev, "VF BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n", 2637 bei - PCI_EA_BEI_VF_BAR0, res, prop); 2638 else 2639 dev_printk(KERN_DEBUG, &dev->dev, "BEI %d res: %pR (from Enhanced Allocation, properties %#02x)\n", 2640 bei, res, prop); 2641 2642 out: 2643 return offset + ent_size; 2644 } 2645 2646 /* Enhanced Allocation Initialization */ 2647 void pci_ea_init(struct pci_dev *dev) 2648 { 2649 int ea; 2650 u8 num_ent; 2651 int offset; 2652 int i; 2653 2654 /* find PCI EA capability in list */ 2655 ea = pci_find_capability(dev, PCI_CAP_ID_EA); 2656 if (!ea) 2657 return; 2658 2659 /* determine the number of entries */ 2660 pci_bus_read_config_byte(dev->bus, dev->devfn, ea + PCI_EA_NUM_ENT, 2661 &num_ent); 2662 num_ent &= PCI_EA_NUM_ENT_MASK; 2663 2664 offset = ea + PCI_EA_FIRST_ENT; 2665 2666 /* Skip DWORD 2 for type 1 functions */ 2667 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) 2668 offset += 4; 2669 2670 /* parse each EA entry */ 2671 for (i = 0; i < num_ent; ++i) 2672 offset = pci_ea_read(dev, offset); 2673 } 2674 2675 static void pci_add_saved_cap(struct pci_dev *pci_dev, 2676 struct pci_cap_saved_state *new_cap) 2677 { 2678 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space); 2679 } 2680 2681 /** 2682 * _pci_add_cap_save_buffer - allocate buffer for saving given 2683 * capability registers 2684 * @dev: the PCI device 2685 * @cap: the capability to allocate the buffer for 2686 * @extended: Standard or Extended capability ID 2687 * @size: requested size of the buffer 2688 */ 2689 static int _pci_add_cap_save_buffer(struct pci_dev *dev, u16 cap, 2690 bool extended, unsigned int size) 2691 { 2692 int pos; 2693 struct pci_cap_saved_state *save_state; 2694 2695 if (extended) 2696 pos = pci_find_ext_capability(dev, cap); 2697 else 2698 pos = pci_find_capability(dev, cap); 2699 2700 if (!pos) 2701 return 0; 2702 2703 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL); 2704 if (!save_state) 2705 return -ENOMEM; 2706 2707 save_state->cap.cap_nr = cap; 2708 save_state->cap.cap_extended = extended; 2709 save_state->cap.size = size; 2710 pci_add_saved_cap(dev, save_state); 2711 2712 return 0; 2713 } 2714 2715 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size) 2716 { 2717 return _pci_add_cap_save_buffer(dev, cap, false, size); 2718 } 2719 2720 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, u16 cap, unsigned int size) 2721 { 2722 return _pci_add_cap_save_buffer(dev, cap, true, size); 2723 } 2724 2725 /** 2726 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities 2727 * @dev: the PCI device 2728 */ 2729 void pci_allocate_cap_save_buffers(struct pci_dev *dev) 2730 { 2731 int error; 2732 2733 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP, 2734 PCI_EXP_SAVE_REGS * sizeof(u16)); 2735 if (error) 2736 dev_err(&dev->dev, 2737 "unable to preallocate PCI Express save buffer\n"); 2738 2739 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16)); 2740 if (error) 2741 dev_err(&dev->dev, 2742 "unable to preallocate PCI-X save buffer\n"); 2743 2744 pci_allocate_vc_save_buffers(dev); 2745 } 2746 2747 void pci_free_cap_save_buffers(struct pci_dev *dev) 2748 { 2749 struct pci_cap_saved_state *tmp; 2750 struct hlist_node *n; 2751 2752 hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next) 2753 kfree(tmp); 2754 } 2755 2756 /** 2757 * pci_configure_ari - enable or disable ARI forwarding 2758 * @dev: the PCI device 2759 * 2760 * If @dev and its upstream bridge both support ARI, enable ARI in the 2761 * bridge. Otherwise, disable ARI in the bridge. 2762 */ 2763 void pci_configure_ari(struct pci_dev *dev) 2764 { 2765 u32 cap; 2766 struct pci_dev *bridge; 2767 2768 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn) 2769 return; 2770 2771 bridge = dev->bus->self; 2772 if (!bridge) 2773 return; 2774 2775 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap); 2776 if (!(cap & PCI_EXP_DEVCAP2_ARI)) 2777 return; 2778 2779 if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) { 2780 pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2, 2781 PCI_EXP_DEVCTL2_ARI); 2782 bridge->ari_enabled = 1; 2783 } else { 2784 pcie_capability_clear_word(bridge, PCI_EXP_DEVCTL2, 2785 PCI_EXP_DEVCTL2_ARI); 2786 bridge->ari_enabled = 0; 2787 } 2788 } 2789 2790 static int pci_acs_enable; 2791 2792 /** 2793 * pci_request_acs - ask for ACS to be enabled if supported 2794 */ 2795 void pci_request_acs(void) 2796 { 2797 pci_acs_enable = 1; 2798 } 2799 2800 /** 2801 * pci_std_enable_acs - enable ACS on devices using standard ACS capabilites 2802 * @dev: the PCI device 2803 */ 2804 static void pci_std_enable_acs(struct pci_dev *dev) 2805 { 2806 int pos; 2807 u16 cap; 2808 u16 ctrl; 2809 2810 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS); 2811 if (!pos) 2812 return; 2813 2814 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap); 2815 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl); 2816 2817 /* Source Validation */ 2818 ctrl |= (cap & PCI_ACS_SV); 2819 2820 /* P2P Request Redirect */ 2821 ctrl |= (cap & PCI_ACS_RR); 2822 2823 /* P2P Completion Redirect */ 2824 ctrl |= (cap & PCI_ACS_CR); 2825 2826 /* Upstream Forwarding */ 2827 ctrl |= (cap & PCI_ACS_UF); 2828 2829 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl); 2830 } 2831 2832 /** 2833 * pci_enable_acs - enable ACS if hardware support it 2834 * @dev: the PCI device 2835 */ 2836 void pci_enable_acs(struct pci_dev *dev) 2837 { 2838 if (!pci_acs_enable) 2839 return; 2840 2841 if (!pci_dev_specific_enable_acs(dev)) 2842 return; 2843 2844 pci_std_enable_acs(dev); 2845 } 2846 2847 static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags) 2848 { 2849 int pos; 2850 u16 cap, ctrl; 2851 2852 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ACS); 2853 if (!pos) 2854 return false; 2855 2856 /* 2857 * Except for egress control, capabilities are either required 2858 * or only required if controllable. Features missing from the 2859 * capability field can therefore be assumed as hard-wired enabled. 2860 */ 2861 pci_read_config_word(pdev, pos + PCI_ACS_CAP, &cap); 2862 acs_flags &= (cap | PCI_ACS_EC); 2863 2864 pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl); 2865 return (ctrl & acs_flags) == acs_flags; 2866 } 2867 2868 /** 2869 * pci_acs_enabled - test ACS against required flags for a given device 2870 * @pdev: device to test 2871 * @acs_flags: required PCI ACS flags 2872 * 2873 * Return true if the device supports the provided flags. Automatically 2874 * filters out flags that are not implemented on multifunction devices. 2875 * 2876 * Note that this interface checks the effective ACS capabilities of the 2877 * device rather than the actual capabilities. For instance, most single 2878 * function endpoints are not required to support ACS because they have no 2879 * opportunity for peer-to-peer access. We therefore return 'true' 2880 * regardless of whether the device exposes an ACS capability. This makes 2881 * it much easier for callers of this function to ignore the actual type 2882 * or topology of the device when testing ACS support. 2883 */ 2884 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags) 2885 { 2886 int ret; 2887 2888 ret = pci_dev_specific_acs_enabled(pdev, acs_flags); 2889 if (ret >= 0) 2890 return ret > 0; 2891 2892 /* 2893 * Conventional PCI and PCI-X devices never support ACS, either 2894 * effectively or actually. The shared bus topology implies that 2895 * any device on the bus can receive or snoop DMA. 2896 */ 2897 if (!pci_is_pcie(pdev)) 2898 return false; 2899 2900 switch (pci_pcie_type(pdev)) { 2901 /* 2902 * PCI/X-to-PCIe bridges are not specifically mentioned by the spec, 2903 * but since their primary interface is PCI/X, we conservatively 2904 * handle them as we would a non-PCIe device. 2905 */ 2906 case PCI_EXP_TYPE_PCIE_BRIDGE: 2907 /* 2908 * PCIe 3.0, 6.12.1 excludes ACS on these devices. "ACS is never 2909 * applicable... must never implement an ACS Extended Capability...". 2910 * This seems arbitrary, but we take a conservative interpretation 2911 * of this statement. 2912 */ 2913 case PCI_EXP_TYPE_PCI_BRIDGE: 2914 case PCI_EXP_TYPE_RC_EC: 2915 return false; 2916 /* 2917 * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should 2918 * implement ACS in order to indicate their peer-to-peer capabilities, 2919 * regardless of whether they are single- or multi-function devices. 2920 */ 2921 case PCI_EXP_TYPE_DOWNSTREAM: 2922 case PCI_EXP_TYPE_ROOT_PORT: 2923 return pci_acs_flags_enabled(pdev, acs_flags); 2924 /* 2925 * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be 2926 * implemented by the remaining PCIe types to indicate peer-to-peer 2927 * capabilities, but only when they are part of a multifunction 2928 * device. The footnote for section 6.12 indicates the specific 2929 * PCIe types included here. 2930 */ 2931 case PCI_EXP_TYPE_ENDPOINT: 2932 case PCI_EXP_TYPE_UPSTREAM: 2933 case PCI_EXP_TYPE_LEG_END: 2934 case PCI_EXP_TYPE_RC_END: 2935 if (!pdev->multifunction) 2936 break; 2937 2938 return pci_acs_flags_enabled(pdev, acs_flags); 2939 } 2940 2941 /* 2942 * PCIe 3.0, 6.12.1.3 specifies no ACS capabilities are applicable 2943 * to single function devices with the exception of downstream ports. 2944 */ 2945 return true; 2946 } 2947 2948 /** 2949 * pci_acs_path_enable - test ACS flags from start to end in a hierarchy 2950 * @start: starting downstream device 2951 * @end: ending upstream device or NULL to search to the root bus 2952 * @acs_flags: required flags 2953 * 2954 * Walk up a device tree from start to end testing PCI ACS support. If 2955 * any step along the way does not support the required flags, return false. 2956 */ 2957 bool pci_acs_path_enabled(struct pci_dev *start, 2958 struct pci_dev *end, u16 acs_flags) 2959 { 2960 struct pci_dev *pdev, *parent = start; 2961 2962 do { 2963 pdev = parent; 2964 2965 if (!pci_acs_enabled(pdev, acs_flags)) 2966 return false; 2967 2968 if (pci_is_root_bus(pdev->bus)) 2969 return (end == NULL); 2970 2971 parent = pdev->bus->self; 2972 } while (pdev != end); 2973 2974 return true; 2975 } 2976 2977 /** 2978 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge 2979 * @dev: the PCI device 2980 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD) 2981 * 2982 * Perform INTx swizzling for a device behind one level of bridge. This is 2983 * required by section 9.1 of the PCI-to-PCI bridge specification for devices 2984 * behind bridges on add-in cards. For devices with ARI enabled, the slot 2985 * number is always 0 (see the Implementation Note in section 2.2.8.1 of 2986 * the PCI Express Base Specification, Revision 2.1) 2987 */ 2988 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin) 2989 { 2990 int slot; 2991 2992 if (pci_ari_enabled(dev->bus)) 2993 slot = 0; 2994 else 2995 slot = PCI_SLOT(dev->devfn); 2996 2997 return (((pin - 1) + slot) % 4) + 1; 2998 } 2999 3000 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge) 3001 { 3002 u8 pin; 3003 3004 pin = dev->pin; 3005 if (!pin) 3006 return -1; 3007 3008 while (!pci_is_root_bus(dev->bus)) { 3009 pin = pci_swizzle_interrupt_pin(dev, pin); 3010 dev = dev->bus->self; 3011 } 3012 *bridge = dev; 3013 return pin; 3014 } 3015 3016 /** 3017 * pci_common_swizzle - swizzle INTx all the way to root bridge 3018 * @dev: the PCI device 3019 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD) 3020 * 3021 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI 3022 * bridges all the way up to a PCI root bus. 3023 */ 3024 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp) 3025 { 3026 u8 pin = *pinp; 3027 3028 while (!pci_is_root_bus(dev->bus)) { 3029 pin = pci_swizzle_interrupt_pin(dev, pin); 3030 dev = dev->bus->self; 3031 } 3032 *pinp = pin; 3033 return PCI_SLOT(dev->devfn); 3034 } 3035 EXPORT_SYMBOL_GPL(pci_common_swizzle); 3036 3037 /** 3038 * pci_release_region - Release a PCI bar 3039 * @pdev: PCI device whose resources were previously reserved by pci_request_region 3040 * @bar: BAR to release 3041 * 3042 * Releases the PCI I/O and memory resources previously reserved by a 3043 * successful call to pci_request_region. Call this function only 3044 * after all use of the PCI regions has ceased. 3045 */ 3046 void pci_release_region(struct pci_dev *pdev, int bar) 3047 { 3048 struct pci_devres *dr; 3049 3050 if (pci_resource_len(pdev, bar) == 0) 3051 return; 3052 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) 3053 release_region(pci_resource_start(pdev, bar), 3054 pci_resource_len(pdev, bar)); 3055 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) 3056 release_mem_region(pci_resource_start(pdev, bar), 3057 pci_resource_len(pdev, bar)); 3058 3059 dr = find_pci_dr(pdev); 3060 if (dr) 3061 dr->region_mask &= ~(1 << bar); 3062 } 3063 EXPORT_SYMBOL(pci_release_region); 3064 3065 /** 3066 * __pci_request_region - Reserved PCI I/O and memory resource 3067 * @pdev: PCI device whose resources are to be reserved 3068 * @bar: BAR to be reserved 3069 * @res_name: Name to be associated with resource. 3070 * @exclusive: whether the region access is exclusive or not 3071 * 3072 * Mark the PCI region associated with PCI device @pdev BR @bar as 3073 * being reserved by owner @res_name. Do not access any 3074 * address inside the PCI regions unless this call returns 3075 * successfully. 3076 * 3077 * If @exclusive is set, then the region is marked so that userspace 3078 * is explicitly not allowed to map the resource via /dev/mem or 3079 * sysfs MMIO access. 3080 * 3081 * Returns 0 on success, or %EBUSY on error. A warning 3082 * message is also printed on failure. 3083 */ 3084 static int __pci_request_region(struct pci_dev *pdev, int bar, 3085 const char *res_name, int exclusive) 3086 { 3087 struct pci_devres *dr; 3088 3089 if (pci_resource_len(pdev, bar) == 0) 3090 return 0; 3091 3092 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) { 3093 if (!request_region(pci_resource_start(pdev, bar), 3094 pci_resource_len(pdev, bar), res_name)) 3095 goto err_out; 3096 } else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) { 3097 if (!__request_mem_region(pci_resource_start(pdev, bar), 3098 pci_resource_len(pdev, bar), res_name, 3099 exclusive)) 3100 goto err_out; 3101 } 3102 3103 dr = find_pci_dr(pdev); 3104 if (dr) 3105 dr->region_mask |= 1 << bar; 3106 3107 return 0; 3108 3109 err_out: 3110 dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar, 3111 &pdev->resource[bar]); 3112 return -EBUSY; 3113 } 3114 3115 /** 3116 * pci_request_region - Reserve PCI I/O and memory resource 3117 * @pdev: PCI device whose resources are to be reserved 3118 * @bar: BAR to be reserved 3119 * @res_name: Name to be associated with resource 3120 * 3121 * Mark the PCI region associated with PCI device @pdev BAR @bar as 3122 * being reserved by owner @res_name. Do not access any 3123 * address inside the PCI regions unless this call returns 3124 * successfully. 3125 * 3126 * Returns 0 on success, or %EBUSY on error. A warning 3127 * message is also printed on failure. 3128 */ 3129 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) 3130 { 3131 return __pci_request_region(pdev, bar, res_name, 0); 3132 } 3133 EXPORT_SYMBOL(pci_request_region); 3134 3135 /** 3136 * pci_request_region_exclusive - Reserved PCI I/O and memory resource 3137 * @pdev: PCI device whose resources are to be reserved 3138 * @bar: BAR to be reserved 3139 * @res_name: Name to be associated with resource. 3140 * 3141 * Mark the PCI region associated with PCI device @pdev BR @bar as 3142 * being reserved by owner @res_name. Do not access any 3143 * address inside the PCI regions unless this call returns 3144 * successfully. 3145 * 3146 * Returns 0 on success, or %EBUSY on error. A warning 3147 * message is also printed on failure. 3148 * 3149 * The key difference that _exclusive makes it that userspace is 3150 * explicitly not allowed to map the resource via /dev/mem or 3151 * sysfs. 3152 */ 3153 int pci_request_region_exclusive(struct pci_dev *pdev, int bar, 3154 const char *res_name) 3155 { 3156 return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE); 3157 } 3158 EXPORT_SYMBOL(pci_request_region_exclusive); 3159 3160 /** 3161 * pci_release_selected_regions - Release selected PCI I/O and memory resources 3162 * @pdev: PCI device whose resources were previously reserved 3163 * @bars: Bitmask of BARs to be released 3164 * 3165 * Release selected PCI I/O and memory resources previously reserved. 3166 * Call this function only after all use of the PCI regions has ceased. 3167 */ 3168 void pci_release_selected_regions(struct pci_dev *pdev, int bars) 3169 { 3170 int i; 3171 3172 for (i = 0; i < 6; i++) 3173 if (bars & (1 << i)) 3174 pci_release_region(pdev, i); 3175 } 3176 EXPORT_SYMBOL(pci_release_selected_regions); 3177 3178 static int __pci_request_selected_regions(struct pci_dev *pdev, int bars, 3179 const char *res_name, int excl) 3180 { 3181 int i; 3182 3183 for (i = 0; i < 6; i++) 3184 if (bars & (1 << i)) 3185 if (__pci_request_region(pdev, i, res_name, excl)) 3186 goto err_out; 3187 return 0; 3188 3189 err_out: 3190 while (--i >= 0) 3191 if (bars & (1 << i)) 3192 pci_release_region(pdev, i); 3193 3194 return -EBUSY; 3195 } 3196 3197 3198 /** 3199 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources 3200 * @pdev: PCI device whose resources are to be reserved 3201 * @bars: Bitmask of BARs to be requested 3202 * @res_name: Name to be associated with resource 3203 */ 3204 int pci_request_selected_regions(struct pci_dev *pdev, int bars, 3205 const char *res_name) 3206 { 3207 return __pci_request_selected_regions(pdev, bars, res_name, 0); 3208 } 3209 EXPORT_SYMBOL(pci_request_selected_regions); 3210 3211 int pci_request_selected_regions_exclusive(struct pci_dev *pdev, int bars, 3212 const char *res_name) 3213 { 3214 return __pci_request_selected_regions(pdev, bars, res_name, 3215 IORESOURCE_EXCLUSIVE); 3216 } 3217 EXPORT_SYMBOL(pci_request_selected_regions_exclusive); 3218 3219 /** 3220 * pci_release_regions - Release reserved PCI I/O and memory resources 3221 * @pdev: PCI device whose resources were previously reserved by pci_request_regions 3222 * 3223 * Releases all PCI I/O and memory resources previously reserved by a 3224 * successful call to pci_request_regions. Call this function only 3225 * after all use of the PCI regions has ceased. 3226 */ 3227 3228 void pci_release_regions(struct pci_dev *pdev) 3229 { 3230 pci_release_selected_regions(pdev, (1 << 6) - 1); 3231 } 3232 EXPORT_SYMBOL(pci_release_regions); 3233 3234 /** 3235 * pci_request_regions - Reserved PCI I/O and memory resources 3236 * @pdev: PCI device whose resources are to be reserved 3237 * @res_name: Name to be associated with resource. 3238 * 3239 * Mark all PCI regions associated with PCI device @pdev as 3240 * being reserved by owner @res_name. Do not access any 3241 * address inside the PCI regions unless this call returns 3242 * successfully. 3243 * 3244 * Returns 0 on success, or %EBUSY on error. A warning 3245 * message is also printed on failure. 3246 */ 3247 int pci_request_regions(struct pci_dev *pdev, const char *res_name) 3248 { 3249 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name); 3250 } 3251 EXPORT_SYMBOL(pci_request_regions); 3252 3253 /** 3254 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources 3255 * @pdev: PCI device whose resources are to be reserved 3256 * @res_name: Name to be associated with resource. 3257 * 3258 * Mark all PCI regions associated with PCI device @pdev as 3259 * being reserved by owner @res_name. Do not access any 3260 * address inside the PCI regions unless this call returns 3261 * successfully. 3262 * 3263 * pci_request_regions_exclusive() will mark the region so that 3264 * /dev/mem and the sysfs MMIO access will not be allowed. 3265 * 3266 * Returns 0 on success, or %EBUSY on error. A warning 3267 * message is also printed on failure. 3268 */ 3269 int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name) 3270 { 3271 return pci_request_selected_regions_exclusive(pdev, 3272 ((1 << 6) - 1), res_name); 3273 } 3274 EXPORT_SYMBOL(pci_request_regions_exclusive); 3275 3276 #ifdef PCI_IOBASE 3277 struct io_range { 3278 struct list_head list; 3279 phys_addr_t start; 3280 resource_size_t size; 3281 }; 3282 3283 static LIST_HEAD(io_range_list); 3284 static DEFINE_SPINLOCK(io_range_lock); 3285 #endif 3286 3287 /* 3288 * Record the PCI IO range (expressed as CPU physical address + size). 3289 * Return a negative value if an error has occured, zero otherwise 3290 */ 3291 int __weak pci_register_io_range(phys_addr_t addr, resource_size_t size) 3292 { 3293 int err = 0; 3294 3295 #ifdef PCI_IOBASE 3296 struct io_range *range; 3297 resource_size_t allocated_size = 0; 3298 3299 /* check if the range hasn't been previously recorded */ 3300 spin_lock(&io_range_lock); 3301 list_for_each_entry(range, &io_range_list, list) { 3302 if (addr >= range->start && addr + size <= range->start + size) { 3303 /* range already registered, bail out */ 3304 goto end_register; 3305 } 3306 allocated_size += range->size; 3307 } 3308 3309 /* range not registed yet, check for available space */ 3310 if (allocated_size + size - 1 > IO_SPACE_LIMIT) { 3311 /* if it's too big check if 64K space can be reserved */ 3312 if (allocated_size + SZ_64K - 1 > IO_SPACE_LIMIT) { 3313 err = -E2BIG; 3314 goto end_register; 3315 } 3316 3317 size = SZ_64K; 3318 pr_warn("Requested IO range too big, new size set to 64K\n"); 3319 } 3320 3321 /* add the range to the list */ 3322 range = kzalloc(sizeof(*range), GFP_ATOMIC); 3323 if (!range) { 3324 err = -ENOMEM; 3325 goto end_register; 3326 } 3327 3328 range->start = addr; 3329 range->size = size; 3330 3331 list_add_tail(&range->list, &io_range_list); 3332 3333 end_register: 3334 spin_unlock(&io_range_lock); 3335 #endif 3336 3337 return err; 3338 } 3339 3340 phys_addr_t pci_pio_to_address(unsigned long pio) 3341 { 3342 phys_addr_t address = (phys_addr_t)OF_BAD_ADDR; 3343 3344 #ifdef PCI_IOBASE 3345 struct io_range *range; 3346 resource_size_t allocated_size = 0; 3347 3348 if (pio > IO_SPACE_LIMIT) 3349 return address; 3350 3351 spin_lock(&io_range_lock); 3352 list_for_each_entry(range, &io_range_list, list) { 3353 if (pio >= allocated_size && pio < allocated_size + range->size) { 3354 address = range->start + pio - allocated_size; 3355 break; 3356 } 3357 allocated_size += range->size; 3358 } 3359 spin_unlock(&io_range_lock); 3360 #endif 3361 3362 return address; 3363 } 3364 3365 unsigned long __weak pci_address_to_pio(phys_addr_t address) 3366 { 3367 #ifdef PCI_IOBASE 3368 struct io_range *res; 3369 resource_size_t offset = 0; 3370 unsigned long addr = -1; 3371 3372 spin_lock(&io_range_lock); 3373 list_for_each_entry(res, &io_range_list, list) { 3374 if (address >= res->start && address < res->start + res->size) { 3375 addr = address - res->start + offset; 3376 break; 3377 } 3378 offset += res->size; 3379 } 3380 spin_unlock(&io_range_lock); 3381 3382 return addr; 3383 #else 3384 if (address > IO_SPACE_LIMIT) 3385 return (unsigned long)-1; 3386 3387 return (unsigned long) address; 3388 #endif 3389 } 3390 3391 /** 3392 * pci_remap_iospace - Remap the memory mapped I/O space 3393 * @res: Resource describing the I/O space 3394 * @phys_addr: physical address of range to be mapped 3395 * 3396 * Remap the memory mapped I/O space described by the @res 3397 * and the CPU physical address @phys_addr into virtual address space. 3398 * Only architectures that have memory mapped IO functions defined 3399 * (and the PCI_IOBASE value defined) should call this function. 3400 */ 3401 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr) 3402 { 3403 #if defined(PCI_IOBASE) && defined(CONFIG_MMU) 3404 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start; 3405 3406 if (!(res->flags & IORESOURCE_IO)) 3407 return -EINVAL; 3408 3409 if (res->end > IO_SPACE_LIMIT) 3410 return -EINVAL; 3411 3412 return ioremap_page_range(vaddr, vaddr + resource_size(res), phys_addr, 3413 pgprot_device(PAGE_KERNEL)); 3414 #else 3415 /* this architecture does not have memory mapped I/O space, 3416 so this function should never be called */ 3417 WARN_ONCE(1, "This architecture does not support memory mapped I/O\n"); 3418 return -ENODEV; 3419 #endif 3420 } 3421 EXPORT_SYMBOL(pci_remap_iospace); 3422 3423 /** 3424 * pci_unmap_iospace - Unmap the memory mapped I/O space 3425 * @res: resource to be unmapped 3426 * 3427 * Unmap the CPU virtual address @res from virtual address space. 3428 * Only architectures that have memory mapped IO functions defined 3429 * (and the PCI_IOBASE value defined) should call this function. 3430 */ 3431 void pci_unmap_iospace(struct resource *res) 3432 { 3433 #if defined(PCI_IOBASE) && defined(CONFIG_MMU) 3434 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start; 3435 3436 unmap_kernel_range(vaddr, resource_size(res)); 3437 #endif 3438 } 3439 EXPORT_SYMBOL(pci_unmap_iospace); 3440 3441 /** 3442 * devm_pci_remap_cfgspace - Managed pci_remap_cfgspace() 3443 * @dev: Generic device to remap IO address for 3444 * @offset: Resource address to map 3445 * @size: Size of map 3446 * 3447 * Managed pci_remap_cfgspace(). Map is automatically unmapped on driver 3448 * detach. 3449 */ 3450 void __iomem *devm_pci_remap_cfgspace(struct device *dev, 3451 resource_size_t offset, 3452 resource_size_t size) 3453 { 3454 void __iomem **ptr, *addr; 3455 3456 ptr = devres_alloc(devm_ioremap_release, sizeof(*ptr), GFP_KERNEL); 3457 if (!ptr) 3458 return NULL; 3459 3460 addr = pci_remap_cfgspace(offset, size); 3461 if (addr) { 3462 *ptr = addr; 3463 devres_add(dev, ptr); 3464 } else 3465 devres_free(ptr); 3466 3467 return addr; 3468 } 3469 EXPORT_SYMBOL(devm_pci_remap_cfgspace); 3470 3471 /** 3472 * devm_pci_remap_cfg_resource - check, request region and ioremap cfg resource 3473 * @dev: generic device to handle the resource for 3474 * @res: configuration space resource to be handled 3475 * 3476 * Checks that a resource is a valid memory region, requests the memory 3477 * region and ioremaps with pci_remap_cfgspace() API that ensures the 3478 * proper PCI configuration space memory attributes are guaranteed. 3479 * 3480 * All operations are managed and will be undone on driver detach. 3481 * 3482 * Returns a pointer to the remapped memory or an ERR_PTR() encoded error code 3483 * on failure. Usage example: 3484 * 3485 * res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 3486 * base = devm_pci_remap_cfg_resource(&pdev->dev, res); 3487 * if (IS_ERR(base)) 3488 * return PTR_ERR(base); 3489 */ 3490 void __iomem *devm_pci_remap_cfg_resource(struct device *dev, 3491 struct resource *res) 3492 { 3493 resource_size_t size; 3494 const char *name; 3495 void __iomem *dest_ptr; 3496 3497 BUG_ON(!dev); 3498 3499 if (!res || resource_type(res) != IORESOURCE_MEM) { 3500 dev_err(dev, "invalid resource\n"); 3501 return IOMEM_ERR_PTR(-EINVAL); 3502 } 3503 3504 size = resource_size(res); 3505 name = res->name ?: dev_name(dev); 3506 3507 if (!devm_request_mem_region(dev, res->start, size, name)) { 3508 dev_err(dev, "can't request region for resource %pR\n", res); 3509 return IOMEM_ERR_PTR(-EBUSY); 3510 } 3511 3512 dest_ptr = devm_pci_remap_cfgspace(dev, res->start, size); 3513 if (!dest_ptr) { 3514 dev_err(dev, "ioremap failed for resource %pR\n", res); 3515 devm_release_mem_region(dev, res->start, size); 3516 dest_ptr = IOMEM_ERR_PTR(-ENOMEM); 3517 } 3518 3519 return dest_ptr; 3520 } 3521 EXPORT_SYMBOL(devm_pci_remap_cfg_resource); 3522 3523 static void __pci_set_master(struct pci_dev *dev, bool enable) 3524 { 3525 u16 old_cmd, cmd; 3526 3527 pci_read_config_word(dev, PCI_COMMAND, &old_cmd); 3528 if (enable) 3529 cmd = old_cmd | PCI_COMMAND_MASTER; 3530 else 3531 cmd = old_cmd & ~PCI_COMMAND_MASTER; 3532 if (cmd != old_cmd) { 3533 dev_dbg(&dev->dev, "%s bus mastering\n", 3534 enable ? "enabling" : "disabling"); 3535 pci_write_config_word(dev, PCI_COMMAND, cmd); 3536 } 3537 dev->is_busmaster = enable; 3538 } 3539 3540 /** 3541 * pcibios_setup - process "pci=" kernel boot arguments 3542 * @str: string used to pass in "pci=" kernel boot arguments 3543 * 3544 * Process kernel boot arguments. This is the default implementation. 3545 * Architecture specific implementations can override this as necessary. 3546 */ 3547 char * __weak __init pcibios_setup(char *str) 3548 { 3549 return str; 3550 } 3551 3552 /** 3553 * pcibios_set_master - enable PCI bus-mastering for device dev 3554 * @dev: the PCI device to enable 3555 * 3556 * Enables PCI bus-mastering for the device. This is the default 3557 * implementation. Architecture specific implementations can override 3558 * this if necessary. 3559 */ 3560 void __weak pcibios_set_master(struct pci_dev *dev) 3561 { 3562 u8 lat; 3563 3564 /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */ 3565 if (pci_is_pcie(dev)) 3566 return; 3567 3568 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat); 3569 if (lat < 16) 3570 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency; 3571 else if (lat > pcibios_max_latency) 3572 lat = pcibios_max_latency; 3573 else 3574 return; 3575 3576 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat); 3577 } 3578 3579 /** 3580 * pci_set_master - enables bus-mastering for device dev 3581 * @dev: the PCI device to enable 3582 * 3583 * Enables bus-mastering on the device and calls pcibios_set_master() 3584 * to do the needed arch specific settings. 3585 */ 3586 void pci_set_master(struct pci_dev *dev) 3587 { 3588 __pci_set_master(dev, true); 3589 pcibios_set_master(dev); 3590 } 3591 EXPORT_SYMBOL(pci_set_master); 3592 3593 /** 3594 * pci_clear_master - disables bus-mastering for device dev 3595 * @dev: the PCI device to disable 3596 */ 3597 void pci_clear_master(struct pci_dev *dev) 3598 { 3599 __pci_set_master(dev, false); 3600 } 3601 EXPORT_SYMBOL(pci_clear_master); 3602 3603 /** 3604 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed 3605 * @dev: the PCI device for which MWI is to be enabled 3606 * 3607 * Helper function for pci_set_mwi. 3608 * Originally copied from drivers/net/acenic.c. 3609 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. 3610 * 3611 * RETURNS: An appropriate -ERRNO error value on error, or zero for success. 3612 */ 3613 int pci_set_cacheline_size(struct pci_dev *dev) 3614 { 3615 u8 cacheline_size; 3616 3617 if (!pci_cache_line_size) 3618 return -EINVAL; 3619 3620 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be 3621 equal to or multiple of the right value. */ 3622 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); 3623 if (cacheline_size >= pci_cache_line_size && 3624 (cacheline_size % pci_cache_line_size) == 0) 3625 return 0; 3626 3627 /* Write the correct value. */ 3628 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size); 3629 /* Read it back. */ 3630 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); 3631 if (cacheline_size == pci_cache_line_size) 3632 return 0; 3633 3634 dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not supported\n", 3635 pci_cache_line_size << 2); 3636 3637 return -EINVAL; 3638 } 3639 EXPORT_SYMBOL_GPL(pci_set_cacheline_size); 3640 3641 /** 3642 * pci_set_mwi - enables memory-write-invalidate PCI transaction 3643 * @dev: the PCI device for which MWI is enabled 3644 * 3645 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. 3646 * 3647 * RETURNS: An appropriate -ERRNO error value on error, or zero for success. 3648 */ 3649 int pci_set_mwi(struct pci_dev *dev) 3650 { 3651 #ifdef PCI_DISABLE_MWI 3652 return 0; 3653 #else 3654 int rc; 3655 u16 cmd; 3656 3657 rc = pci_set_cacheline_size(dev); 3658 if (rc) 3659 return rc; 3660 3661 pci_read_config_word(dev, PCI_COMMAND, &cmd); 3662 if (!(cmd & PCI_COMMAND_INVALIDATE)) { 3663 dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n"); 3664 cmd |= PCI_COMMAND_INVALIDATE; 3665 pci_write_config_word(dev, PCI_COMMAND, cmd); 3666 } 3667 return 0; 3668 #endif 3669 } 3670 EXPORT_SYMBOL(pci_set_mwi); 3671 3672 /** 3673 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction 3674 * @dev: the PCI device for which MWI is enabled 3675 * 3676 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. 3677 * Callers are not required to check the return value. 3678 * 3679 * RETURNS: An appropriate -ERRNO error value on error, or zero for success. 3680 */ 3681 int pci_try_set_mwi(struct pci_dev *dev) 3682 { 3683 #ifdef PCI_DISABLE_MWI 3684 return 0; 3685 #else 3686 return pci_set_mwi(dev); 3687 #endif 3688 } 3689 EXPORT_SYMBOL(pci_try_set_mwi); 3690 3691 /** 3692 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev 3693 * @dev: the PCI device to disable 3694 * 3695 * Disables PCI Memory-Write-Invalidate transaction on the device 3696 */ 3697 void pci_clear_mwi(struct pci_dev *dev) 3698 { 3699 #ifndef PCI_DISABLE_MWI 3700 u16 cmd; 3701 3702 pci_read_config_word(dev, PCI_COMMAND, &cmd); 3703 if (cmd & PCI_COMMAND_INVALIDATE) { 3704 cmd &= ~PCI_COMMAND_INVALIDATE; 3705 pci_write_config_word(dev, PCI_COMMAND, cmd); 3706 } 3707 #endif 3708 } 3709 EXPORT_SYMBOL(pci_clear_mwi); 3710 3711 /** 3712 * pci_intx - enables/disables PCI INTx for device dev 3713 * @pdev: the PCI device to operate on 3714 * @enable: boolean: whether to enable or disable PCI INTx 3715 * 3716 * Enables/disables PCI INTx for device dev 3717 */ 3718 void pci_intx(struct pci_dev *pdev, int enable) 3719 { 3720 u16 pci_command, new; 3721 3722 pci_read_config_word(pdev, PCI_COMMAND, &pci_command); 3723 3724 if (enable) 3725 new = pci_command & ~PCI_COMMAND_INTX_DISABLE; 3726 else 3727 new = pci_command | PCI_COMMAND_INTX_DISABLE; 3728 3729 if (new != pci_command) { 3730 struct pci_devres *dr; 3731 3732 pci_write_config_word(pdev, PCI_COMMAND, new); 3733 3734 dr = find_pci_dr(pdev); 3735 if (dr && !dr->restore_intx) { 3736 dr->restore_intx = 1; 3737 dr->orig_intx = !enable; 3738 } 3739 } 3740 } 3741 EXPORT_SYMBOL_GPL(pci_intx); 3742 3743 static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask) 3744 { 3745 struct pci_bus *bus = dev->bus; 3746 bool mask_updated = true; 3747 u32 cmd_status_dword; 3748 u16 origcmd, newcmd; 3749 unsigned long flags; 3750 bool irq_pending; 3751 3752 /* 3753 * We do a single dword read to retrieve both command and status. 3754 * Document assumptions that make this possible. 3755 */ 3756 BUILD_BUG_ON(PCI_COMMAND % 4); 3757 BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS); 3758 3759 raw_spin_lock_irqsave(&pci_lock, flags); 3760 3761 bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword); 3762 3763 irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT; 3764 3765 /* 3766 * Check interrupt status register to see whether our device 3767 * triggered the interrupt (when masking) or the next IRQ is 3768 * already pending (when unmasking). 3769 */ 3770 if (mask != irq_pending) { 3771 mask_updated = false; 3772 goto done; 3773 } 3774 3775 origcmd = cmd_status_dword; 3776 newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE; 3777 if (mask) 3778 newcmd |= PCI_COMMAND_INTX_DISABLE; 3779 if (newcmd != origcmd) 3780 bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd); 3781 3782 done: 3783 raw_spin_unlock_irqrestore(&pci_lock, flags); 3784 3785 return mask_updated; 3786 } 3787 3788 /** 3789 * pci_check_and_mask_intx - mask INTx on pending interrupt 3790 * @dev: the PCI device to operate on 3791 * 3792 * Check if the device dev has its INTx line asserted, mask it and 3793 * return true in that case. False is returned if no interrupt was 3794 * pending. 3795 */ 3796 bool pci_check_and_mask_intx(struct pci_dev *dev) 3797 { 3798 return pci_check_and_set_intx_mask(dev, true); 3799 } 3800 EXPORT_SYMBOL_GPL(pci_check_and_mask_intx); 3801 3802 /** 3803 * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending 3804 * @dev: the PCI device to operate on 3805 * 3806 * Check if the device dev has its INTx line asserted, unmask it if not 3807 * and return true. False is returned and the mask remains active if 3808 * there was still an interrupt pending. 3809 */ 3810 bool pci_check_and_unmask_intx(struct pci_dev *dev) 3811 { 3812 return pci_check_and_set_intx_mask(dev, false); 3813 } 3814 EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx); 3815 3816 /** 3817 * pci_wait_for_pending_transaction - waits for pending transaction 3818 * @dev: the PCI device to operate on 3819 * 3820 * Return 0 if transaction is pending 1 otherwise. 3821 */ 3822 int pci_wait_for_pending_transaction(struct pci_dev *dev) 3823 { 3824 if (!pci_is_pcie(dev)) 3825 return 1; 3826 3827 return pci_wait_for_pending(dev, pci_pcie_cap(dev) + PCI_EXP_DEVSTA, 3828 PCI_EXP_DEVSTA_TRPND); 3829 } 3830 EXPORT_SYMBOL(pci_wait_for_pending_transaction); 3831 3832 static void pci_flr_wait(struct pci_dev *dev) 3833 { 3834 int delay = 1, timeout = 60000; 3835 u32 id; 3836 3837 /* 3838 * Per PCIe r3.1, sec 6.6.2, a device must complete an FLR within 3839 * 100ms, but may silently discard requests while the FLR is in 3840 * progress. Wait 100ms before trying to access the device. 3841 */ 3842 msleep(100); 3843 3844 /* 3845 * After 100ms, the device should not silently discard config 3846 * requests, but it may still indicate that it needs more time by 3847 * responding to them with CRS completions. The Root Port will 3848 * generally synthesize ~0 data to complete the read (except when 3849 * CRS SV is enabled and the read was for the Vendor ID; in that 3850 * case it synthesizes 0x0001 data). 3851 * 3852 * Wait for the device to return a non-CRS completion. Read the 3853 * Command register instead of Vendor ID so we don't have to 3854 * contend with the CRS SV value. 3855 */ 3856 pci_read_config_dword(dev, PCI_COMMAND, &id); 3857 while (id == ~0) { 3858 if (delay > timeout) { 3859 dev_warn(&dev->dev, "not ready %dms after FLR; giving up\n", 3860 100 + delay - 1); 3861 return; 3862 } 3863 3864 if (delay > 1000) 3865 dev_info(&dev->dev, "not ready %dms after FLR; waiting\n", 3866 100 + delay - 1); 3867 3868 msleep(delay); 3869 delay *= 2; 3870 pci_read_config_dword(dev, PCI_COMMAND, &id); 3871 } 3872 3873 if (delay > 1000) 3874 dev_info(&dev->dev, "ready %dms after FLR\n", 100 + delay - 1); 3875 } 3876 3877 /** 3878 * pcie_has_flr - check if a device supports function level resets 3879 * @dev: device to check 3880 * 3881 * Returns true if the device advertises support for PCIe function level 3882 * resets. 3883 */ 3884 static bool pcie_has_flr(struct pci_dev *dev) 3885 { 3886 u32 cap; 3887 3888 if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET) 3889 return false; 3890 3891 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap); 3892 return cap & PCI_EXP_DEVCAP_FLR; 3893 } 3894 3895 /** 3896 * pcie_flr - initiate a PCIe function level reset 3897 * @dev: device to reset 3898 * 3899 * Initiate a function level reset on @dev. The caller should ensure the 3900 * device supports FLR before calling this function, e.g. by using the 3901 * pcie_has_flr() helper. 3902 */ 3903 void pcie_flr(struct pci_dev *dev) 3904 { 3905 if (!pci_wait_for_pending_transaction(dev)) 3906 dev_err(&dev->dev, "timed out waiting for pending transaction; performing function level reset anyway\n"); 3907 3908 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR); 3909 pci_flr_wait(dev); 3910 } 3911 EXPORT_SYMBOL_GPL(pcie_flr); 3912 3913 static int pci_af_flr(struct pci_dev *dev, int probe) 3914 { 3915 int pos; 3916 u8 cap; 3917 3918 pos = pci_find_capability(dev, PCI_CAP_ID_AF); 3919 if (!pos) 3920 return -ENOTTY; 3921 3922 if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET) 3923 return -ENOTTY; 3924 3925 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap); 3926 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR)) 3927 return -ENOTTY; 3928 3929 if (probe) 3930 return 0; 3931 3932 /* 3933 * Wait for Transaction Pending bit to clear. A word-aligned test 3934 * is used, so we use the conrol offset rather than status and shift 3935 * the test bit to match. 3936 */ 3937 if (!pci_wait_for_pending(dev, pos + PCI_AF_CTRL, 3938 PCI_AF_STATUS_TP << 8)) 3939 dev_err(&dev->dev, "timed out waiting for pending transaction; performing AF function level reset anyway\n"); 3940 3941 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR); 3942 pci_flr_wait(dev); 3943 return 0; 3944 } 3945 3946 /** 3947 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0. 3948 * @dev: Device to reset. 3949 * @probe: If set, only check if the device can be reset this way. 3950 * 3951 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is 3952 * unset, it will be reinitialized internally when going from PCI_D3hot to 3953 * PCI_D0. If that's the case and the device is not in a low-power state 3954 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset. 3955 * 3956 * NOTE: This causes the caller to sleep for twice the device power transition 3957 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms 3958 * by default (i.e. unless the @dev's d3_delay field has a different value). 3959 * Moreover, only devices in D0 can be reset by this function. 3960 */ 3961 static int pci_pm_reset(struct pci_dev *dev, int probe) 3962 { 3963 u16 csr; 3964 3965 if (!dev->pm_cap || dev->dev_flags & PCI_DEV_FLAGS_NO_PM_RESET) 3966 return -ENOTTY; 3967 3968 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr); 3969 if (csr & PCI_PM_CTRL_NO_SOFT_RESET) 3970 return -ENOTTY; 3971 3972 if (probe) 3973 return 0; 3974 3975 if (dev->current_state != PCI_D0) 3976 return -EINVAL; 3977 3978 csr &= ~PCI_PM_CTRL_STATE_MASK; 3979 csr |= PCI_D3hot; 3980 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); 3981 pci_dev_d3_sleep(dev); 3982 3983 csr &= ~PCI_PM_CTRL_STATE_MASK; 3984 csr |= PCI_D0; 3985 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); 3986 pci_dev_d3_sleep(dev); 3987 3988 return 0; 3989 } 3990 3991 void pci_reset_secondary_bus(struct pci_dev *dev) 3992 { 3993 u16 ctrl; 3994 3995 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl); 3996 ctrl |= PCI_BRIDGE_CTL_BUS_RESET; 3997 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl); 3998 /* 3999 * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double 4000 * this to 2ms to ensure that we meet the minimum requirement. 4001 */ 4002 msleep(2); 4003 4004 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET; 4005 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl); 4006 4007 /* 4008 * Trhfa for conventional PCI is 2^25 clock cycles. 4009 * Assuming a minimum 33MHz clock this results in a 1s 4010 * delay before we can consider subordinate devices to 4011 * be re-initialized. PCIe has some ways to shorten this, 4012 * but we don't make use of them yet. 4013 */ 4014 ssleep(1); 4015 } 4016 4017 void __weak pcibios_reset_secondary_bus(struct pci_dev *dev) 4018 { 4019 pci_reset_secondary_bus(dev); 4020 } 4021 4022 /** 4023 * pci_reset_bridge_secondary_bus - Reset the secondary bus on a PCI bridge. 4024 * @dev: Bridge device 4025 * 4026 * Use the bridge control register to assert reset on the secondary bus. 4027 * Devices on the secondary bus are left in power-on state. 4028 */ 4029 void pci_reset_bridge_secondary_bus(struct pci_dev *dev) 4030 { 4031 pcibios_reset_secondary_bus(dev); 4032 } 4033 EXPORT_SYMBOL_GPL(pci_reset_bridge_secondary_bus); 4034 4035 static int pci_parent_bus_reset(struct pci_dev *dev, int probe) 4036 { 4037 struct pci_dev *pdev; 4038 4039 if (pci_is_root_bus(dev->bus) || dev->subordinate || 4040 !dev->bus->self || dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET) 4041 return -ENOTTY; 4042 4043 list_for_each_entry(pdev, &dev->bus->devices, bus_list) 4044 if (pdev != dev) 4045 return -ENOTTY; 4046 4047 if (probe) 4048 return 0; 4049 4050 pci_reset_bridge_secondary_bus(dev->bus->self); 4051 4052 return 0; 4053 } 4054 4055 static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, int probe) 4056 { 4057 int rc = -ENOTTY; 4058 4059 if (!hotplug || !try_module_get(hotplug->ops->owner)) 4060 return rc; 4061 4062 if (hotplug->ops->reset_slot) 4063 rc = hotplug->ops->reset_slot(hotplug, probe); 4064 4065 module_put(hotplug->ops->owner); 4066 4067 return rc; 4068 } 4069 4070 static int pci_dev_reset_slot_function(struct pci_dev *dev, int probe) 4071 { 4072 struct pci_dev *pdev; 4073 4074 if (dev->subordinate || !dev->slot || 4075 dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET) 4076 return -ENOTTY; 4077 4078 list_for_each_entry(pdev, &dev->bus->devices, bus_list) 4079 if (pdev != dev && pdev->slot == dev->slot) 4080 return -ENOTTY; 4081 4082 return pci_reset_hotplug_slot(dev->slot->hotplug, probe); 4083 } 4084 4085 static void pci_dev_lock(struct pci_dev *dev) 4086 { 4087 pci_cfg_access_lock(dev); 4088 /* block PM suspend, driver probe, etc. */ 4089 device_lock(&dev->dev); 4090 } 4091 4092 /* Return 1 on successful lock, 0 on contention */ 4093 static int pci_dev_trylock(struct pci_dev *dev) 4094 { 4095 if (pci_cfg_access_trylock(dev)) { 4096 if (device_trylock(&dev->dev)) 4097 return 1; 4098 pci_cfg_access_unlock(dev); 4099 } 4100 4101 return 0; 4102 } 4103 4104 static void pci_dev_unlock(struct pci_dev *dev) 4105 { 4106 device_unlock(&dev->dev); 4107 pci_cfg_access_unlock(dev); 4108 } 4109 4110 static void pci_dev_save_and_disable(struct pci_dev *dev) 4111 { 4112 const struct pci_error_handlers *err_handler = 4113 dev->driver ? dev->driver->err_handler : NULL; 4114 4115 /* 4116 * dev->driver->err_handler->reset_prepare() is protected against 4117 * races with ->remove() by the device lock, which must be held by 4118 * the caller. 4119 */ 4120 if (err_handler && err_handler->reset_prepare) 4121 err_handler->reset_prepare(dev); 4122 4123 /* 4124 * Wake-up device prior to save. PM registers default to D0 after 4125 * reset and a simple register restore doesn't reliably return 4126 * to a non-D0 state anyway. 4127 */ 4128 pci_set_power_state(dev, PCI_D0); 4129 4130 pci_save_state(dev); 4131 /* 4132 * Disable the device by clearing the Command register, except for 4133 * INTx-disable which is set. This not only disables MMIO and I/O port 4134 * BARs, but also prevents the device from being Bus Master, preventing 4135 * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3 4136 * compliant devices, INTx-disable prevents legacy interrupts. 4137 */ 4138 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE); 4139 } 4140 4141 static void pci_dev_restore(struct pci_dev *dev) 4142 { 4143 const struct pci_error_handlers *err_handler = 4144 dev->driver ? dev->driver->err_handler : NULL; 4145 4146 pci_restore_state(dev); 4147 4148 /* 4149 * dev->driver->err_handler->reset_done() is protected against 4150 * races with ->remove() by the device lock, which must be held by 4151 * the caller. 4152 */ 4153 if (err_handler && err_handler->reset_done) 4154 err_handler->reset_done(dev); 4155 } 4156 4157 /** 4158 * __pci_reset_function - reset a PCI device function 4159 * @dev: PCI device to reset 4160 * 4161 * Some devices allow an individual function to be reset without affecting 4162 * other functions in the same device. The PCI device must be responsive 4163 * to PCI config space in order to use this function. 4164 * 4165 * The device function is presumed to be unused when this function is called. 4166 * Resetting the device will make the contents of PCI configuration space 4167 * random, so any caller of this must be prepared to reinitialise the 4168 * device including MSI, bus mastering, BARs, decoding IO and memory spaces, 4169 * etc. 4170 * 4171 * Returns 0 if the device function was successfully reset or negative if the 4172 * device doesn't support resetting a single function. 4173 */ 4174 int __pci_reset_function(struct pci_dev *dev) 4175 { 4176 int ret; 4177 4178 pci_dev_lock(dev); 4179 ret = __pci_reset_function_locked(dev); 4180 pci_dev_unlock(dev); 4181 4182 return ret; 4183 } 4184 EXPORT_SYMBOL_GPL(__pci_reset_function); 4185 4186 /** 4187 * __pci_reset_function_locked - reset a PCI device function while holding 4188 * the @dev mutex lock. 4189 * @dev: PCI device to reset 4190 * 4191 * Some devices allow an individual function to be reset without affecting 4192 * other functions in the same device. The PCI device must be responsive 4193 * to PCI config space in order to use this function. 4194 * 4195 * The device function is presumed to be unused and the caller is holding 4196 * the device mutex lock when this function is called. 4197 * Resetting the device will make the contents of PCI configuration space 4198 * random, so any caller of this must be prepared to reinitialise the 4199 * device including MSI, bus mastering, BARs, decoding IO and memory spaces, 4200 * etc. 4201 * 4202 * Returns 0 if the device function was successfully reset or negative if the 4203 * device doesn't support resetting a single function. 4204 */ 4205 int __pci_reset_function_locked(struct pci_dev *dev) 4206 { 4207 int rc; 4208 4209 might_sleep(); 4210 4211 rc = pci_dev_specific_reset(dev, 0); 4212 if (rc != -ENOTTY) 4213 return rc; 4214 if (pcie_has_flr(dev)) { 4215 pcie_flr(dev); 4216 return 0; 4217 } 4218 rc = pci_af_flr(dev, 0); 4219 if (rc != -ENOTTY) 4220 return rc; 4221 rc = pci_pm_reset(dev, 0); 4222 if (rc != -ENOTTY) 4223 return rc; 4224 rc = pci_dev_reset_slot_function(dev, 0); 4225 if (rc != -ENOTTY) 4226 return rc; 4227 return pci_parent_bus_reset(dev, 0); 4228 } 4229 EXPORT_SYMBOL_GPL(__pci_reset_function_locked); 4230 4231 /** 4232 * pci_probe_reset_function - check whether the device can be safely reset 4233 * @dev: PCI device to reset 4234 * 4235 * Some devices allow an individual function to be reset without affecting 4236 * other functions in the same device. The PCI device must be responsive 4237 * to PCI config space in order to use this function. 4238 * 4239 * Returns 0 if the device function can be reset or negative if the 4240 * device doesn't support resetting a single function. 4241 */ 4242 int pci_probe_reset_function(struct pci_dev *dev) 4243 { 4244 int rc; 4245 4246 might_sleep(); 4247 4248 rc = pci_dev_specific_reset(dev, 1); 4249 if (rc != -ENOTTY) 4250 return rc; 4251 if (pcie_has_flr(dev)) 4252 return 0; 4253 rc = pci_af_flr(dev, 1); 4254 if (rc != -ENOTTY) 4255 return rc; 4256 rc = pci_pm_reset(dev, 1); 4257 if (rc != -ENOTTY) 4258 return rc; 4259 rc = pci_dev_reset_slot_function(dev, 1); 4260 if (rc != -ENOTTY) 4261 return rc; 4262 4263 return pci_parent_bus_reset(dev, 1); 4264 } 4265 4266 /** 4267 * pci_reset_function - quiesce and reset a PCI device function 4268 * @dev: PCI device to reset 4269 * 4270 * Some devices allow an individual function to be reset without affecting 4271 * other functions in the same device. The PCI device must be responsive 4272 * to PCI config space in order to use this function. 4273 * 4274 * This function does not just reset the PCI portion of a device, but 4275 * clears all the state associated with the device. This function differs 4276 * from __pci_reset_function in that it saves and restores device state 4277 * over the reset. 4278 * 4279 * Returns 0 if the device function was successfully reset or negative if the 4280 * device doesn't support resetting a single function. 4281 */ 4282 int pci_reset_function(struct pci_dev *dev) 4283 { 4284 int rc; 4285 4286 rc = pci_probe_reset_function(dev); 4287 if (rc) 4288 return rc; 4289 4290 pci_dev_lock(dev); 4291 pci_dev_save_and_disable(dev); 4292 4293 rc = __pci_reset_function_locked(dev); 4294 4295 pci_dev_restore(dev); 4296 pci_dev_unlock(dev); 4297 4298 return rc; 4299 } 4300 EXPORT_SYMBOL_GPL(pci_reset_function); 4301 4302 /** 4303 * pci_reset_function_locked - quiesce and reset a PCI device function 4304 * @dev: PCI device to reset 4305 * 4306 * Some devices allow an individual function to be reset without affecting 4307 * other functions in the same device. The PCI device must be responsive 4308 * to PCI config space in order to use this function. 4309 * 4310 * This function does not just reset the PCI portion of a device, but 4311 * clears all the state associated with the device. This function differs 4312 * from __pci_reset_function() in that it saves and restores device state 4313 * over the reset. It also differs from pci_reset_function() in that it 4314 * requires the PCI device lock to be held. 4315 * 4316 * Returns 0 if the device function was successfully reset or negative if the 4317 * device doesn't support resetting a single function. 4318 */ 4319 int pci_reset_function_locked(struct pci_dev *dev) 4320 { 4321 int rc; 4322 4323 rc = pci_probe_reset_function(dev); 4324 if (rc) 4325 return rc; 4326 4327 pci_dev_save_and_disable(dev); 4328 4329 rc = __pci_reset_function_locked(dev); 4330 4331 pci_dev_restore(dev); 4332 4333 return rc; 4334 } 4335 EXPORT_SYMBOL_GPL(pci_reset_function_locked); 4336 4337 /** 4338 * pci_try_reset_function - quiesce and reset a PCI device function 4339 * @dev: PCI device to reset 4340 * 4341 * Same as above, except return -EAGAIN if unable to lock device. 4342 */ 4343 int pci_try_reset_function(struct pci_dev *dev) 4344 { 4345 int rc; 4346 4347 rc = pci_probe_reset_function(dev); 4348 if (rc) 4349 return rc; 4350 4351 if (!pci_dev_trylock(dev)) 4352 return -EAGAIN; 4353 4354 pci_dev_save_and_disable(dev); 4355 rc = __pci_reset_function_locked(dev); 4356 pci_dev_unlock(dev); 4357 4358 pci_dev_restore(dev); 4359 return rc; 4360 } 4361 EXPORT_SYMBOL_GPL(pci_try_reset_function); 4362 4363 /* Do any devices on or below this bus prevent a bus reset? */ 4364 static bool pci_bus_resetable(struct pci_bus *bus) 4365 { 4366 struct pci_dev *dev; 4367 4368 list_for_each_entry(dev, &bus->devices, bus_list) { 4369 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET || 4370 (dev->subordinate && !pci_bus_resetable(dev->subordinate))) 4371 return false; 4372 } 4373 4374 return true; 4375 } 4376 4377 /* Lock devices from the top of the tree down */ 4378 static void pci_bus_lock(struct pci_bus *bus) 4379 { 4380 struct pci_dev *dev; 4381 4382 list_for_each_entry(dev, &bus->devices, bus_list) { 4383 pci_dev_lock(dev); 4384 if (dev->subordinate) 4385 pci_bus_lock(dev->subordinate); 4386 } 4387 } 4388 4389 /* Unlock devices from the bottom of the tree up */ 4390 static void pci_bus_unlock(struct pci_bus *bus) 4391 { 4392 struct pci_dev *dev; 4393 4394 list_for_each_entry(dev, &bus->devices, bus_list) { 4395 if (dev->subordinate) 4396 pci_bus_unlock(dev->subordinate); 4397 pci_dev_unlock(dev); 4398 } 4399 } 4400 4401 /* Return 1 on successful lock, 0 on contention */ 4402 static int pci_bus_trylock(struct pci_bus *bus) 4403 { 4404 struct pci_dev *dev; 4405 4406 list_for_each_entry(dev, &bus->devices, bus_list) { 4407 if (!pci_dev_trylock(dev)) 4408 goto unlock; 4409 if (dev->subordinate) { 4410 if (!pci_bus_trylock(dev->subordinate)) { 4411 pci_dev_unlock(dev); 4412 goto unlock; 4413 } 4414 } 4415 } 4416 return 1; 4417 4418 unlock: 4419 list_for_each_entry_continue_reverse(dev, &bus->devices, bus_list) { 4420 if (dev->subordinate) 4421 pci_bus_unlock(dev->subordinate); 4422 pci_dev_unlock(dev); 4423 } 4424 return 0; 4425 } 4426 4427 /* Do any devices on or below this slot prevent a bus reset? */ 4428 static bool pci_slot_resetable(struct pci_slot *slot) 4429 { 4430 struct pci_dev *dev; 4431 4432 list_for_each_entry(dev, &slot->bus->devices, bus_list) { 4433 if (!dev->slot || dev->slot != slot) 4434 continue; 4435 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET || 4436 (dev->subordinate && !pci_bus_resetable(dev->subordinate))) 4437 return false; 4438 } 4439 4440 return true; 4441 } 4442 4443 /* Lock devices from the top of the tree down */ 4444 static void pci_slot_lock(struct pci_slot *slot) 4445 { 4446 struct pci_dev *dev; 4447 4448 list_for_each_entry(dev, &slot->bus->devices, bus_list) { 4449 if (!dev->slot || dev->slot != slot) 4450 continue; 4451 pci_dev_lock(dev); 4452 if (dev->subordinate) 4453 pci_bus_lock(dev->subordinate); 4454 } 4455 } 4456 4457 /* Unlock devices from the bottom of the tree up */ 4458 static void pci_slot_unlock(struct pci_slot *slot) 4459 { 4460 struct pci_dev *dev; 4461 4462 list_for_each_entry(dev, &slot->bus->devices, bus_list) { 4463 if (!dev->slot || dev->slot != slot) 4464 continue; 4465 if (dev->subordinate) 4466 pci_bus_unlock(dev->subordinate); 4467 pci_dev_unlock(dev); 4468 } 4469 } 4470 4471 /* Return 1 on successful lock, 0 on contention */ 4472 static int pci_slot_trylock(struct pci_slot *slot) 4473 { 4474 struct pci_dev *dev; 4475 4476 list_for_each_entry(dev, &slot->bus->devices, bus_list) { 4477 if (!dev->slot || dev->slot != slot) 4478 continue; 4479 if (!pci_dev_trylock(dev)) 4480 goto unlock; 4481 if (dev->subordinate) { 4482 if (!pci_bus_trylock(dev->subordinate)) { 4483 pci_dev_unlock(dev); 4484 goto unlock; 4485 } 4486 } 4487 } 4488 return 1; 4489 4490 unlock: 4491 list_for_each_entry_continue_reverse(dev, 4492 &slot->bus->devices, bus_list) { 4493 if (!dev->slot || dev->slot != slot) 4494 continue; 4495 if (dev->subordinate) 4496 pci_bus_unlock(dev->subordinate); 4497 pci_dev_unlock(dev); 4498 } 4499 return 0; 4500 } 4501 4502 /* Save and disable devices from the top of the tree down */ 4503 static void pci_bus_save_and_disable(struct pci_bus *bus) 4504 { 4505 struct pci_dev *dev; 4506 4507 list_for_each_entry(dev, &bus->devices, bus_list) { 4508 pci_dev_lock(dev); 4509 pci_dev_save_and_disable(dev); 4510 pci_dev_unlock(dev); 4511 if (dev->subordinate) 4512 pci_bus_save_and_disable(dev->subordinate); 4513 } 4514 } 4515 4516 /* 4517 * Restore devices from top of the tree down - parent bridges need to be 4518 * restored before we can get to subordinate devices. 4519 */ 4520 static void pci_bus_restore(struct pci_bus *bus) 4521 { 4522 struct pci_dev *dev; 4523 4524 list_for_each_entry(dev, &bus->devices, bus_list) { 4525 pci_dev_lock(dev); 4526 pci_dev_restore(dev); 4527 pci_dev_unlock(dev); 4528 if (dev->subordinate) 4529 pci_bus_restore(dev->subordinate); 4530 } 4531 } 4532 4533 /* Save and disable devices from the top of the tree down */ 4534 static void pci_slot_save_and_disable(struct pci_slot *slot) 4535 { 4536 struct pci_dev *dev; 4537 4538 list_for_each_entry(dev, &slot->bus->devices, bus_list) { 4539 if (!dev->slot || dev->slot != slot) 4540 continue; 4541 pci_dev_save_and_disable(dev); 4542 if (dev->subordinate) 4543 pci_bus_save_and_disable(dev->subordinate); 4544 } 4545 } 4546 4547 /* 4548 * Restore devices from top of the tree down - parent bridges need to be 4549 * restored before we can get to subordinate devices. 4550 */ 4551 static void pci_slot_restore(struct pci_slot *slot) 4552 { 4553 struct pci_dev *dev; 4554 4555 list_for_each_entry(dev, &slot->bus->devices, bus_list) { 4556 if (!dev->slot || dev->slot != slot) 4557 continue; 4558 pci_dev_restore(dev); 4559 if (dev->subordinate) 4560 pci_bus_restore(dev->subordinate); 4561 } 4562 } 4563 4564 static int pci_slot_reset(struct pci_slot *slot, int probe) 4565 { 4566 int rc; 4567 4568 if (!slot || !pci_slot_resetable(slot)) 4569 return -ENOTTY; 4570 4571 if (!probe) 4572 pci_slot_lock(slot); 4573 4574 might_sleep(); 4575 4576 rc = pci_reset_hotplug_slot(slot->hotplug, probe); 4577 4578 if (!probe) 4579 pci_slot_unlock(slot); 4580 4581 return rc; 4582 } 4583 4584 /** 4585 * pci_probe_reset_slot - probe whether a PCI slot can be reset 4586 * @slot: PCI slot to probe 4587 * 4588 * Return 0 if slot can be reset, negative if a slot reset is not supported. 4589 */ 4590 int pci_probe_reset_slot(struct pci_slot *slot) 4591 { 4592 return pci_slot_reset(slot, 1); 4593 } 4594 EXPORT_SYMBOL_GPL(pci_probe_reset_slot); 4595 4596 /** 4597 * pci_reset_slot - reset a PCI slot 4598 * @slot: PCI slot to reset 4599 * 4600 * A PCI bus may host multiple slots, each slot may support a reset mechanism 4601 * independent of other slots. For instance, some slots may support slot power 4602 * control. In the case of a 1:1 bus to slot architecture, this function may 4603 * wrap the bus reset to avoid spurious slot related events such as hotplug. 4604 * Generally a slot reset should be attempted before a bus reset. All of the 4605 * function of the slot and any subordinate buses behind the slot are reset 4606 * through this function. PCI config space of all devices in the slot and 4607 * behind the slot is saved before and restored after reset. 4608 * 4609 * Return 0 on success, non-zero on error. 4610 */ 4611 int pci_reset_slot(struct pci_slot *slot) 4612 { 4613 int rc; 4614 4615 rc = pci_slot_reset(slot, 1); 4616 if (rc) 4617 return rc; 4618 4619 pci_slot_save_and_disable(slot); 4620 4621 rc = pci_slot_reset(slot, 0); 4622 4623 pci_slot_restore(slot); 4624 4625 return rc; 4626 } 4627 EXPORT_SYMBOL_GPL(pci_reset_slot); 4628 4629 /** 4630 * pci_try_reset_slot - Try to reset a PCI slot 4631 * @slot: PCI slot to reset 4632 * 4633 * Same as above except return -EAGAIN if the slot cannot be locked 4634 */ 4635 int pci_try_reset_slot(struct pci_slot *slot) 4636 { 4637 int rc; 4638 4639 rc = pci_slot_reset(slot, 1); 4640 if (rc) 4641 return rc; 4642 4643 pci_slot_save_and_disable(slot); 4644 4645 if (pci_slot_trylock(slot)) { 4646 might_sleep(); 4647 rc = pci_reset_hotplug_slot(slot->hotplug, 0); 4648 pci_slot_unlock(slot); 4649 } else 4650 rc = -EAGAIN; 4651 4652 pci_slot_restore(slot); 4653 4654 return rc; 4655 } 4656 EXPORT_SYMBOL_GPL(pci_try_reset_slot); 4657 4658 static int pci_bus_reset(struct pci_bus *bus, int probe) 4659 { 4660 if (!bus->self || !pci_bus_resetable(bus)) 4661 return -ENOTTY; 4662 4663 if (probe) 4664 return 0; 4665 4666 pci_bus_lock(bus); 4667 4668 might_sleep(); 4669 4670 pci_reset_bridge_secondary_bus(bus->self); 4671 4672 pci_bus_unlock(bus); 4673 4674 return 0; 4675 } 4676 4677 /** 4678 * pci_probe_reset_bus - probe whether a PCI bus can be reset 4679 * @bus: PCI bus to probe 4680 * 4681 * Return 0 if bus can be reset, negative if a bus reset is not supported. 4682 */ 4683 int pci_probe_reset_bus(struct pci_bus *bus) 4684 { 4685 return pci_bus_reset(bus, 1); 4686 } 4687 EXPORT_SYMBOL_GPL(pci_probe_reset_bus); 4688 4689 /** 4690 * pci_reset_bus - reset a PCI bus 4691 * @bus: top level PCI bus to reset 4692 * 4693 * Do a bus reset on the given bus and any subordinate buses, saving 4694 * and restoring state of all devices. 4695 * 4696 * Return 0 on success, non-zero on error. 4697 */ 4698 int pci_reset_bus(struct pci_bus *bus) 4699 { 4700 int rc; 4701 4702 rc = pci_bus_reset(bus, 1); 4703 if (rc) 4704 return rc; 4705 4706 pci_bus_save_and_disable(bus); 4707 4708 rc = pci_bus_reset(bus, 0); 4709 4710 pci_bus_restore(bus); 4711 4712 return rc; 4713 } 4714 EXPORT_SYMBOL_GPL(pci_reset_bus); 4715 4716 /** 4717 * pci_try_reset_bus - Try to reset a PCI bus 4718 * @bus: top level PCI bus to reset 4719 * 4720 * Same as above except return -EAGAIN if the bus cannot be locked 4721 */ 4722 int pci_try_reset_bus(struct pci_bus *bus) 4723 { 4724 int rc; 4725 4726 rc = pci_bus_reset(bus, 1); 4727 if (rc) 4728 return rc; 4729 4730 pci_bus_save_and_disable(bus); 4731 4732 if (pci_bus_trylock(bus)) { 4733 might_sleep(); 4734 pci_reset_bridge_secondary_bus(bus->self); 4735 pci_bus_unlock(bus); 4736 } else 4737 rc = -EAGAIN; 4738 4739 pci_bus_restore(bus); 4740 4741 return rc; 4742 } 4743 EXPORT_SYMBOL_GPL(pci_try_reset_bus); 4744 4745 /** 4746 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count 4747 * @dev: PCI device to query 4748 * 4749 * Returns mmrbc: maximum designed memory read count in bytes 4750 * or appropriate error value. 4751 */ 4752 int pcix_get_max_mmrbc(struct pci_dev *dev) 4753 { 4754 int cap; 4755 u32 stat; 4756 4757 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); 4758 if (!cap) 4759 return -EINVAL; 4760 4761 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat)) 4762 return -EINVAL; 4763 4764 return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21); 4765 } 4766 EXPORT_SYMBOL(pcix_get_max_mmrbc); 4767 4768 /** 4769 * pcix_get_mmrbc - get PCI-X maximum memory read byte count 4770 * @dev: PCI device to query 4771 * 4772 * Returns mmrbc: maximum memory read count in bytes 4773 * or appropriate error value. 4774 */ 4775 int pcix_get_mmrbc(struct pci_dev *dev) 4776 { 4777 int cap; 4778 u16 cmd; 4779 4780 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); 4781 if (!cap) 4782 return -EINVAL; 4783 4784 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd)) 4785 return -EINVAL; 4786 4787 return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2); 4788 } 4789 EXPORT_SYMBOL(pcix_get_mmrbc); 4790 4791 /** 4792 * pcix_set_mmrbc - set PCI-X maximum memory read byte count 4793 * @dev: PCI device to query 4794 * @mmrbc: maximum memory read count in bytes 4795 * valid values are 512, 1024, 2048, 4096 4796 * 4797 * If possible sets maximum memory read byte count, some bridges have erratas 4798 * that prevent this. 4799 */ 4800 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc) 4801 { 4802 int cap; 4803 u32 stat, v, o; 4804 u16 cmd; 4805 4806 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc)) 4807 return -EINVAL; 4808 4809 v = ffs(mmrbc) - 10; 4810 4811 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); 4812 if (!cap) 4813 return -EINVAL; 4814 4815 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat)) 4816 return -EINVAL; 4817 4818 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21) 4819 return -E2BIG; 4820 4821 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd)) 4822 return -EINVAL; 4823 4824 o = (cmd & PCI_X_CMD_MAX_READ) >> 2; 4825 if (o != v) { 4826 if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC)) 4827 return -EIO; 4828 4829 cmd &= ~PCI_X_CMD_MAX_READ; 4830 cmd |= v << 2; 4831 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd)) 4832 return -EIO; 4833 } 4834 return 0; 4835 } 4836 EXPORT_SYMBOL(pcix_set_mmrbc); 4837 4838 /** 4839 * pcie_get_readrq - get PCI Express read request size 4840 * @dev: PCI device to query 4841 * 4842 * Returns maximum memory read request in bytes 4843 * or appropriate error value. 4844 */ 4845 int pcie_get_readrq(struct pci_dev *dev) 4846 { 4847 u16 ctl; 4848 4849 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl); 4850 4851 return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12); 4852 } 4853 EXPORT_SYMBOL(pcie_get_readrq); 4854 4855 /** 4856 * pcie_set_readrq - set PCI Express maximum memory read request 4857 * @dev: PCI device to query 4858 * @rq: maximum memory read count in bytes 4859 * valid values are 128, 256, 512, 1024, 2048, 4096 4860 * 4861 * If possible sets maximum memory read request in bytes 4862 */ 4863 int pcie_set_readrq(struct pci_dev *dev, int rq) 4864 { 4865 u16 v; 4866 4867 if (rq < 128 || rq > 4096 || !is_power_of_2(rq)) 4868 return -EINVAL; 4869 4870 /* 4871 * If using the "performance" PCIe config, we clamp the 4872 * read rq size to the max packet size to prevent the 4873 * host bridge generating requests larger than we can 4874 * cope with 4875 */ 4876 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) { 4877 int mps = pcie_get_mps(dev); 4878 4879 if (mps < rq) 4880 rq = mps; 4881 } 4882 4883 v = (ffs(rq) - 8) << 12; 4884 4885 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL, 4886 PCI_EXP_DEVCTL_READRQ, v); 4887 } 4888 EXPORT_SYMBOL(pcie_set_readrq); 4889 4890 /** 4891 * pcie_get_mps - get PCI Express maximum payload size 4892 * @dev: PCI device to query 4893 * 4894 * Returns maximum payload size in bytes 4895 */ 4896 int pcie_get_mps(struct pci_dev *dev) 4897 { 4898 u16 ctl; 4899 4900 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl); 4901 4902 return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5); 4903 } 4904 EXPORT_SYMBOL(pcie_get_mps); 4905 4906 /** 4907 * pcie_set_mps - set PCI Express maximum payload size 4908 * @dev: PCI device to query 4909 * @mps: maximum payload size in bytes 4910 * valid values are 128, 256, 512, 1024, 2048, 4096 4911 * 4912 * If possible sets maximum payload size 4913 */ 4914 int pcie_set_mps(struct pci_dev *dev, int mps) 4915 { 4916 u16 v; 4917 4918 if (mps < 128 || mps > 4096 || !is_power_of_2(mps)) 4919 return -EINVAL; 4920 4921 v = ffs(mps) - 8; 4922 if (v > dev->pcie_mpss) 4923 return -EINVAL; 4924 v <<= 5; 4925 4926 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL, 4927 PCI_EXP_DEVCTL_PAYLOAD, v); 4928 } 4929 EXPORT_SYMBOL(pcie_set_mps); 4930 4931 /** 4932 * pcie_get_minimum_link - determine minimum link settings of a PCI device 4933 * @dev: PCI device to query 4934 * @speed: storage for minimum speed 4935 * @width: storage for minimum width 4936 * 4937 * This function will walk up the PCI device chain and determine the minimum 4938 * link width and speed of the device. 4939 */ 4940 int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed, 4941 enum pcie_link_width *width) 4942 { 4943 int ret; 4944 4945 *speed = PCI_SPEED_UNKNOWN; 4946 *width = PCIE_LNK_WIDTH_UNKNOWN; 4947 4948 while (dev) { 4949 u16 lnksta; 4950 enum pci_bus_speed next_speed; 4951 enum pcie_link_width next_width; 4952 4953 ret = pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta); 4954 if (ret) 4955 return ret; 4956 4957 next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS]; 4958 next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >> 4959 PCI_EXP_LNKSTA_NLW_SHIFT; 4960 4961 if (next_speed < *speed) 4962 *speed = next_speed; 4963 4964 if (next_width < *width) 4965 *width = next_width; 4966 4967 dev = dev->bus->self; 4968 } 4969 4970 return 0; 4971 } 4972 EXPORT_SYMBOL(pcie_get_minimum_link); 4973 4974 /** 4975 * pci_select_bars - Make BAR mask from the type of resource 4976 * @dev: the PCI device for which BAR mask is made 4977 * @flags: resource type mask to be selected 4978 * 4979 * This helper routine makes bar mask from the type of resource. 4980 */ 4981 int pci_select_bars(struct pci_dev *dev, unsigned long flags) 4982 { 4983 int i, bars = 0; 4984 for (i = 0; i < PCI_NUM_RESOURCES; i++) 4985 if (pci_resource_flags(dev, i) & flags) 4986 bars |= (1 << i); 4987 return bars; 4988 } 4989 EXPORT_SYMBOL(pci_select_bars); 4990 4991 /* Some architectures require additional programming to enable VGA */ 4992 static arch_set_vga_state_t arch_set_vga_state; 4993 4994 void __init pci_register_set_vga_state(arch_set_vga_state_t func) 4995 { 4996 arch_set_vga_state = func; /* NULL disables */ 4997 } 4998 4999 static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode, 5000 unsigned int command_bits, u32 flags) 5001 { 5002 if (arch_set_vga_state) 5003 return arch_set_vga_state(dev, decode, command_bits, 5004 flags); 5005 return 0; 5006 } 5007 5008 /** 5009 * pci_set_vga_state - set VGA decode state on device and parents if requested 5010 * @dev: the PCI device 5011 * @decode: true = enable decoding, false = disable decoding 5012 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY 5013 * @flags: traverse ancestors and change bridges 5014 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE 5015 */ 5016 int pci_set_vga_state(struct pci_dev *dev, bool decode, 5017 unsigned int command_bits, u32 flags) 5018 { 5019 struct pci_bus *bus; 5020 struct pci_dev *bridge; 5021 u16 cmd; 5022 int rc; 5023 5024 WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) && (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY))); 5025 5026 /* ARCH specific VGA enables */ 5027 rc = pci_set_vga_state_arch(dev, decode, command_bits, flags); 5028 if (rc) 5029 return rc; 5030 5031 if (flags & PCI_VGA_STATE_CHANGE_DECODES) { 5032 pci_read_config_word(dev, PCI_COMMAND, &cmd); 5033 if (decode == true) 5034 cmd |= command_bits; 5035 else 5036 cmd &= ~command_bits; 5037 pci_write_config_word(dev, PCI_COMMAND, cmd); 5038 } 5039 5040 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE)) 5041 return 0; 5042 5043 bus = dev->bus; 5044 while (bus) { 5045 bridge = bus->self; 5046 if (bridge) { 5047 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL, 5048 &cmd); 5049 if (decode == true) 5050 cmd |= PCI_BRIDGE_CTL_VGA; 5051 else 5052 cmd &= ~PCI_BRIDGE_CTL_VGA; 5053 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, 5054 cmd); 5055 } 5056 bus = bus->parent; 5057 } 5058 return 0; 5059 } 5060 5061 /** 5062 * pci_add_dma_alias - Add a DMA devfn alias for a device 5063 * @dev: the PCI device for which alias is added 5064 * @devfn: alias slot and function 5065 * 5066 * This helper encodes 8-bit devfn as bit number in dma_alias_mask. 5067 * It should be called early, preferably as PCI fixup header quirk. 5068 */ 5069 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn) 5070 { 5071 if (!dev->dma_alias_mask) 5072 dev->dma_alias_mask = kcalloc(BITS_TO_LONGS(U8_MAX), 5073 sizeof(long), GFP_KERNEL); 5074 if (!dev->dma_alias_mask) { 5075 dev_warn(&dev->dev, "Unable to allocate DMA alias mask\n"); 5076 return; 5077 } 5078 5079 set_bit(devfn, dev->dma_alias_mask); 5080 dev_info(&dev->dev, "Enabling fixed DMA alias to %02x.%d\n", 5081 PCI_SLOT(devfn), PCI_FUNC(devfn)); 5082 } 5083 5084 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2) 5085 { 5086 return (dev1->dma_alias_mask && 5087 test_bit(dev2->devfn, dev1->dma_alias_mask)) || 5088 (dev2->dma_alias_mask && 5089 test_bit(dev1->devfn, dev2->dma_alias_mask)); 5090 } 5091 5092 bool pci_device_is_present(struct pci_dev *pdev) 5093 { 5094 u32 v; 5095 5096 if (pci_dev_is_disconnected(pdev)) 5097 return false; 5098 return pci_bus_read_dev_vendor_id(pdev->bus, pdev->devfn, &v, 0); 5099 } 5100 EXPORT_SYMBOL_GPL(pci_device_is_present); 5101 5102 void pci_ignore_hotplug(struct pci_dev *dev) 5103 { 5104 struct pci_dev *bridge = dev->bus->self; 5105 5106 dev->ignore_hotplug = 1; 5107 /* Propagate the "ignore hotplug" setting to the parent bridge. */ 5108 if (bridge) 5109 bridge->ignore_hotplug = 1; 5110 } 5111 EXPORT_SYMBOL_GPL(pci_ignore_hotplug); 5112 5113 resource_size_t __weak pcibios_default_alignment(void) 5114 { 5115 return 0; 5116 } 5117 5118 #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE 5119 static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0}; 5120 static DEFINE_SPINLOCK(resource_alignment_lock); 5121 5122 /** 5123 * pci_specified_resource_alignment - get resource alignment specified by user. 5124 * @dev: the PCI device to get 5125 * @resize: whether or not to change resources' size when reassigning alignment 5126 * 5127 * RETURNS: Resource alignment if it is specified. 5128 * Zero if it is not specified. 5129 */ 5130 static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev, 5131 bool *resize) 5132 { 5133 int seg, bus, slot, func, align_order, count; 5134 unsigned short vendor, device, subsystem_vendor, subsystem_device; 5135 resource_size_t align = pcibios_default_alignment(); 5136 char *p; 5137 5138 spin_lock(&resource_alignment_lock); 5139 p = resource_alignment_param; 5140 if (!*p && !align) 5141 goto out; 5142 if (pci_has_flag(PCI_PROBE_ONLY)) { 5143 align = 0; 5144 pr_info_once("PCI: Ignoring requested alignments (PCI_PROBE_ONLY)\n"); 5145 goto out; 5146 } 5147 5148 while (*p) { 5149 count = 0; 5150 if (sscanf(p, "%d%n", &align_order, &count) == 1 && 5151 p[count] == '@') { 5152 p += count + 1; 5153 } else { 5154 align_order = -1; 5155 } 5156 if (strncmp(p, "pci:", 4) == 0) { 5157 /* PCI vendor/device (subvendor/subdevice) ids are specified */ 5158 p += 4; 5159 if (sscanf(p, "%hx:%hx:%hx:%hx%n", 5160 &vendor, &device, &subsystem_vendor, &subsystem_device, &count) != 4) { 5161 if (sscanf(p, "%hx:%hx%n", &vendor, &device, &count) != 2) { 5162 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: pci:%s\n", 5163 p); 5164 break; 5165 } 5166 subsystem_vendor = subsystem_device = 0; 5167 } 5168 p += count; 5169 if ((!vendor || (vendor == dev->vendor)) && 5170 (!device || (device == dev->device)) && 5171 (!subsystem_vendor || (subsystem_vendor == dev->subsystem_vendor)) && 5172 (!subsystem_device || (subsystem_device == dev->subsystem_device))) { 5173 *resize = true; 5174 if (align_order == -1) 5175 align = PAGE_SIZE; 5176 else 5177 align = 1 << align_order; 5178 /* Found */ 5179 break; 5180 } 5181 } 5182 else { 5183 if (sscanf(p, "%x:%x:%x.%x%n", 5184 &seg, &bus, &slot, &func, &count) != 4) { 5185 seg = 0; 5186 if (sscanf(p, "%x:%x.%x%n", 5187 &bus, &slot, &func, &count) != 3) { 5188 /* Invalid format */ 5189 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n", 5190 p); 5191 break; 5192 } 5193 } 5194 p += count; 5195 if (seg == pci_domain_nr(dev->bus) && 5196 bus == dev->bus->number && 5197 slot == PCI_SLOT(dev->devfn) && 5198 func == PCI_FUNC(dev->devfn)) { 5199 *resize = true; 5200 if (align_order == -1) 5201 align = PAGE_SIZE; 5202 else 5203 align = 1 << align_order; 5204 /* Found */ 5205 break; 5206 } 5207 } 5208 if (*p != ';' && *p != ',') { 5209 /* End of param or invalid format */ 5210 break; 5211 } 5212 p++; 5213 } 5214 out: 5215 spin_unlock(&resource_alignment_lock); 5216 return align; 5217 } 5218 5219 static void pci_request_resource_alignment(struct pci_dev *dev, int bar, 5220 resource_size_t align, bool resize) 5221 { 5222 struct resource *r = &dev->resource[bar]; 5223 resource_size_t size; 5224 5225 if (!(r->flags & IORESOURCE_MEM)) 5226 return; 5227 5228 if (r->flags & IORESOURCE_PCI_FIXED) { 5229 dev_info(&dev->dev, "BAR%d %pR: ignoring requested alignment %#llx\n", 5230 bar, r, (unsigned long long)align); 5231 return; 5232 } 5233 5234 size = resource_size(r); 5235 if (size >= align) 5236 return; 5237 5238 /* 5239 * Increase the alignment of the resource. There are two ways we 5240 * can do this: 5241 * 5242 * 1) Increase the size of the resource. BARs are aligned on their 5243 * size, so when we reallocate space for this resource, we'll 5244 * allocate it with the larger alignment. This also prevents 5245 * assignment of any other BARs inside the alignment region, so 5246 * if we're requesting page alignment, this means no other BARs 5247 * will share the page. 5248 * 5249 * The disadvantage is that this makes the resource larger than 5250 * the hardware BAR, which may break drivers that compute things 5251 * based on the resource size, e.g., to find registers at a 5252 * fixed offset before the end of the BAR. 5253 * 5254 * 2) Retain the resource size, but use IORESOURCE_STARTALIGN and 5255 * set r->start to the desired alignment. By itself this 5256 * doesn't prevent other BARs being put inside the alignment 5257 * region, but if we realign *every* resource of every device in 5258 * the system, none of them will share an alignment region. 5259 * 5260 * When the user has requested alignment for only some devices via 5261 * the "pci=resource_alignment" argument, "resize" is true and we 5262 * use the first method. Otherwise we assume we're aligning all 5263 * devices and we use the second. 5264 */ 5265 5266 dev_info(&dev->dev, "BAR%d %pR: requesting alignment to %#llx\n", 5267 bar, r, (unsigned long long)align); 5268 5269 if (resize) { 5270 r->start = 0; 5271 r->end = align - 1; 5272 } else { 5273 r->flags &= ~IORESOURCE_SIZEALIGN; 5274 r->flags |= IORESOURCE_STARTALIGN; 5275 r->start = align; 5276 r->end = r->start + size - 1; 5277 } 5278 r->flags |= IORESOURCE_UNSET; 5279 } 5280 5281 /* 5282 * This function disables memory decoding and releases memory resources 5283 * of the device specified by kernel's boot parameter 'pci=resource_alignment='. 5284 * It also rounds up size to specified alignment. 5285 * Later on, the kernel will assign page-aligned memory resource back 5286 * to the device. 5287 */ 5288 void pci_reassigndev_resource_alignment(struct pci_dev *dev) 5289 { 5290 int i; 5291 struct resource *r; 5292 resource_size_t align; 5293 u16 command; 5294 bool resize = false; 5295 5296 /* 5297 * VF BARs are read-only zero according to SR-IOV spec r1.1, sec 5298 * 3.4.1.11. Their resources are allocated from the space 5299 * described by the VF BARx register in the PF's SR-IOV capability. 5300 * We can't influence their alignment here. 5301 */ 5302 if (dev->is_virtfn) 5303 return; 5304 5305 /* check if specified PCI is target device to reassign */ 5306 align = pci_specified_resource_alignment(dev, &resize); 5307 if (!align) 5308 return; 5309 5310 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL && 5311 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) { 5312 dev_warn(&dev->dev, 5313 "Can't reassign resources to host bridge.\n"); 5314 return; 5315 } 5316 5317 dev_info(&dev->dev, 5318 "Disabling memory decoding and releasing memory resources.\n"); 5319 pci_read_config_word(dev, PCI_COMMAND, &command); 5320 command &= ~PCI_COMMAND_MEMORY; 5321 pci_write_config_word(dev, PCI_COMMAND, command); 5322 5323 for (i = 0; i <= PCI_ROM_RESOURCE; i++) 5324 pci_request_resource_alignment(dev, i, align, resize); 5325 5326 /* 5327 * Need to disable bridge's resource window, 5328 * to enable the kernel to reassign new resource 5329 * window later on. 5330 */ 5331 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE && 5332 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { 5333 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) { 5334 r = &dev->resource[i]; 5335 if (!(r->flags & IORESOURCE_MEM)) 5336 continue; 5337 r->flags |= IORESOURCE_UNSET; 5338 r->end = resource_size(r) - 1; 5339 r->start = 0; 5340 } 5341 pci_disable_bridge_window(dev); 5342 } 5343 } 5344 5345 static ssize_t pci_set_resource_alignment_param(const char *buf, size_t count) 5346 { 5347 if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1) 5348 count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1; 5349 spin_lock(&resource_alignment_lock); 5350 strncpy(resource_alignment_param, buf, count); 5351 resource_alignment_param[count] = '\0'; 5352 spin_unlock(&resource_alignment_lock); 5353 return count; 5354 } 5355 5356 static ssize_t pci_get_resource_alignment_param(char *buf, size_t size) 5357 { 5358 size_t count; 5359 spin_lock(&resource_alignment_lock); 5360 count = snprintf(buf, size, "%s", resource_alignment_param); 5361 spin_unlock(&resource_alignment_lock); 5362 return count; 5363 } 5364 5365 static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf) 5366 { 5367 return pci_get_resource_alignment_param(buf, PAGE_SIZE); 5368 } 5369 5370 static ssize_t pci_resource_alignment_store(struct bus_type *bus, 5371 const char *buf, size_t count) 5372 { 5373 return pci_set_resource_alignment_param(buf, count); 5374 } 5375 5376 static BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show, 5377 pci_resource_alignment_store); 5378 5379 static int __init pci_resource_alignment_sysfs_init(void) 5380 { 5381 return bus_create_file(&pci_bus_type, 5382 &bus_attr_resource_alignment); 5383 } 5384 late_initcall(pci_resource_alignment_sysfs_init); 5385 5386 static void pci_no_domains(void) 5387 { 5388 #ifdef CONFIG_PCI_DOMAINS 5389 pci_domains_supported = 0; 5390 #endif 5391 } 5392 5393 #ifdef CONFIG_PCI_DOMAINS 5394 static atomic_t __domain_nr = ATOMIC_INIT(-1); 5395 5396 int pci_get_new_domain_nr(void) 5397 { 5398 return atomic_inc_return(&__domain_nr); 5399 } 5400 5401 #ifdef CONFIG_PCI_DOMAINS_GENERIC 5402 static int of_pci_bus_find_domain_nr(struct device *parent) 5403 { 5404 static int use_dt_domains = -1; 5405 int domain = -1; 5406 5407 if (parent) 5408 domain = of_get_pci_domain_nr(parent->of_node); 5409 /* 5410 * Check DT domain and use_dt_domains values. 5411 * 5412 * If DT domain property is valid (domain >= 0) and 5413 * use_dt_domains != 0, the DT assignment is valid since this means 5414 * we have not previously allocated a domain number by using 5415 * pci_get_new_domain_nr(); we should also update use_dt_domains to 5416 * 1, to indicate that we have just assigned a domain number from 5417 * DT. 5418 * 5419 * If DT domain property value is not valid (ie domain < 0), and we 5420 * have not previously assigned a domain number from DT 5421 * (use_dt_domains != 1) we should assign a domain number by 5422 * using the: 5423 * 5424 * pci_get_new_domain_nr() 5425 * 5426 * API and update the use_dt_domains value to keep track of method we 5427 * are using to assign domain numbers (use_dt_domains = 0). 5428 * 5429 * All other combinations imply we have a platform that is trying 5430 * to mix domain numbers obtained from DT and pci_get_new_domain_nr(), 5431 * which is a recipe for domain mishandling and it is prevented by 5432 * invalidating the domain value (domain = -1) and printing a 5433 * corresponding error. 5434 */ 5435 if (domain >= 0 && use_dt_domains) { 5436 use_dt_domains = 1; 5437 } else if (domain < 0 && use_dt_domains != 1) { 5438 use_dt_domains = 0; 5439 domain = pci_get_new_domain_nr(); 5440 } else { 5441 dev_err(parent, "Node %pOF has inconsistent \"linux,pci-domain\" property in DT\n", 5442 parent->of_node); 5443 domain = -1; 5444 } 5445 5446 return domain; 5447 } 5448 5449 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent) 5450 { 5451 return acpi_disabled ? of_pci_bus_find_domain_nr(parent) : 5452 acpi_pci_bus_find_domain_nr(bus); 5453 } 5454 #endif 5455 #endif 5456 5457 /** 5458 * pci_ext_cfg_avail - can we access extended PCI config space? 5459 * 5460 * Returns 1 if we can access PCI extended config space (offsets 5461 * greater than 0xff). This is the default implementation. Architecture 5462 * implementations can override this. 5463 */ 5464 int __weak pci_ext_cfg_avail(void) 5465 { 5466 return 1; 5467 } 5468 5469 void __weak pci_fixup_cardbus(struct pci_bus *bus) 5470 { 5471 } 5472 EXPORT_SYMBOL(pci_fixup_cardbus); 5473 5474 static int __init pci_setup(char *str) 5475 { 5476 while (str) { 5477 char *k = strchr(str, ','); 5478 if (k) 5479 *k++ = 0; 5480 if (*str && (str = pcibios_setup(str)) && *str) { 5481 if (!strcmp(str, "nomsi")) { 5482 pci_no_msi(); 5483 } else if (!strcmp(str, "noaer")) { 5484 pci_no_aer(); 5485 } else if (!strncmp(str, "realloc=", 8)) { 5486 pci_realloc_get_opt(str + 8); 5487 } else if (!strncmp(str, "realloc", 7)) { 5488 pci_realloc_get_opt("on"); 5489 } else if (!strcmp(str, "nodomains")) { 5490 pci_no_domains(); 5491 } else if (!strncmp(str, "noari", 5)) { 5492 pcie_ari_disabled = true; 5493 } else if (!strncmp(str, "cbiosize=", 9)) { 5494 pci_cardbus_io_size = memparse(str + 9, &str); 5495 } else if (!strncmp(str, "cbmemsize=", 10)) { 5496 pci_cardbus_mem_size = memparse(str + 10, &str); 5497 } else if (!strncmp(str, "resource_alignment=", 19)) { 5498 pci_set_resource_alignment_param(str + 19, 5499 strlen(str + 19)); 5500 } else if (!strncmp(str, "ecrc=", 5)) { 5501 pcie_ecrc_get_policy(str + 5); 5502 } else if (!strncmp(str, "hpiosize=", 9)) { 5503 pci_hotplug_io_size = memparse(str + 9, &str); 5504 } else if (!strncmp(str, "hpmemsize=", 10)) { 5505 pci_hotplug_mem_size = memparse(str + 10, &str); 5506 } else if (!strncmp(str, "hpbussize=", 10)) { 5507 pci_hotplug_bus_size = 5508 simple_strtoul(str + 10, &str, 0); 5509 if (pci_hotplug_bus_size > 0xff) 5510 pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE; 5511 } else if (!strncmp(str, "pcie_bus_tune_off", 17)) { 5512 pcie_bus_config = PCIE_BUS_TUNE_OFF; 5513 } else if (!strncmp(str, "pcie_bus_safe", 13)) { 5514 pcie_bus_config = PCIE_BUS_SAFE; 5515 } else if (!strncmp(str, "pcie_bus_perf", 13)) { 5516 pcie_bus_config = PCIE_BUS_PERFORMANCE; 5517 } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) { 5518 pcie_bus_config = PCIE_BUS_PEER2PEER; 5519 } else if (!strncmp(str, "pcie_scan_all", 13)) { 5520 pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS); 5521 } else { 5522 printk(KERN_ERR "PCI: Unknown option `%s'\n", 5523 str); 5524 } 5525 } 5526 str = k; 5527 } 5528 return 0; 5529 } 5530 early_param("pci", pci_setup); 5531