1 /* 2 * $Id: pci.c,v 1.91 1999/01/21 13:34:01 davem Exp $ 3 * 4 * PCI Bus Services, see include/linux/pci.h for further explanation. 5 * 6 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter, 7 * David Mosberger-Tang 8 * 9 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz> 10 */ 11 12 #include <linux/kernel.h> 13 #include <linux/delay.h> 14 #include <linux/init.h> 15 #include <linux/pci.h> 16 #include <linux/pm.h> 17 #include <linux/module.h> 18 #include <linux/spinlock.h> 19 #include <linux/string.h> 20 #include <linux/log2.h> 21 #include <linux/aspm.h> 22 #include <asm/dma.h> /* isa_dma_bridge_buggy */ 23 #include "pci.h" 24 25 unsigned int pci_pm_d3_delay = 10; 26 27 #ifdef CONFIG_PCI_DOMAINS 28 int pci_domains_supported = 1; 29 #endif 30 31 #define DEFAULT_CARDBUS_IO_SIZE (256) 32 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024) 33 /* pci=cbmemsize=nnM,cbiosize=nn can override this */ 34 unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE; 35 unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE; 36 37 /** 38 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children 39 * @bus: pointer to PCI bus structure to search 40 * 41 * Given a PCI bus, returns the highest PCI bus number present in the set 42 * including the given PCI bus and its list of child PCI buses. 43 */ 44 unsigned char pci_bus_max_busnr(struct pci_bus* bus) 45 { 46 struct list_head *tmp; 47 unsigned char max, n; 48 49 max = bus->subordinate; 50 list_for_each(tmp, &bus->children) { 51 n = pci_bus_max_busnr(pci_bus_b(tmp)); 52 if(n > max) 53 max = n; 54 } 55 return max; 56 } 57 EXPORT_SYMBOL_GPL(pci_bus_max_busnr); 58 59 #if 0 60 /** 61 * pci_max_busnr - returns maximum PCI bus number 62 * 63 * Returns the highest PCI bus number present in the system global list of 64 * PCI buses. 65 */ 66 unsigned char __devinit 67 pci_max_busnr(void) 68 { 69 struct pci_bus *bus = NULL; 70 unsigned char max, n; 71 72 max = 0; 73 while ((bus = pci_find_next_bus(bus)) != NULL) { 74 n = pci_bus_max_busnr(bus); 75 if(n > max) 76 max = n; 77 } 78 return max; 79 } 80 81 #endif /* 0 */ 82 83 #define PCI_FIND_CAP_TTL 48 84 85 static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn, 86 u8 pos, int cap, int *ttl) 87 { 88 u8 id; 89 90 while ((*ttl)--) { 91 pci_bus_read_config_byte(bus, devfn, pos, &pos); 92 if (pos < 0x40) 93 break; 94 pos &= ~3; 95 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID, 96 &id); 97 if (id == 0xff) 98 break; 99 if (id == cap) 100 return pos; 101 pos += PCI_CAP_LIST_NEXT; 102 } 103 return 0; 104 } 105 106 static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn, 107 u8 pos, int cap) 108 { 109 int ttl = PCI_FIND_CAP_TTL; 110 111 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl); 112 } 113 114 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap) 115 { 116 return __pci_find_next_cap(dev->bus, dev->devfn, 117 pos + PCI_CAP_LIST_NEXT, cap); 118 } 119 EXPORT_SYMBOL_GPL(pci_find_next_capability); 120 121 static int __pci_bus_find_cap_start(struct pci_bus *bus, 122 unsigned int devfn, u8 hdr_type) 123 { 124 u16 status; 125 126 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status); 127 if (!(status & PCI_STATUS_CAP_LIST)) 128 return 0; 129 130 switch (hdr_type) { 131 case PCI_HEADER_TYPE_NORMAL: 132 case PCI_HEADER_TYPE_BRIDGE: 133 return PCI_CAPABILITY_LIST; 134 case PCI_HEADER_TYPE_CARDBUS: 135 return PCI_CB_CAPABILITY_LIST; 136 default: 137 return 0; 138 } 139 140 return 0; 141 } 142 143 /** 144 * pci_find_capability - query for devices' capabilities 145 * @dev: PCI device to query 146 * @cap: capability code 147 * 148 * Tell if a device supports a given PCI capability. 149 * Returns the address of the requested capability structure within the 150 * device's PCI configuration space or 0 in case the device does not 151 * support it. Possible values for @cap: 152 * 153 * %PCI_CAP_ID_PM Power Management 154 * %PCI_CAP_ID_AGP Accelerated Graphics Port 155 * %PCI_CAP_ID_VPD Vital Product Data 156 * %PCI_CAP_ID_SLOTID Slot Identification 157 * %PCI_CAP_ID_MSI Message Signalled Interrupts 158 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap 159 * %PCI_CAP_ID_PCIX PCI-X 160 * %PCI_CAP_ID_EXP PCI Express 161 */ 162 int pci_find_capability(struct pci_dev *dev, int cap) 163 { 164 int pos; 165 166 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); 167 if (pos) 168 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap); 169 170 return pos; 171 } 172 173 /** 174 * pci_bus_find_capability - query for devices' capabilities 175 * @bus: the PCI bus to query 176 * @devfn: PCI device to query 177 * @cap: capability code 178 * 179 * Like pci_find_capability() but works for pci devices that do not have a 180 * pci_dev structure set up yet. 181 * 182 * Returns the address of the requested capability structure within the 183 * device's PCI configuration space or 0 in case the device does not 184 * support it. 185 */ 186 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap) 187 { 188 int pos; 189 u8 hdr_type; 190 191 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type); 192 193 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f); 194 if (pos) 195 pos = __pci_find_next_cap(bus, devfn, pos, cap); 196 197 return pos; 198 } 199 200 /** 201 * pci_find_ext_capability - Find an extended capability 202 * @dev: PCI device to query 203 * @cap: capability code 204 * 205 * Returns the address of the requested extended capability structure 206 * within the device's PCI configuration space or 0 if the device does 207 * not support it. Possible values for @cap: 208 * 209 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting 210 * %PCI_EXT_CAP_ID_VC Virtual Channel 211 * %PCI_EXT_CAP_ID_DSN Device Serial Number 212 * %PCI_EXT_CAP_ID_PWR Power Budgeting 213 */ 214 int pci_find_ext_capability(struct pci_dev *dev, int cap) 215 { 216 u32 header; 217 int ttl = 480; /* 3840 bytes, minimum 8 bytes per capability */ 218 int pos = 0x100; 219 220 if (dev->cfg_size <= 256) 221 return 0; 222 223 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) 224 return 0; 225 226 /* 227 * If we have no capabilities, this is indicated by cap ID, 228 * cap version and next pointer all being 0. 229 */ 230 if (header == 0) 231 return 0; 232 233 while (ttl-- > 0) { 234 if (PCI_EXT_CAP_ID(header) == cap) 235 return pos; 236 237 pos = PCI_EXT_CAP_NEXT(header); 238 if (pos < 0x100) 239 break; 240 241 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) 242 break; 243 } 244 245 return 0; 246 } 247 EXPORT_SYMBOL_GPL(pci_find_ext_capability); 248 249 static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap) 250 { 251 int rc, ttl = PCI_FIND_CAP_TTL; 252 u8 cap, mask; 253 254 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST) 255 mask = HT_3BIT_CAP_MASK; 256 else 257 mask = HT_5BIT_CAP_MASK; 258 259 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos, 260 PCI_CAP_ID_HT, &ttl); 261 while (pos) { 262 rc = pci_read_config_byte(dev, pos + 3, &cap); 263 if (rc != PCIBIOS_SUCCESSFUL) 264 return 0; 265 266 if ((cap & mask) == ht_cap) 267 return pos; 268 269 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, 270 pos + PCI_CAP_LIST_NEXT, 271 PCI_CAP_ID_HT, &ttl); 272 } 273 274 return 0; 275 } 276 /** 277 * pci_find_next_ht_capability - query a device's Hypertransport capabilities 278 * @dev: PCI device to query 279 * @pos: Position from which to continue searching 280 * @ht_cap: Hypertransport capability code 281 * 282 * To be used in conjunction with pci_find_ht_capability() to search for 283 * all capabilities matching @ht_cap. @pos should always be a value returned 284 * from pci_find_ht_capability(). 285 * 286 * NB. To be 100% safe against broken PCI devices, the caller should take 287 * steps to avoid an infinite loop. 288 */ 289 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap) 290 { 291 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap); 292 } 293 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability); 294 295 /** 296 * pci_find_ht_capability - query a device's Hypertransport capabilities 297 * @dev: PCI device to query 298 * @ht_cap: Hypertransport capability code 299 * 300 * Tell if a device supports a given Hypertransport capability. 301 * Returns an address within the device's PCI configuration space 302 * or 0 in case the device does not support the request capability. 303 * The address points to the PCI capability, of type PCI_CAP_ID_HT, 304 * which has a Hypertransport capability matching @ht_cap. 305 */ 306 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap) 307 { 308 int pos; 309 310 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); 311 if (pos) 312 pos = __pci_find_next_ht_cap(dev, pos, ht_cap); 313 314 return pos; 315 } 316 EXPORT_SYMBOL_GPL(pci_find_ht_capability); 317 318 void pcie_wait_pending_transaction(struct pci_dev *dev) 319 { 320 int pos; 321 u16 reg16; 322 323 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 324 if (!pos) 325 return; 326 while (1) { 327 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, ®16); 328 if (!(reg16 & PCI_EXP_DEVSTA_TRPND)) 329 break; 330 cpu_relax(); 331 } 332 333 } 334 EXPORT_SYMBOL_GPL(pcie_wait_pending_transaction); 335 336 /** 337 * pci_find_parent_resource - return resource region of parent bus of given region 338 * @dev: PCI device structure contains resources to be searched 339 * @res: child resource record for which parent is sought 340 * 341 * For given resource region of given device, return the resource 342 * region of parent bus the given region is contained in or where 343 * it should be allocated from. 344 */ 345 struct resource * 346 pci_find_parent_resource(const struct pci_dev *dev, struct resource *res) 347 { 348 const struct pci_bus *bus = dev->bus; 349 int i; 350 struct resource *best = NULL; 351 352 for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++) { 353 struct resource *r = bus->resource[i]; 354 if (!r) 355 continue; 356 if (res->start && !(res->start >= r->start && res->end <= r->end)) 357 continue; /* Not contained */ 358 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM)) 359 continue; /* Wrong type */ 360 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH)) 361 return r; /* Exact match */ 362 if ((res->flags & IORESOURCE_PREFETCH) && !(r->flags & IORESOURCE_PREFETCH)) 363 best = r; /* Approximating prefetchable by non-prefetchable */ 364 } 365 return best; 366 } 367 368 /** 369 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up) 370 * @dev: PCI device to have its BARs restored 371 * 372 * Restore the BAR values for a given device, so as to make it 373 * accessible by its driver. 374 */ 375 static void 376 pci_restore_bars(struct pci_dev *dev) 377 { 378 int i, numres; 379 380 switch (dev->hdr_type) { 381 case PCI_HEADER_TYPE_NORMAL: 382 numres = 6; 383 break; 384 case PCI_HEADER_TYPE_BRIDGE: 385 numres = 2; 386 break; 387 case PCI_HEADER_TYPE_CARDBUS: 388 numres = 1; 389 break; 390 default: 391 /* Should never get here, but just in case... */ 392 return; 393 } 394 395 for (i = 0; i < numres; i ++) 396 pci_update_resource(dev, &dev->resource[i], i); 397 } 398 399 int (*platform_pci_set_power_state)(struct pci_dev *dev, pci_power_t t); 400 401 /** 402 * pci_set_power_state - Set the power state of a PCI device 403 * @dev: PCI device to be suspended 404 * @state: PCI power state (D0, D1, D2, D3hot, D3cold) we're entering 405 * 406 * Transition a device to a new power state, using the Power Management 407 * Capabilities in the device's config space. 408 * 409 * RETURN VALUE: 410 * -EINVAL if trying to enter a lower state than we're already in. 411 * 0 if we're already in the requested state. 412 * -EIO if device does not support PCI PM. 413 * 0 if we can successfully change the power state. 414 */ 415 int 416 pci_set_power_state(struct pci_dev *dev, pci_power_t state) 417 { 418 int pm, need_restore = 0; 419 u16 pmcsr, pmc; 420 421 /* bound the state we're entering */ 422 if (state > PCI_D3hot) 423 state = PCI_D3hot; 424 425 /* 426 * If the device or the parent bridge can't support PCI PM, ignore 427 * the request if we're doing anything besides putting it into D0 428 * (which would only happen on boot). 429 */ 430 if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev)) 431 return 0; 432 433 /* find PCI PM capability in list */ 434 pm = pci_find_capability(dev, PCI_CAP_ID_PM); 435 436 /* abort if the device doesn't support PM capabilities */ 437 if (!pm) 438 return -EIO; 439 440 /* Validate current state: 441 * Can enter D0 from any state, but if we can only go deeper 442 * to sleep if we're already in a low power state 443 */ 444 if (state != PCI_D0 && dev->current_state > state) { 445 printk(KERN_ERR "%s(): %s: state=%d, current state=%d\n", 446 __FUNCTION__, pci_name(dev), state, dev->current_state); 447 return -EINVAL; 448 } else if (dev->current_state == state) 449 return 0; /* we're already there */ 450 451 452 pci_read_config_word(dev,pm + PCI_PM_PMC,&pmc); 453 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) { 454 printk(KERN_DEBUG 455 "PCI: %s has unsupported PM cap regs version (%u)\n", 456 pci_name(dev), pmc & PCI_PM_CAP_VER_MASK); 457 return -EIO; 458 } 459 460 /* check if this device supports the desired state */ 461 if (state == PCI_D1 && !(pmc & PCI_PM_CAP_D1)) 462 return -EIO; 463 else if (state == PCI_D2 && !(pmc & PCI_PM_CAP_D2)) 464 return -EIO; 465 466 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr); 467 468 /* If we're (effectively) in D3, force entire word to 0. 469 * This doesn't affect PME_Status, disables PME_En, and 470 * sets PowerState to 0. 471 */ 472 switch (dev->current_state) { 473 case PCI_D0: 474 case PCI_D1: 475 case PCI_D2: 476 pmcsr &= ~PCI_PM_CTRL_STATE_MASK; 477 pmcsr |= state; 478 break; 479 case PCI_UNKNOWN: /* Boot-up */ 480 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot 481 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET)) 482 need_restore = 1; 483 /* Fall-through: force to D0 */ 484 default: 485 pmcsr = 0; 486 break; 487 } 488 489 /* enter specified state */ 490 pci_write_config_word(dev, pm + PCI_PM_CTRL, pmcsr); 491 492 /* Mandatory power management transition delays */ 493 /* see PCI PM 1.1 5.6.1 table 18 */ 494 if (state == PCI_D3hot || dev->current_state == PCI_D3hot) 495 msleep(pci_pm_d3_delay); 496 else if (state == PCI_D2 || dev->current_state == PCI_D2) 497 udelay(200); 498 499 /* 500 * Give firmware a chance to be called, such as ACPI _PRx, _PSx 501 * Firmware method after native method ? 502 */ 503 if (platform_pci_set_power_state) 504 platform_pci_set_power_state(dev, state); 505 506 dev->current_state = state; 507 508 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT 509 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning 510 * from D3hot to D0 _may_ perform an internal reset, thereby 511 * going to "D0 Uninitialized" rather than "D0 Initialized". 512 * For example, at least some versions of the 3c905B and the 513 * 3c556B exhibit this behaviour. 514 * 515 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave 516 * devices in a D3hot state at boot. Consequently, we need to 517 * restore at least the BARs so that the device will be 518 * accessible to its driver. 519 */ 520 if (need_restore) 521 pci_restore_bars(dev); 522 523 if (dev->bus->self) 524 pcie_aspm_pm_state_change(dev->bus->self); 525 526 return 0; 527 } 528 529 pci_power_t (*platform_pci_choose_state)(struct pci_dev *dev, pm_message_t state); 530 531 /** 532 * pci_choose_state - Choose the power state of a PCI device 533 * @dev: PCI device to be suspended 534 * @state: target sleep state for the whole system. This is the value 535 * that is passed to suspend() function. 536 * 537 * Returns PCI power state suitable for given device and given system 538 * message. 539 */ 540 541 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state) 542 { 543 pci_power_t ret; 544 545 if (!pci_find_capability(dev, PCI_CAP_ID_PM)) 546 return PCI_D0; 547 548 if (platform_pci_choose_state) { 549 ret = platform_pci_choose_state(dev, state); 550 if (ret != PCI_POWER_ERROR) 551 return ret; 552 } 553 554 switch (state.event) { 555 case PM_EVENT_ON: 556 return PCI_D0; 557 case PM_EVENT_FREEZE: 558 case PM_EVENT_PRETHAW: 559 /* REVISIT both freeze and pre-thaw "should" use D0 */ 560 case PM_EVENT_SUSPEND: 561 return PCI_D3hot; 562 default: 563 printk("Unrecognized suspend event %d\n", state.event); 564 BUG(); 565 } 566 return PCI_D0; 567 } 568 569 EXPORT_SYMBOL(pci_choose_state); 570 571 static int pci_save_pcie_state(struct pci_dev *dev) 572 { 573 int pos, i = 0; 574 struct pci_cap_saved_state *save_state; 575 u16 *cap; 576 int found = 0; 577 578 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 579 if (pos <= 0) 580 return 0; 581 582 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); 583 if (!save_state) 584 save_state = kzalloc(sizeof(*save_state) + sizeof(u16) * 4, GFP_KERNEL); 585 else 586 found = 1; 587 if (!save_state) { 588 dev_err(&dev->dev, "Out of memory in pci_save_pcie_state\n"); 589 return -ENOMEM; 590 } 591 cap = (u16 *)&save_state->data[0]; 592 593 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]); 594 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]); 595 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]); 596 pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]); 597 save_state->cap_nr = PCI_CAP_ID_EXP; 598 if (!found) 599 pci_add_saved_cap(dev, save_state); 600 return 0; 601 } 602 603 static void pci_restore_pcie_state(struct pci_dev *dev) 604 { 605 int i = 0, pos; 606 struct pci_cap_saved_state *save_state; 607 u16 *cap; 608 609 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); 610 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 611 if (!save_state || pos <= 0) 612 return; 613 cap = (u16 *)&save_state->data[0]; 614 615 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]); 616 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]); 617 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]); 618 pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]); 619 } 620 621 622 static int pci_save_pcix_state(struct pci_dev *dev) 623 { 624 int pos, i = 0; 625 struct pci_cap_saved_state *save_state; 626 u16 *cap; 627 int found = 0; 628 629 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); 630 if (pos <= 0) 631 return 0; 632 633 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); 634 if (!save_state) 635 save_state = kzalloc(sizeof(*save_state) + sizeof(u16), GFP_KERNEL); 636 else 637 found = 1; 638 if (!save_state) { 639 dev_err(&dev->dev, "Out of memory in pci_save_pcie_state\n"); 640 return -ENOMEM; 641 } 642 cap = (u16 *)&save_state->data[0]; 643 644 pci_read_config_word(dev, pos + PCI_X_CMD, &cap[i++]); 645 save_state->cap_nr = PCI_CAP_ID_PCIX; 646 if (!found) 647 pci_add_saved_cap(dev, save_state); 648 return 0; 649 } 650 651 static void pci_restore_pcix_state(struct pci_dev *dev) 652 { 653 int i = 0, pos; 654 struct pci_cap_saved_state *save_state; 655 u16 *cap; 656 657 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); 658 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); 659 if (!save_state || pos <= 0) 660 return; 661 cap = (u16 *)&save_state->data[0]; 662 663 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]); 664 } 665 666 667 /** 668 * pci_save_state - save the PCI configuration space of a device before suspending 669 * @dev: - PCI device that we're dealing with 670 */ 671 int 672 pci_save_state(struct pci_dev *dev) 673 { 674 int i; 675 /* XXX: 100% dword access ok here? */ 676 for (i = 0; i < 16; i++) 677 pci_read_config_dword(dev, i * 4,&dev->saved_config_space[i]); 678 if ((i = pci_save_pcie_state(dev)) != 0) 679 return i; 680 if ((i = pci_save_pcix_state(dev)) != 0) 681 return i; 682 return 0; 683 } 684 685 /** 686 * pci_restore_state - Restore the saved state of a PCI device 687 * @dev: - PCI device that we're dealing with 688 */ 689 int 690 pci_restore_state(struct pci_dev *dev) 691 { 692 int i; 693 u32 val; 694 695 /* PCI Express register must be restored first */ 696 pci_restore_pcie_state(dev); 697 698 /* 699 * The Base Address register should be programmed before the command 700 * register(s) 701 */ 702 for (i = 15; i >= 0; i--) { 703 pci_read_config_dword(dev, i * 4, &val); 704 if (val != dev->saved_config_space[i]) { 705 printk(KERN_DEBUG "PM: Writing back config space on " 706 "device %s at offset %x (was %x, writing %x)\n", 707 pci_name(dev), i, 708 val, (int)dev->saved_config_space[i]); 709 pci_write_config_dword(dev,i * 4, 710 dev->saved_config_space[i]); 711 } 712 } 713 pci_restore_pcix_state(dev); 714 pci_restore_msi_state(dev); 715 716 return 0; 717 } 718 719 static int do_pci_enable_device(struct pci_dev *dev, int bars) 720 { 721 int err; 722 723 err = pci_set_power_state(dev, PCI_D0); 724 if (err < 0 && err != -EIO) 725 return err; 726 err = pcibios_enable_device(dev, bars); 727 if (err < 0) 728 return err; 729 pci_fixup_device(pci_fixup_enable, dev); 730 731 return 0; 732 } 733 734 /** 735 * pci_reenable_device - Resume abandoned device 736 * @dev: PCI device to be resumed 737 * 738 * Note this function is a backend of pci_default_resume and is not supposed 739 * to be called by normal code, write proper resume handler and use it instead. 740 */ 741 int pci_reenable_device(struct pci_dev *dev) 742 { 743 if (atomic_read(&dev->enable_cnt)) 744 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1); 745 return 0; 746 } 747 748 static int __pci_enable_device_flags(struct pci_dev *dev, 749 resource_size_t flags) 750 { 751 int err; 752 int i, bars = 0; 753 754 if (atomic_add_return(1, &dev->enable_cnt) > 1) 755 return 0; /* already enabled */ 756 757 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) 758 if (dev->resource[i].flags & flags) 759 bars |= (1 << i); 760 761 err = do_pci_enable_device(dev, bars); 762 if (err < 0) 763 atomic_dec(&dev->enable_cnt); 764 return err; 765 } 766 767 /** 768 * pci_enable_device_io - Initialize a device for use with IO space 769 * @dev: PCI device to be initialized 770 * 771 * Initialize device before it's used by a driver. Ask low-level code 772 * to enable I/O resources. Wake up the device if it was suspended. 773 * Beware, this function can fail. 774 */ 775 int pci_enable_device_io(struct pci_dev *dev) 776 { 777 return __pci_enable_device_flags(dev, IORESOURCE_IO); 778 } 779 780 /** 781 * pci_enable_device_mem - Initialize a device for use with Memory space 782 * @dev: PCI device to be initialized 783 * 784 * Initialize device before it's used by a driver. Ask low-level code 785 * to enable Memory resources. Wake up the device if it was suspended. 786 * Beware, this function can fail. 787 */ 788 int pci_enable_device_mem(struct pci_dev *dev) 789 { 790 return __pci_enable_device_flags(dev, IORESOURCE_MEM); 791 } 792 793 /** 794 * pci_enable_device - Initialize device before it's used by a driver. 795 * @dev: PCI device to be initialized 796 * 797 * Initialize device before it's used by a driver. Ask low-level code 798 * to enable I/O and memory. Wake up the device if it was suspended. 799 * Beware, this function can fail. 800 * 801 * Note we don't actually enable the device many times if we call 802 * this function repeatedly (we just increment the count). 803 */ 804 int pci_enable_device(struct pci_dev *dev) 805 { 806 return __pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO); 807 } 808 809 /* 810 * Managed PCI resources. This manages device on/off, intx/msi/msix 811 * on/off and BAR regions. pci_dev itself records msi/msix status, so 812 * there's no need to track it separately. pci_devres is initialized 813 * when a device is enabled using managed PCI device enable interface. 814 */ 815 struct pci_devres { 816 unsigned int enabled:1; 817 unsigned int pinned:1; 818 unsigned int orig_intx:1; 819 unsigned int restore_intx:1; 820 u32 region_mask; 821 }; 822 823 static void pcim_release(struct device *gendev, void *res) 824 { 825 struct pci_dev *dev = container_of(gendev, struct pci_dev, dev); 826 struct pci_devres *this = res; 827 int i; 828 829 if (dev->msi_enabled) 830 pci_disable_msi(dev); 831 if (dev->msix_enabled) 832 pci_disable_msix(dev); 833 834 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) 835 if (this->region_mask & (1 << i)) 836 pci_release_region(dev, i); 837 838 if (this->restore_intx) 839 pci_intx(dev, this->orig_intx); 840 841 if (this->enabled && !this->pinned) 842 pci_disable_device(dev); 843 } 844 845 static struct pci_devres * get_pci_dr(struct pci_dev *pdev) 846 { 847 struct pci_devres *dr, *new_dr; 848 849 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL); 850 if (dr) 851 return dr; 852 853 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL); 854 if (!new_dr) 855 return NULL; 856 return devres_get(&pdev->dev, new_dr, NULL, NULL); 857 } 858 859 static struct pci_devres * find_pci_dr(struct pci_dev *pdev) 860 { 861 if (pci_is_managed(pdev)) 862 return devres_find(&pdev->dev, pcim_release, NULL, NULL); 863 return NULL; 864 } 865 866 /** 867 * pcim_enable_device - Managed pci_enable_device() 868 * @pdev: PCI device to be initialized 869 * 870 * Managed pci_enable_device(). 871 */ 872 int pcim_enable_device(struct pci_dev *pdev) 873 { 874 struct pci_devres *dr; 875 int rc; 876 877 dr = get_pci_dr(pdev); 878 if (unlikely(!dr)) 879 return -ENOMEM; 880 if (dr->enabled) 881 return 0; 882 883 rc = pci_enable_device(pdev); 884 if (!rc) { 885 pdev->is_managed = 1; 886 dr->enabled = 1; 887 } 888 return rc; 889 } 890 891 /** 892 * pcim_pin_device - Pin managed PCI device 893 * @pdev: PCI device to pin 894 * 895 * Pin managed PCI device @pdev. Pinned device won't be disabled on 896 * driver detach. @pdev must have been enabled with 897 * pcim_enable_device(). 898 */ 899 void pcim_pin_device(struct pci_dev *pdev) 900 { 901 struct pci_devres *dr; 902 903 dr = find_pci_dr(pdev); 904 WARN_ON(!dr || !dr->enabled); 905 if (dr) 906 dr->pinned = 1; 907 } 908 909 /** 910 * pcibios_disable_device - disable arch specific PCI resources for device dev 911 * @dev: the PCI device to disable 912 * 913 * Disables architecture specific PCI resources for the device. This 914 * is the default implementation. Architecture implementations can 915 * override this. 916 */ 917 void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {} 918 919 /** 920 * pci_disable_device - Disable PCI device after use 921 * @dev: PCI device to be disabled 922 * 923 * Signal to the system that the PCI device is not in use by the system 924 * anymore. This only involves disabling PCI bus-mastering, if active. 925 * 926 * Note we don't actually disable the device until all callers of 927 * pci_device_enable() have called pci_device_disable(). 928 */ 929 void 930 pci_disable_device(struct pci_dev *dev) 931 { 932 struct pci_devres *dr; 933 u16 pci_command; 934 935 dr = find_pci_dr(dev); 936 if (dr) 937 dr->enabled = 0; 938 939 if (atomic_sub_return(1, &dev->enable_cnt) != 0) 940 return; 941 942 /* Wait for all transactions are finished before disabling the device */ 943 pcie_wait_pending_transaction(dev); 944 945 pci_read_config_word(dev, PCI_COMMAND, &pci_command); 946 if (pci_command & PCI_COMMAND_MASTER) { 947 pci_command &= ~PCI_COMMAND_MASTER; 948 pci_write_config_word(dev, PCI_COMMAND, pci_command); 949 } 950 dev->is_busmaster = 0; 951 952 pcibios_disable_device(dev); 953 } 954 955 /** 956 * pcibios_set_pcie_reset_state - set reset state for device dev 957 * @dev: the PCI-E device reset 958 * @state: Reset state to enter into 959 * 960 * 961 * Sets the PCI-E reset state for the device. This is the default 962 * implementation. Architecture implementations can override this. 963 */ 964 int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev, 965 enum pcie_reset_state state) 966 { 967 return -EINVAL; 968 } 969 970 /** 971 * pci_set_pcie_reset_state - set reset state for device dev 972 * @dev: the PCI-E device reset 973 * @state: Reset state to enter into 974 * 975 * 976 * Sets the PCI reset state for the device. 977 */ 978 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state) 979 { 980 return pcibios_set_pcie_reset_state(dev, state); 981 } 982 983 /** 984 * pci_enable_wake - enable PCI device as wakeup event source 985 * @dev: PCI device affected 986 * @state: PCI state from which device will issue wakeup events 987 * @enable: True to enable event generation; false to disable 988 * 989 * This enables the device as a wakeup event source, or disables it. 990 * When such events involves platform-specific hooks, those hooks are 991 * called automatically by this routine. 992 * 993 * Devices with legacy power management (no standard PCI PM capabilities) 994 * always require such platform hooks. Depending on the platform, devices 995 * supporting the standard PCI PME# signal may require such platform hooks; 996 * they always update bits in config space to allow PME# generation. 997 * 998 * -EIO is returned if the device can't ever be a wakeup event source. 999 * -EINVAL is returned if the device can't generate wakeup events from 1000 * the specified PCI state. Returns zero if the operation is successful. 1001 */ 1002 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable) 1003 { 1004 int pm; 1005 int status; 1006 u16 value; 1007 1008 /* Note that drivers should verify device_may_wakeup(&dev->dev) 1009 * before calling this function. Platform code should report 1010 * errors when drivers try to enable wakeup on devices that 1011 * can't issue wakeups, or on which wakeups were disabled by 1012 * userspace updating the /sys/devices.../power/wakeup file. 1013 */ 1014 1015 status = call_platform_enable_wakeup(&dev->dev, enable); 1016 1017 /* find PCI PM capability in list */ 1018 pm = pci_find_capability(dev, PCI_CAP_ID_PM); 1019 1020 /* If device doesn't support PM Capabilities, but caller wants to 1021 * disable wake events, it's a NOP. Otherwise fail unless the 1022 * platform hooks handled this legacy device already. 1023 */ 1024 if (!pm) 1025 return enable ? status : 0; 1026 1027 /* Check device's ability to generate PME# */ 1028 pci_read_config_word(dev,pm+PCI_PM_PMC,&value); 1029 1030 value &= PCI_PM_CAP_PME_MASK; 1031 value >>= ffs(PCI_PM_CAP_PME_MASK) - 1; /* First bit of mask */ 1032 1033 /* Check if it can generate PME# from requested state. */ 1034 if (!value || !(value & (1 << state))) { 1035 /* if it can't, revert what the platform hook changed, 1036 * always reporting the base "EINVAL, can't PME#" error 1037 */ 1038 if (enable) 1039 call_platform_enable_wakeup(&dev->dev, 0); 1040 return enable ? -EINVAL : 0; 1041 } 1042 1043 pci_read_config_word(dev, pm + PCI_PM_CTRL, &value); 1044 1045 /* Clear PME_Status by writing 1 to it and enable PME# */ 1046 value |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE; 1047 1048 if (!enable) 1049 value &= ~PCI_PM_CTRL_PME_ENABLE; 1050 1051 pci_write_config_word(dev, pm + PCI_PM_CTRL, value); 1052 1053 return 0; 1054 } 1055 1056 int 1057 pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge) 1058 { 1059 u8 pin; 1060 1061 pin = dev->pin; 1062 if (!pin) 1063 return -1; 1064 pin--; 1065 while (dev->bus->self) { 1066 pin = (pin + PCI_SLOT(dev->devfn)) % 4; 1067 dev = dev->bus->self; 1068 } 1069 *bridge = dev; 1070 return pin; 1071 } 1072 1073 /** 1074 * pci_release_region - Release a PCI bar 1075 * @pdev: PCI device whose resources were previously reserved by pci_request_region 1076 * @bar: BAR to release 1077 * 1078 * Releases the PCI I/O and memory resources previously reserved by a 1079 * successful call to pci_request_region. Call this function only 1080 * after all use of the PCI regions has ceased. 1081 */ 1082 void pci_release_region(struct pci_dev *pdev, int bar) 1083 { 1084 struct pci_devres *dr; 1085 1086 if (pci_resource_len(pdev, bar) == 0) 1087 return; 1088 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) 1089 release_region(pci_resource_start(pdev, bar), 1090 pci_resource_len(pdev, bar)); 1091 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) 1092 release_mem_region(pci_resource_start(pdev, bar), 1093 pci_resource_len(pdev, bar)); 1094 1095 dr = find_pci_dr(pdev); 1096 if (dr) 1097 dr->region_mask &= ~(1 << bar); 1098 } 1099 1100 /** 1101 * pci_request_region - Reserved PCI I/O and memory resource 1102 * @pdev: PCI device whose resources are to be reserved 1103 * @bar: BAR to be reserved 1104 * @res_name: Name to be associated with resource. 1105 * 1106 * Mark the PCI region associated with PCI device @pdev BR @bar as 1107 * being reserved by owner @res_name. Do not access any 1108 * address inside the PCI regions unless this call returns 1109 * successfully. 1110 * 1111 * Returns 0 on success, or %EBUSY on error. A warning 1112 * message is also printed on failure. 1113 */ 1114 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) 1115 { 1116 struct pci_devres *dr; 1117 1118 if (pci_resource_len(pdev, bar) == 0) 1119 return 0; 1120 1121 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) { 1122 if (!request_region(pci_resource_start(pdev, bar), 1123 pci_resource_len(pdev, bar), res_name)) 1124 goto err_out; 1125 } 1126 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) { 1127 if (!request_mem_region(pci_resource_start(pdev, bar), 1128 pci_resource_len(pdev, bar), res_name)) 1129 goto err_out; 1130 } 1131 1132 dr = find_pci_dr(pdev); 1133 if (dr) 1134 dr->region_mask |= 1 << bar; 1135 1136 return 0; 1137 1138 err_out: 1139 printk (KERN_WARNING "PCI: Unable to reserve %s region #%d:%llx@%llx " 1140 "for device %s\n", 1141 pci_resource_flags(pdev, bar) & IORESOURCE_IO ? "I/O" : "mem", 1142 bar + 1, /* PCI BAR # */ 1143 (unsigned long long)pci_resource_len(pdev, bar), 1144 (unsigned long long)pci_resource_start(pdev, bar), 1145 pci_name(pdev)); 1146 return -EBUSY; 1147 } 1148 1149 /** 1150 * pci_release_selected_regions - Release selected PCI I/O and memory resources 1151 * @pdev: PCI device whose resources were previously reserved 1152 * @bars: Bitmask of BARs to be released 1153 * 1154 * Release selected PCI I/O and memory resources previously reserved. 1155 * Call this function only after all use of the PCI regions has ceased. 1156 */ 1157 void pci_release_selected_regions(struct pci_dev *pdev, int bars) 1158 { 1159 int i; 1160 1161 for (i = 0; i < 6; i++) 1162 if (bars & (1 << i)) 1163 pci_release_region(pdev, i); 1164 } 1165 1166 /** 1167 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources 1168 * @pdev: PCI device whose resources are to be reserved 1169 * @bars: Bitmask of BARs to be requested 1170 * @res_name: Name to be associated with resource 1171 */ 1172 int pci_request_selected_regions(struct pci_dev *pdev, int bars, 1173 const char *res_name) 1174 { 1175 int i; 1176 1177 for (i = 0; i < 6; i++) 1178 if (bars & (1 << i)) 1179 if(pci_request_region(pdev, i, res_name)) 1180 goto err_out; 1181 return 0; 1182 1183 err_out: 1184 while(--i >= 0) 1185 if (bars & (1 << i)) 1186 pci_release_region(pdev, i); 1187 1188 return -EBUSY; 1189 } 1190 1191 /** 1192 * pci_release_regions - Release reserved PCI I/O and memory resources 1193 * @pdev: PCI device whose resources were previously reserved by pci_request_regions 1194 * 1195 * Releases all PCI I/O and memory resources previously reserved by a 1196 * successful call to pci_request_regions. Call this function only 1197 * after all use of the PCI regions has ceased. 1198 */ 1199 1200 void pci_release_regions(struct pci_dev *pdev) 1201 { 1202 pci_release_selected_regions(pdev, (1 << 6) - 1); 1203 } 1204 1205 /** 1206 * pci_request_regions - Reserved PCI I/O and memory resources 1207 * @pdev: PCI device whose resources are to be reserved 1208 * @res_name: Name to be associated with resource. 1209 * 1210 * Mark all PCI regions associated with PCI device @pdev as 1211 * being reserved by owner @res_name. Do not access any 1212 * address inside the PCI regions unless this call returns 1213 * successfully. 1214 * 1215 * Returns 0 on success, or %EBUSY on error. A warning 1216 * message is also printed on failure. 1217 */ 1218 int pci_request_regions(struct pci_dev *pdev, const char *res_name) 1219 { 1220 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name); 1221 } 1222 1223 /** 1224 * pci_set_master - enables bus-mastering for device dev 1225 * @dev: the PCI device to enable 1226 * 1227 * Enables bus-mastering on the device and calls pcibios_set_master() 1228 * to do the needed arch specific settings. 1229 */ 1230 void 1231 pci_set_master(struct pci_dev *dev) 1232 { 1233 u16 cmd; 1234 1235 pci_read_config_word(dev, PCI_COMMAND, &cmd); 1236 if (! (cmd & PCI_COMMAND_MASTER)) { 1237 pr_debug("PCI: Enabling bus mastering for device %s\n", pci_name(dev)); 1238 cmd |= PCI_COMMAND_MASTER; 1239 pci_write_config_word(dev, PCI_COMMAND, cmd); 1240 } 1241 dev->is_busmaster = 1; 1242 pcibios_set_master(dev); 1243 } 1244 1245 #ifdef PCI_DISABLE_MWI 1246 int pci_set_mwi(struct pci_dev *dev) 1247 { 1248 return 0; 1249 } 1250 1251 int pci_try_set_mwi(struct pci_dev *dev) 1252 { 1253 return 0; 1254 } 1255 1256 void pci_clear_mwi(struct pci_dev *dev) 1257 { 1258 } 1259 1260 #else 1261 1262 #ifndef PCI_CACHE_LINE_BYTES 1263 #define PCI_CACHE_LINE_BYTES L1_CACHE_BYTES 1264 #endif 1265 1266 /* This can be overridden by arch code. */ 1267 /* Don't forget this is measured in 32-bit words, not bytes */ 1268 u8 pci_cache_line_size = PCI_CACHE_LINE_BYTES / 4; 1269 1270 /** 1271 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed 1272 * @dev: the PCI device for which MWI is to be enabled 1273 * 1274 * Helper function for pci_set_mwi. 1275 * Originally copied from drivers/net/acenic.c. 1276 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. 1277 * 1278 * RETURNS: An appropriate -ERRNO error value on error, or zero for success. 1279 */ 1280 static int 1281 pci_set_cacheline_size(struct pci_dev *dev) 1282 { 1283 u8 cacheline_size; 1284 1285 if (!pci_cache_line_size) 1286 return -EINVAL; /* The system doesn't support MWI. */ 1287 1288 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be 1289 equal to or multiple of the right value. */ 1290 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); 1291 if (cacheline_size >= pci_cache_line_size && 1292 (cacheline_size % pci_cache_line_size) == 0) 1293 return 0; 1294 1295 /* Write the correct value. */ 1296 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size); 1297 /* Read it back. */ 1298 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); 1299 if (cacheline_size == pci_cache_line_size) 1300 return 0; 1301 1302 printk(KERN_DEBUG "PCI: cache line size of %d is not supported " 1303 "by device %s\n", pci_cache_line_size << 2, pci_name(dev)); 1304 1305 return -EINVAL; 1306 } 1307 1308 /** 1309 * pci_set_mwi - enables memory-write-invalidate PCI transaction 1310 * @dev: the PCI device for which MWI is enabled 1311 * 1312 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. 1313 * 1314 * RETURNS: An appropriate -ERRNO error value on error, or zero for success. 1315 */ 1316 int 1317 pci_set_mwi(struct pci_dev *dev) 1318 { 1319 int rc; 1320 u16 cmd; 1321 1322 rc = pci_set_cacheline_size(dev); 1323 if (rc) 1324 return rc; 1325 1326 pci_read_config_word(dev, PCI_COMMAND, &cmd); 1327 if (! (cmd & PCI_COMMAND_INVALIDATE)) { 1328 pr_debug("PCI: Enabling Mem-Wr-Inval for device %s\n", 1329 pci_name(dev)); 1330 cmd |= PCI_COMMAND_INVALIDATE; 1331 pci_write_config_word(dev, PCI_COMMAND, cmd); 1332 } 1333 1334 return 0; 1335 } 1336 1337 /** 1338 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction 1339 * @dev: the PCI device for which MWI is enabled 1340 * 1341 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. 1342 * Callers are not required to check the return value. 1343 * 1344 * RETURNS: An appropriate -ERRNO error value on error, or zero for success. 1345 */ 1346 int pci_try_set_mwi(struct pci_dev *dev) 1347 { 1348 int rc = pci_set_mwi(dev); 1349 return rc; 1350 } 1351 1352 /** 1353 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev 1354 * @dev: the PCI device to disable 1355 * 1356 * Disables PCI Memory-Write-Invalidate transaction on the device 1357 */ 1358 void 1359 pci_clear_mwi(struct pci_dev *dev) 1360 { 1361 u16 cmd; 1362 1363 pci_read_config_word(dev, PCI_COMMAND, &cmd); 1364 if (cmd & PCI_COMMAND_INVALIDATE) { 1365 cmd &= ~PCI_COMMAND_INVALIDATE; 1366 pci_write_config_word(dev, PCI_COMMAND, cmd); 1367 } 1368 } 1369 #endif /* ! PCI_DISABLE_MWI */ 1370 1371 /** 1372 * pci_intx - enables/disables PCI INTx for device dev 1373 * @pdev: the PCI device to operate on 1374 * @enable: boolean: whether to enable or disable PCI INTx 1375 * 1376 * Enables/disables PCI INTx for device dev 1377 */ 1378 void 1379 pci_intx(struct pci_dev *pdev, int enable) 1380 { 1381 u16 pci_command, new; 1382 1383 pci_read_config_word(pdev, PCI_COMMAND, &pci_command); 1384 1385 if (enable) { 1386 new = pci_command & ~PCI_COMMAND_INTX_DISABLE; 1387 } else { 1388 new = pci_command | PCI_COMMAND_INTX_DISABLE; 1389 } 1390 1391 if (new != pci_command) { 1392 struct pci_devres *dr; 1393 1394 pci_write_config_word(pdev, PCI_COMMAND, new); 1395 1396 dr = find_pci_dr(pdev); 1397 if (dr && !dr->restore_intx) { 1398 dr->restore_intx = 1; 1399 dr->orig_intx = !enable; 1400 } 1401 } 1402 } 1403 1404 /** 1405 * pci_msi_off - disables any msi or msix capabilities 1406 * @dev: the PCI device to operate on 1407 * 1408 * If you want to use msi see pci_enable_msi and friends. 1409 * This is a lower level primitive that allows us to disable 1410 * msi operation at the device level. 1411 */ 1412 void pci_msi_off(struct pci_dev *dev) 1413 { 1414 int pos; 1415 u16 control; 1416 1417 pos = pci_find_capability(dev, PCI_CAP_ID_MSI); 1418 if (pos) { 1419 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); 1420 control &= ~PCI_MSI_FLAGS_ENABLE; 1421 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); 1422 } 1423 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); 1424 if (pos) { 1425 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); 1426 control &= ~PCI_MSIX_FLAGS_ENABLE; 1427 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); 1428 } 1429 } 1430 1431 #ifndef HAVE_ARCH_PCI_SET_DMA_MASK 1432 /* 1433 * These can be overridden by arch-specific implementations 1434 */ 1435 int 1436 pci_set_dma_mask(struct pci_dev *dev, u64 mask) 1437 { 1438 if (!pci_dma_supported(dev, mask)) 1439 return -EIO; 1440 1441 dev->dma_mask = mask; 1442 1443 return 0; 1444 } 1445 1446 int 1447 pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask) 1448 { 1449 if (!pci_dma_supported(dev, mask)) 1450 return -EIO; 1451 1452 dev->dev.coherent_dma_mask = mask; 1453 1454 return 0; 1455 } 1456 #endif 1457 1458 /** 1459 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count 1460 * @dev: PCI device to query 1461 * 1462 * Returns mmrbc: maximum designed memory read count in bytes 1463 * or appropriate error value. 1464 */ 1465 int pcix_get_max_mmrbc(struct pci_dev *dev) 1466 { 1467 int err, cap; 1468 u32 stat; 1469 1470 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); 1471 if (!cap) 1472 return -EINVAL; 1473 1474 err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat); 1475 if (err) 1476 return -EINVAL; 1477 1478 return (stat & PCI_X_STATUS_MAX_READ) >> 12; 1479 } 1480 EXPORT_SYMBOL(pcix_get_max_mmrbc); 1481 1482 /** 1483 * pcix_get_mmrbc - get PCI-X maximum memory read byte count 1484 * @dev: PCI device to query 1485 * 1486 * Returns mmrbc: maximum memory read count in bytes 1487 * or appropriate error value. 1488 */ 1489 int pcix_get_mmrbc(struct pci_dev *dev) 1490 { 1491 int ret, cap; 1492 u32 cmd; 1493 1494 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); 1495 if (!cap) 1496 return -EINVAL; 1497 1498 ret = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd); 1499 if (!ret) 1500 ret = 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2); 1501 1502 return ret; 1503 } 1504 EXPORT_SYMBOL(pcix_get_mmrbc); 1505 1506 /** 1507 * pcix_set_mmrbc - set PCI-X maximum memory read byte count 1508 * @dev: PCI device to query 1509 * @mmrbc: maximum memory read count in bytes 1510 * valid values are 512, 1024, 2048, 4096 1511 * 1512 * If possible sets maximum memory read byte count, some bridges have erratas 1513 * that prevent this. 1514 */ 1515 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc) 1516 { 1517 int cap, err = -EINVAL; 1518 u32 stat, cmd, v, o; 1519 1520 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc)) 1521 goto out; 1522 1523 v = ffs(mmrbc) - 10; 1524 1525 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); 1526 if (!cap) 1527 goto out; 1528 1529 err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat); 1530 if (err) 1531 goto out; 1532 1533 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21) 1534 return -E2BIG; 1535 1536 err = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd); 1537 if (err) 1538 goto out; 1539 1540 o = (cmd & PCI_X_CMD_MAX_READ) >> 2; 1541 if (o != v) { 1542 if (v > o && dev->bus && 1543 (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC)) 1544 return -EIO; 1545 1546 cmd &= ~PCI_X_CMD_MAX_READ; 1547 cmd |= v << 2; 1548 err = pci_write_config_dword(dev, cap + PCI_X_CMD, cmd); 1549 } 1550 out: 1551 return err; 1552 } 1553 EXPORT_SYMBOL(pcix_set_mmrbc); 1554 1555 /** 1556 * pcie_get_readrq - get PCI Express read request size 1557 * @dev: PCI device to query 1558 * 1559 * Returns maximum memory read request in bytes 1560 * or appropriate error value. 1561 */ 1562 int pcie_get_readrq(struct pci_dev *dev) 1563 { 1564 int ret, cap; 1565 u16 ctl; 1566 1567 cap = pci_find_capability(dev, PCI_CAP_ID_EXP); 1568 if (!cap) 1569 return -EINVAL; 1570 1571 ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl); 1572 if (!ret) 1573 ret = 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12); 1574 1575 return ret; 1576 } 1577 EXPORT_SYMBOL(pcie_get_readrq); 1578 1579 /** 1580 * pcie_set_readrq - set PCI Express maximum memory read request 1581 * @dev: PCI device to query 1582 * @rq: maximum memory read count in bytes 1583 * valid values are 128, 256, 512, 1024, 2048, 4096 1584 * 1585 * If possible sets maximum read byte count 1586 */ 1587 int pcie_set_readrq(struct pci_dev *dev, int rq) 1588 { 1589 int cap, err = -EINVAL; 1590 u16 ctl, v; 1591 1592 if (rq < 128 || rq > 4096 || !is_power_of_2(rq)) 1593 goto out; 1594 1595 v = (ffs(rq) - 8) << 12; 1596 1597 cap = pci_find_capability(dev, PCI_CAP_ID_EXP); 1598 if (!cap) 1599 goto out; 1600 1601 err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl); 1602 if (err) 1603 goto out; 1604 1605 if ((ctl & PCI_EXP_DEVCTL_READRQ) != v) { 1606 ctl &= ~PCI_EXP_DEVCTL_READRQ; 1607 ctl |= v; 1608 err = pci_write_config_dword(dev, cap + PCI_EXP_DEVCTL, ctl); 1609 } 1610 1611 out: 1612 return err; 1613 } 1614 EXPORT_SYMBOL(pcie_set_readrq); 1615 1616 /** 1617 * pci_select_bars - Make BAR mask from the type of resource 1618 * @dev: the PCI device for which BAR mask is made 1619 * @flags: resource type mask to be selected 1620 * 1621 * This helper routine makes bar mask from the type of resource. 1622 */ 1623 int pci_select_bars(struct pci_dev *dev, unsigned long flags) 1624 { 1625 int i, bars = 0; 1626 for (i = 0; i < PCI_NUM_RESOURCES; i++) 1627 if (pci_resource_flags(dev, i) & flags) 1628 bars |= (1 << i); 1629 return bars; 1630 } 1631 1632 static void __devinit pci_no_domains(void) 1633 { 1634 #ifdef CONFIG_PCI_DOMAINS 1635 pci_domains_supported = 0; 1636 #endif 1637 } 1638 1639 static int __devinit pci_init(void) 1640 { 1641 struct pci_dev *dev = NULL; 1642 1643 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { 1644 pci_fixup_device(pci_fixup_final, dev); 1645 } 1646 return 0; 1647 } 1648 1649 static int __devinit pci_setup(char *str) 1650 { 1651 while (str) { 1652 char *k = strchr(str, ','); 1653 if (k) 1654 *k++ = 0; 1655 if (*str && (str = pcibios_setup(str)) && *str) { 1656 if (!strcmp(str, "nomsi")) { 1657 pci_no_msi(); 1658 } else if (!strcmp(str, "noaer")) { 1659 pci_no_aer(); 1660 } else if (!strcmp(str, "nodomains")) { 1661 pci_no_domains(); 1662 } else if (!strncmp(str, "cbiosize=", 9)) { 1663 pci_cardbus_io_size = memparse(str + 9, &str); 1664 } else if (!strncmp(str, "cbmemsize=", 10)) { 1665 pci_cardbus_mem_size = memparse(str + 10, &str); 1666 } else { 1667 printk(KERN_ERR "PCI: Unknown option `%s'\n", 1668 str); 1669 } 1670 } 1671 str = k; 1672 } 1673 return 0; 1674 } 1675 early_param("pci", pci_setup); 1676 1677 device_initcall(pci_init); 1678 1679 EXPORT_SYMBOL(pci_reenable_device); 1680 EXPORT_SYMBOL(pci_enable_device_io); 1681 EXPORT_SYMBOL(pci_enable_device_mem); 1682 EXPORT_SYMBOL(pci_enable_device); 1683 EXPORT_SYMBOL(pcim_enable_device); 1684 EXPORT_SYMBOL(pcim_pin_device); 1685 EXPORT_SYMBOL(pci_disable_device); 1686 EXPORT_SYMBOL(pci_find_capability); 1687 EXPORT_SYMBOL(pci_bus_find_capability); 1688 EXPORT_SYMBOL(pci_release_regions); 1689 EXPORT_SYMBOL(pci_request_regions); 1690 EXPORT_SYMBOL(pci_release_region); 1691 EXPORT_SYMBOL(pci_request_region); 1692 EXPORT_SYMBOL(pci_release_selected_regions); 1693 EXPORT_SYMBOL(pci_request_selected_regions); 1694 EXPORT_SYMBOL(pci_set_master); 1695 EXPORT_SYMBOL(pci_set_mwi); 1696 EXPORT_SYMBOL(pci_try_set_mwi); 1697 EXPORT_SYMBOL(pci_clear_mwi); 1698 EXPORT_SYMBOL_GPL(pci_intx); 1699 EXPORT_SYMBOL(pci_set_dma_mask); 1700 EXPORT_SYMBOL(pci_set_consistent_dma_mask); 1701 EXPORT_SYMBOL(pci_assign_resource); 1702 EXPORT_SYMBOL(pci_find_parent_resource); 1703 EXPORT_SYMBOL(pci_select_bars); 1704 1705 EXPORT_SYMBOL(pci_set_power_state); 1706 EXPORT_SYMBOL(pci_save_state); 1707 EXPORT_SYMBOL(pci_restore_state); 1708 EXPORT_SYMBOL(pci_enable_wake); 1709 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state); 1710 1711