1 /* 2 * PCI Bus Services, see include/linux/pci.h for further explanation. 3 * 4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter, 5 * David Mosberger-Tang 6 * 7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz> 8 */ 9 10 #include <linux/kernel.h> 11 #include <linux/delay.h> 12 #include <linux/init.h> 13 #include <linux/pci.h> 14 #include <linux/pm.h> 15 #include <linux/slab.h> 16 #include <linux/module.h> 17 #include <linux/spinlock.h> 18 #include <linux/string.h> 19 #include <linux/log2.h> 20 #include <linux/pci-aspm.h> 21 #include <linux/pm_wakeup.h> 22 #include <linux/interrupt.h> 23 #include <linux/device.h> 24 #include <linux/pm_runtime.h> 25 #include <linux/pci_hotplug.h> 26 #include <asm-generic/pci-bridge.h> 27 #include <asm/setup.h> 28 #include "pci.h" 29 30 const char *pci_power_names[] = { 31 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown", 32 }; 33 EXPORT_SYMBOL_GPL(pci_power_names); 34 35 int isa_dma_bridge_buggy; 36 EXPORT_SYMBOL(isa_dma_bridge_buggy); 37 38 int pci_pci_problems; 39 EXPORT_SYMBOL(pci_pci_problems); 40 41 unsigned int pci_pm_d3_delay; 42 43 static void pci_pme_list_scan(struct work_struct *work); 44 45 static LIST_HEAD(pci_pme_list); 46 static DEFINE_MUTEX(pci_pme_list_mutex); 47 static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan); 48 49 struct pci_pme_device { 50 struct list_head list; 51 struct pci_dev *dev; 52 }; 53 54 #define PME_TIMEOUT 1000 /* How long between PME checks */ 55 56 static void pci_dev_d3_sleep(struct pci_dev *dev) 57 { 58 unsigned int delay = dev->d3_delay; 59 60 if (delay < pci_pm_d3_delay) 61 delay = pci_pm_d3_delay; 62 63 msleep(delay); 64 } 65 66 #ifdef CONFIG_PCI_DOMAINS 67 int pci_domains_supported = 1; 68 #endif 69 70 #define DEFAULT_CARDBUS_IO_SIZE (256) 71 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024) 72 /* pci=cbmemsize=nnM,cbiosize=nn can override this */ 73 unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE; 74 unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE; 75 76 #define DEFAULT_HOTPLUG_IO_SIZE (256) 77 #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024) 78 /* pci=hpmemsize=nnM,hpiosize=nn can override this */ 79 unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE; 80 unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE; 81 82 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_TUNE_OFF; 83 84 /* 85 * The default CLS is used if arch didn't set CLS explicitly and not 86 * all pci devices agree on the same value. Arch can override either 87 * the dfl or actual value as it sees fit. Don't forget this is 88 * measured in 32-bit words, not bytes. 89 */ 90 u8 pci_dfl_cache_line_size = L1_CACHE_BYTES >> 2; 91 u8 pci_cache_line_size; 92 93 /* 94 * If we set up a device for bus mastering, we need to check the latency 95 * timer as certain BIOSes forget to set it properly. 96 */ 97 unsigned int pcibios_max_latency = 255; 98 99 /* If set, the PCIe ARI capability will not be used. */ 100 static bool pcie_ari_disabled; 101 102 /** 103 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children 104 * @bus: pointer to PCI bus structure to search 105 * 106 * Given a PCI bus, returns the highest PCI bus number present in the set 107 * including the given PCI bus and its list of child PCI buses. 108 */ 109 unsigned char pci_bus_max_busnr(struct pci_bus* bus) 110 { 111 struct list_head *tmp; 112 unsigned char max, n; 113 114 max = bus->busn_res.end; 115 list_for_each(tmp, &bus->children) { 116 n = pci_bus_max_busnr(pci_bus_b(tmp)); 117 if(n > max) 118 max = n; 119 } 120 return max; 121 } 122 EXPORT_SYMBOL_GPL(pci_bus_max_busnr); 123 124 #ifdef CONFIG_HAS_IOMEM 125 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar) 126 { 127 /* 128 * Make sure the BAR is actually a memory resource, not an IO resource 129 */ 130 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { 131 WARN_ON(1); 132 return NULL; 133 } 134 return ioremap_nocache(pci_resource_start(pdev, bar), 135 pci_resource_len(pdev, bar)); 136 } 137 EXPORT_SYMBOL_GPL(pci_ioremap_bar); 138 #endif 139 140 #define PCI_FIND_CAP_TTL 48 141 142 static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn, 143 u8 pos, int cap, int *ttl) 144 { 145 u8 id; 146 147 while ((*ttl)--) { 148 pci_bus_read_config_byte(bus, devfn, pos, &pos); 149 if (pos < 0x40) 150 break; 151 pos &= ~3; 152 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID, 153 &id); 154 if (id == 0xff) 155 break; 156 if (id == cap) 157 return pos; 158 pos += PCI_CAP_LIST_NEXT; 159 } 160 return 0; 161 } 162 163 static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn, 164 u8 pos, int cap) 165 { 166 int ttl = PCI_FIND_CAP_TTL; 167 168 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl); 169 } 170 171 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap) 172 { 173 return __pci_find_next_cap(dev->bus, dev->devfn, 174 pos + PCI_CAP_LIST_NEXT, cap); 175 } 176 EXPORT_SYMBOL_GPL(pci_find_next_capability); 177 178 static int __pci_bus_find_cap_start(struct pci_bus *bus, 179 unsigned int devfn, u8 hdr_type) 180 { 181 u16 status; 182 183 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status); 184 if (!(status & PCI_STATUS_CAP_LIST)) 185 return 0; 186 187 switch (hdr_type) { 188 case PCI_HEADER_TYPE_NORMAL: 189 case PCI_HEADER_TYPE_BRIDGE: 190 return PCI_CAPABILITY_LIST; 191 case PCI_HEADER_TYPE_CARDBUS: 192 return PCI_CB_CAPABILITY_LIST; 193 default: 194 return 0; 195 } 196 197 return 0; 198 } 199 200 /** 201 * pci_find_capability - query for devices' capabilities 202 * @dev: PCI device to query 203 * @cap: capability code 204 * 205 * Tell if a device supports a given PCI capability. 206 * Returns the address of the requested capability structure within the 207 * device's PCI configuration space or 0 in case the device does not 208 * support it. Possible values for @cap: 209 * 210 * %PCI_CAP_ID_PM Power Management 211 * %PCI_CAP_ID_AGP Accelerated Graphics Port 212 * %PCI_CAP_ID_VPD Vital Product Data 213 * %PCI_CAP_ID_SLOTID Slot Identification 214 * %PCI_CAP_ID_MSI Message Signalled Interrupts 215 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap 216 * %PCI_CAP_ID_PCIX PCI-X 217 * %PCI_CAP_ID_EXP PCI Express 218 */ 219 int pci_find_capability(struct pci_dev *dev, int cap) 220 { 221 int pos; 222 223 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); 224 if (pos) 225 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap); 226 227 return pos; 228 } 229 230 /** 231 * pci_bus_find_capability - query for devices' capabilities 232 * @bus: the PCI bus to query 233 * @devfn: PCI device to query 234 * @cap: capability code 235 * 236 * Like pci_find_capability() but works for pci devices that do not have a 237 * pci_dev structure set up yet. 238 * 239 * Returns the address of the requested capability structure within the 240 * device's PCI configuration space or 0 in case the device does not 241 * support it. 242 */ 243 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap) 244 { 245 int pos; 246 u8 hdr_type; 247 248 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type); 249 250 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f); 251 if (pos) 252 pos = __pci_find_next_cap(bus, devfn, pos, cap); 253 254 return pos; 255 } 256 257 /** 258 * pci_find_next_ext_capability - Find an extended capability 259 * @dev: PCI device to query 260 * @start: address at which to start looking (0 to start at beginning of list) 261 * @cap: capability code 262 * 263 * Returns the address of the next matching extended capability structure 264 * within the device's PCI configuration space or 0 if the device does 265 * not support it. Some capabilities can occur several times, e.g., the 266 * vendor-specific capability, and this provides a way to find them all. 267 */ 268 int pci_find_next_ext_capability(struct pci_dev *dev, int start, int cap) 269 { 270 u32 header; 271 int ttl; 272 int pos = PCI_CFG_SPACE_SIZE; 273 274 /* minimum 8 bytes per capability */ 275 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; 276 277 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE) 278 return 0; 279 280 if (start) 281 pos = start; 282 283 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) 284 return 0; 285 286 /* 287 * If we have no capabilities, this is indicated by cap ID, 288 * cap version and next pointer all being 0. 289 */ 290 if (header == 0) 291 return 0; 292 293 while (ttl-- > 0) { 294 if (PCI_EXT_CAP_ID(header) == cap && pos != start) 295 return pos; 296 297 pos = PCI_EXT_CAP_NEXT(header); 298 if (pos < PCI_CFG_SPACE_SIZE) 299 break; 300 301 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) 302 break; 303 } 304 305 return 0; 306 } 307 EXPORT_SYMBOL_GPL(pci_find_next_ext_capability); 308 309 /** 310 * pci_find_ext_capability - Find an extended capability 311 * @dev: PCI device to query 312 * @cap: capability code 313 * 314 * Returns the address of the requested extended capability structure 315 * within the device's PCI configuration space or 0 if the device does 316 * not support it. Possible values for @cap: 317 * 318 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting 319 * %PCI_EXT_CAP_ID_VC Virtual Channel 320 * %PCI_EXT_CAP_ID_DSN Device Serial Number 321 * %PCI_EXT_CAP_ID_PWR Power Budgeting 322 */ 323 int pci_find_ext_capability(struct pci_dev *dev, int cap) 324 { 325 return pci_find_next_ext_capability(dev, 0, cap); 326 } 327 EXPORT_SYMBOL_GPL(pci_find_ext_capability); 328 329 static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap) 330 { 331 int rc, ttl = PCI_FIND_CAP_TTL; 332 u8 cap, mask; 333 334 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST) 335 mask = HT_3BIT_CAP_MASK; 336 else 337 mask = HT_5BIT_CAP_MASK; 338 339 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos, 340 PCI_CAP_ID_HT, &ttl); 341 while (pos) { 342 rc = pci_read_config_byte(dev, pos + 3, &cap); 343 if (rc != PCIBIOS_SUCCESSFUL) 344 return 0; 345 346 if ((cap & mask) == ht_cap) 347 return pos; 348 349 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, 350 pos + PCI_CAP_LIST_NEXT, 351 PCI_CAP_ID_HT, &ttl); 352 } 353 354 return 0; 355 } 356 /** 357 * pci_find_next_ht_capability - query a device's Hypertransport capabilities 358 * @dev: PCI device to query 359 * @pos: Position from which to continue searching 360 * @ht_cap: Hypertransport capability code 361 * 362 * To be used in conjunction with pci_find_ht_capability() to search for 363 * all capabilities matching @ht_cap. @pos should always be a value returned 364 * from pci_find_ht_capability(). 365 * 366 * NB. To be 100% safe against broken PCI devices, the caller should take 367 * steps to avoid an infinite loop. 368 */ 369 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap) 370 { 371 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap); 372 } 373 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability); 374 375 /** 376 * pci_find_ht_capability - query a device's Hypertransport capabilities 377 * @dev: PCI device to query 378 * @ht_cap: Hypertransport capability code 379 * 380 * Tell if a device supports a given Hypertransport capability. 381 * Returns an address within the device's PCI configuration space 382 * or 0 in case the device does not support the request capability. 383 * The address points to the PCI capability, of type PCI_CAP_ID_HT, 384 * which has a Hypertransport capability matching @ht_cap. 385 */ 386 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap) 387 { 388 int pos; 389 390 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); 391 if (pos) 392 pos = __pci_find_next_ht_cap(dev, pos, ht_cap); 393 394 return pos; 395 } 396 EXPORT_SYMBOL_GPL(pci_find_ht_capability); 397 398 /** 399 * pci_find_parent_resource - return resource region of parent bus of given region 400 * @dev: PCI device structure contains resources to be searched 401 * @res: child resource record for which parent is sought 402 * 403 * For given resource region of given device, return the resource 404 * region of parent bus the given region is contained in or where 405 * it should be allocated from. 406 */ 407 struct resource * 408 pci_find_parent_resource(const struct pci_dev *dev, struct resource *res) 409 { 410 const struct pci_bus *bus = dev->bus; 411 int i; 412 struct resource *best = NULL, *r; 413 414 pci_bus_for_each_resource(bus, r, i) { 415 if (!r) 416 continue; 417 if (res->start && !(res->start >= r->start && res->end <= r->end)) 418 continue; /* Not contained */ 419 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM)) 420 continue; /* Wrong type */ 421 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH)) 422 return r; /* Exact match */ 423 /* We can't insert a non-prefetch resource inside a prefetchable parent .. */ 424 if (r->flags & IORESOURCE_PREFETCH) 425 continue; 426 /* .. but we can put a prefetchable resource inside a non-prefetchable one */ 427 if (!best) 428 best = r; 429 } 430 return best; 431 } 432 433 /** 434 * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos 435 * @dev: the PCI device to operate on 436 * @pos: config space offset of status word 437 * @mask: mask of bit(s) to care about in status word 438 * 439 * Return 1 when mask bit(s) in status word clear, 0 otherwise. 440 */ 441 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask) 442 { 443 int i; 444 445 /* Wait for Transaction Pending bit clean */ 446 for (i = 0; i < 4; i++) { 447 u16 status; 448 if (i) 449 msleep((1 << (i - 1)) * 100); 450 451 pci_read_config_word(dev, pos, &status); 452 if (!(status & mask)) 453 return 1; 454 } 455 456 return 0; 457 } 458 459 /** 460 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up) 461 * @dev: PCI device to have its BARs restored 462 * 463 * Restore the BAR values for a given device, so as to make it 464 * accessible by its driver. 465 */ 466 static void 467 pci_restore_bars(struct pci_dev *dev) 468 { 469 int i; 470 471 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) 472 pci_update_resource(dev, i); 473 } 474 475 static struct pci_platform_pm_ops *pci_platform_pm; 476 477 int pci_set_platform_pm(struct pci_platform_pm_ops *ops) 478 { 479 if (!ops->is_manageable || !ops->set_state || !ops->choose_state 480 || !ops->sleep_wake) 481 return -EINVAL; 482 pci_platform_pm = ops; 483 return 0; 484 } 485 486 static inline bool platform_pci_power_manageable(struct pci_dev *dev) 487 { 488 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false; 489 } 490 491 static inline int platform_pci_set_power_state(struct pci_dev *dev, 492 pci_power_t t) 493 { 494 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS; 495 } 496 497 static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev) 498 { 499 return pci_platform_pm ? 500 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR; 501 } 502 503 static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable) 504 { 505 return pci_platform_pm ? 506 pci_platform_pm->sleep_wake(dev, enable) : -ENODEV; 507 } 508 509 static inline int platform_pci_run_wake(struct pci_dev *dev, bool enable) 510 { 511 return pci_platform_pm ? 512 pci_platform_pm->run_wake(dev, enable) : -ENODEV; 513 } 514 515 /** 516 * pci_raw_set_power_state - Use PCI PM registers to set the power state of 517 * given PCI device 518 * @dev: PCI device to handle. 519 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into. 520 * 521 * RETURN VALUE: 522 * -EINVAL if the requested state is invalid. 523 * -EIO if device does not support PCI PM or its PM capabilities register has a 524 * wrong version, or device doesn't support the requested state. 525 * 0 if device already is in the requested state. 526 * 0 if device's power state has been successfully changed. 527 */ 528 static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state) 529 { 530 u16 pmcsr; 531 bool need_restore = false; 532 533 /* Check if we're already there */ 534 if (dev->current_state == state) 535 return 0; 536 537 if (!dev->pm_cap) 538 return -EIO; 539 540 if (state < PCI_D0 || state > PCI_D3hot) 541 return -EINVAL; 542 543 /* Validate current state: 544 * Can enter D0 from any state, but if we can only go deeper 545 * to sleep if we're already in a low power state 546 */ 547 if (state != PCI_D0 && dev->current_state <= PCI_D3cold 548 && dev->current_state > state) { 549 dev_err(&dev->dev, "invalid power transition " 550 "(from state %d to %d)\n", dev->current_state, state); 551 return -EINVAL; 552 } 553 554 /* check if this device supports the desired state */ 555 if ((state == PCI_D1 && !dev->d1_support) 556 || (state == PCI_D2 && !dev->d2_support)) 557 return -EIO; 558 559 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); 560 561 /* If we're (effectively) in D3, force entire word to 0. 562 * This doesn't affect PME_Status, disables PME_En, and 563 * sets PowerState to 0. 564 */ 565 switch (dev->current_state) { 566 case PCI_D0: 567 case PCI_D1: 568 case PCI_D2: 569 pmcsr &= ~PCI_PM_CTRL_STATE_MASK; 570 pmcsr |= state; 571 break; 572 case PCI_D3hot: 573 case PCI_D3cold: 574 case PCI_UNKNOWN: /* Boot-up */ 575 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot 576 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET)) 577 need_restore = true; 578 /* Fall-through: force to D0 */ 579 default: 580 pmcsr = 0; 581 break; 582 } 583 584 /* enter specified state */ 585 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); 586 587 /* Mandatory power management transition delays */ 588 /* see PCI PM 1.1 5.6.1 table 18 */ 589 if (state == PCI_D3hot || dev->current_state == PCI_D3hot) 590 pci_dev_d3_sleep(dev); 591 else if (state == PCI_D2 || dev->current_state == PCI_D2) 592 udelay(PCI_PM_D2_DELAY); 593 594 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); 595 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); 596 if (dev->current_state != state && printk_ratelimit()) 597 dev_info(&dev->dev, "Refused to change power state, " 598 "currently in D%d\n", dev->current_state); 599 600 /* 601 * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT 602 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning 603 * from D3hot to D0 _may_ perform an internal reset, thereby 604 * going to "D0 Uninitialized" rather than "D0 Initialized". 605 * For example, at least some versions of the 3c905B and the 606 * 3c556B exhibit this behaviour. 607 * 608 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave 609 * devices in a D3hot state at boot. Consequently, we need to 610 * restore at least the BARs so that the device will be 611 * accessible to its driver. 612 */ 613 if (need_restore) 614 pci_restore_bars(dev); 615 616 if (dev->bus->self) 617 pcie_aspm_pm_state_change(dev->bus->self); 618 619 return 0; 620 } 621 622 /** 623 * pci_update_current_state - Read PCI power state of given device from its 624 * PCI PM registers and cache it 625 * @dev: PCI device to handle. 626 * @state: State to cache in case the device doesn't have the PM capability 627 */ 628 void pci_update_current_state(struct pci_dev *dev, pci_power_t state) 629 { 630 if (dev->pm_cap) { 631 u16 pmcsr; 632 633 /* 634 * Configuration space is not accessible for device in 635 * D3cold, so just keep or set D3cold for safety 636 */ 637 if (dev->current_state == PCI_D3cold) 638 return; 639 if (state == PCI_D3cold) { 640 dev->current_state = PCI_D3cold; 641 return; 642 } 643 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); 644 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); 645 } else { 646 dev->current_state = state; 647 } 648 } 649 650 /** 651 * pci_power_up - Put the given device into D0 forcibly 652 * @dev: PCI device to power up 653 */ 654 void pci_power_up(struct pci_dev *dev) 655 { 656 if (platform_pci_power_manageable(dev)) 657 platform_pci_set_power_state(dev, PCI_D0); 658 659 pci_raw_set_power_state(dev, PCI_D0); 660 pci_update_current_state(dev, PCI_D0); 661 } 662 663 /** 664 * pci_platform_power_transition - Use platform to change device power state 665 * @dev: PCI device to handle. 666 * @state: State to put the device into. 667 */ 668 static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state) 669 { 670 int error; 671 672 if (platform_pci_power_manageable(dev)) { 673 error = platform_pci_set_power_state(dev, state); 674 if (!error) 675 pci_update_current_state(dev, state); 676 } else 677 error = -ENODEV; 678 679 if (error && !dev->pm_cap) /* Fall back to PCI_D0 */ 680 dev->current_state = PCI_D0; 681 682 return error; 683 } 684 685 /** 686 * pci_wakeup - Wake up a PCI device 687 * @pci_dev: Device to handle. 688 * @ign: ignored parameter 689 */ 690 static int pci_wakeup(struct pci_dev *pci_dev, void *ign) 691 { 692 pci_wakeup_event(pci_dev); 693 pm_request_resume(&pci_dev->dev); 694 return 0; 695 } 696 697 /** 698 * pci_wakeup_bus - Walk given bus and wake up devices on it 699 * @bus: Top bus of the subtree to walk. 700 */ 701 static void pci_wakeup_bus(struct pci_bus *bus) 702 { 703 if (bus) 704 pci_walk_bus(bus, pci_wakeup, NULL); 705 } 706 707 /** 708 * __pci_start_power_transition - Start power transition of a PCI device 709 * @dev: PCI device to handle. 710 * @state: State to put the device into. 711 */ 712 static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state) 713 { 714 if (state == PCI_D0) { 715 pci_platform_power_transition(dev, PCI_D0); 716 /* 717 * Mandatory power management transition delays, see 718 * PCI Express Base Specification Revision 2.0 Section 719 * 6.6.1: Conventional Reset. Do not delay for 720 * devices powered on/off by corresponding bridge, 721 * because have already delayed for the bridge. 722 */ 723 if (dev->runtime_d3cold) { 724 msleep(dev->d3cold_delay); 725 /* 726 * When powering on a bridge from D3cold, the 727 * whole hierarchy may be powered on into 728 * D0uninitialized state, resume them to give 729 * them a chance to suspend again 730 */ 731 pci_wakeup_bus(dev->subordinate); 732 } 733 } 734 } 735 736 /** 737 * __pci_dev_set_current_state - Set current state of a PCI device 738 * @dev: Device to handle 739 * @data: pointer to state to be set 740 */ 741 static int __pci_dev_set_current_state(struct pci_dev *dev, void *data) 742 { 743 pci_power_t state = *(pci_power_t *)data; 744 745 dev->current_state = state; 746 return 0; 747 } 748 749 /** 750 * __pci_bus_set_current_state - Walk given bus and set current state of devices 751 * @bus: Top bus of the subtree to walk. 752 * @state: state to be set 753 */ 754 static void __pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state) 755 { 756 if (bus) 757 pci_walk_bus(bus, __pci_dev_set_current_state, &state); 758 } 759 760 /** 761 * __pci_complete_power_transition - Complete power transition of a PCI device 762 * @dev: PCI device to handle. 763 * @state: State to put the device into. 764 * 765 * This function should not be called directly by device drivers. 766 */ 767 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state) 768 { 769 int ret; 770 771 if (state <= PCI_D0) 772 return -EINVAL; 773 ret = pci_platform_power_transition(dev, state); 774 /* Power off the bridge may power off the whole hierarchy */ 775 if (!ret && state == PCI_D3cold) 776 __pci_bus_set_current_state(dev->subordinate, PCI_D3cold); 777 return ret; 778 } 779 EXPORT_SYMBOL_GPL(__pci_complete_power_transition); 780 781 /** 782 * pci_set_power_state - Set the power state of a PCI device 783 * @dev: PCI device to handle. 784 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into. 785 * 786 * Transition a device to a new power state, using the platform firmware and/or 787 * the device's PCI PM registers. 788 * 789 * RETURN VALUE: 790 * -EINVAL if the requested state is invalid. 791 * -EIO if device does not support PCI PM or its PM capabilities register has a 792 * wrong version, or device doesn't support the requested state. 793 * 0 if device already is in the requested state. 794 * 0 if device's power state has been successfully changed. 795 */ 796 int pci_set_power_state(struct pci_dev *dev, pci_power_t state) 797 { 798 int error; 799 800 /* bound the state we're entering */ 801 if (state > PCI_D3cold) 802 state = PCI_D3cold; 803 else if (state < PCI_D0) 804 state = PCI_D0; 805 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev)) 806 /* 807 * If the device or the parent bridge do not support PCI PM, 808 * ignore the request if we're doing anything other than putting 809 * it into D0 (which would only happen on boot). 810 */ 811 return 0; 812 813 /* Check if we're already there */ 814 if (dev->current_state == state) 815 return 0; 816 817 __pci_start_power_transition(dev, state); 818 819 /* This device is quirked not to be put into D3, so 820 don't put it in D3 */ 821 if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3)) 822 return 0; 823 824 /* 825 * To put device in D3cold, we put device into D3hot in native 826 * way, then put device into D3cold with platform ops 827 */ 828 error = pci_raw_set_power_state(dev, state > PCI_D3hot ? 829 PCI_D3hot : state); 830 831 if (!__pci_complete_power_transition(dev, state)) 832 error = 0; 833 /* 834 * When aspm_policy is "powersave" this call ensures 835 * that ASPM is configured. 836 */ 837 if (!error && dev->bus->self) 838 pcie_aspm_powersave_config_link(dev->bus->self); 839 840 return error; 841 } 842 843 /** 844 * pci_choose_state - Choose the power state of a PCI device 845 * @dev: PCI device to be suspended 846 * @state: target sleep state for the whole system. This is the value 847 * that is passed to suspend() function. 848 * 849 * Returns PCI power state suitable for given device and given system 850 * message. 851 */ 852 853 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state) 854 { 855 pci_power_t ret; 856 857 if (!dev->pm_cap) 858 return PCI_D0; 859 860 ret = platform_pci_choose_state(dev); 861 if (ret != PCI_POWER_ERROR) 862 return ret; 863 864 switch (state.event) { 865 case PM_EVENT_ON: 866 return PCI_D0; 867 case PM_EVENT_FREEZE: 868 case PM_EVENT_PRETHAW: 869 /* REVISIT both freeze and pre-thaw "should" use D0 */ 870 case PM_EVENT_SUSPEND: 871 case PM_EVENT_HIBERNATE: 872 return PCI_D3hot; 873 default: 874 dev_info(&dev->dev, "unrecognized suspend event %d\n", 875 state.event); 876 BUG(); 877 } 878 return PCI_D0; 879 } 880 881 EXPORT_SYMBOL(pci_choose_state); 882 883 #define PCI_EXP_SAVE_REGS 7 884 885 886 static struct pci_cap_saved_state *_pci_find_saved_cap(struct pci_dev *pci_dev, 887 u16 cap, bool extended) 888 { 889 struct pci_cap_saved_state *tmp; 890 891 hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) { 892 if (tmp->cap.cap_extended == extended && tmp->cap.cap_nr == cap) 893 return tmp; 894 } 895 return NULL; 896 } 897 898 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap) 899 { 900 return _pci_find_saved_cap(dev, cap, false); 901 } 902 903 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, u16 cap) 904 { 905 return _pci_find_saved_cap(dev, cap, true); 906 } 907 908 static int pci_save_pcie_state(struct pci_dev *dev) 909 { 910 int i = 0; 911 struct pci_cap_saved_state *save_state; 912 u16 *cap; 913 914 if (!pci_is_pcie(dev)) 915 return 0; 916 917 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); 918 if (!save_state) { 919 dev_err(&dev->dev, "buffer not found in %s\n", __func__); 920 return -ENOMEM; 921 } 922 923 cap = (u16 *)&save_state->cap.data[0]; 924 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]); 925 pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]); 926 pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]); 927 pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]); 928 pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]); 929 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]); 930 pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]); 931 932 return 0; 933 } 934 935 static void pci_restore_pcie_state(struct pci_dev *dev) 936 { 937 int i = 0; 938 struct pci_cap_saved_state *save_state; 939 u16 *cap; 940 941 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); 942 if (!save_state) 943 return; 944 945 cap = (u16 *)&save_state->cap.data[0]; 946 pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]); 947 pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]); 948 pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]); 949 pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]); 950 pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]); 951 pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]); 952 pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]); 953 } 954 955 956 static int pci_save_pcix_state(struct pci_dev *dev) 957 { 958 int pos; 959 struct pci_cap_saved_state *save_state; 960 961 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); 962 if (pos <= 0) 963 return 0; 964 965 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); 966 if (!save_state) { 967 dev_err(&dev->dev, "buffer not found in %s\n", __func__); 968 return -ENOMEM; 969 } 970 971 pci_read_config_word(dev, pos + PCI_X_CMD, 972 (u16 *)save_state->cap.data); 973 974 return 0; 975 } 976 977 static void pci_restore_pcix_state(struct pci_dev *dev) 978 { 979 int i = 0, pos; 980 struct pci_cap_saved_state *save_state; 981 u16 *cap; 982 983 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); 984 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); 985 if (!save_state || pos <= 0) 986 return; 987 cap = (u16 *)&save_state->cap.data[0]; 988 989 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]); 990 } 991 992 993 /** 994 * pci_save_state - save the PCI configuration space of a device before suspending 995 * @dev: - PCI device that we're dealing with 996 */ 997 int 998 pci_save_state(struct pci_dev *dev) 999 { 1000 int i; 1001 /* XXX: 100% dword access ok here? */ 1002 for (i = 0; i < 16; i++) 1003 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]); 1004 dev->state_saved = true; 1005 if ((i = pci_save_pcie_state(dev)) != 0) 1006 return i; 1007 if ((i = pci_save_pcix_state(dev)) != 0) 1008 return i; 1009 if ((i = pci_save_vc_state(dev)) != 0) 1010 return i; 1011 return 0; 1012 } 1013 1014 static void pci_restore_config_dword(struct pci_dev *pdev, int offset, 1015 u32 saved_val, int retry) 1016 { 1017 u32 val; 1018 1019 pci_read_config_dword(pdev, offset, &val); 1020 if (val == saved_val) 1021 return; 1022 1023 for (;;) { 1024 dev_dbg(&pdev->dev, "restoring config space at offset " 1025 "%#x (was %#x, writing %#x)\n", offset, val, saved_val); 1026 pci_write_config_dword(pdev, offset, saved_val); 1027 if (retry-- <= 0) 1028 return; 1029 1030 pci_read_config_dword(pdev, offset, &val); 1031 if (val == saved_val) 1032 return; 1033 1034 mdelay(1); 1035 } 1036 } 1037 1038 static void pci_restore_config_space_range(struct pci_dev *pdev, 1039 int start, int end, int retry) 1040 { 1041 int index; 1042 1043 for (index = end; index >= start; index--) 1044 pci_restore_config_dword(pdev, 4 * index, 1045 pdev->saved_config_space[index], 1046 retry); 1047 } 1048 1049 static void pci_restore_config_space(struct pci_dev *pdev) 1050 { 1051 if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) { 1052 pci_restore_config_space_range(pdev, 10, 15, 0); 1053 /* Restore BARs before the command register. */ 1054 pci_restore_config_space_range(pdev, 4, 9, 10); 1055 pci_restore_config_space_range(pdev, 0, 3, 0); 1056 } else { 1057 pci_restore_config_space_range(pdev, 0, 15, 0); 1058 } 1059 } 1060 1061 /** 1062 * pci_restore_state - Restore the saved state of a PCI device 1063 * @dev: - PCI device that we're dealing with 1064 */ 1065 void pci_restore_state(struct pci_dev *dev) 1066 { 1067 if (!dev->state_saved) 1068 return; 1069 1070 /* PCI Express register must be restored first */ 1071 pci_restore_pcie_state(dev); 1072 pci_restore_ats_state(dev); 1073 pci_restore_vc_state(dev); 1074 1075 pci_restore_config_space(dev); 1076 1077 pci_restore_pcix_state(dev); 1078 pci_restore_msi_state(dev); 1079 pci_restore_iov_state(dev); 1080 1081 dev->state_saved = false; 1082 } 1083 1084 struct pci_saved_state { 1085 u32 config_space[16]; 1086 struct pci_cap_saved_data cap[0]; 1087 }; 1088 1089 /** 1090 * pci_store_saved_state - Allocate and return an opaque struct containing 1091 * the device saved state. 1092 * @dev: PCI device that we're dealing with 1093 * 1094 * Return NULL if no state or error. 1095 */ 1096 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev) 1097 { 1098 struct pci_saved_state *state; 1099 struct pci_cap_saved_state *tmp; 1100 struct pci_cap_saved_data *cap; 1101 size_t size; 1102 1103 if (!dev->state_saved) 1104 return NULL; 1105 1106 size = sizeof(*state) + sizeof(struct pci_cap_saved_data); 1107 1108 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) 1109 size += sizeof(struct pci_cap_saved_data) + tmp->cap.size; 1110 1111 state = kzalloc(size, GFP_KERNEL); 1112 if (!state) 1113 return NULL; 1114 1115 memcpy(state->config_space, dev->saved_config_space, 1116 sizeof(state->config_space)); 1117 1118 cap = state->cap; 1119 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) { 1120 size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size; 1121 memcpy(cap, &tmp->cap, len); 1122 cap = (struct pci_cap_saved_data *)((u8 *)cap + len); 1123 } 1124 /* Empty cap_save terminates list */ 1125 1126 return state; 1127 } 1128 EXPORT_SYMBOL_GPL(pci_store_saved_state); 1129 1130 /** 1131 * pci_load_saved_state - Reload the provided save state into struct pci_dev. 1132 * @dev: PCI device that we're dealing with 1133 * @state: Saved state returned from pci_store_saved_state() 1134 */ 1135 static int pci_load_saved_state(struct pci_dev *dev, 1136 struct pci_saved_state *state) 1137 { 1138 struct pci_cap_saved_data *cap; 1139 1140 dev->state_saved = false; 1141 1142 if (!state) 1143 return 0; 1144 1145 memcpy(dev->saved_config_space, state->config_space, 1146 sizeof(state->config_space)); 1147 1148 cap = state->cap; 1149 while (cap->size) { 1150 struct pci_cap_saved_state *tmp; 1151 1152 tmp = _pci_find_saved_cap(dev, cap->cap_nr, cap->cap_extended); 1153 if (!tmp || tmp->cap.size != cap->size) 1154 return -EINVAL; 1155 1156 memcpy(tmp->cap.data, cap->data, tmp->cap.size); 1157 cap = (struct pci_cap_saved_data *)((u8 *)cap + 1158 sizeof(struct pci_cap_saved_data) + cap->size); 1159 } 1160 1161 dev->state_saved = true; 1162 return 0; 1163 } 1164 1165 /** 1166 * pci_load_and_free_saved_state - Reload the save state pointed to by state, 1167 * and free the memory allocated for it. 1168 * @dev: PCI device that we're dealing with 1169 * @state: Pointer to saved state returned from pci_store_saved_state() 1170 */ 1171 int pci_load_and_free_saved_state(struct pci_dev *dev, 1172 struct pci_saved_state **state) 1173 { 1174 int ret = pci_load_saved_state(dev, *state); 1175 kfree(*state); 1176 *state = NULL; 1177 return ret; 1178 } 1179 EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state); 1180 1181 static int do_pci_enable_device(struct pci_dev *dev, int bars) 1182 { 1183 int err; 1184 u16 cmd; 1185 u8 pin; 1186 1187 err = pci_set_power_state(dev, PCI_D0); 1188 if (err < 0 && err != -EIO) 1189 return err; 1190 err = pcibios_enable_device(dev, bars); 1191 if (err < 0) 1192 return err; 1193 pci_fixup_device(pci_fixup_enable, dev); 1194 1195 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); 1196 if (pin) { 1197 pci_read_config_word(dev, PCI_COMMAND, &cmd); 1198 if (cmd & PCI_COMMAND_INTX_DISABLE) 1199 pci_write_config_word(dev, PCI_COMMAND, 1200 cmd & ~PCI_COMMAND_INTX_DISABLE); 1201 } 1202 1203 return 0; 1204 } 1205 1206 /** 1207 * pci_reenable_device - Resume abandoned device 1208 * @dev: PCI device to be resumed 1209 * 1210 * Note this function is a backend of pci_default_resume and is not supposed 1211 * to be called by normal code, write proper resume handler and use it instead. 1212 */ 1213 int pci_reenable_device(struct pci_dev *dev) 1214 { 1215 if (pci_is_enabled(dev)) 1216 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1); 1217 return 0; 1218 } 1219 1220 static void pci_enable_bridge(struct pci_dev *dev) 1221 { 1222 struct pci_dev *bridge; 1223 int retval; 1224 1225 bridge = pci_upstream_bridge(dev); 1226 if (bridge) 1227 pci_enable_bridge(bridge); 1228 1229 if (pci_is_enabled(dev)) { 1230 if (!dev->is_busmaster) 1231 pci_set_master(dev); 1232 return; 1233 } 1234 1235 retval = pci_enable_device(dev); 1236 if (retval) 1237 dev_err(&dev->dev, "Error enabling bridge (%d), continuing\n", 1238 retval); 1239 pci_set_master(dev); 1240 } 1241 1242 static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags) 1243 { 1244 struct pci_dev *bridge; 1245 int err; 1246 int i, bars = 0; 1247 1248 /* 1249 * Power state could be unknown at this point, either due to a fresh 1250 * boot or a device removal call. So get the current power state 1251 * so that things like MSI message writing will behave as expected 1252 * (e.g. if the device really is in D0 at enable time). 1253 */ 1254 if (dev->pm_cap) { 1255 u16 pmcsr; 1256 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); 1257 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); 1258 } 1259 1260 if (atomic_inc_return(&dev->enable_cnt) > 1) 1261 return 0; /* already enabled */ 1262 1263 bridge = pci_upstream_bridge(dev); 1264 if (bridge) 1265 pci_enable_bridge(bridge); 1266 1267 /* only skip sriov related */ 1268 for (i = 0; i <= PCI_ROM_RESOURCE; i++) 1269 if (dev->resource[i].flags & flags) 1270 bars |= (1 << i); 1271 for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++) 1272 if (dev->resource[i].flags & flags) 1273 bars |= (1 << i); 1274 1275 err = do_pci_enable_device(dev, bars); 1276 if (err < 0) 1277 atomic_dec(&dev->enable_cnt); 1278 return err; 1279 } 1280 1281 /** 1282 * pci_enable_device_io - Initialize a device for use with IO space 1283 * @dev: PCI device to be initialized 1284 * 1285 * Initialize device before it's used by a driver. Ask low-level code 1286 * to enable I/O resources. Wake up the device if it was suspended. 1287 * Beware, this function can fail. 1288 */ 1289 int pci_enable_device_io(struct pci_dev *dev) 1290 { 1291 return pci_enable_device_flags(dev, IORESOURCE_IO); 1292 } 1293 1294 /** 1295 * pci_enable_device_mem - Initialize a device for use with Memory space 1296 * @dev: PCI device to be initialized 1297 * 1298 * Initialize device before it's used by a driver. Ask low-level code 1299 * to enable Memory resources. Wake up the device if it was suspended. 1300 * Beware, this function can fail. 1301 */ 1302 int pci_enable_device_mem(struct pci_dev *dev) 1303 { 1304 return pci_enable_device_flags(dev, IORESOURCE_MEM); 1305 } 1306 1307 /** 1308 * pci_enable_device - Initialize device before it's used by a driver. 1309 * @dev: PCI device to be initialized 1310 * 1311 * Initialize device before it's used by a driver. Ask low-level code 1312 * to enable I/O and memory. Wake up the device if it was suspended. 1313 * Beware, this function can fail. 1314 * 1315 * Note we don't actually enable the device many times if we call 1316 * this function repeatedly (we just increment the count). 1317 */ 1318 int pci_enable_device(struct pci_dev *dev) 1319 { 1320 return pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO); 1321 } 1322 1323 /* 1324 * Managed PCI resources. This manages device on/off, intx/msi/msix 1325 * on/off and BAR regions. pci_dev itself records msi/msix status, so 1326 * there's no need to track it separately. pci_devres is initialized 1327 * when a device is enabled using managed PCI device enable interface. 1328 */ 1329 struct pci_devres { 1330 unsigned int enabled:1; 1331 unsigned int pinned:1; 1332 unsigned int orig_intx:1; 1333 unsigned int restore_intx:1; 1334 u32 region_mask; 1335 }; 1336 1337 static void pcim_release(struct device *gendev, void *res) 1338 { 1339 struct pci_dev *dev = container_of(gendev, struct pci_dev, dev); 1340 struct pci_devres *this = res; 1341 int i; 1342 1343 if (dev->msi_enabled) 1344 pci_disable_msi(dev); 1345 if (dev->msix_enabled) 1346 pci_disable_msix(dev); 1347 1348 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) 1349 if (this->region_mask & (1 << i)) 1350 pci_release_region(dev, i); 1351 1352 if (this->restore_intx) 1353 pci_intx(dev, this->orig_intx); 1354 1355 if (this->enabled && !this->pinned) 1356 pci_disable_device(dev); 1357 } 1358 1359 static struct pci_devres * get_pci_dr(struct pci_dev *pdev) 1360 { 1361 struct pci_devres *dr, *new_dr; 1362 1363 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL); 1364 if (dr) 1365 return dr; 1366 1367 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL); 1368 if (!new_dr) 1369 return NULL; 1370 return devres_get(&pdev->dev, new_dr, NULL, NULL); 1371 } 1372 1373 static struct pci_devres * find_pci_dr(struct pci_dev *pdev) 1374 { 1375 if (pci_is_managed(pdev)) 1376 return devres_find(&pdev->dev, pcim_release, NULL, NULL); 1377 return NULL; 1378 } 1379 1380 /** 1381 * pcim_enable_device - Managed pci_enable_device() 1382 * @pdev: PCI device to be initialized 1383 * 1384 * Managed pci_enable_device(). 1385 */ 1386 int pcim_enable_device(struct pci_dev *pdev) 1387 { 1388 struct pci_devres *dr; 1389 int rc; 1390 1391 dr = get_pci_dr(pdev); 1392 if (unlikely(!dr)) 1393 return -ENOMEM; 1394 if (dr->enabled) 1395 return 0; 1396 1397 rc = pci_enable_device(pdev); 1398 if (!rc) { 1399 pdev->is_managed = 1; 1400 dr->enabled = 1; 1401 } 1402 return rc; 1403 } 1404 1405 /** 1406 * pcim_pin_device - Pin managed PCI device 1407 * @pdev: PCI device to pin 1408 * 1409 * Pin managed PCI device @pdev. Pinned device won't be disabled on 1410 * driver detach. @pdev must have been enabled with 1411 * pcim_enable_device(). 1412 */ 1413 void pcim_pin_device(struct pci_dev *pdev) 1414 { 1415 struct pci_devres *dr; 1416 1417 dr = find_pci_dr(pdev); 1418 WARN_ON(!dr || !dr->enabled); 1419 if (dr) 1420 dr->pinned = 1; 1421 } 1422 1423 /* 1424 * pcibios_add_device - provide arch specific hooks when adding device dev 1425 * @dev: the PCI device being added 1426 * 1427 * Permits the platform to provide architecture specific functionality when 1428 * devices are added. This is the default implementation. Architecture 1429 * implementations can override this. 1430 */ 1431 int __weak pcibios_add_device (struct pci_dev *dev) 1432 { 1433 return 0; 1434 } 1435 1436 /** 1437 * pcibios_release_device - provide arch specific hooks when releasing device dev 1438 * @dev: the PCI device being released 1439 * 1440 * Permits the platform to provide architecture specific functionality when 1441 * devices are released. This is the default implementation. Architecture 1442 * implementations can override this. 1443 */ 1444 void __weak pcibios_release_device(struct pci_dev *dev) {} 1445 1446 /** 1447 * pcibios_disable_device - disable arch specific PCI resources for device dev 1448 * @dev: the PCI device to disable 1449 * 1450 * Disables architecture specific PCI resources for the device. This 1451 * is the default implementation. Architecture implementations can 1452 * override this. 1453 */ 1454 void __weak pcibios_disable_device (struct pci_dev *dev) {} 1455 1456 static void do_pci_disable_device(struct pci_dev *dev) 1457 { 1458 u16 pci_command; 1459 1460 pci_read_config_word(dev, PCI_COMMAND, &pci_command); 1461 if (pci_command & PCI_COMMAND_MASTER) { 1462 pci_command &= ~PCI_COMMAND_MASTER; 1463 pci_write_config_word(dev, PCI_COMMAND, pci_command); 1464 } 1465 1466 pcibios_disable_device(dev); 1467 } 1468 1469 /** 1470 * pci_disable_enabled_device - Disable device without updating enable_cnt 1471 * @dev: PCI device to disable 1472 * 1473 * NOTE: This function is a backend of PCI power management routines and is 1474 * not supposed to be called drivers. 1475 */ 1476 void pci_disable_enabled_device(struct pci_dev *dev) 1477 { 1478 if (pci_is_enabled(dev)) 1479 do_pci_disable_device(dev); 1480 } 1481 1482 /** 1483 * pci_disable_device - Disable PCI device after use 1484 * @dev: PCI device to be disabled 1485 * 1486 * Signal to the system that the PCI device is not in use by the system 1487 * anymore. This only involves disabling PCI bus-mastering, if active. 1488 * 1489 * Note we don't actually disable the device until all callers of 1490 * pci_enable_device() have called pci_disable_device(). 1491 */ 1492 void 1493 pci_disable_device(struct pci_dev *dev) 1494 { 1495 struct pci_devres *dr; 1496 1497 dr = find_pci_dr(dev); 1498 if (dr) 1499 dr->enabled = 0; 1500 1501 dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0, 1502 "disabling already-disabled device"); 1503 1504 if (atomic_dec_return(&dev->enable_cnt) != 0) 1505 return; 1506 1507 do_pci_disable_device(dev); 1508 1509 dev->is_busmaster = 0; 1510 } 1511 1512 /** 1513 * pcibios_set_pcie_reset_state - set reset state for device dev 1514 * @dev: the PCIe device reset 1515 * @state: Reset state to enter into 1516 * 1517 * 1518 * Sets the PCIe reset state for the device. This is the default 1519 * implementation. Architecture implementations can override this. 1520 */ 1521 int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev, 1522 enum pcie_reset_state state) 1523 { 1524 return -EINVAL; 1525 } 1526 1527 /** 1528 * pci_set_pcie_reset_state - set reset state for device dev 1529 * @dev: the PCIe device reset 1530 * @state: Reset state to enter into 1531 * 1532 * 1533 * Sets the PCI reset state for the device. 1534 */ 1535 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state) 1536 { 1537 return pcibios_set_pcie_reset_state(dev, state); 1538 } 1539 1540 /** 1541 * pci_check_pme_status - Check if given device has generated PME. 1542 * @dev: Device to check. 1543 * 1544 * Check the PME status of the device and if set, clear it and clear PME enable 1545 * (if set). Return 'true' if PME status and PME enable were both set or 1546 * 'false' otherwise. 1547 */ 1548 bool pci_check_pme_status(struct pci_dev *dev) 1549 { 1550 int pmcsr_pos; 1551 u16 pmcsr; 1552 bool ret = false; 1553 1554 if (!dev->pm_cap) 1555 return false; 1556 1557 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL; 1558 pci_read_config_word(dev, pmcsr_pos, &pmcsr); 1559 if (!(pmcsr & PCI_PM_CTRL_PME_STATUS)) 1560 return false; 1561 1562 /* Clear PME status. */ 1563 pmcsr |= PCI_PM_CTRL_PME_STATUS; 1564 if (pmcsr & PCI_PM_CTRL_PME_ENABLE) { 1565 /* Disable PME to avoid interrupt flood. */ 1566 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE; 1567 ret = true; 1568 } 1569 1570 pci_write_config_word(dev, pmcsr_pos, pmcsr); 1571 1572 return ret; 1573 } 1574 1575 /** 1576 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set. 1577 * @dev: Device to handle. 1578 * @pme_poll_reset: Whether or not to reset the device's pme_poll flag. 1579 * 1580 * Check if @dev has generated PME and queue a resume request for it in that 1581 * case. 1582 */ 1583 static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset) 1584 { 1585 if (pme_poll_reset && dev->pme_poll) 1586 dev->pme_poll = false; 1587 1588 if (pci_check_pme_status(dev)) { 1589 pci_wakeup_event(dev); 1590 pm_request_resume(&dev->dev); 1591 } 1592 return 0; 1593 } 1594 1595 /** 1596 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary. 1597 * @bus: Top bus of the subtree to walk. 1598 */ 1599 void pci_pme_wakeup_bus(struct pci_bus *bus) 1600 { 1601 if (bus) 1602 pci_walk_bus(bus, pci_pme_wakeup, (void *)true); 1603 } 1604 1605 1606 /** 1607 * pci_pme_capable - check the capability of PCI device to generate PME# 1608 * @dev: PCI device to handle. 1609 * @state: PCI state from which device will issue PME#. 1610 */ 1611 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state) 1612 { 1613 if (!dev->pm_cap) 1614 return false; 1615 1616 return !!(dev->pme_support & (1 << state)); 1617 } 1618 1619 static void pci_pme_list_scan(struct work_struct *work) 1620 { 1621 struct pci_pme_device *pme_dev, *n; 1622 1623 mutex_lock(&pci_pme_list_mutex); 1624 if (!list_empty(&pci_pme_list)) { 1625 list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) { 1626 if (pme_dev->dev->pme_poll) { 1627 struct pci_dev *bridge; 1628 1629 bridge = pme_dev->dev->bus->self; 1630 /* 1631 * If bridge is in low power state, the 1632 * configuration space of subordinate devices 1633 * may be not accessible 1634 */ 1635 if (bridge && bridge->current_state != PCI_D0) 1636 continue; 1637 pci_pme_wakeup(pme_dev->dev, NULL); 1638 } else { 1639 list_del(&pme_dev->list); 1640 kfree(pme_dev); 1641 } 1642 } 1643 if (!list_empty(&pci_pme_list)) 1644 schedule_delayed_work(&pci_pme_work, 1645 msecs_to_jiffies(PME_TIMEOUT)); 1646 } 1647 mutex_unlock(&pci_pme_list_mutex); 1648 } 1649 1650 /** 1651 * pci_pme_active - enable or disable PCI device's PME# function 1652 * @dev: PCI device to handle. 1653 * @enable: 'true' to enable PME# generation; 'false' to disable it. 1654 * 1655 * The caller must verify that the device is capable of generating PME# before 1656 * calling this function with @enable equal to 'true'. 1657 */ 1658 void pci_pme_active(struct pci_dev *dev, bool enable) 1659 { 1660 u16 pmcsr; 1661 1662 if (!dev->pme_support) 1663 return; 1664 1665 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); 1666 /* Clear PME_Status by writing 1 to it and enable PME# */ 1667 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE; 1668 if (!enable) 1669 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE; 1670 1671 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); 1672 1673 /* 1674 * PCI (as opposed to PCIe) PME requires that the device have 1675 * its PME# line hooked up correctly. Not all hardware vendors 1676 * do this, so the PME never gets delivered and the device 1677 * remains asleep. The easiest way around this is to 1678 * periodically walk the list of suspended devices and check 1679 * whether any have their PME flag set. The assumption is that 1680 * we'll wake up often enough anyway that this won't be a huge 1681 * hit, and the power savings from the devices will still be a 1682 * win. 1683 * 1684 * Although PCIe uses in-band PME message instead of PME# line 1685 * to report PME, PME does not work for some PCIe devices in 1686 * reality. For example, there are devices that set their PME 1687 * status bits, but don't really bother to send a PME message; 1688 * there are PCI Express Root Ports that don't bother to 1689 * trigger interrupts when they receive PME messages from the 1690 * devices below. So PME poll is used for PCIe devices too. 1691 */ 1692 1693 if (dev->pme_poll) { 1694 struct pci_pme_device *pme_dev; 1695 if (enable) { 1696 pme_dev = kmalloc(sizeof(struct pci_pme_device), 1697 GFP_KERNEL); 1698 if (!pme_dev) { 1699 dev_warn(&dev->dev, "can't enable PME#\n"); 1700 return; 1701 } 1702 pme_dev->dev = dev; 1703 mutex_lock(&pci_pme_list_mutex); 1704 list_add(&pme_dev->list, &pci_pme_list); 1705 if (list_is_singular(&pci_pme_list)) 1706 schedule_delayed_work(&pci_pme_work, 1707 msecs_to_jiffies(PME_TIMEOUT)); 1708 mutex_unlock(&pci_pme_list_mutex); 1709 } else { 1710 mutex_lock(&pci_pme_list_mutex); 1711 list_for_each_entry(pme_dev, &pci_pme_list, list) { 1712 if (pme_dev->dev == dev) { 1713 list_del(&pme_dev->list); 1714 kfree(pme_dev); 1715 break; 1716 } 1717 } 1718 mutex_unlock(&pci_pme_list_mutex); 1719 } 1720 } 1721 1722 dev_dbg(&dev->dev, "PME# %s\n", enable ? "enabled" : "disabled"); 1723 } 1724 1725 /** 1726 * __pci_enable_wake - enable PCI device as wakeup event source 1727 * @dev: PCI device affected 1728 * @state: PCI state from which device will issue wakeup events 1729 * @runtime: True if the events are to be generated at run time 1730 * @enable: True to enable event generation; false to disable 1731 * 1732 * This enables the device as a wakeup event source, or disables it. 1733 * When such events involves platform-specific hooks, those hooks are 1734 * called automatically by this routine. 1735 * 1736 * Devices with legacy power management (no standard PCI PM capabilities) 1737 * always require such platform hooks. 1738 * 1739 * RETURN VALUE: 1740 * 0 is returned on success 1741 * -EINVAL is returned if device is not supposed to wake up the system 1742 * Error code depending on the platform is returned if both the platform and 1743 * the native mechanism fail to enable the generation of wake-up events 1744 */ 1745 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, 1746 bool runtime, bool enable) 1747 { 1748 int ret = 0; 1749 1750 if (enable && !runtime && !device_may_wakeup(&dev->dev)) 1751 return -EINVAL; 1752 1753 /* Don't do the same thing twice in a row for one device. */ 1754 if (!!enable == !!dev->wakeup_prepared) 1755 return 0; 1756 1757 /* 1758 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don 1759 * Anderson we should be doing PME# wake enable followed by ACPI wake 1760 * enable. To disable wake-up we call the platform first, for symmetry. 1761 */ 1762 1763 if (enable) { 1764 int error; 1765 1766 if (pci_pme_capable(dev, state)) 1767 pci_pme_active(dev, true); 1768 else 1769 ret = 1; 1770 error = runtime ? platform_pci_run_wake(dev, true) : 1771 platform_pci_sleep_wake(dev, true); 1772 if (ret) 1773 ret = error; 1774 if (!ret) 1775 dev->wakeup_prepared = true; 1776 } else { 1777 if (runtime) 1778 platform_pci_run_wake(dev, false); 1779 else 1780 platform_pci_sleep_wake(dev, false); 1781 pci_pme_active(dev, false); 1782 dev->wakeup_prepared = false; 1783 } 1784 1785 return ret; 1786 } 1787 EXPORT_SYMBOL(__pci_enable_wake); 1788 1789 /** 1790 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold 1791 * @dev: PCI device to prepare 1792 * @enable: True to enable wake-up event generation; false to disable 1793 * 1794 * Many drivers want the device to wake up the system from D3_hot or D3_cold 1795 * and this function allows them to set that up cleanly - pci_enable_wake() 1796 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI 1797 * ordering constraints. 1798 * 1799 * This function only returns error code if the device is not capable of 1800 * generating PME# from both D3_hot and D3_cold, and the platform is unable to 1801 * enable wake-up power for it. 1802 */ 1803 int pci_wake_from_d3(struct pci_dev *dev, bool enable) 1804 { 1805 return pci_pme_capable(dev, PCI_D3cold) ? 1806 pci_enable_wake(dev, PCI_D3cold, enable) : 1807 pci_enable_wake(dev, PCI_D3hot, enable); 1808 } 1809 1810 /** 1811 * pci_target_state - find an appropriate low power state for a given PCI dev 1812 * @dev: PCI device 1813 * 1814 * Use underlying platform code to find a supported low power state for @dev. 1815 * If the platform can't manage @dev, return the deepest state from which it 1816 * can generate wake events, based on any available PME info. 1817 */ 1818 static pci_power_t pci_target_state(struct pci_dev *dev) 1819 { 1820 pci_power_t target_state = PCI_D3hot; 1821 1822 if (platform_pci_power_manageable(dev)) { 1823 /* 1824 * Call the platform to choose the target state of the device 1825 * and enable wake-up from this state if supported. 1826 */ 1827 pci_power_t state = platform_pci_choose_state(dev); 1828 1829 switch (state) { 1830 case PCI_POWER_ERROR: 1831 case PCI_UNKNOWN: 1832 break; 1833 case PCI_D1: 1834 case PCI_D2: 1835 if (pci_no_d1d2(dev)) 1836 break; 1837 default: 1838 target_state = state; 1839 } 1840 } else if (!dev->pm_cap) { 1841 target_state = PCI_D0; 1842 } else if (device_may_wakeup(&dev->dev)) { 1843 /* 1844 * Find the deepest state from which the device can generate 1845 * wake-up events, make it the target state and enable device 1846 * to generate PME#. 1847 */ 1848 if (dev->pme_support) { 1849 while (target_state 1850 && !(dev->pme_support & (1 << target_state))) 1851 target_state--; 1852 } 1853 } 1854 1855 return target_state; 1856 } 1857 1858 /** 1859 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state 1860 * @dev: Device to handle. 1861 * 1862 * Choose the power state appropriate for the device depending on whether 1863 * it can wake up the system and/or is power manageable by the platform 1864 * (PCI_D3hot is the default) and put the device into that state. 1865 */ 1866 int pci_prepare_to_sleep(struct pci_dev *dev) 1867 { 1868 pci_power_t target_state = pci_target_state(dev); 1869 int error; 1870 1871 if (target_state == PCI_POWER_ERROR) 1872 return -EIO; 1873 1874 /* D3cold during system suspend/hibernate is not supported */ 1875 if (target_state > PCI_D3hot) 1876 target_state = PCI_D3hot; 1877 1878 pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev)); 1879 1880 error = pci_set_power_state(dev, target_state); 1881 1882 if (error) 1883 pci_enable_wake(dev, target_state, false); 1884 1885 return error; 1886 } 1887 1888 /** 1889 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state 1890 * @dev: Device to handle. 1891 * 1892 * Disable device's system wake-up capability and put it into D0. 1893 */ 1894 int pci_back_from_sleep(struct pci_dev *dev) 1895 { 1896 pci_enable_wake(dev, PCI_D0, false); 1897 return pci_set_power_state(dev, PCI_D0); 1898 } 1899 1900 /** 1901 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend. 1902 * @dev: PCI device being suspended. 1903 * 1904 * Prepare @dev to generate wake-up events at run time and put it into a low 1905 * power state. 1906 */ 1907 int pci_finish_runtime_suspend(struct pci_dev *dev) 1908 { 1909 pci_power_t target_state = pci_target_state(dev); 1910 int error; 1911 1912 if (target_state == PCI_POWER_ERROR) 1913 return -EIO; 1914 1915 dev->runtime_d3cold = target_state == PCI_D3cold; 1916 1917 __pci_enable_wake(dev, target_state, true, pci_dev_run_wake(dev)); 1918 1919 error = pci_set_power_state(dev, target_state); 1920 1921 if (error) { 1922 __pci_enable_wake(dev, target_state, true, false); 1923 dev->runtime_d3cold = false; 1924 } 1925 1926 return error; 1927 } 1928 1929 /** 1930 * pci_dev_run_wake - Check if device can generate run-time wake-up events. 1931 * @dev: Device to check. 1932 * 1933 * Return true if the device itself is capable of generating wake-up events 1934 * (through the platform or using the native PCIe PME) or if the device supports 1935 * PME and one of its upstream bridges can generate wake-up events. 1936 */ 1937 bool pci_dev_run_wake(struct pci_dev *dev) 1938 { 1939 struct pci_bus *bus = dev->bus; 1940 1941 if (device_run_wake(&dev->dev)) 1942 return true; 1943 1944 if (!dev->pme_support) 1945 return false; 1946 1947 while (bus->parent) { 1948 struct pci_dev *bridge = bus->self; 1949 1950 if (device_run_wake(&bridge->dev)) 1951 return true; 1952 1953 bus = bus->parent; 1954 } 1955 1956 /* We have reached the root bus. */ 1957 if (bus->bridge) 1958 return device_run_wake(bus->bridge); 1959 1960 return false; 1961 } 1962 EXPORT_SYMBOL_GPL(pci_dev_run_wake); 1963 1964 void pci_config_pm_runtime_get(struct pci_dev *pdev) 1965 { 1966 struct device *dev = &pdev->dev; 1967 struct device *parent = dev->parent; 1968 1969 if (parent) 1970 pm_runtime_get_sync(parent); 1971 pm_runtime_get_noresume(dev); 1972 /* 1973 * pdev->current_state is set to PCI_D3cold during suspending, 1974 * so wait until suspending completes 1975 */ 1976 pm_runtime_barrier(dev); 1977 /* 1978 * Only need to resume devices in D3cold, because config 1979 * registers are still accessible for devices suspended but 1980 * not in D3cold. 1981 */ 1982 if (pdev->current_state == PCI_D3cold) 1983 pm_runtime_resume(dev); 1984 } 1985 1986 void pci_config_pm_runtime_put(struct pci_dev *pdev) 1987 { 1988 struct device *dev = &pdev->dev; 1989 struct device *parent = dev->parent; 1990 1991 pm_runtime_put(dev); 1992 if (parent) 1993 pm_runtime_put_sync(parent); 1994 } 1995 1996 /** 1997 * pci_pm_init - Initialize PM functions of given PCI device 1998 * @dev: PCI device to handle. 1999 */ 2000 void pci_pm_init(struct pci_dev *dev) 2001 { 2002 int pm; 2003 u16 pmc; 2004 2005 pm_runtime_forbid(&dev->dev); 2006 pm_runtime_set_active(&dev->dev); 2007 pm_runtime_enable(&dev->dev); 2008 device_enable_async_suspend(&dev->dev); 2009 dev->wakeup_prepared = false; 2010 2011 dev->pm_cap = 0; 2012 dev->pme_support = 0; 2013 2014 /* find PCI PM capability in list */ 2015 pm = pci_find_capability(dev, PCI_CAP_ID_PM); 2016 if (!pm) 2017 return; 2018 /* Check device's ability to generate PME# */ 2019 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc); 2020 2021 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) { 2022 dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n", 2023 pmc & PCI_PM_CAP_VER_MASK); 2024 return; 2025 } 2026 2027 dev->pm_cap = pm; 2028 dev->d3_delay = PCI_PM_D3_WAIT; 2029 dev->d3cold_delay = PCI_PM_D3COLD_WAIT; 2030 dev->d3cold_allowed = true; 2031 2032 dev->d1_support = false; 2033 dev->d2_support = false; 2034 if (!pci_no_d1d2(dev)) { 2035 if (pmc & PCI_PM_CAP_D1) 2036 dev->d1_support = true; 2037 if (pmc & PCI_PM_CAP_D2) 2038 dev->d2_support = true; 2039 2040 if (dev->d1_support || dev->d2_support) 2041 dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n", 2042 dev->d1_support ? " D1" : "", 2043 dev->d2_support ? " D2" : ""); 2044 } 2045 2046 pmc &= PCI_PM_CAP_PME_MASK; 2047 if (pmc) { 2048 dev_printk(KERN_DEBUG, &dev->dev, 2049 "PME# supported from%s%s%s%s%s\n", 2050 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "", 2051 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "", 2052 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "", 2053 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "", 2054 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : ""); 2055 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT; 2056 dev->pme_poll = true; 2057 /* 2058 * Make device's PM flags reflect the wake-up capability, but 2059 * let the user space enable it to wake up the system as needed. 2060 */ 2061 device_set_wakeup_capable(&dev->dev, true); 2062 /* Disable the PME# generation functionality */ 2063 pci_pme_active(dev, false); 2064 } 2065 } 2066 2067 static void pci_add_saved_cap(struct pci_dev *pci_dev, 2068 struct pci_cap_saved_state *new_cap) 2069 { 2070 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space); 2071 } 2072 2073 /** 2074 * _pci_add_cap_save_buffer - allocate buffer for saving given 2075 * capability registers 2076 * @dev: the PCI device 2077 * @cap: the capability to allocate the buffer for 2078 * @extended: Standard or Extended capability ID 2079 * @size: requested size of the buffer 2080 */ 2081 static int _pci_add_cap_save_buffer(struct pci_dev *dev, u16 cap, 2082 bool extended, unsigned int size) 2083 { 2084 int pos; 2085 struct pci_cap_saved_state *save_state; 2086 2087 if (extended) 2088 pos = pci_find_ext_capability(dev, cap); 2089 else 2090 pos = pci_find_capability(dev, cap); 2091 2092 if (pos <= 0) 2093 return 0; 2094 2095 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL); 2096 if (!save_state) 2097 return -ENOMEM; 2098 2099 save_state->cap.cap_nr = cap; 2100 save_state->cap.cap_extended = extended; 2101 save_state->cap.size = size; 2102 pci_add_saved_cap(dev, save_state); 2103 2104 return 0; 2105 } 2106 2107 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size) 2108 { 2109 return _pci_add_cap_save_buffer(dev, cap, false, size); 2110 } 2111 2112 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, u16 cap, unsigned int size) 2113 { 2114 return _pci_add_cap_save_buffer(dev, cap, true, size); 2115 } 2116 2117 /** 2118 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities 2119 * @dev: the PCI device 2120 */ 2121 void pci_allocate_cap_save_buffers(struct pci_dev *dev) 2122 { 2123 int error; 2124 2125 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP, 2126 PCI_EXP_SAVE_REGS * sizeof(u16)); 2127 if (error) 2128 dev_err(&dev->dev, 2129 "unable to preallocate PCI Express save buffer\n"); 2130 2131 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16)); 2132 if (error) 2133 dev_err(&dev->dev, 2134 "unable to preallocate PCI-X save buffer\n"); 2135 2136 pci_allocate_vc_save_buffers(dev); 2137 } 2138 2139 void pci_free_cap_save_buffers(struct pci_dev *dev) 2140 { 2141 struct pci_cap_saved_state *tmp; 2142 struct hlist_node *n; 2143 2144 hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next) 2145 kfree(tmp); 2146 } 2147 2148 /** 2149 * pci_configure_ari - enable or disable ARI forwarding 2150 * @dev: the PCI device 2151 * 2152 * If @dev and its upstream bridge both support ARI, enable ARI in the 2153 * bridge. Otherwise, disable ARI in the bridge. 2154 */ 2155 void pci_configure_ari(struct pci_dev *dev) 2156 { 2157 u32 cap; 2158 struct pci_dev *bridge; 2159 2160 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn) 2161 return; 2162 2163 bridge = dev->bus->self; 2164 if (!bridge) 2165 return; 2166 2167 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap); 2168 if (!(cap & PCI_EXP_DEVCAP2_ARI)) 2169 return; 2170 2171 if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) { 2172 pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2, 2173 PCI_EXP_DEVCTL2_ARI); 2174 bridge->ari_enabled = 1; 2175 } else { 2176 pcie_capability_clear_word(bridge, PCI_EXP_DEVCTL2, 2177 PCI_EXP_DEVCTL2_ARI); 2178 bridge->ari_enabled = 0; 2179 } 2180 } 2181 2182 static int pci_acs_enable; 2183 2184 /** 2185 * pci_request_acs - ask for ACS to be enabled if supported 2186 */ 2187 void pci_request_acs(void) 2188 { 2189 pci_acs_enable = 1; 2190 } 2191 2192 /** 2193 * pci_enable_acs - enable ACS if hardware support it 2194 * @dev: the PCI device 2195 */ 2196 void pci_enable_acs(struct pci_dev *dev) 2197 { 2198 int pos; 2199 u16 cap; 2200 u16 ctrl; 2201 2202 if (!pci_acs_enable) 2203 return; 2204 2205 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS); 2206 if (!pos) 2207 return; 2208 2209 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap); 2210 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl); 2211 2212 /* Source Validation */ 2213 ctrl |= (cap & PCI_ACS_SV); 2214 2215 /* P2P Request Redirect */ 2216 ctrl |= (cap & PCI_ACS_RR); 2217 2218 /* P2P Completion Redirect */ 2219 ctrl |= (cap & PCI_ACS_CR); 2220 2221 /* Upstream Forwarding */ 2222 ctrl |= (cap & PCI_ACS_UF); 2223 2224 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl); 2225 } 2226 2227 static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags) 2228 { 2229 int pos; 2230 u16 cap, ctrl; 2231 2232 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ACS); 2233 if (!pos) 2234 return false; 2235 2236 /* 2237 * Except for egress control, capabilities are either required 2238 * or only required if controllable. Features missing from the 2239 * capability field can therefore be assumed as hard-wired enabled. 2240 */ 2241 pci_read_config_word(pdev, pos + PCI_ACS_CAP, &cap); 2242 acs_flags &= (cap | PCI_ACS_EC); 2243 2244 pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl); 2245 return (ctrl & acs_flags) == acs_flags; 2246 } 2247 2248 /** 2249 * pci_acs_enabled - test ACS against required flags for a given device 2250 * @pdev: device to test 2251 * @acs_flags: required PCI ACS flags 2252 * 2253 * Return true if the device supports the provided flags. Automatically 2254 * filters out flags that are not implemented on multifunction devices. 2255 * 2256 * Note that this interface checks the effective ACS capabilities of the 2257 * device rather than the actual capabilities. For instance, most single 2258 * function endpoints are not required to support ACS because they have no 2259 * opportunity for peer-to-peer access. We therefore return 'true' 2260 * regardless of whether the device exposes an ACS capability. This makes 2261 * it much easier for callers of this function to ignore the actual type 2262 * or topology of the device when testing ACS support. 2263 */ 2264 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags) 2265 { 2266 int ret; 2267 2268 ret = pci_dev_specific_acs_enabled(pdev, acs_flags); 2269 if (ret >= 0) 2270 return ret > 0; 2271 2272 /* 2273 * Conventional PCI and PCI-X devices never support ACS, either 2274 * effectively or actually. The shared bus topology implies that 2275 * any device on the bus can receive or snoop DMA. 2276 */ 2277 if (!pci_is_pcie(pdev)) 2278 return false; 2279 2280 switch (pci_pcie_type(pdev)) { 2281 /* 2282 * PCI/X-to-PCIe bridges are not specifically mentioned by the spec, 2283 * but since their primary interface is PCI/X, we conservatively 2284 * handle them as we would a non-PCIe device. 2285 */ 2286 case PCI_EXP_TYPE_PCIE_BRIDGE: 2287 /* 2288 * PCIe 3.0, 6.12.1 excludes ACS on these devices. "ACS is never 2289 * applicable... must never implement an ACS Extended Capability...". 2290 * This seems arbitrary, but we take a conservative interpretation 2291 * of this statement. 2292 */ 2293 case PCI_EXP_TYPE_PCI_BRIDGE: 2294 case PCI_EXP_TYPE_RC_EC: 2295 return false; 2296 /* 2297 * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should 2298 * implement ACS in order to indicate their peer-to-peer capabilities, 2299 * regardless of whether they are single- or multi-function devices. 2300 */ 2301 case PCI_EXP_TYPE_DOWNSTREAM: 2302 case PCI_EXP_TYPE_ROOT_PORT: 2303 return pci_acs_flags_enabled(pdev, acs_flags); 2304 /* 2305 * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be 2306 * implemented by the remaining PCIe types to indicate peer-to-peer 2307 * capabilities, but only when they are part of a multifunction 2308 * device. The footnote for section 6.12 indicates the specific 2309 * PCIe types included here. 2310 */ 2311 case PCI_EXP_TYPE_ENDPOINT: 2312 case PCI_EXP_TYPE_UPSTREAM: 2313 case PCI_EXP_TYPE_LEG_END: 2314 case PCI_EXP_TYPE_RC_END: 2315 if (!pdev->multifunction) 2316 break; 2317 2318 return pci_acs_flags_enabled(pdev, acs_flags); 2319 } 2320 2321 /* 2322 * PCIe 3.0, 6.12.1.3 specifies no ACS capabilities are applicable 2323 * to single function devices with the exception of downstream ports. 2324 */ 2325 return true; 2326 } 2327 2328 /** 2329 * pci_acs_path_enable - test ACS flags from start to end in a hierarchy 2330 * @start: starting downstream device 2331 * @end: ending upstream device or NULL to search to the root bus 2332 * @acs_flags: required flags 2333 * 2334 * Walk up a device tree from start to end testing PCI ACS support. If 2335 * any step along the way does not support the required flags, return false. 2336 */ 2337 bool pci_acs_path_enabled(struct pci_dev *start, 2338 struct pci_dev *end, u16 acs_flags) 2339 { 2340 struct pci_dev *pdev, *parent = start; 2341 2342 do { 2343 pdev = parent; 2344 2345 if (!pci_acs_enabled(pdev, acs_flags)) 2346 return false; 2347 2348 if (pci_is_root_bus(pdev->bus)) 2349 return (end == NULL); 2350 2351 parent = pdev->bus->self; 2352 } while (pdev != end); 2353 2354 return true; 2355 } 2356 2357 /** 2358 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge 2359 * @dev: the PCI device 2360 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD) 2361 * 2362 * Perform INTx swizzling for a device behind one level of bridge. This is 2363 * required by section 9.1 of the PCI-to-PCI bridge specification for devices 2364 * behind bridges on add-in cards. For devices with ARI enabled, the slot 2365 * number is always 0 (see the Implementation Note in section 2.2.8.1 of 2366 * the PCI Express Base Specification, Revision 2.1) 2367 */ 2368 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin) 2369 { 2370 int slot; 2371 2372 if (pci_ari_enabled(dev->bus)) 2373 slot = 0; 2374 else 2375 slot = PCI_SLOT(dev->devfn); 2376 2377 return (((pin - 1) + slot) % 4) + 1; 2378 } 2379 2380 int 2381 pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge) 2382 { 2383 u8 pin; 2384 2385 pin = dev->pin; 2386 if (!pin) 2387 return -1; 2388 2389 while (!pci_is_root_bus(dev->bus)) { 2390 pin = pci_swizzle_interrupt_pin(dev, pin); 2391 dev = dev->bus->self; 2392 } 2393 *bridge = dev; 2394 return pin; 2395 } 2396 2397 /** 2398 * pci_common_swizzle - swizzle INTx all the way to root bridge 2399 * @dev: the PCI device 2400 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD) 2401 * 2402 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI 2403 * bridges all the way up to a PCI root bus. 2404 */ 2405 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp) 2406 { 2407 u8 pin = *pinp; 2408 2409 while (!pci_is_root_bus(dev->bus)) { 2410 pin = pci_swizzle_interrupt_pin(dev, pin); 2411 dev = dev->bus->self; 2412 } 2413 *pinp = pin; 2414 return PCI_SLOT(dev->devfn); 2415 } 2416 2417 /** 2418 * pci_release_region - Release a PCI bar 2419 * @pdev: PCI device whose resources were previously reserved by pci_request_region 2420 * @bar: BAR to release 2421 * 2422 * Releases the PCI I/O and memory resources previously reserved by a 2423 * successful call to pci_request_region. Call this function only 2424 * after all use of the PCI regions has ceased. 2425 */ 2426 void pci_release_region(struct pci_dev *pdev, int bar) 2427 { 2428 struct pci_devres *dr; 2429 2430 if (pci_resource_len(pdev, bar) == 0) 2431 return; 2432 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) 2433 release_region(pci_resource_start(pdev, bar), 2434 pci_resource_len(pdev, bar)); 2435 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) 2436 release_mem_region(pci_resource_start(pdev, bar), 2437 pci_resource_len(pdev, bar)); 2438 2439 dr = find_pci_dr(pdev); 2440 if (dr) 2441 dr->region_mask &= ~(1 << bar); 2442 } 2443 2444 /** 2445 * __pci_request_region - Reserved PCI I/O and memory resource 2446 * @pdev: PCI device whose resources are to be reserved 2447 * @bar: BAR to be reserved 2448 * @res_name: Name to be associated with resource. 2449 * @exclusive: whether the region access is exclusive or not 2450 * 2451 * Mark the PCI region associated with PCI device @pdev BR @bar as 2452 * being reserved by owner @res_name. Do not access any 2453 * address inside the PCI regions unless this call returns 2454 * successfully. 2455 * 2456 * If @exclusive is set, then the region is marked so that userspace 2457 * is explicitly not allowed to map the resource via /dev/mem or 2458 * sysfs MMIO access. 2459 * 2460 * Returns 0 on success, or %EBUSY on error. A warning 2461 * message is also printed on failure. 2462 */ 2463 static int __pci_request_region(struct pci_dev *pdev, int bar, const char *res_name, 2464 int exclusive) 2465 { 2466 struct pci_devres *dr; 2467 2468 if (pci_resource_len(pdev, bar) == 0) 2469 return 0; 2470 2471 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) { 2472 if (!request_region(pci_resource_start(pdev, bar), 2473 pci_resource_len(pdev, bar), res_name)) 2474 goto err_out; 2475 } 2476 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) { 2477 if (!__request_mem_region(pci_resource_start(pdev, bar), 2478 pci_resource_len(pdev, bar), res_name, 2479 exclusive)) 2480 goto err_out; 2481 } 2482 2483 dr = find_pci_dr(pdev); 2484 if (dr) 2485 dr->region_mask |= 1 << bar; 2486 2487 return 0; 2488 2489 err_out: 2490 dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar, 2491 &pdev->resource[bar]); 2492 return -EBUSY; 2493 } 2494 2495 /** 2496 * pci_request_region - Reserve PCI I/O and memory resource 2497 * @pdev: PCI device whose resources are to be reserved 2498 * @bar: BAR to be reserved 2499 * @res_name: Name to be associated with resource 2500 * 2501 * Mark the PCI region associated with PCI device @pdev BAR @bar as 2502 * being reserved by owner @res_name. Do not access any 2503 * address inside the PCI regions unless this call returns 2504 * successfully. 2505 * 2506 * Returns 0 on success, or %EBUSY on error. A warning 2507 * message is also printed on failure. 2508 */ 2509 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) 2510 { 2511 return __pci_request_region(pdev, bar, res_name, 0); 2512 } 2513 2514 /** 2515 * pci_request_region_exclusive - Reserved PCI I/O and memory resource 2516 * @pdev: PCI device whose resources are to be reserved 2517 * @bar: BAR to be reserved 2518 * @res_name: Name to be associated with resource. 2519 * 2520 * Mark the PCI region associated with PCI device @pdev BR @bar as 2521 * being reserved by owner @res_name. Do not access any 2522 * address inside the PCI regions unless this call returns 2523 * successfully. 2524 * 2525 * Returns 0 on success, or %EBUSY on error. A warning 2526 * message is also printed on failure. 2527 * 2528 * The key difference that _exclusive makes it that userspace is 2529 * explicitly not allowed to map the resource via /dev/mem or 2530 * sysfs. 2531 */ 2532 int pci_request_region_exclusive(struct pci_dev *pdev, int bar, const char *res_name) 2533 { 2534 return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE); 2535 } 2536 /** 2537 * pci_release_selected_regions - Release selected PCI I/O and memory resources 2538 * @pdev: PCI device whose resources were previously reserved 2539 * @bars: Bitmask of BARs to be released 2540 * 2541 * Release selected PCI I/O and memory resources previously reserved. 2542 * Call this function only after all use of the PCI regions has ceased. 2543 */ 2544 void pci_release_selected_regions(struct pci_dev *pdev, int bars) 2545 { 2546 int i; 2547 2548 for (i = 0; i < 6; i++) 2549 if (bars & (1 << i)) 2550 pci_release_region(pdev, i); 2551 } 2552 2553 static int __pci_request_selected_regions(struct pci_dev *pdev, int bars, 2554 const char *res_name, int excl) 2555 { 2556 int i; 2557 2558 for (i = 0; i < 6; i++) 2559 if (bars & (1 << i)) 2560 if (__pci_request_region(pdev, i, res_name, excl)) 2561 goto err_out; 2562 return 0; 2563 2564 err_out: 2565 while(--i >= 0) 2566 if (bars & (1 << i)) 2567 pci_release_region(pdev, i); 2568 2569 return -EBUSY; 2570 } 2571 2572 2573 /** 2574 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources 2575 * @pdev: PCI device whose resources are to be reserved 2576 * @bars: Bitmask of BARs to be requested 2577 * @res_name: Name to be associated with resource 2578 */ 2579 int pci_request_selected_regions(struct pci_dev *pdev, int bars, 2580 const char *res_name) 2581 { 2582 return __pci_request_selected_regions(pdev, bars, res_name, 0); 2583 } 2584 2585 int pci_request_selected_regions_exclusive(struct pci_dev *pdev, 2586 int bars, const char *res_name) 2587 { 2588 return __pci_request_selected_regions(pdev, bars, res_name, 2589 IORESOURCE_EXCLUSIVE); 2590 } 2591 2592 /** 2593 * pci_release_regions - Release reserved PCI I/O and memory resources 2594 * @pdev: PCI device whose resources were previously reserved by pci_request_regions 2595 * 2596 * Releases all PCI I/O and memory resources previously reserved by a 2597 * successful call to pci_request_regions. Call this function only 2598 * after all use of the PCI regions has ceased. 2599 */ 2600 2601 void pci_release_regions(struct pci_dev *pdev) 2602 { 2603 pci_release_selected_regions(pdev, (1 << 6) - 1); 2604 } 2605 2606 /** 2607 * pci_request_regions - Reserved PCI I/O and memory resources 2608 * @pdev: PCI device whose resources are to be reserved 2609 * @res_name: Name to be associated with resource. 2610 * 2611 * Mark all PCI regions associated with PCI device @pdev as 2612 * being reserved by owner @res_name. Do not access any 2613 * address inside the PCI regions unless this call returns 2614 * successfully. 2615 * 2616 * Returns 0 on success, or %EBUSY on error. A warning 2617 * message is also printed on failure. 2618 */ 2619 int pci_request_regions(struct pci_dev *pdev, const char *res_name) 2620 { 2621 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name); 2622 } 2623 2624 /** 2625 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources 2626 * @pdev: PCI device whose resources are to be reserved 2627 * @res_name: Name to be associated with resource. 2628 * 2629 * Mark all PCI regions associated with PCI device @pdev as 2630 * being reserved by owner @res_name. Do not access any 2631 * address inside the PCI regions unless this call returns 2632 * successfully. 2633 * 2634 * pci_request_regions_exclusive() will mark the region so that 2635 * /dev/mem and the sysfs MMIO access will not be allowed. 2636 * 2637 * Returns 0 on success, or %EBUSY on error. A warning 2638 * message is also printed on failure. 2639 */ 2640 int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name) 2641 { 2642 return pci_request_selected_regions_exclusive(pdev, 2643 ((1 << 6) - 1), res_name); 2644 } 2645 2646 static void __pci_set_master(struct pci_dev *dev, bool enable) 2647 { 2648 u16 old_cmd, cmd; 2649 2650 pci_read_config_word(dev, PCI_COMMAND, &old_cmd); 2651 if (enable) 2652 cmd = old_cmd | PCI_COMMAND_MASTER; 2653 else 2654 cmd = old_cmd & ~PCI_COMMAND_MASTER; 2655 if (cmd != old_cmd) { 2656 dev_dbg(&dev->dev, "%s bus mastering\n", 2657 enable ? "enabling" : "disabling"); 2658 pci_write_config_word(dev, PCI_COMMAND, cmd); 2659 } 2660 dev->is_busmaster = enable; 2661 } 2662 2663 /** 2664 * pcibios_setup - process "pci=" kernel boot arguments 2665 * @str: string used to pass in "pci=" kernel boot arguments 2666 * 2667 * Process kernel boot arguments. This is the default implementation. 2668 * Architecture specific implementations can override this as necessary. 2669 */ 2670 char * __weak __init pcibios_setup(char *str) 2671 { 2672 return str; 2673 } 2674 2675 /** 2676 * pcibios_set_master - enable PCI bus-mastering for device dev 2677 * @dev: the PCI device to enable 2678 * 2679 * Enables PCI bus-mastering for the device. This is the default 2680 * implementation. Architecture specific implementations can override 2681 * this if necessary. 2682 */ 2683 void __weak pcibios_set_master(struct pci_dev *dev) 2684 { 2685 u8 lat; 2686 2687 /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */ 2688 if (pci_is_pcie(dev)) 2689 return; 2690 2691 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat); 2692 if (lat < 16) 2693 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency; 2694 else if (lat > pcibios_max_latency) 2695 lat = pcibios_max_latency; 2696 else 2697 return; 2698 2699 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat); 2700 } 2701 2702 /** 2703 * pci_set_master - enables bus-mastering for device dev 2704 * @dev: the PCI device to enable 2705 * 2706 * Enables bus-mastering on the device and calls pcibios_set_master() 2707 * to do the needed arch specific settings. 2708 */ 2709 void pci_set_master(struct pci_dev *dev) 2710 { 2711 __pci_set_master(dev, true); 2712 pcibios_set_master(dev); 2713 } 2714 2715 /** 2716 * pci_clear_master - disables bus-mastering for device dev 2717 * @dev: the PCI device to disable 2718 */ 2719 void pci_clear_master(struct pci_dev *dev) 2720 { 2721 __pci_set_master(dev, false); 2722 } 2723 2724 /** 2725 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed 2726 * @dev: the PCI device for which MWI is to be enabled 2727 * 2728 * Helper function for pci_set_mwi. 2729 * Originally copied from drivers/net/acenic.c. 2730 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. 2731 * 2732 * RETURNS: An appropriate -ERRNO error value on error, or zero for success. 2733 */ 2734 int pci_set_cacheline_size(struct pci_dev *dev) 2735 { 2736 u8 cacheline_size; 2737 2738 if (!pci_cache_line_size) 2739 return -EINVAL; 2740 2741 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be 2742 equal to or multiple of the right value. */ 2743 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); 2744 if (cacheline_size >= pci_cache_line_size && 2745 (cacheline_size % pci_cache_line_size) == 0) 2746 return 0; 2747 2748 /* Write the correct value. */ 2749 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size); 2750 /* Read it back. */ 2751 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); 2752 if (cacheline_size == pci_cache_line_size) 2753 return 0; 2754 2755 dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not " 2756 "supported\n", pci_cache_line_size << 2); 2757 2758 return -EINVAL; 2759 } 2760 EXPORT_SYMBOL_GPL(pci_set_cacheline_size); 2761 2762 #ifdef PCI_DISABLE_MWI 2763 int pci_set_mwi(struct pci_dev *dev) 2764 { 2765 return 0; 2766 } 2767 2768 int pci_try_set_mwi(struct pci_dev *dev) 2769 { 2770 return 0; 2771 } 2772 2773 void pci_clear_mwi(struct pci_dev *dev) 2774 { 2775 } 2776 2777 #else 2778 2779 /** 2780 * pci_set_mwi - enables memory-write-invalidate PCI transaction 2781 * @dev: the PCI device for which MWI is enabled 2782 * 2783 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. 2784 * 2785 * RETURNS: An appropriate -ERRNO error value on error, or zero for success. 2786 */ 2787 int 2788 pci_set_mwi(struct pci_dev *dev) 2789 { 2790 int rc; 2791 u16 cmd; 2792 2793 rc = pci_set_cacheline_size(dev); 2794 if (rc) 2795 return rc; 2796 2797 pci_read_config_word(dev, PCI_COMMAND, &cmd); 2798 if (! (cmd & PCI_COMMAND_INVALIDATE)) { 2799 dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n"); 2800 cmd |= PCI_COMMAND_INVALIDATE; 2801 pci_write_config_word(dev, PCI_COMMAND, cmd); 2802 } 2803 2804 return 0; 2805 } 2806 2807 /** 2808 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction 2809 * @dev: the PCI device for which MWI is enabled 2810 * 2811 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. 2812 * Callers are not required to check the return value. 2813 * 2814 * RETURNS: An appropriate -ERRNO error value on error, or zero for success. 2815 */ 2816 int pci_try_set_mwi(struct pci_dev *dev) 2817 { 2818 int rc = pci_set_mwi(dev); 2819 return rc; 2820 } 2821 2822 /** 2823 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev 2824 * @dev: the PCI device to disable 2825 * 2826 * Disables PCI Memory-Write-Invalidate transaction on the device 2827 */ 2828 void 2829 pci_clear_mwi(struct pci_dev *dev) 2830 { 2831 u16 cmd; 2832 2833 pci_read_config_word(dev, PCI_COMMAND, &cmd); 2834 if (cmd & PCI_COMMAND_INVALIDATE) { 2835 cmd &= ~PCI_COMMAND_INVALIDATE; 2836 pci_write_config_word(dev, PCI_COMMAND, cmd); 2837 } 2838 } 2839 #endif /* ! PCI_DISABLE_MWI */ 2840 2841 /** 2842 * pci_intx - enables/disables PCI INTx for device dev 2843 * @pdev: the PCI device to operate on 2844 * @enable: boolean: whether to enable or disable PCI INTx 2845 * 2846 * Enables/disables PCI INTx for device dev 2847 */ 2848 void 2849 pci_intx(struct pci_dev *pdev, int enable) 2850 { 2851 u16 pci_command, new; 2852 2853 pci_read_config_word(pdev, PCI_COMMAND, &pci_command); 2854 2855 if (enable) { 2856 new = pci_command & ~PCI_COMMAND_INTX_DISABLE; 2857 } else { 2858 new = pci_command | PCI_COMMAND_INTX_DISABLE; 2859 } 2860 2861 if (new != pci_command) { 2862 struct pci_devres *dr; 2863 2864 pci_write_config_word(pdev, PCI_COMMAND, new); 2865 2866 dr = find_pci_dr(pdev); 2867 if (dr && !dr->restore_intx) { 2868 dr->restore_intx = 1; 2869 dr->orig_intx = !enable; 2870 } 2871 } 2872 } 2873 2874 /** 2875 * pci_intx_mask_supported - probe for INTx masking support 2876 * @dev: the PCI device to operate on 2877 * 2878 * Check if the device dev support INTx masking via the config space 2879 * command word. 2880 */ 2881 bool pci_intx_mask_supported(struct pci_dev *dev) 2882 { 2883 bool mask_supported = false; 2884 u16 orig, new; 2885 2886 if (dev->broken_intx_masking) 2887 return false; 2888 2889 pci_cfg_access_lock(dev); 2890 2891 pci_read_config_word(dev, PCI_COMMAND, &orig); 2892 pci_write_config_word(dev, PCI_COMMAND, 2893 orig ^ PCI_COMMAND_INTX_DISABLE); 2894 pci_read_config_word(dev, PCI_COMMAND, &new); 2895 2896 /* 2897 * There's no way to protect against hardware bugs or detect them 2898 * reliably, but as long as we know what the value should be, let's 2899 * go ahead and check it. 2900 */ 2901 if ((new ^ orig) & ~PCI_COMMAND_INTX_DISABLE) { 2902 dev_err(&dev->dev, "Command register changed from " 2903 "0x%x to 0x%x: driver or hardware bug?\n", orig, new); 2904 } else if ((new ^ orig) & PCI_COMMAND_INTX_DISABLE) { 2905 mask_supported = true; 2906 pci_write_config_word(dev, PCI_COMMAND, orig); 2907 } 2908 2909 pci_cfg_access_unlock(dev); 2910 return mask_supported; 2911 } 2912 EXPORT_SYMBOL_GPL(pci_intx_mask_supported); 2913 2914 static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask) 2915 { 2916 struct pci_bus *bus = dev->bus; 2917 bool mask_updated = true; 2918 u32 cmd_status_dword; 2919 u16 origcmd, newcmd; 2920 unsigned long flags; 2921 bool irq_pending; 2922 2923 /* 2924 * We do a single dword read to retrieve both command and status. 2925 * Document assumptions that make this possible. 2926 */ 2927 BUILD_BUG_ON(PCI_COMMAND % 4); 2928 BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS); 2929 2930 raw_spin_lock_irqsave(&pci_lock, flags); 2931 2932 bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword); 2933 2934 irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT; 2935 2936 /* 2937 * Check interrupt status register to see whether our device 2938 * triggered the interrupt (when masking) or the next IRQ is 2939 * already pending (when unmasking). 2940 */ 2941 if (mask != irq_pending) { 2942 mask_updated = false; 2943 goto done; 2944 } 2945 2946 origcmd = cmd_status_dword; 2947 newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE; 2948 if (mask) 2949 newcmd |= PCI_COMMAND_INTX_DISABLE; 2950 if (newcmd != origcmd) 2951 bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd); 2952 2953 done: 2954 raw_spin_unlock_irqrestore(&pci_lock, flags); 2955 2956 return mask_updated; 2957 } 2958 2959 /** 2960 * pci_check_and_mask_intx - mask INTx on pending interrupt 2961 * @dev: the PCI device to operate on 2962 * 2963 * Check if the device dev has its INTx line asserted, mask it and 2964 * return true in that case. False is returned if not interrupt was 2965 * pending. 2966 */ 2967 bool pci_check_and_mask_intx(struct pci_dev *dev) 2968 { 2969 return pci_check_and_set_intx_mask(dev, true); 2970 } 2971 EXPORT_SYMBOL_GPL(pci_check_and_mask_intx); 2972 2973 /** 2974 * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending 2975 * @dev: the PCI device to operate on 2976 * 2977 * Check if the device dev has its INTx line asserted, unmask it if not 2978 * and return true. False is returned and the mask remains active if 2979 * there was still an interrupt pending. 2980 */ 2981 bool pci_check_and_unmask_intx(struct pci_dev *dev) 2982 { 2983 return pci_check_and_set_intx_mask(dev, false); 2984 } 2985 EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx); 2986 2987 /** 2988 * pci_msi_off - disables any MSI or MSI-X capabilities 2989 * @dev: the PCI device to operate on 2990 * 2991 * If you want to use MSI, see pci_enable_msi() and friends. 2992 * This is a lower-level primitive that allows us to disable 2993 * MSI operation at the device level. 2994 */ 2995 void pci_msi_off(struct pci_dev *dev) 2996 { 2997 int pos; 2998 u16 control; 2999 3000 /* 3001 * This looks like it could go in msi.c, but we need it even when 3002 * CONFIG_PCI_MSI=n. For the same reason, we can't use 3003 * dev->msi_cap or dev->msix_cap here. 3004 */ 3005 pos = pci_find_capability(dev, PCI_CAP_ID_MSI); 3006 if (pos) { 3007 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); 3008 control &= ~PCI_MSI_FLAGS_ENABLE; 3009 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); 3010 } 3011 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); 3012 if (pos) { 3013 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); 3014 control &= ~PCI_MSIX_FLAGS_ENABLE; 3015 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); 3016 } 3017 } 3018 EXPORT_SYMBOL_GPL(pci_msi_off); 3019 3020 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size) 3021 { 3022 return dma_set_max_seg_size(&dev->dev, size); 3023 } 3024 EXPORT_SYMBOL(pci_set_dma_max_seg_size); 3025 3026 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask) 3027 { 3028 return dma_set_seg_boundary(&dev->dev, mask); 3029 } 3030 EXPORT_SYMBOL(pci_set_dma_seg_boundary); 3031 3032 /** 3033 * pci_wait_for_pending_transaction - waits for pending transaction 3034 * @dev: the PCI device to operate on 3035 * 3036 * Return 0 if transaction is pending 1 otherwise. 3037 */ 3038 int pci_wait_for_pending_transaction(struct pci_dev *dev) 3039 { 3040 if (!pci_is_pcie(dev)) 3041 return 1; 3042 3043 return pci_wait_for_pending(dev, PCI_EXP_DEVSTA, PCI_EXP_DEVSTA_TRPND); 3044 } 3045 EXPORT_SYMBOL(pci_wait_for_pending_transaction); 3046 3047 static int pcie_flr(struct pci_dev *dev, int probe) 3048 { 3049 u32 cap; 3050 3051 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap); 3052 if (!(cap & PCI_EXP_DEVCAP_FLR)) 3053 return -ENOTTY; 3054 3055 if (probe) 3056 return 0; 3057 3058 if (!pci_wait_for_pending_transaction(dev)) 3059 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n"); 3060 3061 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR); 3062 3063 msleep(100); 3064 3065 return 0; 3066 } 3067 3068 static int pci_af_flr(struct pci_dev *dev, int probe) 3069 { 3070 int pos; 3071 u8 cap; 3072 3073 pos = pci_find_capability(dev, PCI_CAP_ID_AF); 3074 if (!pos) 3075 return -ENOTTY; 3076 3077 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap); 3078 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR)) 3079 return -ENOTTY; 3080 3081 if (probe) 3082 return 0; 3083 3084 /* Wait for Transaction Pending bit clean */ 3085 if (pci_wait_for_pending(dev, PCI_AF_STATUS, PCI_AF_STATUS_TP)) 3086 goto clear; 3087 3088 dev_err(&dev->dev, "transaction is not cleared; " 3089 "proceeding with reset anyway\n"); 3090 3091 clear: 3092 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR); 3093 msleep(100); 3094 3095 return 0; 3096 } 3097 3098 /** 3099 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0. 3100 * @dev: Device to reset. 3101 * @probe: If set, only check if the device can be reset this way. 3102 * 3103 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is 3104 * unset, it will be reinitialized internally when going from PCI_D3hot to 3105 * PCI_D0. If that's the case and the device is not in a low-power state 3106 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset. 3107 * 3108 * NOTE: This causes the caller to sleep for twice the device power transition 3109 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms 3110 * by default (i.e. unless the @dev's d3_delay field has a different value). 3111 * Moreover, only devices in D0 can be reset by this function. 3112 */ 3113 static int pci_pm_reset(struct pci_dev *dev, int probe) 3114 { 3115 u16 csr; 3116 3117 if (!dev->pm_cap) 3118 return -ENOTTY; 3119 3120 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr); 3121 if (csr & PCI_PM_CTRL_NO_SOFT_RESET) 3122 return -ENOTTY; 3123 3124 if (probe) 3125 return 0; 3126 3127 if (dev->current_state != PCI_D0) 3128 return -EINVAL; 3129 3130 csr &= ~PCI_PM_CTRL_STATE_MASK; 3131 csr |= PCI_D3hot; 3132 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); 3133 pci_dev_d3_sleep(dev); 3134 3135 csr &= ~PCI_PM_CTRL_STATE_MASK; 3136 csr |= PCI_D0; 3137 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); 3138 pci_dev_d3_sleep(dev); 3139 3140 return 0; 3141 } 3142 3143 /** 3144 * pci_reset_bridge_secondary_bus - Reset the secondary bus on a PCI bridge. 3145 * @dev: Bridge device 3146 * 3147 * Use the bridge control register to assert reset on the secondary bus. 3148 * Devices on the secondary bus are left in power-on state. 3149 */ 3150 void pci_reset_bridge_secondary_bus(struct pci_dev *dev) 3151 { 3152 u16 ctrl; 3153 3154 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl); 3155 ctrl |= PCI_BRIDGE_CTL_BUS_RESET; 3156 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl); 3157 /* 3158 * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double 3159 * this to 2ms to ensure that we meet the minimum requirement. 3160 */ 3161 msleep(2); 3162 3163 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET; 3164 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl); 3165 3166 /* 3167 * Trhfa for conventional PCI is 2^25 clock cycles. 3168 * Assuming a minimum 33MHz clock this results in a 1s 3169 * delay before we can consider subordinate devices to 3170 * be re-initialized. PCIe has some ways to shorten this, 3171 * but we don't make use of them yet. 3172 */ 3173 ssleep(1); 3174 } 3175 EXPORT_SYMBOL_GPL(pci_reset_bridge_secondary_bus); 3176 3177 static int pci_parent_bus_reset(struct pci_dev *dev, int probe) 3178 { 3179 struct pci_dev *pdev; 3180 3181 if (pci_is_root_bus(dev->bus) || dev->subordinate || !dev->bus->self) 3182 return -ENOTTY; 3183 3184 list_for_each_entry(pdev, &dev->bus->devices, bus_list) 3185 if (pdev != dev) 3186 return -ENOTTY; 3187 3188 if (probe) 3189 return 0; 3190 3191 pci_reset_bridge_secondary_bus(dev->bus->self); 3192 3193 return 0; 3194 } 3195 3196 static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, int probe) 3197 { 3198 int rc = -ENOTTY; 3199 3200 if (!hotplug || !try_module_get(hotplug->ops->owner)) 3201 return rc; 3202 3203 if (hotplug->ops->reset_slot) 3204 rc = hotplug->ops->reset_slot(hotplug, probe); 3205 3206 module_put(hotplug->ops->owner); 3207 3208 return rc; 3209 } 3210 3211 static int pci_dev_reset_slot_function(struct pci_dev *dev, int probe) 3212 { 3213 struct pci_dev *pdev; 3214 3215 if (dev->subordinate || !dev->slot) 3216 return -ENOTTY; 3217 3218 list_for_each_entry(pdev, &dev->bus->devices, bus_list) 3219 if (pdev != dev && pdev->slot == dev->slot) 3220 return -ENOTTY; 3221 3222 return pci_reset_hotplug_slot(dev->slot->hotplug, probe); 3223 } 3224 3225 static int __pci_dev_reset(struct pci_dev *dev, int probe) 3226 { 3227 int rc; 3228 3229 might_sleep(); 3230 3231 rc = pci_dev_specific_reset(dev, probe); 3232 if (rc != -ENOTTY) 3233 goto done; 3234 3235 rc = pcie_flr(dev, probe); 3236 if (rc != -ENOTTY) 3237 goto done; 3238 3239 rc = pci_af_flr(dev, probe); 3240 if (rc != -ENOTTY) 3241 goto done; 3242 3243 rc = pci_pm_reset(dev, probe); 3244 if (rc != -ENOTTY) 3245 goto done; 3246 3247 rc = pci_dev_reset_slot_function(dev, probe); 3248 if (rc != -ENOTTY) 3249 goto done; 3250 3251 rc = pci_parent_bus_reset(dev, probe); 3252 done: 3253 return rc; 3254 } 3255 3256 static void pci_dev_lock(struct pci_dev *dev) 3257 { 3258 pci_cfg_access_lock(dev); 3259 /* block PM suspend, driver probe, etc. */ 3260 device_lock(&dev->dev); 3261 } 3262 3263 /* Return 1 on successful lock, 0 on contention */ 3264 static int pci_dev_trylock(struct pci_dev *dev) 3265 { 3266 if (pci_cfg_access_trylock(dev)) { 3267 if (device_trylock(&dev->dev)) 3268 return 1; 3269 pci_cfg_access_unlock(dev); 3270 } 3271 3272 return 0; 3273 } 3274 3275 static void pci_dev_unlock(struct pci_dev *dev) 3276 { 3277 device_unlock(&dev->dev); 3278 pci_cfg_access_unlock(dev); 3279 } 3280 3281 static void pci_dev_save_and_disable(struct pci_dev *dev) 3282 { 3283 /* 3284 * Wake-up device prior to save. PM registers default to D0 after 3285 * reset and a simple register restore doesn't reliably return 3286 * to a non-D0 state anyway. 3287 */ 3288 pci_set_power_state(dev, PCI_D0); 3289 3290 pci_save_state(dev); 3291 /* 3292 * Disable the device by clearing the Command register, except for 3293 * INTx-disable which is set. This not only disables MMIO and I/O port 3294 * BARs, but also prevents the device from being Bus Master, preventing 3295 * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3 3296 * compliant devices, INTx-disable prevents legacy interrupts. 3297 */ 3298 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE); 3299 } 3300 3301 static void pci_dev_restore(struct pci_dev *dev) 3302 { 3303 pci_restore_state(dev); 3304 } 3305 3306 static int pci_dev_reset(struct pci_dev *dev, int probe) 3307 { 3308 int rc; 3309 3310 if (!probe) 3311 pci_dev_lock(dev); 3312 3313 rc = __pci_dev_reset(dev, probe); 3314 3315 if (!probe) 3316 pci_dev_unlock(dev); 3317 3318 return rc; 3319 } 3320 /** 3321 * __pci_reset_function - reset a PCI device function 3322 * @dev: PCI device to reset 3323 * 3324 * Some devices allow an individual function to be reset without affecting 3325 * other functions in the same device. The PCI device must be responsive 3326 * to PCI config space in order to use this function. 3327 * 3328 * The device function is presumed to be unused when this function is called. 3329 * Resetting the device will make the contents of PCI configuration space 3330 * random, so any caller of this must be prepared to reinitialise the 3331 * device including MSI, bus mastering, BARs, decoding IO and memory spaces, 3332 * etc. 3333 * 3334 * Returns 0 if the device function was successfully reset or negative if the 3335 * device doesn't support resetting a single function. 3336 */ 3337 int __pci_reset_function(struct pci_dev *dev) 3338 { 3339 return pci_dev_reset(dev, 0); 3340 } 3341 EXPORT_SYMBOL_GPL(__pci_reset_function); 3342 3343 /** 3344 * __pci_reset_function_locked - reset a PCI device function while holding 3345 * the @dev mutex lock. 3346 * @dev: PCI device to reset 3347 * 3348 * Some devices allow an individual function to be reset without affecting 3349 * other functions in the same device. The PCI device must be responsive 3350 * to PCI config space in order to use this function. 3351 * 3352 * The device function is presumed to be unused and the caller is holding 3353 * the device mutex lock when this function is called. 3354 * Resetting the device will make the contents of PCI configuration space 3355 * random, so any caller of this must be prepared to reinitialise the 3356 * device including MSI, bus mastering, BARs, decoding IO and memory spaces, 3357 * etc. 3358 * 3359 * Returns 0 if the device function was successfully reset or negative if the 3360 * device doesn't support resetting a single function. 3361 */ 3362 int __pci_reset_function_locked(struct pci_dev *dev) 3363 { 3364 return __pci_dev_reset(dev, 0); 3365 } 3366 EXPORT_SYMBOL_GPL(__pci_reset_function_locked); 3367 3368 /** 3369 * pci_probe_reset_function - check whether the device can be safely reset 3370 * @dev: PCI device to reset 3371 * 3372 * Some devices allow an individual function to be reset without affecting 3373 * other functions in the same device. The PCI device must be responsive 3374 * to PCI config space in order to use this function. 3375 * 3376 * Returns 0 if the device function can be reset or negative if the 3377 * device doesn't support resetting a single function. 3378 */ 3379 int pci_probe_reset_function(struct pci_dev *dev) 3380 { 3381 return pci_dev_reset(dev, 1); 3382 } 3383 3384 /** 3385 * pci_reset_function - quiesce and reset a PCI device function 3386 * @dev: PCI device to reset 3387 * 3388 * Some devices allow an individual function to be reset without affecting 3389 * other functions in the same device. The PCI device must be responsive 3390 * to PCI config space in order to use this function. 3391 * 3392 * This function does not just reset the PCI portion of a device, but 3393 * clears all the state associated with the device. This function differs 3394 * from __pci_reset_function in that it saves and restores device state 3395 * over the reset. 3396 * 3397 * Returns 0 if the device function was successfully reset or negative if the 3398 * device doesn't support resetting a single function. 3399 */ 3400 int pci_reset_function(struct pci_dev *dev) 3401 { 3402 int rc; 3403 3404 rc = pci_dev_reset(dev, 1); 3405 if (rc) 3406 return rc; 3407 3408 pci_dev_save_and_disable(dev); 3409 3410 rc = pci_dev_reset(dev, 0); 3411 3412 pci_dev_restore(dev); 3413 3414 return rc; 3415 } 3416 EXPORT_SYMBOL_GPL(pci_reset_function); 3417 3418 /** 3419 * pci_try_reset_function - quiesce and reset a PCI device function 3420 * @dev: PCI device to reset 3421 * 3422 * Same as above, except return -EAGAIN if unable to lock device. 3423 */ 3424 int pci_try_reset_function(struct pci_dev *dev) 3425 { 3426 int rc; 3427 3428 rc = pci_dev_reset(dev, 1); 3429 if (rc) 3430 return rc; 3431 3432 pci_dev_save_and_disable(dev); 3433 3434 if (pci_dev_trylock(dev)) { 3435 rc = __pci_dev_reset(dev, 0); 3436 pci_dev_unlock(dev); 3437 } else 3438 rc = -EAGAIN; 3439 3440 pci_dev_restore(dev); 3441 3442 return rc; 3443 } 3444 EXPORT_SYMBOL_GPL(pci_try_reset_function); 3445 3446 /* Lock devices from the top of the tree down */ 3447 static void pci_bus_lock(struct pci_bus *bus) 3448 { 3449 struct pci_dev *dev; 3450 3451 list_for_each_entry(dev, &bus->devices, bus_list) { 3452 pci_dev_lock(dev); 3453 if (dev->subordinate) 3454 pci_bus_lock(dev->subordinate); 3455 } 3456 } 3457 3458 /* Unlock devices from the bottom of the tree up */ 3459 static void pci_bus_unlock(struct pci_bus *bus) 3460 { 3461 struct pci_dev *dev; 3462 3463 list_for_each_entry(dev, &bus->devices, bus_list) { 3464 if (dev->subordinate) 3465 pci_bus_unlock(dev->subordinate); 3466 pci_dev_unlock(dev); 3467 } 3468 } 3469 3470 /* Return 1 on successful lock, 0 on contention */ 3471 static int pci_bus_trylock(struct pci_bus *bus) 3472 { 3473 struct pci_dev *dev; 3474 3475 list_for_each_entry(dev, &bus->devices, bus_list) { 3476 if (!pci_dev_trylock(dev)) 3477 goto unlock; 3478 if (dev->subordinate) { 3479 if (!pci_bus_trylock(dev->subordinate)) { 3480 pci_dev_unlock(dev); 3481 goto unlock; 3482 } 3483 } 3484 } 3485 return 1; 3486 3487 unlock: 3488 list_for_each_entry_continue_reverse(dev, &bus->devices, bus_list) { 3489 if (dev->subordinate) 3490 pci_bus_unlock(dev->subordinate); 3491 pci_dev_unlock(dev); 3492 } 3493 return 0; 3494 } 3495 3496 /* Lock devices from the top of the tree down */ 3497 static void pci_slot_lock(struct pci_slot *slot) 3498 { 3499 struct pci_dev *dev; 3500 3501 list_for_each_entry(dev, &slot->bus->devices, bus_list) { 3502 if (!dev->slot || dev->slot != slot) 3503 continue; 3504 pci_dev_lock(dev); 3505 if (dev->subordinate) 3506 pci_bus_lock(dev->subordinate); 3507 } 3508 } 3509 3510 /* Unlock devices from the bottom of the tree up */ 3511 static void pci_slot_unlock(struct pci_slot *slot) 3512 { 3513 struct pci_dev *dev; 3514 3515 list_for_each_entry(dev, &slot->bus->devices, bus_list) { 3516 if (!dev->slot || dev->slot != slot) 3517 continue; 3518 if (dev->subordinate) 3519 pci_bus_unlock(dev->subordinate); 3520 pci_dev_unlock(dev); 3521 } 3522 } 3523 3524 /* Return 1 on successful lock, 0 on contention */ 3525 static int pci_slot_trylock(struct pci_slot *slot) 3526 { 3527 struct pci_dev *dev; 3528 3529 list_for_each_entry(dev, &slot->bus->devices, bus_list) { 3530 if (!dev->slot || dev->slot != slot) 3531 continue; 3532 if (!pci_dev_trylock(dev)) 3533 goto unlock; 3534 if (dev->subordinate) { 3535 if (!pci_bus_trylock(dev->subordinate)) { 3536 pci_dev_unlock(dev); 3537 goto unlock; 3538 } 3539 } 3540 } 3541 return 1; 3542 3543 unlock: 3544 list_for_each_entry_continue_reverse(dev, 3545 &slot->bus->devices, bus_list) { 3546 if (!dev->slot || dev->slot != slot) 3547 continue; 3548 if (dev->subordinate) 3549 pci_bus_unlock(dev->subordinate); 3550 pci_dev_unlock(dev); 3551 } 3552 return 0; 3553 } 3554 3555 /* Save and disable devices from the top of the tree down */ 3556 static void pci_bus_save_and_disable(struct pci_bus *bus) 3557 { 3558 struct pci_dev *dev; 3559 3560 list_for_each_entry(dev, &bus->devices, bus_list) { 3561 pci_dev_save_and_disable(dev); 3562 if (dev->subordinate) 3563 pci_bus_save_and_disable(dev->subordinate); 3564 } 3565 } 3566 3567 /* 3568 * Restore devices from top of the tree down - parent bridges need to be 3569 * restored before we can get to subordinate devices. 3570 */ 3571 static void pci_bus_restore(struct pci_bus *bus) 3572 { 3573 struct pci_dev *dev; 3574 3575 list_for_each_entry(dev, &bus->devices, bus_list) { 3576 pci_dev_restore(dev); 3577 if (dev->subordinate) 3578 pci_bus_restore(dev->subordinate); 3579 } 3580 } 3581 3582 /* Save and disable devices from the top of the tree down */ 3583 static void pci_slot_save_and_disable(struct pci_slot *slot) 3584 { 3585 struct pci_dev *dev; 3586 3587 list_for_each_entry(dev, &slot->bus->devices, bus_list) { 3588 if (!dev->slot || dev->slot != slot) 3589 continue; 3590 pci_dev_save_and_disable(dev); 3591 if (dev->subordinate) 3592 pci_bus_save_and_disable(dev->subordinate); 3593 } 3594 } 3595 3596 /* 3597 * Restore devices from top of the tree down - parent bridges need to be 3598 * restored before we can get to subordinate devices. 3599 */ 3600 static void pci_slot_restore(struct pci_slot *slot) 3601 { 3602 struct pci_dev *dev; 3603 3604 list_for_each_entry(dev, &slot->bus->devices, bus_list) { 3605 if (!dev->slot || dev->slot != slot) 3606 continue; 3607 pci_dev_restore(dev); 3608 if (dev->subordinate) 3609 pci_bus_restore(dev->subordinate); 3610 } 3611 } 3612 3613 static int pci_slot_reset(struct pci_slot *slot, int probe) 3614 { 3615 int rc; 3616 3617 if (!slot) 3618 return -ENOTTY; 3619 3620 if (!probe) 3621 pci_slot_lock(slot); 3622 3623 might_sleep(); 3624 3625 rc = pci_reset_hotplug_slot(slot->hotplug, probe); 3626 3627 if (!probe) 3628 pci_slot_unlock(slot); 3629 3630 return rc; 3631 } 3632 3633 /** 3634 * pci_probe_reset_slot - probe whether a PCI slot can be reset 3635 * @slot: PCI slot to probe 3636 * 3637 * Return 0 if slot can be reset, negative if a slot reset is not supported. 3638 */ 3639 int pci_probe_reset_slot(struct pci_slot *slot) 3640 { 3641 return pci_slot_reset(slot, 1); 3642 } 3643 EXPORT_SYMBOL_GPL(pci_probe_reset_slot); 3644 3645 /** 3646 * pci_reset_slot - reset a PCI slot 3647 * @slot: PCI slot to reset 3648 * 3649 * A PCI bus may host multiple slots, each slot may support a reset mechanism 3650 * independent of other slots. For instance, some slots may support slot power 3651 * control. In the case of a 1:1 bus to slot architecture, this function may 3652 * wrap the bus reset to avoid spurious slot related events such as hotplug. 3653 * Generally a slot reset should be attempted before a bus reset. All of the 3654 * function of the slot and any subordinate buses behind the slot are reset 3655 * through this function. PCI config space of all devices in the slot and 3656 * behind the slot is saved before and restored after reset. 3657 * 3658 * Return 0 on success, non-zero on error. 3659 */ 3660 int pci_reset_slot(struct pci_slot *slot) 3661 { 3662 int rc; 3663 3664 rc = pci_slot_reset(slot, 1); 3665 if (rc) 3666 return rc; 3667 3668 pci_slot_save_and_disable(slot); 3669 3670 rc = pci_slot_reset(slot, 0); 3671 3672 pci_slot_restore(slot); 3673 3674 return rc; 3675 } 3676 EXPORT_SYMBOL_GPL(pci_reset_slot); 3677 3678 /** 3679 * pci_try_reset_slot - Try to reset a PCI slot 3680 * @slot: PCI slot to reset 3681 * 3682 * Same as above except return -EAGAIN if the slot cannot be locked 3683 */ 3684 int pci_try_reset_slot(struct pci_slot *slot) 3685 { 3686 int rc; 3687 3688 rc = pci_slot_reset(slot, 1); 3689 if (rc) 3690 return rc; 3691 3692 pci_slot_save_and_disable(slot); 3693 3694 if (pci_slot_trylock(slot)) { 3695 might_sleep(); 3696 rc = pci_reset_hotplug_slot(slot->hotplug, 0); 3697 pci_slot_unlock(slot); 3698 } else 3699 rc = -EAGAIN; 3700 3701 pci_slot_restore(slot); 3702 3703 return rc; 3704 } 3705 EXPORT_SYMBOL_GPL(pci_try_reset_slot); 3706 3707 static int pci_bus_reset(struct pci_bus *bus, int probe) 3708 { 3709 if (!bus->self) 3710 return -ENOTTY; 3711 3712 if (probe) 3713 return 0; 3714 3715 pci_bus_lock(bus); 3716 3717 might_sleep(); 3718 3719 pci_reset_bridge_secondary_bus(bus->self); 3720 3721 pci_bus_unlock(bus); 3722 3723 return 0; 3724 } 3725 3726 /** 3727 * pci_probe_reset_bus - probe whether a PCI bus can be reset 3728 * @bus: PCI bus to probe 3729 * 3730 * Return 0 if bus can be reset, negative if a bus reset is not supported. 3731 */ 3732 int pci_probe_reset_bus(struct pci_bus *bus) 3733 { 3734 return pci_bus_reset(bus, 1); 3735 } 3736 EXPORT_SYMBOL_GPL(pci_probe_reset_bus); 3737 3738 /** 3739 * pci_reset_bus - reset a PCI bus 3740 * @bus: top level PCI bus to reset 3741 * 3742 * Do a bus reset on the given bus and any subordinate buses, saving 3743 * and restoring state of all devices. 3744 * 3745 * Return 0 on success, non-zero on error. 3746 */ 3747 int pci_reset_bus(struct pci_bus *bus) 3748 { 3749 int rc; 3750 3751 rc = pci_bus_reset(bus, 1); 3752 if (rc) 3753 return rc; 3754 3755 pci_bus_save_and_disable(bus); 3756 3757 rc = pci_bus_reset(bus, 0); 3758 3759 pci_bus_restore(bus); 3760 3761 return rc; 3762 } 3763 EXPORT_SYMBOL_GPL(pci_reset_bus); 3764 3765 /** 3766 * pci_try_reset_bus - Try to reset a PCI bus 3767 * @bus: top level PCI bus to reset 3768 * 3769 * Same as above except return -EAGAIN if the bus cannot be locked 3770 */ 3771 int pci_try_reset_bus(struct pci_bus *bus) 3772 { 3773 int rc; 3774 3775 rc = pci_bus_reset(bus, 1); 3776 if (rc) 3777 return rc; 3778 3779 pci_bus_save_and_disable(bus); 3780 3781 if (pci_bus_trylock(bus)) { 3782 might_sleep(); 3783 pci_reset_bridge_secondary_bus(bus->self); 3784 pci_bus_unlock(bus); 3785 } else 3786 rc = -EAGAIN; 3787 3788 pci_bus_restore(bus); 3789 3790 return rc; 3791 } 3792 EXPORT_SYMBOL_GPL(pci_try_reset_bus); 3793 3794 /** 3795 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count 3796 * @dev: PCI device to query 3797 * 3798 * Returns mmrbc: maximum designed memory read count in bytes 3799 * or appropriate error value. 3800 */ 3801 int pcix_get_max_mmrbc(struct pci_dev *dev) 3802 { 3803 int cap; 3804 u32 stat; 3805 3806 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); 3807 if (!cap) 3808 return -EINVAL; 3809 3810 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat)) 3811 return -EINVAL; 3812 3813 return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21); 3814 } 3815 EXPORT_SYMBOL(pcix_get_max_mmrbc); 3816 3817 /** 3818 * pcix_get_mmrbc - get PCI-X maximum memory read byte count 3819 * @dev: PCI device to query 3820 * 3821 * Returns mmrbc: maximum memory read count in bytes 3822 * or appropriate error value. 3823 */ 3824 int pcix_get_mmrbc(struct pci_dev *dev) 3825 { 3826 int cap; 3827 u16 cmd; 3828 3829 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); 3830 if (!cap) 3831 return -EINVAL; 3832 3833 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd)) 3834 return -EINVAL; 3835 3836 return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2); 3837 } 3838 EXPORT_SYMBOL(pcix_get_mmrbc); 3839 3840 /** 3841 * pcix_set_mmrbc - set PCI-X maximum memory read byte count 3842 * @dev: PCI device to query 3843 * @mmrbc: maximum memory read count in bytes 3844 * valid values are 512, 1024, 2048, 4096 3845 * 3846 * If possible sets maximum memory read byte count, some bridges have erratas 3847 * that prevent this. 3848 */ 3849 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc) 3850 { 3851 int cap; 3852 u32 stat, v, o; 3853 u16 cmd; 3854 3855 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc)) 3856 return -EINVAL; 3857 3858 v = ffs(mmrbc) - 10; 3859 3860 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); 3861 if (!cap) 3862 return -EINVAL; 3863 3864 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat)) 3865 return -EINVAL; 3866 3867 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21) 3868 return -E2BIG; 3869 3870 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd)) 3871 return -EINVAL; 3872 3873 o = (cmd & PCI_X_CMD_MAX_READ) >> 2; 3874 if (o != v) { 3875 if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC)) 3876 return -EIO; 3877 3878 cmd &= ~PCI_X_CMD_MAX_READ; 3879 cmd |= v << 2; 3880 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd)) 3881 return -EIO; 3882 } 3883 return 0; 3884 } 3885 EXPORT_SYMBOL(pcix_set_mmrbc); 3886 3887 /** 3888 * pcie_get_readrq - get PCI Express read request size 3889 * @dev: PCI device to query 3890 * 3891 * Returns maximum memory read request in bytes 3892 * or appropriate error value. 3893 */ 3894 int pcie_get_readrq(struct pci_dev *dev) 3895 { 3896 u16 ctl; 3897 3898 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl); 3899 3900 return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12); 3901 } 3902 EXPORT_SYMBOL(pcie_get_readrq); 3903 3904 /** 3905 * pcie_set_readrq - set PCI Express maximum memory read request 3906 * @dev: PCI device to query 3907 * @rq: maximum memory read count in bytes 3908 * valid values are 128, 256, 512, 1024, 2048, 4096 3909 * 3910 * If possible sets maximum memory read request in bytes 3911 */ 3912 int pcie_set_readrq(struct pci_dev *dev, int rq) 3913 { 3914 u16 v; 3915 3916 if (rq < 128 || rq > 4096 || !is_power_of_2(rq)) 3917 return -EINVAL; 3918 3919 /* 3920 * If using the "performance" PCIe config, we clamp the 3921 * read rq size to the max packet size to prevent the 3922 * host bridge generating requests larger than we can 3923 * cope with 3924 */ 3925 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) { 3926 int mps = pcie_get_mps(dev); 3927 3928 if (mps < rq) 3929 rq = mps; 3930 } 3931 3932 v = (ffs(rq) - 8) << 12; 3933 3934 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL, 3935 PCI_EXP_DEVCTL_READRQ, v); 3936 } 3937 EXPORT_SYMBOL(pcie_set_readrq); 3938 3939 /** 3940 * pcie_get_mps - get PCI Express maximum payload size 3941 * @dev: PCI device to query 3942 * 3943 * Returns maximum payload size in bytes 3944 */ 3945 int pcie_get_mps(struct pci_dev *dev) 3946 { 3947 u16 ctl; 3948 3949 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl); 3950 3951 return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5); 3952 } 3953 EXPORT_SYMBOL(pcie_get_mps); 3954 3955 /** 3956 * pcie_set_mps - set PCI Express maximum payload size 3957 * @dev: PCI device to query 3958 * @mps: maximum payload size in bytes 3959 * valid values are 128, 256, 512, 1024, 2048, 4096 3960 * 3961 * If possible sets maximum payload size 3962 */ 3963 int pcie_set_mps(struct pci_dev *dev, int mps) 3964 { 3965 u16 v; 3966 3967 if (mps < 128 || mps > 4096 || !is_power_of_2(mps)) 3968 return -EINVAL; 3969 3970 v = ffs(mps) - 8; 3971 if (v > dev->pcie_mpss) 3972 return -EINVAL; 3973 v <<= 5; 3974 3975 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL, 3976 PCI_EXP_DEVCTL_PAYLOAD, v); 3977 } 3978 EXPORT_SYMBOL(pcie_set_mps); 3979 3980 /** 3981 * pcie_get_minimum_link - determine minimum link settings of a PCI device 3982 * @dev: PCI device to query 3983 * @speed: storage for minimum speed 3984 * @width: storage for minimum width 3985 * 3986 * This function will walk up the PCI device chain and determine the minimum 3987 * link width and speed of the device. 3988 */ 3989 int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed, 3990 enum pcie_link_width *width) 3991 { 3992 int ret; 3993 3994 *speed = PCI_SPEED_UNKNOWN; 3995 *width = PCIE_LNK_WIDTH_UNKNOWN; 3996 3997 while (dev) { 3998 u16 lnksta; 3999 enum pci_bus_speed next_speed; 4000 enum pcie_link_width next_width; 4001 4002 ret = pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta); 4003 if (ret) 4004 return ret; 4005 4006 next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS]; 4007 next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >> 4008 PCI_EXP_LNKSTA_NLW_SHIFT; 4009 4010 if (next_speed < *speed) 4011 *speed = next_speed; 4012 4013 if (next_width < *width) 4014 *width = next_width; 4015 4016 dev = dev->bus->self; 4017 } 4018 4019 return 0; 4020 } 4021 EXPORT_SYMBOL(pcie_get_minimum_link); 4022 4023 /** 4024 * pci_select_bars - Make BAR mask from the type of resource 4025 * @dev: the PCI device for which BAR mask is made 4026 * @flags: resource type mask to be selected 4027 * 4028 * This helper routine makes bar mask from the type of resource. 4029 */ 4030 int pci_select_bars(struct pci_dev *dev, unsigned long flags) 4031 { 4032 int i, bars = 0; 4033 for (i = 0; i < PCI_NUM_RESOURCES; i++) 4034 if (pci_resource_flags(dev, i) & flags) 4035 bars |= (1 << i); 4036 return bars; 4037 } 4038 4039 /** 4040 * pci_resource_bar - get position of the BAR associated with a resource 4041 * @dev: the PCI device 4042 * @resno: the resource number 4043 * @type: the BAR type to be filled in 4044 * 4045 * Returns BAR position in config space, or 0 if the BAR is invalid. 4046 */ 4047 int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type) 4048 { 4049 int reg; 4050 4051 if (resno < PCI_ROM_RESOURCE) { 4052 *type = pci_bar_unknown; 4053 return PCI_BASE_ADDRESS_0 + 4 * resno; 4054 } else if (resno == PCI_ROM_RESOURCE) { 4055 *type = pci_bar_mem32; 4056 return dev->rom_base_reg; 4057 } else if (resno < PCI_BRIDGE_RESOURCES) { 4058 /* device specific resource */ 4059 reg = pci_iov_resource_bar(dev, resno, type); 4060 if (reg) 4061 return reg; 4062 } 4063 4064 dev_err(&dev->dev, "BAR %d: invalid resource\n", resno); 4065 return 0; 4066 } 4067 4068 /* Some architectures require additional programming to enable VGA */ 4069 static arch_set_vga_state_t arch_set_vga_state; 4070 4071 void __init pci_register_set_vga_state(arch_set_vga_state_t func) 4072 { 4073 arch_set_vga_state = func; /* NULL disables */ 4074 } 4075 4076 static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode, 4077 unsigned int command_bits, u32 flags) 4078 { 4079 if (arch_set_vga_state) 4080 return arch_set_vga_state(dev, decode, command_bits, 4081 flags); 4082 return 0; 4083 } 4084 4085 /** 4086 * pci_set_vga_state - set VGA decode state on device and parents if requested 4087 * @dev: the PCI device 4088 * @decode: true = enable decoding, false = disable decoding 4089 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY 4090 * @flags: traverse ancestors and change bridges 4091 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE 4092 */ 4093 int pci_set_vga_state(struct pci_dev *dev, bool decode, 4094 unsigned int command_bits, u32 flags) 4095 { 4096 struct pci_bus *bus; 4097 struct pci_dev *bridge; 4098 u16 cmd; 4099 int rc; 4100 4101 WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) & (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY))); 4102 4103 /* ARCH specific VGA enables */ 4104 rc = pci_set_vga_state_arch(dev, decode, command_bits, flags); 4105 if (rc) 4106 return rc; 4107 4108 if (flags & PCI_VGA_STATE_CHANGE_DECODES) { 4109 pci_read_config_word(dev, PCI_COMMAND, &cmd); 4110 if (decode == true) 4111 cmd |= command_bits; 4112 else 4113 cmd &= ~command_bits; 4114 pci_write_config_word(dev, PCI_COMMAND, cmd); 4115 } 4116 4117 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE)) 4118 return 0; 4119 4120 bus = dev->bus; 4121 while (bus) { 4122 bridge = bus->self; 4123 if (bridge) { 4124 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL, 4125 &cmd); 4126 if (decode == true) 4127 cmd |= PCI_BRIDGE_CTL_VGA; 4128 else 4129 cmd &= ~PCI_BRIDGE_CTL_VGA; 4130 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, 4131 cmd); 4132 } 4133 bus = bus->parent; 4134 } 4135 return 0; 4136 } 4137 4138 bool pci_device_is_present(struct pci_dev *pdev) 4139 { 4140 u32 v; 4141 4142 return pci_bus_read_dev_vendor_id(pdev->bus, pdev->devfn, &v, 0); 4143 } 4144 EXPORT_SYMBOL_GPL(pci_device_is_present); 4145 4146 #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE 4147 static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0}; 4148 static DEFINE_SPINLOCK(resource_alignment_lock); 4149 4150 /** 4151 * pci_specified_resource_alignment - get resource alignment specified by user. 4152 * @dev: the PCI device to get 4153 * 4154 * RETURNS: Resource alignment if it is specified. 4155 * Zero if it is not specified. 4156 */ 4157 static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev) 4158 { 4159 int seg, bus, slot, func, align_order, count; 4160 resource_size_t align = 0; 4161 char *p; 4162 4163 spin_lock(&resource_alignment_lock); 4164 p = resource_alignment_param; 4165 while (*p) { 4166 count = 0; 4167 if (sscanf(p, "%d%n", &align_order, &count) == 1 && 4168 p[count] == '@') { 4169 p += count + 1; 4170 } else { 4171 align_order = -1; 4172 } 4173 if (sscanf(p, "%x:%x:%x.%x%n", 4174 &seg, &bus, &slot, &func, &count) != 4) { 4175 seg = 0; 4176 if (sscanf(p, "%x:%x.%x%n", 4177 &bus, &slot, &func, &count) != 3) { 4178 /* Invalid format */ 4179 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n", 4180 p); 4181 break; 4182 } 4183 } 4184 p += count; 4185 if (seg == pci_domain_nr(dev->bus) && 4186 bus == dev->bus->number && 4187 slot == PCI_SLOT(dev->devfn) && 4188 func == PCI_FUNC(dev->devfn)) { 4189 if (align_order == -1) { 4190 align = PAGE_SIZE; 4191 } else { 4192 align = 1 << align_order; 4193 } 4194 /* Found */ 4195 break; 4196 } 4197 if (*p != ';' && *p != ',') { 4198 /* End of param or invalid format */ 4199 break; 4200 } 4201 p++; 4202 } 4203 spin_unlock(&resource_alignment_lock); 4204 return align; 4205 } 4206 4207 /* 4208 * This function disables memory decoding and releases memory resources 4209 * of the device specified by kernel's boot parameter 'pci=resource_alignment='. 4210 * It also rounds up size to specified alignment. 4211 * Later on, the kernel will assign page-aligned memory resource back 4212 * to the device. 4213 */ 4214 void pci_reassigndev_resource_alignment(struct pci_dev *dev) 4215 { 4216 int i; 4217 struct resource *r; 4218 resource_size_t align, size; 4219 u16 command; 4220 4221 /* check if specified PCI is target device to reassign */ 4222 align = pci_specified_resource_alignment(dev); 4223 if (!align) 4224 return; 4225 4226 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL && 4227 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) { 4228 dev_warn(&dev->dev, 4229 "Can't reassign resources to host bridge.\n"); 4230 return; 4231 } 4232 4233 dev_info(&dev->dev, 4234 "Disabling memory decoding and releasing memory resources.\n"); 4235 pci_read_config_word(dev, PCI_COMMAND, &command); 4236 command &= ~PCI_COMMAND_MEMORY; 4237 pci_write_config_word(dev, PCI_COMMAND, command); 4238 4239 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) { 4240 r = &dev->resource[i]; 4241 if (!(r->flags & IORESOURCE_MEM)) 4242 continue; 4243 size = resource_size(r); 4244 if (size < align) { 4245 size = align; 4246 dev_info(&dev->dev, 4247 "Rounding up size of resource #%d to %#llx.\n", 4248 i, (unsigned long long)size); 4249 } 4250 r->end = size - 1; 4251 r->start = 0; 4252 } 4253 /* Need to disable bridge's resource window, 4254 * to enable the kernel to reassign new resource 4255 * window later on. 4256 */ 4257 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE && 4258 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { 4259 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) { 4260 r = &dev->resource[i]; 4261 if (!(r->flags & IORESOURCE_MEM)) 4262 continue; 4263 r->end = resource_size(r) - 1; 4264 r->start = 0; 4265 } 4266 pci_disable_bridge_window(dev); 4267 } 4268 } 4269 4270 static ssize_t pci_set_resource_alignment_param(const char *buf, size_t count) 4271 { 4272 if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1) 4273 count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1; 4274 spin_lock(&resource_alignment_lock); 4275 strncpy(resource_alignment_param, buf, count); 4276 resource_alignment_param[count] = '\0'; 4277 spin_unlock(&resource_alignment_lock); 4278 return count; 4279 } 4280 4281 static ssize_t pci_get_resource_alignment_param(char *buf, size_t size) 4282 { 4283 size_t count; 4284 spin_lock(&resource_alignment_lock); 4285 count = snprintf(buf, size, "%s", resource_alignment_param); 4286 spin_unlock(&resource_alignment_lock); 4287 return count; 4288 } 4289 4290 static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf) 4291 { 4292 return pci_get_resource_alignment_param(buf, PAGE_SIZE); 4293 } 4294 4295 static ssize_t pci_resource_alignment_store(struct bus_type *bus, 4296 const char *buf, size_t count) 4297 { 4298 return pci_set_resource_alignment_param(buf, count); 4299 } 4300 4301 BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show, 4302 pci_resource_alignment_store); 4303 4304 static int __init pci_resource_alignment_sysfs_init(void) 4305 { 4306 return bus_create_file(&pci_bus_type, 4307 &bus_attr_resource_alignment); 4308 } 4309 4310 late_initcall(pci_resource_alignment_sysfs_init); 4311 4312 static void pci_no_domains(void) 4313 { 4314 #ifdef CONFIG_PCI_DOMAINS 4315 pci_domains_supported = 0; 4316 #endif 4317 } 4318 4319 /** 4320 * pci_ext_cfg_avail - can we access extended PCI config space? 4321 * 4322 * Returns 1 if we can access PCI extended config space (offsets 4323 * greater than 0xff). This is the default implementation. Architecture 4324 * implementations can override this. 4325 */ 4326 int __weak pci_ext_cfg_avail(void) 4327 { 4328 return 1; 4329 } 4330 4331 void __weak pci_fixup_cardbus(struct pci_bus *bus) 4332 { 4333 } 4334 EXPORT_SYMBOL(pci_fixup_cardbus); 4335 4336 static int __init pci_setup(char *str) 4337 { 4338 while (str) { 4339 char *k = strchr(str, ','); 4340 if (k) 4341 *k++ = 0; 4342 if (*str && (str = pcibios_setup(str)) && *str) { 4343 if (!strcmp(str, "nomsi")) { 4344 pci_no_msi(); 4345 } else if (!strcmp(str, "noaer")) { 4346 pci_no_aer(); 4347 } else if (!strncmp(str, "realloc=", 8)) { 4348 pci_realloc_get_opt(str + 8); 4349 } else if (!strncmp(str, "realloc", 7)) { 4350 pci_realloc_get_opt("on"); 4351 } else if (!strcmp(str, "nodomains")) { 4352 pci_no_domains(); 4353 } else if (!strncmp(str, "noari", 5)) { 4354 pcie_ari_disabled = true; 4355 } else if (!strncmp(str, "cbiosize=", 9)) { 4356 pci_cardbus_io_size = memparse(str + 9, &str); 4357 } else if (!strncmp(str, "cbmemsize=", 10)) { 4358 pci_cardbus_mem_size = memparse(str + 10, &str); 4359 } else if (!strncmp(str, "resource_alignment=", 19)) { 4360 pci_set_resource_alignment_param(str + 19, 4361 strlen(str + 19)); 4362 } else if (!strncmp(str, "ecrc=", 5)) { 4363 pcie_ecrc_get_policy(str + 5); 4364 } else if (!strncmp(str, "hpiosize=", 9)) { 4365 pci_hotplug_io_size = memparse(str + 9, &str); 4366 } else if (!strncmp(str, "hpmemsize=", 10)) { 4367 pci_hotplug_mem_size = memparse(str + 10, &str); 4368 } else if (!strncmp(str, "pcie_bus_tune_off", 17)) { 4369 pcie_bus_config = PCIE_BUS_TUNE_OFF; 4370 } else if (!strncmp(str, "pcie_bus_safe", 13)) { 4371 pcie_bus_config = PCIE_BUS_SAFE; 4372 } else if (!strncmp(str, "pcie_bus_perf", 13)) { 4373 pcie_bus_config = PCIE_BUS_PERFORMANCE; 4374 } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) { 4375 pcie_bus_config = PCIE_BUS_PEER2PEER; 4376 } else if (!strncmp(str, "pcie_scan_all", 13)) { 4377 pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS); 4378 } else { 4379 printk(KERN_ERR "PCI: Unknown option `%s'\n", 4380 str); 4381 } 4382 } 4383 str = k; 4384 } 4385 return 0; 4386 } 4387 early_param("pci", pci_setup); 4388 4389 EXPORT_SYMBOL(pci_reenable_device); 4390 EXPORT_SYMBOL(pci_enable_device_io); 4391 EXPORT_SYMBOL(pci_enable_device_mem); 4392 EXPORT_SYMBOL(pci_enable_device); 4393 EXPORT_SYMBOL(pcim_enable_device); 4394 EXPORT_SYMBOL(pcim_pin_device); 4395 EXPORT_SYMBOL(pci_disable_device); 4396 EXPORT_SYMBOL(pci_find_capability); 4397 EXPORT_SYMBOL(pci_bus_find_capability); 4398 EXPORT_SYMBOL(pci_release_regions); 4399 EXPORT_SYMBOL(pci_request_regions); 4400 EXPORT_SYMBOL(pci_request_regions_exclusive); 4401 EXPORT_SYMBOL(pci_release_region); 4402 EXPORT_SYMBOL(pci_request_region); 4403 EXPORT_SYMBOL(pci_request_region_exclusive); 4404 EXPORT_SYMBOL(pci_release_selected_regions); 4405 EXPORT_SYMBOL(pci_request_selected_regions); 4406 EXPORT_SYMBOL(pci_request_selected_regions_exclusive); 4407 EXPORT_SYMBOL(pci_set_master); 4408 EXPORT_SYMBOL(pci_clear_master); 4409 EXPORT_SYMBOL(pci_set_mwi); 4410 EXPORT_SYMBOL(pci_try_set_mwi); 4411 EXPORT_SYMBOL(pci_clear_mwi); 4412 EXPORT_SYMBOL_GPL(pci_intx); 4413 EXPORT_SYMBOL(pci_assign_resource); 4414 EXPORT_SYMBOL(pci_find_parent_resource); 4415 EXPORT_SYMBOL(pci_select_bars); 4416 4417 EXPORT_SYMBOL(pci_set_power_state); 4418 EXPORT_SYMBOL(pci_save_state); 4419 EXPORT_SYMBOL(pci_restore_state); 4420 EXPORT_SYMBOL(pci_pme_capable); 4421 EXPORT_SYMBOL(pci_pme_active); 4422 EXPORT_SYMBOL(pci_wake_from_d3); 4423 EXPORT_SYMBOL(pci_prepare_to_sleep); 4424 EXPORT_SYMBOL(pci_back_from_sleep); 4425 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state); 4426