1 /* 2 * PCI Bus Services, see include/linux/pci.h for further explanation. 3 * 4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter, 5 * David Mosberger-Tang 6 * 7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz> 8 */ 9 10 #include <linux/kernel.h> 11 #include <linux/delay.h> 12 #include <linux/init.h> 13 #include <linux/pci.h> 14 #include <linux/pm.h> 15 #include <linux/module.h> 16 #include <linux/spinlock.h> 17 #include <linux/string.h> 18 #include <linux/log2.h> 19 #include <linux/pci-aspm.h> 20 #include <linux/pm_wakeup.h> 21 #include <linux/interrupt.h> 22 #include <asm/dma.h> /* isa_dma_bridge_buggy */ 23 #include <linux/device.h> 24 #include <asm/setup.h> 25 #include "pci.h" 26 27 const char *pci_power_names[] = { 28 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown", 29 }; 30 EXPORT_SYMBOL_GPL(pci_power_names); 31 32 unsigned int pci_pm_d3_delay = PCI_PM_D3_WAIT; 33 34 #ifdef CONFIG_PCI_DOMAINS 35 int pci_domains_supported = 1; 36 #endif 37 38 #define DEFAULT_CARDBUS_IO_SIZE (256) 39 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024) 40 /* pci=cbmemsize=nnM,cbiosize=nn can override this */ 41 unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE; 42 unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE; 43 44 #define DEFAULT_HOTPLUG_IO_SIZE (256) 45 #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024) 46 /* pci=hpmemsize=nnM,hpiosize=nn can override this */ 47 unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE; 48 unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE; 49 50 /* 51 * The default CLS is used if arch didn't set CLS explicitly and not 52 * all pci devices agree on the same value. Arch can override either 53 * the dfl or actual value as it sees fit. Don't forget this is 54 * measured in 32-bit words, not bytes. 55 */ 56 u8 pci_dfl_cache_line_size __devinitdata = L1_CACHE_BYTES >> 2; 57 u8 pci_cache_line_size; 58 59 /** 60 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children 61 * @bus: pointer to PCI bus structure to search 62 * 63 * Given a PCI bus, returns the highest PCI bus number present in the set 64 * including the given PCI bus and its list of child PCI buses. 65 */ 66 unsigned char pci_bus_max_busnr(struct pci_bus* bus) 67 { 68 struct list_head *tmp; 69 unsigned char max, n; 70 71 max = bus->subordinate; 72 list_for_each(tmp, &bus->children) { 73 n = pci_bus_max_busnr(pci_bus_b(tmp)); 74 if(n > max) 75 max = n; 76 } 77 return max; 78 } 79 EXPORT_SYMBOL_GPL(pci_bus_max_busnr); 80 81 #ifdef CONFIG_HAS_IOMEM 82 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar) 83 { 84 /* 85 * Make sure the BAR is actually a memory resource, not an IO resource 86 */ 87 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { 88 WARN_ON(1); 89 return NULL; 90 } 91 return ioremap_nocache(pci_resource_start(pdev, bar), 92 pci_resource_len(pdev, bar)); 93 } 94 EXPORT_SYMBOL_GPL(pci_ioremap_bar); 95 #endif 96 97 #if 0 98 /** 99 * pci_max_busnr - returns maximum PCI bus number 100 * 101 * Returns the highest PCI bus number present in the system global list of 102 * PCI buses. 103 */ 104 unsigned char __devinit 105 pci_max_busnr(void) 106 { 107 struct pci_bus *bus = NULL; 108 unsigned char max, n; 109 110 max = 0; 111 while ((bus = pci_find_next_bus(bus)) != NULL) { 112 n = pci_bus_max_busnr(bus); 113 if(n > max) 114 max = n; 115 } 116 return max; 117 } 118 119 #endif /* 0 */ 120 121 #define PCI_FIND_CAP_TTL 48 122 123 static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn, 124 u8 pos, int cap, int *ttl) 125 { 126 u8 id; 127 128 while ((*ttl)--) { 129 pci_bus_read_config_byte(bus, devfn, pos, &pos); 130 if (pos < 0x40) 131 break; 132 pos &= ~3; 133 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID, 134 &id); 135 if (id == 0xff) 136 break; 137 if (id == cap) 138 return pos; 139 pos += PCI_CAP_LIST_NEXT; 140 } 141 return 0; 142 } 143 144 static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn, 145 u8 pos, int cap) 146 { 147 int ttl = PCI_FIND_CAP_TTL; 148 149 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl); 150 } 151 152 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap) 153 { 154 return __pci_find_next_cap(dev->bus, dev->devfn, 155 pos + PCI_CAP_LIST_NEXT, cap); 156 } 157 EXPORT_SYMBOL_GPL(pci_find_next_capability); 158 159 static int __pci_bus_find_cap_start(struct pci_bus *bus, 160 unsigned int devfn, u8 hdr_type) 161 { 162 u16 status; 163 164 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status); 165 if (!(status & PCI_STATUS_CAP_LIST)) 166 return 0; 167 168 switch (hdr_type) { 169 case PCI_HEADER_TYPE_NORMAL: 170 case PCI_HEADER_TYPE_BRIDGE: 171 return PCI_CAPABILITY_LIST; 172 case PCI_HEADER_TYPE_CARDBUS: 173 return PCI_CB_CAPABILITY_LIST; 174 default: 175 return 0; 176 } 177 178 return 0; 179 } 180 181 /** 182 * pci_find_capability - query for devices' capabilities 183 * @dev: PCI device to query 184 * @cap: capability code 185 * 186 * Tell if a device supports a given PCI capability. 187 * Returns the address of the requested capability structure within the 188 * device's PCI configuration space or 0 in case the device does not 189 * support it. Possible values for @cap: 190 * 191 * %PCI_CAP_ID_PM Power Management 192 * %PCI_CAP_ID_AGP Accelerated Graphics Port 193 * %PCI_CAP_ID_VPD Vital Product Data 194 * %PCI_CAP_ID_SLOTID Slot Identification 195 * %PCI_CAP_ID_MSI Message Signalled Interrupts 196 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap 197 * %PCI_CAP_ID_PCIX PCI-X 198 * %PCI_CAP_ID_EXP PCI Express 199 */ 200 int pci_find_capability(struct pci_dev *dev, int cap) 201 { 202 int pos; 203 204 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); 205 if (pos) 206 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap); 207 208 return pos; 209 } 210 211 /** 212 * pci_bus_find_capability - query for devices' capabilities 213 * @bus: the PCI bus to query 214 * @devfn: PCI device to query 215 * @cap: capability code 216 * 217 * Like pci_find_capability() but works for pci devices that do not have a 218 * pci_dev structure set up yet. 219 * 220 * Returns the address of the requested capability structure within the 221 * device's PCI configuration space or 0 in case the device does not 222 * support it. 223 */ 224 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap) 225 { 226 int pos; 227 u8 hdr_type; 228 229 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type); 230 231 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f); 232 if (pos) 233 pos = __pci_find_next_cap(bus, devfn, pos, cap); 234 235 return pos; 236 } 237 238 /** 239 * pci_find_ext_capability - Find an extended capability 240 * @dev: PCI device to query 241 * @cap: capability code 242 * 243 * Returns the address of the requested extended capability structure 244 * within the device's PCI configuration space or 0 if the device does 245 * not support it. Possible values for @cap: 246 * 247 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting 248 * %PCI_EXT_CAP_ID_VC Virtual Channel 249 * %PCI_EXT_CAP_ID_DSN Device Serial Number 250 * %PCI_EXT_CAP_ID_PWR Power Budgeting 251 */ 252 int pci_find_ext_capability(struct pci_dev *dev, int cap) 253 { 254 u32 header; 255 int ttl; 256 int pos = PCI_CFG_SPACE_SIZE; 257 258 /* minimum 8 bytes per capability */ 259 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; 260 261 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE) 262 return 0; 263 264 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) 265 return 0; 266 267 /* 268 * If we have no capabilities, this is indicated by cap ID, 269 * cap version and next pointer all being 0. 270 */ 271 if (header == 0) 272 return 0; 273 274 while (ttl-- > 0) { 275 if (PCI_EXT_CAP_ID(header) == cap) 276 return pos; 277 278 pos = PCI_EXT_CAP_NEXT(header); 279 if (pos < PCI_CFG_SPACE_SIZE) 280 break; 281 282 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) 283 break; 284 } 285 286 return 0; 287 } 288 EXPORT_SYMBOL_GPL(pci_find_ext_capability); 289 290 static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap) 291 { 292 int rc, ttl = PCI_FIND_CAP_TTL; 293 u8 cap, mask; 294 295 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST) 296 mask = HT_3BIT_CAP_MASK; 297 else 298 mask = HT_5BIT_CAP_MASK; 299 300 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos, 301 PCI_CAP_ID_HT, &ttl); 302 while (pos) { 303 rc = pci_read_config_byte(dev, pos + 3, &cap); 304 if (rc != PCIBIOS_SUCCESSFUL) 305 return 0; 306 307 if ((cap & mask) == ht_cap) 308 return pos; 309 310 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, 311 pos + PCI_CAP_LIST_NEXT, 312 PCI_CAP_ID_HT, &ttl); 313 } 314 315 return 0; 316 } 317 /** 318 * pci_find_next_ht_capability - query a device's Hypertransport capabilities 319 * @dev: PCI device to query 320 * @pos: Position from which to continue searching 321 * @ht_cap: Hypertransport capability code 322 * 323 * To be used in conjunction with pci_find_ht_capability() to search for 324 * all capabilities matching @ht_cap. @pos should always be a value returned 325 * from pci_find_ht_capability(). 326 * 327 * NB. To be 100% safe against broken PCI devices, the caller should take 328 * steps to avoid an infinite loop. 329 */ 330 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap) 331 { 332 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap); 333 } 334 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability); 335 336 /** 337 * pci_find_ht_capability - query a device's Hypertransport capabilities 338 * @dev: PCI device to query 339 * @ht_cap: Hypertransport capability code 340 * 341 * Tell if a device supports a given Hypertransport capability. 342 * Returns an address within the device's PCI configuration space 343 * or 0 in case the device does not support the request capability. 344 * The address points to the PCI capability, of type PCI_CAP_ID_HT, 345 * which has a Hypertransport capability matching @ht_cap. 346 */ 347 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap) 348 { 349 int pos; 350 351 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); 352 if (pos) 353 pos = __pci_find_next_ht_cap(dev, pos, ht_cap); 354 355 return pos; 356 } 357 EXPORT_SYMBOL_GPL(pci_find_ht_capability); 358 359 /** 360 * pci_find_parent_resource - return resource region of parent bus of given region 361 * @dev: PCI device structure contains resources to be searched 362 * @res: child resource record for which parent is sought 363 * 364 * For given resource region of given device, return the resource 365 * region of parent bus the given region is contained in or where 366 * it should be allocated from. 367 */ 368 struct resource * 369 pci_find_parent_resource(const struct pci_dev *dev, struct resource *res) 370 { 371 const struct pci_bus *bus = dev->bus; 372 int i; 373 struct resource *best = NULL; 374 375 for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++) { 376 struct resource *r = bus->resource[i]; 377 if (!r) 378 continue; 379 if (res->start && !(res->start >= r->start && res->end <= r->end)) 380 continue; /* Not contained */ 381 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM)) 382 continue; /* Wrong type */ 383 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH)) 384 return r; /* Exact match */ 385 /* We can't insert a non-prefetch resource inside a prefetchable parent .. */ 386 if (r->flags & IORESOURCE_PREFETCH) 387 continue; 388 /* .. but we can put a prefetchable resource inside a non-prefetchable one */ 389 if (!best) 390 best = r; 391 } 392 return best; 393 } 394 395 /** 396 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up) 397 * @dev: PCI device to have its BARs restored 398 * 399 * Restore the BAR values for a given device, so as to make it 400 * accessible by its driver. 401 */ 402 static void 403 pci_restore_bars(struct pci_dev *dev) 404 { 405 int i; 406 407 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) 408 pci_update_resource(dev, i); 409 } 410 411 static struct pci_platform_pm_ops *pci_platform_pm; 412 413 int pci_set_platform_pm(struct pci_platform_pm_ops *ops) 414 { 415 if (!ops->is_manageable || !ops->set_state || !ops->choose_state 416 || !ops->sleep_wake || !ops->can_wakeup) 417 return -EINVAL; 418 pci_platform_pm = ops; 419 return 0; 420 } 421 422 static inline bool platform_pci_power_manageable(struct pci_dev *dev) 423 { 424 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false; 425 } 426 427 static inline int platform_pci_set_power_state(struct pci_dev *dev, 428 pci_power_t t) 429 { 430 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS; 431 } 432 433 static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev) 434 { 435 return pci_platform_pm ? 436 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR; 437 } 438 439 static inline bool platform_pci_can_wakeup(struct pci_dev *dev) 440 { 441 return pci_platform_pm ? pci_platform_pm->can_wakeup(dev) : false; 442 } 443 444 static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable) 445 { 446 return pci_platform_pm ? 447 pci_platform_pm->sleep_wake(dev, enable) : -ENODEV; 448 } 449 450 /** 451 * pci_raw_set_power_state - Use PCI PM registers to set the power state of 452 * given PCI device 453 * @dev: PCI device to handle. 454 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into. 455 * 456 * RETURN VALUE: 457 * -EINVAL if the requested state is invalid. 458 * -EIO if device does not support PCI PM or its PM capabilities register has a 459 * wrong version, or device doesn't support the requested state. 460 * 0 if device already is in the requested state. 461 * 0 if device's power state has been successfully changed. 462 */ 463 static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state) 464 { 465 u16 pmcsr; 466 bool need_restore = false; 467 468 /* Check if we're already there */ 469 if (dev->current_state == state) 470 return 0; 471 472 if (!dev->pm_cap) 473 return -EIO; 474 475 if (state < PCI_D0 || state > PCI_D3hot) 476 return -EINVAL; 477 478 /* Validate current state: 479 * Can enter D0 from any state, but if we can only go deeper 480 * to sleep if we're already in a low power state 481 */ 482 if (state != PCI_D0 && dev->current_state <= PCI_D3cold 483 && dev->current_state > state) { 484 dev_err(&dev->dev, "invalid power transition " 485 "(from state %d to %d)\n", dev->current_state, state); 486 return -EINVAL; 487 } 488 489 /* check if this device supports the desired state */ 490 if ((state == PCI_D1 && !dev->d1_support) 491 || (state == PCI_D2 && !dev->d2_support)) 492 return -EIO; 493 494 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); 495 496 /* If we're (effectively) in D3, force entire word to 0. 497 * This doesn't affect PME_Status, disables PME_En, and 498 * sets PowerState to 0. 499 */ 500 switch (dev->current_state) { 501 case PCI_D0: 502 case PCI_D1: 503 case PCI_D2: 504 pmcsr &= ~PCI_PM_CTRL_STATE_MASK; 505 pmcsr |= state; 506 break; 507 case PCI_D3hot: 508 case PCI_D3cold: 509 case PCI_UNKNOWN: /* Boot-up */ 510 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot 511 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET)) 512 need_restore = true; 513 /* Fall-through: force to D0 */ 514 default: 515 pmcsr = 0; 516 break; 517 } 518 519 /* enter specified state */ 520 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); 521 522 /* Mandatory power management transition delays */ 523 /* see PCI PM 1.1 5.6.1 table 18 */ 524 if (state == PCI_D3hot || dev->current_state == PCI_D3hot) 525 msleep(pci_pm_d3_delay); 526 else if (state == PCI_D2 || dev->current_state == PCI_D2) 527 udelay(PCI_PM_D2_DELAY); 528 529 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); 530 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); 531 if (dev->current_state != state && printk_ratelimit()) 532 dev_info(&dev->dev, "Refused to change power state, " 533 "currently in D%d\n", dev->current_state); 534 535 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT 536 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning 537 * from D3hot to D0 _may_ perform an internal reset, thereby 538 * going to "D0 Uninitialized" rather than "D0 Initialized". 539 * For example, at least some versions of the 3c905B and the 540 * 3c556B exhibit this behaviour. 541 * 542 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave 543 * devices in a D3hot state at boot. Consequently, we need to 544 * restore at least the BARs so that the device will be 545 * accessible to its driver. 546 */ 547 if (need_restore) 548 pci_restore_bars(dev); 549 550 if (dev->bus->self) 551 pcie_aspm_pm_state_change(dev->bus->self); 552 553 return 0; 554 } 555 556 /** 557 * pci_update_current_state - Read PCI power state of given device from its 558 * PCI PM registers and cache it 559 * @dev: PCI device to handle. 560 * @state: State to cache in case the device doesn't have the PM capability 561 */ 562 void pci_update_current_state(struct pci_dev *dev, pci_power_t state) 563 { 564 if (dev->pm_cap) { 565 u16 pmcsr; 566 567 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); 568 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); 569 } else { 570 dev->current_state = state; 571 } 572 } 573 574 /** 575 * pci_platform_power_transition - Use platform to change device power state 576 * @dev: PCI device to handle. 577 * @state: State to put the device into. 578 */ 579 static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state) 580 { 581 int error; 582 583 if (platform_pci_power_manageable(dev)) { 584 error = platform_pci_set_power_state(dev, state); 585 if (!error) 586 pci_update_current_state(dev, state); 587 } else { 588 error = -ENODEV; 589 /* Fall back to PCI_D0 if native PM is not supported */ 590 if (!dev->pm_cap) 591 dev->current_state = PCI_D0; 592 } 593 594 return error; 595 } 596 597 /** 598 * __pci_start_power_transition - Start power transition of a PCI device 599 * @dev: PCI device to handle. 600 * @state: State to put the device into. 601 */ 602 static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state) 603 { 604 if (state == PCI_D0) 605 pci_platform_power_transition(dev, PCI_D0); 606 } 607 608 /** 609 * __pci_complete_power_transition - Complete power transition of a PCI device 610 * @dev: PCI device to handle. 611 * @state: State to put the device into. 612 * 613 * This function should not be called directly by device drivers. 614 */ 615 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state) 616 { 617 return state > PCI_D0 ? 618 pci_platform_power_transition(dev, state) : -EINVAL; 619 } 620 EXPORT_SYMBOL_GPL(__pci_complete_power_transition); 621 622 /** 623 * pci_set_power_state - Set the power state of a PCI device 624 * @dev: PCI device to handle. 625 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into. 626 * 627 * Transition a device to a new power state, using the platform firmware and/or 628 * the device's PCI PM registers. 629 * 630 * RETURN VALUE: 631 * -EINVAL if the requested state is invalid. 632 * -EIO if device does not support PCI PM or its PM capabilities register has a 633 * wrong version, or device doesn't support the requested state. 634 * 0 if device already is in the requested state. 635 * 0 if device's power state has been successfully changed. 636 */ 637 int pci_set_power_state(struct pci_dev *dev, pci_power_t state) 638 { 639 int error; 640 641 /* bound the state we're entering */ 642 if (state > PCI_D3hot) 643 state = PCI_D3hot; 644 else if (state < PCI_D0) 645 state = PCI_D0; 646 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev)) 647 /* 648 * If the device or the parent bridge do not support PCI PM, 649 * ignore the request if we're doing anything other than putting 650 * it into D0 (which would only happen on boot). 651 */ 652 return 0; 653 654 /* Check if we're already there */ 655 if (dev->current_state == state) 656 return 0; 657 658 __pci_start_power_transition(dev, state); 659 660 /* This device is quirked not to be put into D3, so 661 don't put it in D3 */ 662 if (state == PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3)) 663 return 0; 664 665 error = pci_raw_set_power_state(dev, state); 666 667 if (!__pci_complete_power_transition(dev, state)) 668 error = 0; 669 670 return error; 671 } 672 673 /** 674 * pci_choose_state - Choose the power state of a PCI device 675 * @dev: PCI device to be suspended 676 * @state: target sleep state for the whole system. This is the value 677 * that is passed to suspend() function. 678 * 679 * Returns PCI power state suitable for given device and given system 680 * message. 681 */ 682 683 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state) 684 { 685 pci_power_t ret; 686 687 if (!pci_find_capability(dev, PCI_CAP_ID_PM)) 688 return PCI_D0; 689 690 ret = platform_pci_choose_state(dev); 691 if (ret != PCI_POWER_ERROR) 692 return ret; 693 694 switch (state.event) { 695 case PM_EVENT_ON: 696 return PCI_D0; 697 case PM_EVENT_FREEZE: 698 case PM_EVENT_PRETHAW: 699 /* REVISIT both freeze and pre-thaw "should" use D0 */ 700 case PM_EVENT_SUSPEND: 701 case PM_EVENT_HIBERNATE: 702 return PCI_D3hot; 703 default: 704 dev_info(&dev->dev, "unrecognized suspend event %d\n", 705 state.event); 706 BUG(); 707 } 708 return PCI_D0; 709 } 710 711 EXPORT_SYMBOL(pci_choose_state); 712 713 #define PCI_EXP_SAVE_REGS 7 714 715 #define pcie_cap_has_devctl(type, flags) 1 716 #define pcie_cap_has_lnkctl(type, flags) \ 717 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \ 718 (type == PCI_EXP_TYPE_ROOT_PORT || \ 719 type == PCI_EXP_TYPE_ENDPOINT || \ 720 type == PCI_EXP_TYPE_LEG_END)) 721 #define pcie_cap_has_sltctl(type, flags) \ 722 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \ 723 ((type == PCI_EXP_TYPE_ROOT_PORT) || \ 724 (type == PCI_EXP_TYPE_DOWNSTREAM && \ 725 (flags & PCI_EXP_FLAGS_SLOT)))) 726 #define pcie_cap_has_rtctl(type, flags) \ 727 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \ 728 (type == PCI_EXP_TYPE_ROOT_PORT || \ 729 type == PCI_EXP_TYPE_RC_EC)) 730 #define pcie_cap_has_devctl2(type, flags) \ 731 ((flags & PCI_EXP_FLAGS_VERS) > 1) 732 #define pcie_cap_has_lnkctl2(type, flags) \ 733 ((flags & PCI_EXP_FLAGS_VERS) > 1) 734 #define pcie_cap_has_sltctl2(type, flags) \ 735 ((flags & PCI_EXP_FLAGS_VERS) > 1) 736 737 static int pci_save_pcie_state(struct pci_dev *dev) 738 { 739 int pos, i = 0; 740 struct pci_cap_saved_state *save_state; 741 u16 *cap; 742 u16 flags; 743 744 pos = pci_pcie_cap(dev); 745 if (!pos) 746 return 0; 747 748 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); 749 if (!save_state) { 750 dev_err(&dev->dev, "buffer not found in %s\n", __func__); 751 return -ENOMEM; 752 } 753 cap = (u16 *)&save_state->data[0]; 754 755 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags); 756 757 if (pcie_cap_has_devctl(dev->pcie_type, flags)) 758 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]); 759 if (pcie_cap_has_lnkctl(dev->pcie_type, flags)) 760 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]); 761 if (pcie_cap_has_sltctl(dev->pcie_type, flags)) 762 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]); 763 if (pcie_cap_has_rtctl(dev->pcie_type, flags)) 764 pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]); 765 if (pcie_cap_has_devctl2(dev->pcie_type, flags)) 766 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &cap[i++]); 767 if (pcie_cap_has_lnkctl2(dev->pcie_type, flags)) 768 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL2, &cap[i++]); 769 if (pcie_cap_has_sltctl2(dev->pcie_type, flags)) 770 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL2, &cap[i++]); 771 772 return 0; 773 } 774 775 static void pci_restore_pcie_state(struct pci_dev *dev) 776 { 777 int i = 0, pos; 778 struct pci_cap_saved_state *save_state; 779 u16 *cap; 780 u16 flags; 781 782 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); 783 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 784 if (!save_state || pos <= 0) 785 return; 786 cap = (u16 *)&save_state->data[0]; 787 788 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags); 789 790 if (pcie_cap_has_devctl(dev->pcie_type, flags)) 791 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]); 792 if (pcie_cap_has_lnkctl(dev->pcie_type, flags)) 793 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]); 794 if (pcie_cap_has_sltctl(dev->pcie_type, flags)) 795 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]); 796 if (pcie_cap_has_rtctl(dev->pcie_type, flags)) 797 pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]); 798 if (pcie_cap_has_devctl2(dev->pcie_type, flags)) 799 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, cap[i++]); 800 if (pcie_cap_has_lnkctl2(dev->pcie_type, flags)) 801 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL2, cap[i++]); 802 if (pcie_cap_has_sltctl2(dev->pcie_type, flags)) 803 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL2, cap[i++]); 804 } 805 806 807 static int pci_save_pcix_state(struct pci_dev *dev) 808 { 809 int pos; 810 struct pci_cap_saved_state *save_state; 811 812 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); 813 if (pos <= 0) 814 return 0; 815 816 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); 817 if (!save_state) { 818 dev_err(&dev->dev, "buffer not found in %s\n", __func__); 819 return -ENOMEM; 820 } 821 822 pci_read_config_word(dev, pos + PCI_X_CMD, (u16 *)save_state->data); 823 824 return 0; 825 } 826 827 static void pci_restore_pcix_state(struct pci_dev *dev) 828 { 829 int i = 0, pos; 830 struct pci_cap_saved_state *save_state; 831 u16 *cap; 832 833 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); 834 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); 835 if (!save_state || pos <= 0) 836 return; 837 cap = (u16 *)&save_state->data[0]; 838 839 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]); 840 } 841 842 843 /** 844 * pci_save_state - save the PCI configuration space of a device before suspending 845 * @dev: - PCI device that we're dealing with 846 */ 847 int 848 pci_save_state(struct pci_dev *dev) 849 { 850 int i; 851 /* XXX: 100% dword access ok here? */ 852 for (i = 0; i < 16; i++) 853 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]); 854 dev->state_saved = true; 855 if ((i = pci_save_pcie_state(dev)) != 0) 856 return i; 857 if ((i = pci_save_pcix_state(dev)) != 0) 858 return i; 859 return 0; 860 } 861 862 /** 863 * pci_restore_state - Restore the saved state of a PCI device 864 * @dev: - PCI device that we're dealing with 865 */ 866 int 867 pci_restore_state(struct pci_dev *dev) 868 { 869 int i; 870 u32 val; 871 872 if (!dev->state_saved) 873 return 0; 874 875 /* PCI Express register must be restored first */ 876 pci_restore_pcie_state(dev); 877 878 /* 879 * The Base Address register should be programmed before the command 880 * register(s) 881 */ 882 for (i = 15; i >= 0; i--) { 883 pci_read_config_dword(dev, i * 4, &val); 884 if (val != dev->saved_config_space[i]) { 885 dev_printk(KERN_DEBUG, &dev->dev, "restoring config " 886 "space at offset %#x (was %#x, writing %#x)\n", 887 i, val, (int)dev->saved_config_space[i]); 888 pci_write_config_dword(dev,i * 4, 889 dev->saved_config_space[i]); 890 } 891 } 892 pci_restore_pcix_state(dev); 893 pci_restore_msi_state(dev); 894 pci_restore_iov_state(dev); 895 896 dev->state_saved = false; 897 898 return 0; 899 } 900 901 static int do_pci_enable_device(struct pci_dev *dev, int bars) 902 { 903 int err; 904 905 err = pci_set_power_state(dev, PCI_D0); 906 if (err < 0 && err != -EIO) 907 return err; 908 err = pcibios_enable_device(dev, bars); 909 if (err < 0) 910 return err; 911 pci_fixup_device(pci_fixup_enable, dev); 912 913 return 0; 914 } 915 916 /** 917 * pci_reenable_device - Resume abandoned device 918 * @dev: PCI device to be resumed 919 * 920 * Note this function is a backend of pci_default_resume and is not supposed 921 * to be called by normal code, write proper resume handler and use it instead. 922 */ 923 int pci_reenable_device(struct pci_dev *dev) 924 { 925 if (pci_is_enabled(dev)) 926 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1); 927 return 0; 928 } 929 930 static int __pci_enable_device_flags(struct pci_dev *dev, 931 resource_size_t flags) 932 { 933 int err; 934 int i, bars = 0; 935 936 if (atomic_add_return(1, &dev->enable_cnt) > 1) 937 return 0; /* already enabled */ 938 939 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) 940 if (dev->resource[i].flags & flags) 941 bars |= (1 << i); 942 943 err = do_pci_enable_device(dev, bars); 944 if (err < 0) 945 atomic_dec(&dev->enable_cnt); 946 return err; 947 } 948 949 /** 950 * pci_enable_device_io - Initialize a device for use with IO space 951 * @dev: PCI device to be initialized 952 * 953 * Initialize device before it's used by a driver. Ask low-level code 954 * to enable I/O resources. Wake up the device if it was suspended. 955 * Beware, this function can fail. 956 */ 957 int pci_enable_device_io(struct pci_dev *dev) 958 { 959 return __pci_enable_device_flags(dev, IORESOURCE_IO); 960 } 961 962 /** 963 * pci_enable_device_mem - Initialize a device for use with Memory space 964 * @dev: PCI device to be initialized 965 * 966 * Initialize device before it's used by a driver. Ask low-level code 967 * to enable Memory resources. Wake up the device if it was suspended. 968 * Beware, this function can fail. 969 */ 970 int pci_enable_device_mem(struct pci_dev *dev) 971 { 972 return __pci_enable_device_flags(dev, IORESOURCE_MEM); 973 } 974 975 /** 976 * pci_enable_device - Initialize device before it's used by a driver. 977 * @dev: PCI device to be initialized 978 * 979 * Initialize device before it's used by a driver. Ask low-level code 980 * to enable I/O and memory. Wake up the device if it was suspended. 981 * Beware, this function can fail. 982 * 983 * Note we don't actually enable the device many times if we call 984 * this function repeatedly (we just increment the count). 985 */ 986 int pci_enable_device(struct pci_dev *dev) 987 { 988 return __pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO); 989 } 990 991 /* 992 * Managed PCI resources. This manages device on/off, intx/msi/msix 993 * on/off and BAR regions. pci_dev itself records msi/msix status, so 994 * there's no need to track it separately. pci_devres is initialized 995 * when a device is enabled using managed PCI device enable interface. 996 */ 997 struct pci_devres { 998 unsigned int enabled:1; 999 unsigned int pinned:1; 1000 unsigned int orig_intx:1; 1001 unsigned int restore_intx:1; 1002 u32 region_mask; 1003 }; 1004 1005 static void pcim_release(struct device *gendev, void *res) 1006 { 1007 struct pci_dev *dev = container_of(gendev, struct pci_dev, dev); 1008 struct pci_devres *this = res; 1009 int i; 1010 1011 if (dev->msi_enabled) 1012 pci_disable_msi(dev); 1013 if (dev->msix_enabled) 1014 pci_disable_msix(dev); 1015 1016 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) 1017 if (this->region_mask & (1 << i)) 1018 pci_release_region(dev, i); 1019 1020 if (this->restore_intx) 1021 pci_intx(dev, this->orig_intx); 1022 1023 if (this->enabled && !this->pinned) 1024 pci_disable_device(dev); 1025 } 1026 1027 static struct pci_devres * get_pci_dr(struct pci_dev *pdev) 1028 { 1029 struct pci_devres *dr, *new_dr; 1030 1031 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL); 1032 if (dr) 1033 return dr; 1034 1035 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL); 1036 if (!new_dr) 1037 return NULL; 1038 return devres_get(&pdev->dev, new_dr, NULL, NULL); 1039 } 1040 1041 static struct pci_devres * find_pci_dr(struct pci_dev *pdev) 1042 { 1043 if (pci_is_managed(pdev)) 1044 return devres_find(&pdev->dev, pcim_release, NULL, NULL); 1045 return NULL; 1046 } 1047 1048 /** 1049 * pcim_enable_device - Managed pci_enable_device() 1050 * @pdev: PCI device to be initialized 1051 * 1052 * Managed pci_enable_device(). 1053 */ 1054 int pcim_enable_device(struct pci_dev *pdev) 1055 { 1056 struct pci_devres *dr; 1057 int rc; 1058 1059 dr = get_pci_dr(pdev); 1060 if (unlikely(!dr)) 1061 return -ENOMEM; 1062 if (dr->enabled) 1063 return 0; 1064 1065 rc = pci_enable_device(pdev); 1066 if (!rc) { 1067 pdev->is_managed = 1; 1068 dr->enabled = 1; 1069 } 1070 return rc; 1071 } 1072 1073 /** 1074 * pcim_pin_device - Pin managed PCI device 1075 * @pdev: PCI device to pin 1076 * 1077 * Pin managed PCI device @pdev. Pinned device won't be disabled on 1078 * driver detach. @pdev must have been enabled with 1079 * pcim_enable_device(). 1080 */ 1081 void pcim_pin_device(struct pci_dev *pdev) 1082 { 1083 struct pci_devres *dr; 1084 1085 dr = find_pci_dr(pdev); 1086 WARN_ON(!dr || !dr->enabled); 1087 if (dr) 1088 dr->pinned = 1; 1089 } 1090 1091 /** 1092 * pcibios_disable_device - disable arch specific PCI resources for device dev 1093 * @dev: the PCI device to disable 1094 * 1095 * Disables architecture specific PCI resources for the device. This 1096 * is the default implementation. Architecture implementations can 1097 * override this. 1098 */ 1099 void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {} 1100 1101 static void do_pci_disable_device(struct pci_dev *dev) 1102 { 1103 u16 pci_command; 1104 1105 pci_read_config_word(dev, PCI_COMMAND, &pci_command); 1106 if (pci_command & PCI_COMMAND_MASTER) { 1107 pci_command &= ~PCI_COMMAND_MASTER; 1108 pci_write_config_word(dev, PCI_COMMAND, pci_command); 1109 } 1110 1111 pcibios_disable_device(dev); 1112 } 1113 1114 /** 1115 * pci_disable_enabled_device - Disable device without updating enable_cnt 1116 * @dev: PCI device to disable 1117 * 1118 * NOTE: This function is a backend of PCI power management routines and is 1119 * not supposed to be called drivers. 1120 */ 1121 void pci_disable_enabled_device(struct pci_dev *dev) 1122 { 1123 if (pci_is_enabled(dev)) 1124 do_pci_disable_device(dev); 1125 } 1126 1127 /** 1128 * pci_disable_device - Disable PCI device after use 1129 * @dev: PCI device to be disabled 1130 * 1131 * Signal to the system that the PCI device is not in use by the system 1132 * anymore. This only involves disabling PCI bus-mastering, if active. 1133 * 1134 * Note we don't actually disable the device until all callers of 1135 * pci_device_enable() have called pci_device_disable(). 1136 */ 1137 void 1138 pci_disable_device(struct pci_dev *dev) 1139 { 1140 struct pci_devres *dr; 1141 1142 dr = find_pci_dr(dev); 1143 if (dr) 1144 dr->enabled = 0; 1145 1146 if (atomic_sub_return(1, &dev->enable_cnt) != 0) 1147 return; 1148 1149 do_pci_disable_device(dev); 1150 1151 dev->is_busmaster = 0; 1152 } 1153 1154 /** 1155 * pcibios_set_pcie_reset_state - set reset state for device dev 1156 * @dev: the PCI-E device reset 1157 * @state: Reset state to enter into 1158 * 1159 * 1160 * Sets the PCI-E reset state for the device. This is the default 1161 * implementation. Architecture implementations can override this. 1162 */ 1163 int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev, 1164 enum pcie_reset_state state) 1165 { 1166 return -EINVAL; 1167 } 1168 1169 /** 1170 * pci_set_pcie_reset_state - set reset state for device dev 1171 * @dev: the PCI-E device reset 1172 * @state: Reset state to enter into 1173 * 1174 * 1175 * Sets the PCI reset state for the device. 1176 */ 1177 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state) 1178 { 1179 return pcibios_set_pcie_reset_state(dev, state); 1180 } 1181 1182 /** 1183 * pci_pme_capable - check the capability of PCI device to generate PME# 1184 * @dev: PCI device to handle. 1185 * @state: PCI state from which device will issue PME#. 1186 */ 1187 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state) 1188 { 1189 if (!dev->pm_cap) 1190 return false; 1191 1192 return !!(dev->pme_support & (1 << state)); 1193 } 1194 1195 /** 1196 * pci_pme_active - enable or disable PCI device's PME# function 1197 * @dev: PCI device to handle. 1198 * @enable: 'true' to enable PME# generation; 'false' to disable it. 1199 * 1200 * The caller must verify that the device is capable of generating PME# before 1201 * calling this function with @enable equal to 'true'. 1202 */ 1203 void pci_pme_active(struct pci_dev *dev, bool enable) 1204 { 1205 u16 pmcsr; 1206 1207 if (!dev->pm_cap) 1208 return; 1209 1210 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); 1211 /* Clear PME_Status by writing 1 to it and enable PME# */ 1212 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE; 1213 if (!enable) 1214 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE; 1215 1216 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); 1217 1218 dev_printk(KERN_DEBUG, &dev->dev, "PME# %s\n", 1219 enable ? "enabled" : "disabled"); 1220 } 1221 1222 /** 1223 * pci_enable_wake - enable PCI device as wakeup event source 1224 * @dev: PCI device affected 1225 * @state: PCI state from which device will issue wakeup events 1226 * @enable: True to enable event generation; false to disable 1227 * 1228 * This enables the device as a wakeup event source, or disables it. 1229 * When such events involves platform-specific hooks, those hooks are 1230 * called automatically by this routine. 1231 * 1232 * Devices with legacy power management (no standard PCI PM capabilities) 1233 * always require such platform hooks. 1234 * 1235 * RETURN VALUE: 1236 * 0 is returned on success 1237 * -EINVAL is returned if device is not supposed to wake up the system 1238 * Error code depending on the platform is returned if both the platform and 1239 * the native mechanism fail to enable the generation of wake-up events 1240 */ 1241 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable) 1242 { 1243 int ret = 0; 1244 1245 if (enable && !device_may_wakeup(&dev->dev)) 1246 return -EINVAL; 1247 1248 /* Don't do the same thing twice in a row for one device. */ 1249 if (!!enable == !!dev->wakeup_prepared) 1250 return 0; 1251 1252 /* 1253 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don 1254 * Anderson we should be doing PME# wake enable followed by ACPI wake 1255 * enable. To disable wake-up we call the platform first, for symmetry. 1256 */ 1257 1258 if (enable) { 1259 int error; 1260 1261 if (pci_pme_capable(dev, state)) 1262 pci_pme_active(dev, true); 1263 else 1264 ret = 1; 1265 error = platform_pci_sleep_wake(dev, true); 1266 if (ret) 1267 ret = error; 1268 if (!ret) 1269 dev->wakeup_prepared = true; 1270 } else { 1271 platform_pci_sleep_wake(dev, false); 1272 pci_pme_active(dev, false); 1273 dev->wakeup_prepared = false; 1274 } 1275 1276 return ret; 1277 } 1278 1279 /** 1280 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold 1281 * @dev: PCI device to prepare 1282 * @enable: True to enable wake-up event generation; false to disable 1283 * 1284 * Many drivers want the device to wake up the system from D3_hot or D3_cold 1285 * and this function allows them to set that up cleanly - pci_enable_wake() 1286 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI 1287 * ordering constraints. 1288 * 1289 * This function only returns error code if the device is not capable of 1290 * generating PME# from both D3_hot and D3_cold, and the platform is unable to 1291 * enable wake-up power for it. 1292 */ 1293 int pci_wake_from_d3(struct pci_dev *dev, bool enable) 1294 { 1295 return pci_pme_capable(dev, PCI_D3cold) ? 1296 pci_enable_wake(dev, PCI_D3cold, enable) : 1297 pci_enable_wake(dev, PCI_D3hot, enable); 1298 } 1299 1300 /** 1301 * pci_target_state - find an appropriate low power state for a given PCI dev 1302 * @dev: PCI device 1303 * 1304 * Use underlying platform code to find a supported low power state for @dev. 1305 * If the platform can't manage @dev, return the deepest state from which it 1306 * can generate wake events, based on any available PME info. 1307 */ 1308 pci_power_t pci_target_state(struct pci_dev *dev) 1309 { 1310 pci_power_t target_state = PCI_D3hot; 1311 1312 if (platform_pci_power_manageable(dev)) { 1313 /* 1314 * Call the platform to choose the target state of the device 1315 * and enable wake-up from this state if supported. 1316 */ 1317 pci_power_t state = platform_pci_choose_state(dev); 1318 1319 switch (state) { 1320 case PCI_POWER_ERROR: 1321 case PCI_UNKNOWN: 1322 break; 1323 case PCI_D1: 1324 case PCI_D2: 1325 if (pci_no_d1d2(dev)) 1326 break; 1327 default: 1328 target_state = state; 1329 } 1330 } else if (!dev->pm_cap) { 1331 target_state = PCI_D0; 1332 } else if (device_may_wakeup(&dev->dev)) { 1333 /* 1334 * Find the deepest state from which the device can generate 1335 * wake-up events, make it the target state and enable device 1336 * to generate PME#. 1337 */ 1338 if (dev->pme_support) { 1339 while (target_state 1340 && !(dev->pme_support & (1 << target_state))) 1341 target_state--; 1342 } 1343 } 1344 1345 return target_state; 1346 } 1347 1348 /** 1349 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state 1350 * @dev: Device to handle. 1351 * 1352 * Choose the power state appropriate for the device depending on whether 1353 * it can wake up the system and/or is power manageable by the platform 1354 * (PCI_D3hot is the default) and put the device into that state. 1355 */ 1356 int pci_prepare_to_sleep(struct pci_dev *dev) 1357 { 1358 pci_power_t target_state = pci_target_state(dev); 1359 int error; 1360 1361 if (target_state == PCI_POWER_ERROR) 1362 return -EIO; 1363 1364 pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev)); 1365 1366 error = pci_set_power_state(dev, target_state); 1367 1368 if (error) 1369 pci_enable_wake(dev, target_state, false); 1370 1371 return error; 1372 } 1373 1374 /** 1375 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state 1376 * @dev: Device to handle. 1377 * 1378 * Disable device's sytem wake-up capability and put it into D0. 1379 */ 1380 int pci_back_from_sleep(struct pci_dev *dev) 1381 { 1382 pci_enable_wake(dev, PCI_D0, false); 1383 return pci_set_power_state(dev, PCI_D0); 1384 } 1385 1386 /** 1387 * pci_pm_init - Initialize PM functions of given PCI device 1388 * @dev: PCI device to handle. 1389 */ 1390 void pci_pm_init(struct pci_dev *dev) 1391 { 1392 int pm; 1393 u16 pmc; 1394 1395 dev->wakeup_prepared = false; 1396 dev->pm_cap = 0; 1397 1398 /* find PCI PM capability in list */ 1399 pm = pci_find_capability(dev, PCI_CAP_ID_PM); 1400 if (!pm) 1401 return; 1402 /* Check device's ability to generate PME# */ 1403 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc); 1404 1405 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) { 1406 dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n", 1407 pmc & PCI_PM_CAP_VER_MASK); 1408 return; 1409 } 1410 1411 dev->pm_cap = pm; 1412 1413 dev->d1_support = false; 1414 dev->d2_support = false; 1415 if (!pci_no_d1d2(dev)) { 1416 if (pmc & PCI_PM_CAP_D1) 1417 dev->d1_support = true; 1418 if (pmc & PCI_PM_CAP_D2) 1419 dev->d2_support = true; 1420 1421 if (dev->d1_support || dev->d2_support) 1422 dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n", 1423 dev->d1_support ? " D1" : "", 1424 dev->d2_support ? " D2" : ""); 1425 } 1426 1427 pmc &= PCI_PM_CAP_PME_MASK; 1428 if (pmc) { 1429 dev_printk(KERN_DEBUG, &dev->dev, 1430 "PME# supported from%s%s%s%s%s\n", 1431 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "", 1432 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "", 1433 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "", 1434 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "", 1435 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : ""); 1436 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT; 1437 /* 1438 * Make device's PM flags reflect the wake-up capability, but 1439 * let the user space enable it to wake up the system as needed. 1440 */ 1441 device_set_wakeup_capable(&dev->dev, true); 1442 device_set_wakeup_enable(&dev->dev, false); 1443 /* Disable the PME# generation functionality */ 1444 pci_pme_active(dev, false); 1445 } else { 1446 dev->pme_support = 0; 1447 } 1448 } 1449 1450 /** 1451 * platform_pci_wakeup_init - init platform wakeup if present 1452 * @dev: PCI device 1453 * 1454 * Some devices don't have PCI PM caps but can still generate wakeup 1455 * events through platform methods (like ACPI events). If @dev supports 1456 * platform wakeup events, set the device flag to indicate as much. This 1457 * may be redundant if the device also supports PCI PM caps, but double 1458 * initialization should be safe in that case. 1459 */ 1460 void platform_pci_wakeup_init(struct pci_dev *dev) 1461 { 1462 if (!platform_pci_can_wakeup(dev)) 1463 return; 1464 1465 device_set_wakeup_capable(&dev->dev, true); 1466 device_set_wakeup_enable(&dev->dev, false); 1467 platform_pci_sleep_wake(dev, false); 1468 } 1469 1470 /** 1471 * pci_add_save_buffer - allocate buffer for saving given capability registers 1472 * @dev: the PCI device 1473 * @cap: the capability to allocate the buffer for 1474 * @size: requested size of the buffer 1475 */ 1476 static int pci_add_cap_save_buffer( 1477 struct pci_dev *dev, char cap, unsigned int size) 1478 { 1479 int pos; 1480 struct pci_cap_saved_state *save_state; 1481 1482 pos = pci_find_capability(dev, cap); 1483 if (pos <= 0) 1484 return 0; 1485 1486 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL); 1487 if (!save_state) 1488 return -ENOMEM; 1489 1490 save_state->cap_nr = cap; 1491 pci_add_saved_cap(dev, save_state); 1492 1493 return 0; 1494 } 1495 1496 /** 1497 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities 1498 * @dev: the PCI device 1499 */ 1500 void pci_allocate_cap_save_buffers(struct pci_dev *dev) 1501 { 1502 int error; 1503 1504 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP, 1505 PCI_EXP_SAVE_REGS * sizeof(u16)); 1506 if (error) 1507 dev_err(&dev->dev, 1508 "unable to preallocate PCI Express save buffer\n"); 1509 1510 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16)); 1511 if (error) 1512 dev_err(&dev->dev, 1513 "unable to preallocate PCI-X save buffer\n"); 1514 } 1515 1516 /** 1517 * pci_enable_ari - enable ARI forwarding if hardware support it 1518 * @dev: the PCI device 1519 */ 1520 void pci_enable_ari(struct pci_dev *dev) 1521 { 1522 int pos; 1523 u32 cap; 1524 u16 ctrl; 1525 struct pci_dev *bridge; 1526 1527 if (!pci_is_pcie(dev) || dev->devfn) 1528 return; 1529 1530 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI); 1531 if (!pos) 1532 return; 1533 1534 bridge = dev->bus->self; 1535 if (!bridge || !pci_is_pcie(bridge)) 1536 return; 1537 1538 pos = pci_pcie_cap(bridge); 1539 if (!pos) 1540 return; 1541 1542 pci_read_config_dword(bridge, pos + PCI_EXP_DEVCAP2, &cap); 1543 if (!(cap & PCI_EXP_DEVCAP2_ARI)) 1544 return; 1545 1546 pci_read_config_word(bridge, pos + PCI_EXP_DEVCTL2, &ctrl); 1547 ctrl |= PCI_EXP_DEVCTL2_ARI; 1548 pci_write_config_word(bridge, pos + PCI_EXP_DEVCTL2, ctrl); 1549 1550 bridge->ari_enabled = 1; 1551 } 1552 1553 static int pci_acs_enable; 1554 1555 /** 1556 * pci_request_acs - ask for ACS to be enabled if supported 1557 */ 1558 void pci_request_acs(void) 1559 { 1560 pci_acs_enable = 1; 1561 } 1562 1563 /** 1564 * pci_enable_acs - enable ACS if hardware support it 1565 * @dev: the PCI device 1566 */ 1567 void pci_enable_acs(struct pci_dev *dev) 1568 { 1569 int pos; 1570 u16 cap; 1571 u16 ctrl; 1572 1573 if (!pci_acs_enable) 1574 return; 1575 1576 if (!pci_is_pcie(dev)) 1577 return; 1578 1579 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS); 1580 if (!pos) 1581 return; 1582 1583 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap); 1584 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl); 1585 1586 /* Source Validation */ 1587 ctrl |= (cap & PCI_ACS_SV); 1588 1589 /* P2P Request Redirect */ 1590 ctrl |= (cap & PCI_ACS_RR); 1591 1592 /* P2P Completion Redirect */ 1593 ctrl |= (cap & PCI_ACS_CR); 1594 1595 /* Upstream Forwarding */ 1596 ctrl |= (cap & PCI_ACS_UF); 1597 1598 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl); 1599 } 1600 1601 /** 1602 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge 1603 * @dev: the PCI device 1604 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTD, 4=INTD) 1605 * 1606 * Perform INTx swizzling for a device behind one level of bridge. This is 1607 * required by section 9.1 of the PCI-to-PCI bridge specification for devices 1608 * behind bridges on add-in cards. For devices with ARI enabled, the slot 1609 * number is always 0 (see the Implementation Note in section 2.2.8.1 of 1610 * the PCI Express Base Specification, Revision 2.1) 1611 */ 1612 u8 pci_swizzle_interrupt_pin(struct pci_dev *dev, u8 pin) 1613 { 1614 int slot; 1615 1616 if (pci_ari_enabled(dev->bus)) 1617 slot = 0; 1618 else 1619 slot = PCI_SLOT(dev->devfn); 1620 1621 return (((pin - 1) + slot) % 4) + 1; 1622 } 1623 1624 int 1625 pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge) 1626 { 1627 u8 pin; 1628 1629 pin = dev->pin; 1630 if (!pin) 1631 return -1; 1632 1633 while (!pci_is_root_bus(dev->bus)) { 1634 pin = pci_swizzle_interrupt_pin(dev, pin); 1635 dev = dev->bus->self; 1636 } 1637 *bridge = dev; 1638 return pin; 1639 } 1640 1641 /** 1642 * pci_common_swizzle - swizzle INTx all the way to root bridge 1643 * @dev: the PCI device 1644 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD) 1645 * 1646 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI 1647 * bridges all the way up to a PCI root bus. 1648 */ 1649 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp) 1650 { 1651 u8 pin = *pinp; 1652 1653 while (!pci_is_root_bus(dev->bus)) { 1654 pin = pci_swizzle_interrupt_pin(dev, pin); 1655 dev = dev->bus->self; 1656 } 1657 *pinp = pin; 1658 return PCI_SLOT(dev->devfn); 1659 } 1660 1661 /** 1662 * pci_release_region - Release a PCI bar 1663 * @pdev: PCI device whose resources were previously reserved by pci_request_region 1664 * @bar: BAR to release 1665 * 1666 * Releases the PCI I/O and memory resources previously reserved by a 1667 * successful call to pci_request_region. Call this function only 1668 * after all use of the PCI regions has ceased. 1669 */ 1670 void pci_release_region(struct pci_dev *pdev, int bar) 1671 { 1672 struct pci_devres *dr; 1673 1674 if (pci_resource_len(pdev, bar) == 0) 1675 return; 1676 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) 1677 release_region(pci_resource_start(pdev, bar), 1678 pci_resource_len(pdev, bar)); 1679 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) 1680 release_mem_region(pci_resource_start(pdev, bar), 1681 pci_resource_len(pdev, bar)); 1682 1683 dr = find_pci_dr(pdev); 1684 if (dr) 1685 dr->region_mask &= ~(1 << bar); 1686 } 1687 1688 /** 1689 * __pci_request_region - Reserved PCI I/O and memory resource 1690 * @pdev: PCI device whose resources are to be reserved 1691 * @bar: BAR to be reserved 1692 * @res_name: Name to be associated with resource. 1693 * @exclusive: whether the region access is exclusive or not 1694 * 1695 * Mark the PCI region associated with PCI device @pdev BR @bar as 1696 * being reserved by owner @res_name. Do not access any 1697 * address inside the PCI regions unless this call returns 1698 * successfully. 1699 * 1700 * If @exclusive is set, then the region is marked so that userspace 1701 * is explicitly not allowed to map the resource via /dev/mem or 1702 * sysfs MMIO access. 1703 * 1704 * Returns 0 on success, or %EBUSY on error. A warning 1705 * message is also printed on failure. 1706 */ 1707 static int __pci_request_region(struct pci_dev *pdev, int bar, const char *res_name, 1708 int exclusive) 1709 { 1710 struct pci_devres *dr; 1711 1712 if (pci_resource_len(pdev, bar) == 0) 1713 return 0; 1714 1715 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) { 1716 if (!request_region(pci_resource_start(pdev, bar), 1717 pci_resource_len(pdev, bar), res_name)) 1718 goto err_out; 1719 } 1720 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) { 1721 if (!__request_mem_region(pci_resource_start(pdev, bar), 1722 pci_resource_len(pdev, bar), res_name, 1723 exclusive)) 1724 goto err_out; 1725 } 1726 1727 dr = find_pci_dr(pdev); 1728 if (dr) 1729 dr->region_mask |= 1 << bar; 1730 1731 return 0; 1732 1733 err_out: 1734 dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar, 1735 &pdev->resource[bar]); 1736 return -EBUSY; 1737 } 1738 1739 /** 1740 * pci_request_region - Reserve PCI I/O and memory resource 1741 * @pdev: PCI device whose resources are to be reserved 1742 * @bar: BAR to be reserved 1743 * @res_name: Name to be associated with resource 1744 * 1745 * Mark the PCI region associated with PCI device @pdev BAR @bar as 1746 * being reserved by owner @res_name. Do not access any 1747 * address inside the PCI regions unless this call returns 1748 * successfully. 1749 * 1750 * Returns 0 on success, or %EBUSY on error. A warning 1751 * message is also printed on failure. 1752 */ 1753 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) 1754 { 1755 return __pci_request_region(pdev, bar, res_name, 0); 1756 } 1757 1758 /** 1759 * pci_request_region_exclusive - Reserved PCI I/O and memory resource 1760 * @pdev: PCI device whose resources are to be reserved 1761 * @bar: BAR to be reserved 1762 * @res_name: Name to be associated with resource. 1763 * 1764 * Mark the PCI region associated with PCI device @pdev BR @bar as 1765 * being reserved by owner @res_name. Do not access any 1766 * address inside the PCI regions unless this call returns 1767 * successfully. 1768 * 1769 * Returns 0 on success, or %EBUSY on error. A warning 1770 * message is also printed on failure. 1771 * 1772 * The key difference that _exclusive makes it that userspace is 1773 * explicitly not allowed to map the resource via /dev/mem or 1774 * sysfs. 1775 */ 1776 int pci_request_region_exclusive(struct pci_dev *pdev, int bar, const char *res_name) 1777 { 1778 return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE); 1779 } 1780 /** 1781 * pci_release_selected_regions - Release selected PCI I/O and memory resources 1782 * @pdev: PCI device whose resources were previously reserved 1783 * @bars: Bitmask of BARs to be released 1784 * 1785 * Release selected PCI I/O and memory resources previously reserved. 1786 * Call this function only after all use of the PCI regions has ceased. 1787 */ 1788 void pci_release_selected_regions(struct pci_dev *pdev, int bars) 1789 { 1790 int i; 1791 1792 for (i = 0; i < 6; i++) 1793 if (bars & (1 << i)) 1794 pci_release_region(pdev, i); 1795 } 1796 1797 int __pci_request_selected_regions(struct pci_dev *pdev, int bars, 1798 const char *res_name, int excl) 1799 { 1800 int i; 1801 1802 for (i = 0; i < 6; i++) 1803 if (bars & (1 << i)) 1804 if (__pci_request_region(pdev, i, res_name, excl)) 1805 goto err_out; 1806 return 0; 1807 1808 err_out: 1809 while(--i >= 0) 1810 if (bars & (1 << i)) 1811 pci_release_region(pdev, i); 1812 1813 return -EBUSY; 1814 } 1815 1816 1817 /** 1818 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources 1819 * @pdev: PCI device whose resources are to be reserved 1820 * @bars: Bitmask of BARs to be requested 1821 * @res_name: Name to be associated with resource 1822 */ 1823 int pci_request_selected_regions(struct pci_dev *pdev, int bars, 1824 const char *res_name) 1825 { 1826 return __pci_request_selected_regions(pdev, bars, res_name, 0); 1827 } 1828 1829 int pci_request_selected_regions_exclusive(struct pci_dev *pdev, 1830 int bars, const char *res_name) 1831 { 1832 return __pci_request_selected_regions(pdev, bars, res_name, 1833 IORESOURCE_EXCLUSIVE); 1834 } 1835 1836 /** 1837 * pci_release_regions - Release reserved PCI I/O and memory resources 1838 * @pdev: PCI device whose resources were previously reserved by pci_request_regions 1839 * 1840 * Releases all PCI I/O and memory resources previously reserved by a 1841 * successful call to pci_request_regions. Call this function only 1842 * after all use of the PCI regions has ceased. 1843 */ 1844 1845 void pci_release_regions(struct pci_dev *pdev) 1846 { 1847 pci_release_selected_regions(pdev, (1 << 6) - 1); 1848 } 1849 1850 /** 1851 * pci_request_regions - Reserved PCI I/O and memory resources 1852 * @pdev: PCI device whose resources are to be reserved 1853 * @res_name: Name to be associated with resource. 1854 * 1855 * Mark all PCI regions associated with PCI device @pdev as 1856 * being reserved by owner @res_name. Do not access any 1857 * address inside the PCI regions unless this call returns 1858 * successfully. 1859 * 1860 * Returns 0 on success, or %EBUSY on error. A warning 1861 * message is also printed on failure. 1862 */ 1863 int pci_request_regions(struct pci_dev *pdev, const char *res_name) 1864 { 1865 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name); 1866 } 1867 1868 /** 1869 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources 1870 * @pdev: PCI device whose resources are to be reserved 1871 * @res_name: Name to be associated with resource. 1872 * 1873 * Mark all PCI regions associated with PCI device @pdev as 1874 * being reserved by owner @res_name. Do not access any 1875 * address inside the PCI regions unless this call returns 1876 * successfully. 1877 * 1878 * pci_request_regions_exclusive() will mark the region so that 1879 * /dev/mem and the sysfs MMIO access will not be allowed. 1880 * 1881 * Returns 0 on success, or %EBUSY on error. A warning 1882 * message is also printed on failure. 1883 */ 1884 int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name) 1885 { 1886 return pci_request_selected_regions_exclusive(pdev, 1887 ((1 << 6) - 1), res_name); 1888 } 1889 1890 static void __pci_set_master(struct pci_dev *dev, bool enable) 1891 { 1892 u16 old_cmd, cmd; 1893 1894 pci_read_config_word(dev, PCI_COMMAND, &old_cmd); 1895 if (enable) 1896 cmd = old_cmd | PCI_COMMAND_MASTER; 1897 else 1898 cmd = old_cmd & ~PCI_COMMAND_MASTER; 1899 if (cmd != old_cmd) { 1900 dev_dbg(&dev->dev, "%s bus mastering\n", 1901 enable ? "enabling" : "disabling"); 1902 pci_write_config_word(dev, PCI_COMMAND, cmd); 1903 } 1904 dev->is_busmaster = enable; 1905 } 1906 1907 /** 1908 * pci_set_master - enables bus-mastering for device dev 1909 * @dev: the PCI device to enable 1910 * 1911 * Enables bus-mastering on the device and calls pcibios_set_master() 1912 * to do the needed arch specific settings. 1913 */ 1914 void pci_set_master(struct pci_dev *dev) 1915 { 1916 __pci_set_master(dev, true); 1917 pcibios_set_master(dev); 1918 } 1919 1920 /** 1921 * pci_clear_master - disables bus-mastering for device dev 1922 * @dev: the PCI device to disable 1923 */ 1924 void pci_clear_master(struct pci_dev *dev) 1925 { 1926 __pci_set_master(dev, false); 1927 } 1928 1929 /** 1930 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed 1931 * @dev: the PCI device for which MWI is to be enabled 1932 * 1933 * Helper function for pci_set_mwi. 1934 * Originally copied from drivers/net/acenic.c. 1935 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. 1936 * 1937 * RETURNS: An appropriate -ERRNO error value on error, or zero for success. 1938 */ 1939 int pci_set_cacheline_size(struct pci_dev *dev) 1940 { 1941 u8 cacheline_size; 1942 1943 if (!pci_cache_line_size) 1944 return -EINVAL; 1945 1946 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be 1947 equal to or multiple of the right value. */ 1948 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); 1949 if (cacheline_size >= pci_cache_line_size && 1950 (cacheline_size % pci_cache_line_size) == 0) 1951 return 0; 1952 1953 /* Write the correct value. */ 1954 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size); 1955 /* Read it back. */ 1956 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); 1957 if (cacheline_size == pci_cache_line_size) 1958 return 0; 1959 1960 dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not " 1961 "supported\n", pci_cache_line_size << 2); 1962 1963 return -EINVAL; 1964 } 1965 EXPORT_SYMBOL_GPL(pci_set_cacheline_size); 1966 1967 #ifdef PCI_DISABLE_MWI 1968 int pci_set_mwi(struct pci_dev *dev) 1969 { 1970 return 0; 1971 } 1972 1973 int pci_try_set_mwi(struct pci_dev *dev) 1974 { 1975 return 0; 1976 } 1977 1978 void pci_clear_mwi(struct pci_dev *dev) 1979 { 1980 } 1981 1982 #else 1983 1984 /** 1985 * pci_set_mwi - enables memory-write-invalidate PCI transaction 1986 * @dev: the PCI device for which MWI is enabled 1987 * 1988 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. 1989 * 1990 * RETURNS: An appropriate -ERRNO error value on error, or zero for success. 1991 */ 1992 int 1993 pci_set_mwi(struct pci_dev *dev) 1994 { 1995 int rc; 1996 u16 cmd; 1997 1998 rc = pci_set_cacheline_size(dev); 1999 if (rc) 2000 return rc; 2001 2002 pci_read_config_word(dev, PCI_COMMAND, &cmd); 2003 if (! (cmd & PCI_COMMAND_INVALIDATE)) { 2004 dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n"); 2005 cmd |= PCI_COMMAND_INVALIDATE; 2006 pci_write_config_word(dev, PCI_COMMAND, cmd); 2007 } 2008 2009 return 0; 2010 } 2011 2012 /** 2013 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction 2014 * @dev: the PCI device for which MWI is enabled 2015 * 2016 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. 2017 * Callers are not required to check the return value. 2018 * 2019 * RETURNS: An appropriate -ERRNO error value on error, or zero for success. 2020 */ 2021 int pci_try_set_mwi(struct pci_dev *dev) 2022 { 2023 int rc = pci_set_mwi(dev); 2024 return rc; 2025 } 2026 2027 /** 2028 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev 2029 * @dev: the PCI device to disable 2030 * 2031 * Disables PCI Memory-Write-Invalidate transaction on the device 2032 */ 2033 void 2034 pci_clear_mwi(struct pci_dev *dev) 2035 { 2036 u16 cmd; 2037 2038 pci_read_config_word(dev, PCI_COMMAND, &cmd); 2039 if (cmd & PCI_COMMAND_INVALIDATE) { 2040 cmd &= ~PCI_COMMAND_INVALIDATE; 2041 pci_write_config_word(dev, PCI_COMMAND, cmd); 2042 } 2043 } 2044 #endif /* ! PCI_DISABLE_MWI */ 2045 2046 /** 2047 * pci_intx - enables/disables PCI INTx for device dev 2048 * @pdev: the PCI device to operate on 2049 * @enable: boolean: whether to enable or disable PCI INTx 2050 * 2051 * Enables/disables PCI INTx for device dev 2052 */ 2053 void 2054 pci_intx(struct pci_dev *pdev, int enable) 2055 { 2056 u16 pci_command, new; 2057 2058 pci_read_config_word(pdev, PCI_COMMAND, &pci_command); 2059 2060 if (enable) { 2061 new = pci_command & ~PCI_COMMAND_INTX_DISABLE; 2062 } else { 2063 new = pci_command | PCI_COMMAND_INTX_DISABLE; 2064 } 2065 2066 if (new != pci_command) { 2067 struct pci_devres *dr; 2068 2069 pci_write_config_word(pdev, PCI_COMMAND, new); 2070 2071 dr = find_pci_dr(pdev); 2072 if (dr && !dr->restore_intx) { 2073 dr->restore_intx = 1; 2074 dr->orig_intx = !enable; 2075 } 2076 } 2077 } 2078 2079 /** 2080 * pci_msi_off - disables any msi or msix capabilities 2081 * @dev: the PCI device to operate on 2082 * 2083 * If you want to use msi see pci_enable_msi and friends. 2084 * This is a lower level primitive that allows us to disable 2085 * msi operation at the device level. 2086 */ 2087 void pci_msi_off(struct pci_dev *dev) 2088 { 2089 int pos; 2090 u16 control; 2091 2092 pos = pci_find_capability(dev, PCI_CAP_ID_MSI); 2093 if (pos) { 2094 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); 2095 control &= ~PCI_MSI_FLAGS_ENABLE; 2096 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); 2097 } 2098 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); 2099 if (pos) { 2100 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); 2101 control &= ~PCI_MSIX_FLAGS_ENABLE; 2102 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); 2103 } 2104 } 2105 2106 #ifndef HAVE_ARCH_PCI_SET_DMA_MASK 2107 /* 2108 * These can be overridden by arch-specific implementations 2109 */ 2110 int 2111 pci_set_dma_mask(struct pci_dev *dev, u64 mask) 2112 { 2113 if (!pci_dma_supported(dev, mask)) 2114 return -EIO; 2115 2116 dev->dma_mask = mask; 2117 dev_dbg(&dev->dev, "using %dbit DMA mask\n", fls64(mask)); 2118 2119 return 0; 2120 } 2121 2122 int 2123 pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask) 2124 { 2125 if (!pci_dma_supported(dev, mask)) 2126 return -EIO; 2127 2128 dev->dev.coherent_dma_mask = mask; 2129 dev_dbg(&dev->dev, "using %dbit consistent DMA mask\n", fls64(mask)); 2130 2131 return 0; 2132 } 2133 #endif 2134 2135 #ifndef HAVE_ARCH_PCI_SET_DMA_MAX_SEGMENT_SIZE 2136 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size) 2137 { 2138 return dma_set_max_seg_size(&dev->dev, size); 2139 } 2140 EXPORT_SYMBOL(pci_set_dma_max_seg_size); 2141 #endif 2142 2143 #ifndef HAVE_ARCH_PCI_SET_DMA_SEGMENT_BOUNDARY 2144 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask) 2145 { 2146 return dma_set_seg_boundary(&dev->dev, mask); 2147 } 2148 EXPORT_SYMBOL(pci_set_dma_seg_boundary); 2149 #endif 2150 2151 static int pcie_flr(struct pci_dev *dev, int probe) 2152 { 2153 int i; 2154 int pos; 2155 u32 cap; 2156 u16 status, control; 2157 2158 pos = pci_pcie_cap(dev); 2159 if (!pos) 2160 return -ENOTTY; 2161 2162 pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP, &cap); 2163 if (!(cap & PCI_EXP_DEVCAP_FLR)) 2164 return -ENOTTY; 2165 2166 if (probe) 2167 return 0; 2168 2169 /* Wait for Transaction Pending bit clean */ 2170 for (i = 0; i < 4; i++) { 2171 if (i) 2172 msleep((1 << (i - 1)) * 100); 2173 2174 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status); 2175 if (!(status & PCI_EXP_DEVSTA_TRPND)) 2176 goto clear; 2177 } 2178 2179 dev_err(&dev->dev, "transaction is not cleared; " 2180 "proceeding with reset anyway\n"); 2181 2182 clear: 2183 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &control); 2184 control |= PCI_EXP_DEVCTL_BCR_FLR; 2185 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, control); 2186 2187 msleep(100); 2188 2189 return 0; 2190 } 2191 2192 static int pci_af_flr(struct pci_dev *dev, int probe) 2193 { 2194 int i; 2195 int pos; 2196 u8 cap; 2197 u8 status; 2198 2199 pos = pci_find_capability(dev, PCI_CAP_ID_AF); 2200 if (!pos) 2201 return -ENOTTY; 2202 2203 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap); 2204 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR)) 2205 return -ENOTTY; 2206 2207 if (probe) 2208 return 0; 2209 2210 /* Wait for Transaction Pending bit clean */ 2211 for (i = 0; i < 4; i++) { 2212 if (i) 2213 msleep((1 << (i - 1)) * 100); 2214 2215 pci_read_config_byte(dev, pos + PCI_AF_STATUS, &status); 2216 if (!(status & PCI_AF_STATUS_TP)) 2217 goto clear; 2218 } 2219 2220 dev_err(&dev->dev, "transaction is not cleared; " 2221 "proceeding with reset anyway\n"); 2222 2223 clear: 2224 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR); 2225 msleep(100); 2226 2227 return 0; 2228 } 2229 2230 static int pci_pm_reset(struct pci_dev *dev, int probe) 2231 { 2232 u16 csr; 2233 2234 if (!dev->pm_cap) 2235 return -ENOTTY; 2236 2237 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr); 2238 if (csr & PCI_PM_CTRL_NO_SOFT_RESET) 2239 return -ENOTTY; 2240 2241 if (probe) 2242 return 0; 2243 2244 if (dev->current_state != PCI_D0) 2245 return -EINVAL; 2246 2247 csr &= ~PCI_PM_CTRL_STATE_MASK; 2248 csr |= PCI_D3hot; 2249 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); 2250 msleep(pci_pm_d3_delay); 2251 2252 csr &= ~PCI_PM_CTRL_STATE_MASK; 2253 csr |= PCI_D0; 2254 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); 2255 msleep(pci_pm_d3_delay); 2256 2257 return 0; 2258 } 2259 2260 static int pci_parent_bus_reset(struct pci_dev *dev, int probe) 2261 { 2262 u16 ctrl; 2263 struct pci_dev *pdev; 2264 2265 if (pci_is_root_bus(dev->bus) || dev->subordinate || !dev->bus->self) 2266 return -ENOTTY; 2267 2268 list_for_each_entry(pdev, &dev->bus->devices, bus_list) 2269 if (pdev != dev) 2270 return -ENOTTY; 2271 2272 if (probe) 2273 return 0; 2274 2275 pci_read_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, &ctrl); 2276 ctrl |= PCI_BRIDGE_CTL_BUS_RESET; 2277 pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl); 2278 msleep(100); 2279 2280 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET; 2281 pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl); 2282 msleep(100); 2283 2284 return 0; 2285 } 2286 2287 static int pci_dev_reset(struct pci_dev *dev, int probe) 2288 { 2289 int rc; 2290 2291 might_sleep(); 2292 2293 if (!probe) { 2294 pci_block_user_cfg_access(dev); 2295 /* block PM suspend, driver probe, etc. */ 2296 down(&dev->dev.sem); 2297 } 2298 2299 rc = pcie_flr(dev, probe); 2300 if (rc != -ENOTTY) 2301 goto done; 2302 2303 rc = pci_af_flr(dev, probe); 2304 if (rc != -ENOTTY) 2305 goto done; 2306 2307 rc = pci_pm_reset(dev, probe); 2308 if (rc != -ENOTTY) 2309 goto done; 2310 2311 rc = pci_parent_bus_reset(dev, probe); 2312 done: 2313 if (!probe) { 2314 up(&dev->dev.sem); 2315 pci_unblock_user_cfg_access(dev); 2316 } 2317 2318 return rc; 2319 } 2320 2321 /** 2322 * __pci_reset_function - reset a PCI device function 2323 * @dev: PCI device to reset 2324 * 2325 * Some devices allow an individual function to be reset without affecting 2326 * other functions in the same device. The PCI device must be responsive 2327 * to PCI config space in order to use this function. 2328 * 2329 * The device function is presumed to be unused when this function is called. 2330 * Resetting the device will make the contents of PCI configuration space 2331 * random, so any caller of this must be prepared to reinitialise the 2332 * device including MSI, bus mastering, BARs, decoding IO and memory spaces, 2333 * etc. 2334 * 2335 * Returns 0 if the device function was successfully reset or negative if the 2336 * device doesn't support resetting a single function. 2337 */ 2338 int __pci_reset_function(struct pci_dev *dev) 2339 { 2340 return pci_dev_reset(dev, 0); 2341 } 2342 EXPORT_SYMBOL_GPL(__pci_reset_function); 2343 2344 /** 2345 * pci_probe_reset_function - check whether the device can be safely reset 2346 * @dev: PCI device to reset 2347 * 2348 * Some devices allow an individual function to be reset without affecting 2349 * other functions in the same device. The PCI device must be responsive 2350 * to PCI config space in order to use this function. 2351 * 2352 * Returns 0 if the device function can be reset or negative if the 2353 * device doesn't support resetting a single function. 2354 */ 2355 int pci_probe_reset_function(struct pci_dev *dev) 2356 { 2357 return pci_dev_reset(dev, 1); 2358 } 2359 2360 /** 2361 * pci_reset_function - quiesce and reset a PCI device function 2362 * @dev: PCI device to reset 2363 * 2364 * Some devices allow an individual function to be reset without affecting 2365 * other functions in the same device. The PCI device must be responsive 2366 * to PCI config space in order to use this function. 2367 * 2368 * This function does not just reset the PCI portion of a device, but 2369 * clears all the state associated with the device. This function differs 2370 * from __pci_reset_function in that it saves and restores device state 2371 * over the reset. 2372 * 2373 * Returns 0 if the device function was successfully reset or negative if the 2374 * device doesn't support resetting a single function. 2375 */ 2376 int pci_reset_function(struct pci_dev *dev) 2377 { 2378 int rc; 2379 2380 rc = pci_dev_reset(dev, 1); 2381 if (rc) 2382 return rc; 2383 2384 pci_save_state(dev); 2385 2386 /* 2387 * both INTx and MSI are disabled after the Interrupt Disable bit 2388 * is set and the Bus Master bit is cleared. 2389 */ 2390 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE); 2391 2392 rc = pci_dev_reset(dev, 0); 2393 2394 pci_restore_state(dev); 2395 2396 return rc; 2397 } 2398 EXPORT_SYMBOL_GPL(pci_reset_function); 2399 2400 /** 2401 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count 2402 * @dev: PCI device to query 2403 * 2404 * Returns mmrbc: maximum designed memory read count in bytes 2405 * or appropriate error value. 2406 */ 2407 int pcix_get_max_mmrbc(struct pci_dev *dev) 2408 { 2409 int err, cap; 2410 u32 stat; 2411 2412 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); 2413 if (!cap) 2414 return -EINVAL; 2415 2416 err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat); 2417 if (err) 2418 return -EINVAL; 2419 2420 return (stat & PCI_X_STATUS_MAX_READ) >> 12; 2421 } 2422 EXPORT_SYMBOL(pcix_get_max_mmrbc); 2423 2424 /** 2425 * pcix_get_mmrbc - get PCI-X maximum memory read byte count 2426 * @dev: PCI device to query 2427 * 2428 * Returns mmrbc: maximum memory read count in bytes 2429 * or appropriate error value. 2430 */ 2431 int pcix_get_mmrbc(struct pci_dev *dev) 2432 { 2433 int ret, cap; 2434 u32 cmd; 2435 2436 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); 2437 if (!cap) 2438 return -EINVAL; 2439 2440 ret = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd); 2441 if (!ret) 2442 ret = 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2); 2443 2444 return ret; 2445 } 2446 EXPORT_SYMBOL(pcix_get_mmrbc); 2447 2448 /** 2449 * pcix_set_mmrbc - set PCI-X maximum memory read byte count 2450 * @dev: PCI device to query 2451 * @mmrbc: maximum memory read count in bytes 2452 * valid values are 512, 1024, 2048, 4096 2453 * 2454 * If possible sets maximum memory read byte count, some bridges have erratas 2455 * that prevent this. 2456 */ 2457 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc) 2458 { 2459 int cap, err = -EINVAL; 2460 u32 stat, cmd, v, o; 2461 2462 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc)) 2463 goto out; 2464 2465 v = ffs(mmrbc) - 10; 2466 2467 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); 2468 if (!cap) 2469 goto out; 2470 2471 err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat); 2472 if (err) 2473 goto out; 2474 2475 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21) 2476 return -E2BIG; 2477 2478 err = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd); 2479 if (err) 2480 goto out; 2481 2482 o = (cmd & PCI_X_CMD_MAX_READ) >> 2; 2483 if (o != v) { 2484 if (v > o && dev->bus && 2485 (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC)) 2486 return -EIO; 2487 2488 cmd &= ~PCI_X_CMD_MAX_READ; 2489 cmd |= v << 2; 2490 err = pci_write_config_dword(dev, cap + PCI_X_CMD, cmd); 2491 } 2492 out: 2493 return err; 2494 } 2495 EXPORT_SYMBOL(pcix_set_mmrbc); 2496 2497 /** 2498 * pcie_get_readrq - get PCI Express read request size 2499 * @dev: PCI device to query 2500 * 2501 * Returns maximum memory read request in bytes 2502 * or appropriate error value. 2503 */ 2504 int pcie_get_readrq(struct pci_dev *dev) 2505 { 2506 int ret, cap; 2507 u16 ctl; 2508 2509 cap = pci_pcie_cap(dev); 2510 if (!cap) 2511 return -EINVAL; 2512 2513 ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl); 2514 if (!ret) 2515 ret = 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12); 2516 2517 return ret; 2518 } 2519 EXPORT_SYMBOL(pcie_get_readrq); 2520 2521 /** 2522 * pcie_set_readrq - set PCI Express maximum memory read request 2523 * @dev: PCI device to query 2524 * @rq: maximum memory read count in bytes 2525 * valid values are 128, 256, 512, 1024, 2048, 4096 2526 * 2527 * If possible sets maximum read byte count 2528 */ 2529 int pcie_set_readrq(struct pci_dev *dev, int rq) 2530 { 2531 int cap, err = -EINVAL; 2532 u16 ctl, v; 2533 2534 if (rq < 128 || rq > 4096 || !is_power_of_2(rq)) 2535 goto out; 2536 2537 v = (ffs(rq) - 8) << 12; 2538 2539 cap = pci_pcie_cap(dev); 2540 if (!cap) 2541 goto out; 2542 2543 err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl); 2544 if (err) 2545 goto out; 2546 2547 if ((ctl & PCI_EXP_DEVCTL_READRQ) != v) { 2548 ctl &= ~PCI_EXP_DEVCTL_READRQ; 2549 ctl |= v; 2550 err = pci_write_config_dword(dev, cap + PCI_EXP_DEVCTL, ctl); 2551 } 2552 2553 out: 2554 return err; 2555 } 2556 EXPORT_SYMBOL(pcie_set_readrq); 2557 2558 /** 2559 * pci_select_bars - Make BAR mask from the type of resource 2560 * @dev: the PCI device for which BAR mask is made 2561 * @flags: resource type mask to be selected 2562 * 2563 * This helper routine makes bar mask from the type of resource. 2564 */ 2565 int pci_select_bars(struct pci_dev *dev, unsigned long flags) 2566 { 2567 int i, bars = 0; 2568 for (i = 0; i < PCI_NUM_RESOURCES; i++) 2569 if (pci_resource_flags(dev, i) & flags) 2570 bars |= (1 << i); 2571 return bars; 2572 } 2573 2574 /** 2575 * pci_resource_bar - get position of the BAR associated with a resource 2576 * @dev: the PCI device 2577 * @resno: the resource number 2578 * @type: the BAR type to be filled in 2579 * 2580 * Returns BAR position in config space, or 0 if the BAR is invalid. 2581 */ 2582 int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type) 2583 { 2584 int reg; 2585 2586 if (resno < PCI_ROM_RESOURCE) { 2587 *type = pci_bar_unknown; 2588 return PCI_BASE_ADDRESS_0 + 4 * resno; 2589 } else if (resno == PCI_ROM_RESOURCE) { 2590 *type = pci_bar_mem32; 2591 return dev->rom_base_reg; 2592 } else if (resno < PCI_BRIDGE_RESOURCES) { 2593 /* device specific resource */ 2594 reg = pci_iov_resource_bar(dev, resno, type); 2595 if (reg) 2596 return reg; 2597 } 2598 2599 dev_err(&dev->dev, "BAR %d: invalid resource\n", resno); 2600 return 0; 2601 } 2602 2603 /** 2604 * pci_set_vga_state - set VGA decode state on device and parents if requested 2605 * @dev: the PCI device 2606 * @decode: true = enable decoding, false = disable decoding 2607 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY 2608 * @change_bridge: traverse ancestors and change bridges 2609 */ 2610 int pci_set_vga_state(struct pci_dev *dev, bool decode, 2611 unsigned int command_bits, bool change_bridge) 2612 { 2613 struct pci_bus *bus; 2614 struct pci_dev *bridge; 2615 u16 cmd; 2616 2617 WARN_ON(command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)); 2618 2619 pci_read_config_word(dev, PCI_COMMAND, &cmd); 2620 if (decode == true) 2621 cmd |= command_bits; 2622 else 2623 cmd &= ~command_bits; 2624 pci_write_config_word(dev, PCI_COMMAND, cmd); 2625 2626 if (change_bridge == false) 2627 return 0; 2628 2629 bus = dev->bus; 2630 while (bus) { 2631 bridge = bus->self; 2632 if (bridge) { 2633 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL, 2634 &cmd); 2635 if (decode == true) 2636 cmd |= PCI_BRIDGE_CTL_VGA; 2637 else 2638 cmd &= ~PCI_BRIDGE_CTL_VGA; 2639 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, 2640 cmd); 2641 } 2642 bus = bus->parent; 2643 } 2644 return 0; 2645 } 2646 2647 #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE 2648 static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0}; 2649 static DEFINE_SPINLOCK(resource_alignment_lock); 2650 2651 /** 2652 * pci_specified_resource_alignment - get resource alignment specified by user. 2653 * @dev: the PCI device to get 2654 * 2655 * RETURNS: Resource alignment if it is specified. 2656 * Zero if it is not specified. 2657 */ 2658 resource_size_t pci_specified_resource_alignment(struct pci_dev *dev) 2659 { 2660 int seg, bus, slot, func, align_order, count; 2661 resource_size_t align = 0; 2662 char *p; 2663 2664 spin_lock(&resource_alignment_lock); 2665 p = resource_alignment_param; 2666 while (*p) { 2667 count = 0; 2668 if (sscanf(p, "%d%n", &align_order, &count) == 1 && 2669 p[count] == '@') { 2670 p += count + 1; 2671 } else { 2672 align_order = -1; 2673 } 2674 if (sscanf(p, "%x:%x:%x.%x%n", 2675 &seg, &bus, &slot, &func, &count) != 4) { 2676 seg = 0; 2677 if (sscanf(p, "%x:%x.%x%n", 2678 &bus, &slot, &func, &count) != 3) { 2679 /* Invalid format */ 2680 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n", 2681 p); 2682 break; 2683 } 2684 } 2685 p += count; 2686 if (seg == pci_domain_nr(dev->bus) && 2687 bus == dev->bus->number && 2688 slot == PCI_SLOT(dev->devfn) && 2689 func == PCI_FUNC(dev->devfn)) { 2690 if (align_order == -1) { 2691 align = PAGE_SIZE; 2692 } else { 2693 align = 1 << align_order; 2694 } 2695 /* Found */ 2696 break; 2697 } 2698 if (*p != ';' && *p != ',') { 2699 /* End of param or invalid format */ 2700 break; 2701 } 2702 p++; 2703 } 2704 spin_unlock(&resource_alignment_lock); 2705 return align; 2706 } 2707 2708 /** 2709 * pci_is_reassigndev - check if specified PCI is target device to reassign 2710 * @dev: the PCI device to check 2711 * 2712 * RETURNS: non-zero for PCI device is a target device to reassign, 2713 * or zero is not. 2714 */ 2715 int pci_is_reassigndev(struct pci_dev *dev) 2716 { 2717 return (pci_specified_resource_alignment(dev) != 0); 2718 } 2719 2720 ssize_t pci_set_resource_alignment_param(const char *buf, size_t count) 2721 { 2722 if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1) 2723 count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1; 2724 spin_lock(&resource_alignment_lock); 2725 strncpy(resource_alignment_param, buf, count); 2726 resource_alignment_param[count] = '\0'; 2727 spin_unlock(&resource_alignment_lock); 2728 return count; 2729 } 2730 2731 ssize_t pci_get_resource_alignment_param(char *buf, size_t size) 2732 { 2733 size_t count; 2734 spin_lock(&resource_alignment_lock); 2735 count = snprintf(buf, size, "%s", resource_alignment_param); 2736 spin_unlock(&resource_alignment_lock); 2737 return count; 2738 } 2739 2740 static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf) 2741 { 2742 return pci_get_resource_alignment_param(buf, PAGE_SIZE); 2743 } 2744 2745 static ssize_t pci_resource_alignment_store(struct bus_type *bus, 2746 const char *buf, size_t count) 2747 { 2748 return pci_set_resource_alignment_param(buf, count); 2749 } 2750 2751 BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show, 2752 pci_resource_alignment_store); 2753 2754 static int __init pci_resource_alignment_sysfs_init(void) 2755 { 2756 return bus_create_file(&pci_bus_type, 2757 &bus_attr_resource_alignment); 2758 } 2759 2760 late_initcall(pci_resource_alignment_sysfs_init); 2761 2762 static void __devinit pci_no_domains(void) 2763 { 2764 #ifdef CONFIG_PCI_DOMAINS 2765 pci_domains_supported = 0; 2766 #endif 2767 } 2768 2769 /** 2770 * pci_ext_cfg_enabled - can we access extended PCI config space? 2771 * @dev: The PCI device of the root bridge. 2772 * 2773 * Returns 1 if we can access PCI extended config space (offsets 2774 * greater than 0xff). This is the default implementation. Architecture 2775 * implementations can override this. 2776 */ 2777 int __attribute__ ((weak)) pci_ext_cfg_avail(struct pci_dev *dev) 2778 { 2779 return 1; 2780 } 2781 2782 static int __init pci_setup(char *str) 2783 { 2784 while (str) { 2785 char *k = strchr(str, ','); 2786 if (k) 2787 *k++ = 0; 2788 if (*str && (str = pcibios_setup(str)) && *str) { 2789 if (!strcmp(str, "nomsi")) { 2790 pci_no_msi(); 2791 } else if (!strcmp(str, "noaer")) { 2792 pci_no_aer(); 2793 } else if (!strcmp(str, "nodomains")) { 2794 pci_no_domains(); 2795 } else if (!strncmp(str, "cbiosize=", 9)) { 2796 pci_cardbus_io_size = memparse(str + 9, &str); 2797 } else if (!strncmp(str, "cbmemsize=", 10)) { 2798 pci_cardbus_mem_size = memparse(str + 10, &str); 2799 } else if (!strncmp(str, "resource_alignment=", 19)) { 2800 pci_set_resource_alignment_param(str + 19, 2801 strlen(str + 19)); 2802 } else if (!strncmp(str, "ecrc=", 5)) { 2803 pcie_ecrc_get_policy(str + 5); 2804 } else if (!strncmp(str, "hpiosize=", 9)) { 2805 pci_hotplug_io_size = memparse(str + 9, &str); 2806 } else if (!strncmp(str, "hpmemsize=", 10)) { 2807 pci_hotplug_mem_size = memparse(str + 10, &str); 2808 } else { 2809 printk(KERN_ERR "PCI: Unknown option `%s'\n", 2810 str); 2811 } 2812 } 2813 str = k; 2814 } 2815 return 0; 2816 } 2817 early_param("pci", pci_setup); 2818 2819 EXPORT_SYMBOL(pci_reenable_device); 2820 EXPORT_SYMBOL(pci_enable_device_io); 2821 EXPORT_SYMBOL(pci_enable_device_mem); 2822 EXPORT_SYMBOL(pci_enable_device); 2823 EXPORT_SYMBOL(pcim_enable_device); 2824 EXPORT_SYMBOL(pcim_pin_device); 2825 EXPORT_SYMBOL(pci_disable_device); 2826 EXPORT_SYMBOL(pci_find_capability); 2827 EXPORT_SYMBOL(pci_bus_find_capability); 2828 EXPORT_SYMBOL(pci_release_regions); 2829 EXPORT_SYMBOL(pci_request_regions); 2830 EXPORT_SYMBOL(pci_request_regions_exclusive); 2831 EXPORT_SYMBOL(pci_release_region); 2832 EXPORT_SYMBOL(pci_request_region); 2833 EXPORT_SYMBOL(pci_request_region_exclusive); 2834 EXPORT_SYMBOL(pci_release_selected_regions); 2835 EXPORT_SYMBOL(pci_request_selected_regions); 2836 EXPORT_SYMBOL(pci_request_selected_regions_exclusive); 2837 EXPORT_SYMBOL(pci_set_master); 2838 EXPORT_SYMBOL(pci_clear_master); 2839 EXPORT_SYMBOL(pci_set_mwi); 2840 EXPORT_SYMBOL(pci_try_set_mwi); 2841 EXPORT_SYMBOL(pci_clear_mwi); 2842 EXPORT_SYMBOL_GPL(pci_intx); 2843 EXPORT_SYMBOL(pci_set_dma_mask); 2844 EXPORT_SYMBOL(pci_set_consistent_dma_mask); 2845 EXPORT_SYMBOL(pci_assign_resource); 2846 EXPORT_SYMBOL(pci_find_parent_resource); 2847 EXPORT_SYMBOL(pci_select_bars); 2848 2849 EXPORT_SYMBOL(pci_set_power_state); 2850 EXPORT_SYMBOL(pci_save_state); 2851 EXPORT_SYMBOL(pci_restore_state); 2852 EXPORT_SYMBOL(pci_pme_capable); 2853 EXPORT_SYMBOL(pci_pme_active); 2854 EXPORT_SYMBOL(pci_enable_wake); 2855 EXPORT_SYMBOL(pci_wake_from_d3); 2856 EXPORT_SYMBOL(pci_target_state); 2857 EXPORT_SYMBOL(pci_prepare_to_sleep); 2858 EXPORT_SYMBOL(pci_back_from_sleep); 2859 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state); 2860 2861