1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * PCI support in ACPI 4 * 5 * Copyright (C) 2005 David Shaohua Li <shaohua.li@intel.com> 6 * Copyright (C) 2004 Tom Long Nguyen <tom.l.nguyen@intel.com> 7 * Copyright (C) 2004 Intel Corp. 8 */ 9 10 #include <linux/delay.h> 11 #include <linux/init.h> 12 #include <linux/irqdomain.h> 13 #include <linux/pci.h> 14 #include <linux/msi.h> 15 #include <linux/pci_hotplug.h> 16 #include <linux/module.h> 17 #include <linux/pci-acpi.h> 18 #include <linux/pci-ecam.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/pm_qos.h> 21 #include <linux/rwsem.h> 22 #include "pci.h" 23 24 /* 25 * The GUID is defined in the PCI Firmware Specification available 26 * here to PCI-SIG members: 27 * https://members.pcisig.com/wg/PCI-SIG/document/15350 28 */ 29 const guid_t pci_acpi_dsm_guid = 30 GUID_INIT(0xe5c937d0, 0x3553, 0x4d7a, 31 0x91, 0x17, 0xea, 0x4d, 0x19, 0xc3, 0x43, 0x4d); 32 33 #if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64) 34 static int acpi_get_rc_addr(struct acpi_device *adev, struct resource *res) 35 { 36 struct device *dev = &adev->dev; 37 struct resource_entry *entry; 38 struct list_head list; 39 unsigned long flags; 40 int ret; 41 42 INIT_LIST_HEAD(&list); 43 flags = IORESOURCE_MEM; 44 ret = acpi_dev_get_resources(adev, &list, 45 acpi_dev_filter_resource_type_cb, 46 (void *) flags); 47 if (ret < 0) { 48 dev_err(dev, "failed to parse _CRS method, error code %d\n", 49 ret); 50 return ret; 51 } 52 53 if (ret == 0) { 54 dev_err(dev, "no IO and memory resources present in _CRS\n"); 55 return -EINVAL; 56 } 57 58 entry = list_first_entry(&list, struct resource_entry, node); 59 *res = *entry->res; 60 acpi_dev_free_resource_list(&list); 61 return 0; 62 } 63 64 static acpi_status acpi_match_rc(acpi_handle handle, u32 lvl, void *context, 65 void **retval) 66 { 67 u16 *segment = context; 68 unsigned long long uid; 69 acpi_status status; 70 71 status = acpi_evaluate_integer(handle, METHOD_NAME__UID, NULL, &uid); 72 if (ACPI_FAILURE(status) || uid != *segment) 73 return AE_CTRL_DEPTH; 74 75 *(acpi_handle *)retval = handle; 76 return AE_CTRL_TERMINATE; 77 } 78 79 int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment, 80 struct resource *res) 81 { 82 struct acpi_device *adev; 83 acpi_status status; 84 acpi_handle handle; 85 int ret; 86 87 status = acpi_get_devices(hid, acpi_match_rc, &segment, &handle); 88 if (ACPI_FAILURE(status)) { 89 dev_err(dev, "can't find _HID %s device to locate resources\n", 90 hid); 91 return -ENODEV; 92 } 93 94 adev = acpi_fetch_acpi_dev(handle); 95 if (!adev) 96 return -ENODEV; 97 98 ret = acpi_get_rc_addr(adev, res); 99 if (ret) { 100 dev_err(dev, "can't get resource from %s\n", 101 dev_name(&adev->dev)); 102 return ret; 103 } 104 105 return 0; 106 } 107 #endif 108 109 phys_addr_t acpi_pci_root_get_mcfg_addr(acpi_handle handle) 110 { 111 acpi_status status = AE_NOT_EXIST; 112 unsigned long long mcfg_addr; 113 114 if (handle) 115 status = acpi_evaluate_integer(handle, METHOD_NAME__CBA, 116 NULL, &mcfg_addr); 117 if (ACPI_FAILURE(status)) 118 return 0; 119 120 return (phys_addr_t)mcfg_addr; 121 } 122 123 bool pci_acpi_preserve_config(struct pci_host_bridge *host_bridge) 124 { 125 if (ACPI_HANDLE(&host_bridge->dev)) { 126 union acpi_object *obj; 127 128 /* 129 * Evaluate the "PCI Boot Configuration" _DSM Function. If it 130 * exists and returns 0, we must preserve any PCI resource 131 * assignments made by firmware for this host bridge. 132 */ 133 obj = acpi_evaluate_dsm_typed(ACPI_HANDLE(&host_bridge->dev), 134 &pci_acpi_dsm_guid, 135 1, DSM_PCI_PRESERVE_BOOT_CONFIG, 136 NULL, ACPI_TYPE_INTEGER); 137 if (obj && obj->integer.value == 0) 138 return true; 139 ACPI_FREE(obj); 140 } 141 142 return false; 143 } 144 145 /* _HPX PCI Setting Record (Type 0); same as _HPP */ 146 struct hpx_type0 { 147 u32 revision; /* Not present in _HPP */ 148 u8 cache_line_size; /* Not applicable to PCIe */ 149 u8 latency_timer; /* Not applicable to PCIe */ 150 u8 enable_serr; 151 u8 enable_perr; 152 }; 153 154 static struct hpx_type0 pci_default_type0 = { 155 .revision = 1, 156 .cache_line_size = 8, 157 .latency_timer = 0x40, 158 .enable_serr = 0, 159 .enable_perr = 0, 160 }; 161 162 static void program_hpx_type0(struct pci_dev *dev, struct hpx_type0 *hpx) 163 { 164 u16 pci_cmd, pci_bctl; 165 166 if (!hpx) 167 hpx = &pci_default_type0; 168 169 if (hpx->revision > 1) { 170 pci_warn(dev, "PCI settings rev %d not supported; using defaults\n", 171 hpx->revision); 172 hpx = &pci_default_type0; 173 } 174 175 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, hpx->cache_line_size); 176 pci_write_config_byte(dev, PCI_LATENCY_TIMER, hpx->latency_timer); 177 pci_read_config_word(dev, PCI_COMMAND, &pci_cmd); 178 if (hpx->enable_serr) 179 pci_cmd |= PCI_COMMAND_SERR; 180 if (hpx->enable_perr) 181 pci_cmd |= PCI_COMMAND_PARITY; 182 pci_write_config_word(dev, PCI_COMMAND, pci_cmd); 183 184 /* Program bridge control value */ 185 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { 186 pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 187 hpx->latency_timer); 188 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &pci_bctl); 189 if (hpx->enable_perr) 190 pci_bctl |= PCI_BRIDGE_CTL_PARITY; 191 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, pci_bctl); 192 } 193 } 194 195 static acpi_status decode_type0_hpx_record(union acpi_object *record, 196 struct hpx_type0 *hpx0) 197 { 198 int i; 199 union acpi_object *fields = record->package.elements; 200 u32 revision = fields[1].integer.value; 201 202 switch (revision) { 203 case 1: 204 if (record->package.count != 6) 205 return AE_ERROR; 206 for (i = 2; i < 6; i++) 207 if (fields[i].type != ACPI_TYPE_INTEGER) 208 return AE_ERROR; 209 hpx0->revision = revision; 210 hpx0->cache_line_size = fields[2].integer.value; 211 hpx0->latency_timer = fields[3].integer.value; 212 hpx0->enable_serr = fields[4].integer.value; 213 hpx0->enable_perr = fields[5].integer.value; 214 break; 215 default: 216 pr_warn("%s: Type 0 Revision %d record not supported\n", 217 __func__, revision); 218 return AE_ERROR; 219 } 220 return AE_OK; 221 } 222 223 /* _HPX PCI-X Setting Record (Type 1) */ 224 struct hpx_type1 { 225 u32 revision; 226 u8 max_mem_read; 227 u8 avg_max_split; 228 u16 tot_max_split; 229 }; 230 231 static void program_hpx_type1(struct pci_dev *dev, struct hpx_type1 *hpx) 232 { 233 int pos; 234 235 if (!hpx) 236 return; 237 238 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); 239 if (!pos) 240 return; 241 242 pci_warn(dev, "PCI-X settings not supported\n"); 243 } 244 245 static acpi_status decode_type1_hpx_record(union acpi_object *record, 246 struct hpx_type1 *hpx1) 247 { 248 int i; 249 union acpi_object *fields = record->package.elements; 250 u32 revision = fields[1].integer.value; 251 252 switch (revision) { 253 case 1: 254 if (record->package.count != 5) 255 return AE_ERROR; 256 for (i = 2; i < 5; i++) 257 if (fields[i].type != ACPI_TYPE_INTEGER) 258 return AE_ERROR; 259 hpx1->revision = revision; 260 hpx1->max_mem_read = fields[2].integer.value; 261 hpx1->avg_max_split = fields[3].integer.value; 262 hpx1->tot_max_split = fields[4].integer.value; 263 break; 264 default: 265 pr_warn("%s: Type 1 Revision %d record not supported\n", 266 __func__, revision); 267 return AE_ERROR; 268 } 269 return AE_OK; 270 } 271 272 static bool pcie_root_rcb_set(struct pci_dev *dev) 273 { 274 struct pci_dev *rp = pcie_find_root_port(dev); 275 u16 lnkctl; 276 277 if (!rp) 278 return false; 279 280 pcie_capability_read_word(rp, PCI_EXP_LNKCTL, &lnkctl); 281 if (lnkctl & PCI_EXP_LNKCTL_RCB) 282 return true; 283 284 return false; 285 } 286 287 /* _HPX PCI Express Setting Record (Type 2) */ 288 struct hpx_type2 { 289 u32 revision; 290 u32 unc_err_mask_and; 291 u32 unc_err_mask_or; 292 u32 unc_err_sever_and; 293 u32 unc_err_sever_or; 294 u32 cor_err_mask_and; 295 u32 cor_err_mask_or; 296 u32 adv_err_cap_and; 297 u32 adv_err_cap_or; 298 u16 pci_exp_devctl_and; 299 u16 pci_exp_devctl_or; 300 u16 pci_exp_lnkctl_and; 301 u16 pci_exp_lnkctl_or; 302 u32 sec_unc_err_sever_and; 303 u32 sec_unc_err_sever_or; 304 u32 sec_unc_err_mask_and; 305 u32 sec_unc_err_mask_or; 306 }; 307 308 static void program_hpx_type2(struct pci_dev *dev, struct hpx_type2 *hpx) 309 { 310 int pos; 311 u32 reg32; 312 313 if (!hpx) 314 return; 315 316 if (!pci_is_pcie(dev)) 317 return; 318 319 if (hpx->revision > 1) { 320 pci_warn(dev, "PCIe settings rev %d not supported\n", 321 hpx->revision); 322 return; 323 } 324 325 /* 326 * Don't allow _HPX to change MPS or MRRS settings. We manage 327 * those to make sure they're consistent with the rest of the 328 * platform. 329 */ 330 hpx->pci_exp_devctl_and |= PCI_EXP_DEVCTL_PAYLOAD | 331 PCI_EXP_DEVCTL_READRQ; 332 hpx->pci_exp_devctl_or &= ~(PCI_EXP_DEVCTL_PAYLOAD | 333 PCI_EXP_DEVCTL_READRQ); 334 335 /* Initialize Device Control Register */ 336 pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL, 337 ~hpx->pci_exp_devctl_and, hpx->pci_exp_devctl_or); 338 339 /* Initialize Link Control Register */ 340 if (pcie_cap_has_lnkctl(dev)) { 341 342 /* 343 * If the Root Port supports Read Completion Boundary of 344 * 128, set RCB to 128. Otherwise, clear it. 345 */ 346 hpx->pci_exp_lnkctl_and |= PCI_EXP_LNKCTL_RCB; 347 hpx->pci_exp_lnkctl_or &= ~PCI_EXP_LNKCTL_RCB; 348 if (pcie_root_rcb_set(dev)) 349 hpx->pci_exp_lnkctl_or |= PCI_EXP_LNKCTL_RCB; 350 351 pcie_capability_clear_and_set_word(dev, PCI_EXP_LNKCTL, 352 ~hpx->pci_exp_lnkctl_and, hpx->pci_exp_lnkctl_or); 353 } 354 355 /* Find Advanced Error Reporting Enhanced Capability */ 356 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); 357 if (!pos) 358 return; 359 360 /* Initialize Uncorrectable Error Mask Register */ 361 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, ®32); 362 reg32 = (reg32 & hpx->unc_err_mask_and) | hpx->unc_err_mask_or; 363 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, reg32); 364 365 /* Initialize Uncorrectable Error Severity Register */ 366 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, ®32); 367 reg32 = (reg32 & hpx->unc_err_sever_and) | hpx->unc_err_sever_or; 368 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, reg32); 369 370 /* Initialize Correctable Error Mask Register */ 371 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, ®32); 372 reg32 = (reg32 & hpx->cor_err_mask_and) | hpx->cor_err_mask_or; 373 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg32); 374 375 /* Initialize Advanced Error Capabilities and Control Register */ 376 pci_read_config_dword(dev, pos + PCI_ERR_CAP, ®32); 377 reg32 = (reg32 & hpx->adv_err_cap_and) | hpx->adv_err_cap_or; 378 379 /* Don't enable ECRC generation or checking if unsupported */ 380 if (!(reg32 & PCI_ERR_CAP_ECRC_GENC)) 381 reg32 &= ~PCI_ERR_CAP_ECRC_GENE; 382 if (!(reg32 & PCI_ERR_CAP_ECRC_CHKC)) 383 reg32 &= ~PCI_ERR_CAP_ECRC_CHKE; 384 pci_write_config_dword(dev, pos + PCI_ERR_CAP, reg32); 385 386 /* 387 * FIXME: The following two registers are not supported yet. 388 * 389 * o Secondary Uncorrectable Error Severity Register 390 * o Secondary Uncorrectable Error Mask Register 391 */ 392 } 393 394 static acpi_status decode_type2_hpx_record(union acpi_object *record, 395 struct hpx_type2 *hpx2) 396 { 397 int i; 398 union acpi_object *fields = record->package.elements; 399 u32 revision = fields[1].integer.value; 400 401 switch (revision) { 402 case 1: 403 if (record->package.count != 18) 404 return AE_ERROR; 405 for (i = 2; i < 18; i++) 406 if (fields[i].type != ACPI_TYPE_INTEGER) 407 return AE_ERROR; 408 hpx2->revision = revision; 409 hpx2->unc_err_mask_and = fields[2].integer.value; 410 hpx2->unc_err_mask_or = fields[3].integer.value; 411 hpx2->unc_err_sever_and = fields[4].integer.value; 412 hpx2->unc_err_sever_or = fields[5].integer.value; 413 hpx2->cor_err_mask_and = fields[6].integer.value; 414 hpx2->cor_err_mask_or = fields[7].integer.value; 415 hpx2->adv_err_cap_and = fields[8].integer.value; 416 hpx2->adv_err_cap_or = fields[9].integer.value; 417 hpx2->pci_exp_devctl_and = fields[10].integer.value; 418 hpx2->pci_exp_devctl_or = fields[11].integer.value; 419 hpx2->pci_exp_lnkctl_and = fields[12].integer.value; 420 hpx2->pci_exp_lnkctl_or = fields[13].integer.value; 421 hpx2->sec_unc_err_sever_and = fields[14].integer.value; 422 hpx2->sec_unc_err_sever_or = fields[15].integer.value; 423 hpx2->sec_unc_err_mask_and = fields[16].integer.value; 424 hpx2->sec_unc_err_mask_or = fields[17].integer.value; 425 break; 426 default: 427 pr_warn("%s: Type 2 Revision %d record not supported\n", 428 __func__, revision); 429 return AE_ERROR; 430 } 431 return AE_OK; 432 } 433 434 /* _HPX PCI Express Setting Record (Type 3) */ 435 struct hpx_type3 { 436 u16 device_type; 437 u16 function_type; 438 u16 config_space_location; 439 u16 pci_exp_cap_id; 440 u16 pci_exp_cap_ver; 441 u16 pci_exp_vendor_id; 442 u16 dvsec_id; 443 u16 dvsec_rev; 444 u16 match_offset; 445 u32 match_mask_and; 446 u32 match_value; 447 u16 reg_offset; 448 u32 reg_mask_and; 449 u32 reg_mask_or; 450 }; 451 452 enum hpx_type3_dev_type { 453 HPX_TYPE_ENDPOINT = BIT(0), 454 HPX_TYPE_LEG_END = BIT(1), 455 HPX_TYPE_RC_END = BIT(2), 456 HPX_TYPE_RC_EC = BIT(3), 457 HPX_TYPE_ROOT_PORT = BIT(4), 458 HPX_TYPE_UPSTREAM = BIT(5), 459 HPX_TYPE_DOWNSTREAM = BIT(6), 460 HPX_TYPE_PCI_BRIDGE = BIT(7), 461 HPX_TYPE_PCIE_BRIDGE = BIT(8), 462 }; 463 464 static u16 hpx3_device_type(struct pci_dev *dev) 465 { 466 u16 pcie_type = pci_pcie_type(dev); 467 static const int pcie_to_hpx3_type[] = { 468 [PCI_EXP_TYPE_ENDPOINT] = HPX_TYPE_ENDPOINT, 469 [PCI_EXP_TYPE_LEG_END] = HPX_TYPE_LEG_END, 470 [PCI_EXP_TYPE_RC_END] = HPX_TYPE_RC_END, 471 [PCI_EXP_TYPE_RC_EC] = HPX_TYPE_RC_EC, 472 [PCI_EXP_TYPE_ROOT_PORT] = HPX_TYPE_ROOT_PORT, 473 [PCI_EXP_TYPE_UPSTREAM] = HPX_TYPE_UPSTREAM, 474 [PCI_EXP_TYPE_DOWNSTREAM] = HPX_TYPE_DOWNSTREAM, 475 [PCI_EXP_TYPE_PCI_BRIDGE] = HPX_TYPE_PCI_BRIDGE, 476 [PCI_EXP_TYPE_PCIE_BRIDGE] = HPX_TYPE_PCIE_BRIDGE, 477 }; 478 479 if (pcie_type >= ARRAY_SIZE(pcie_to_hpx3_type)) 480 return 0; 481 482 return pcie_to_hpx3_type[pcie_type]; 483 } 484 485 enum hpx_type3_fn_type { 486 HPX_FN_NORMAL = BIT(0), 487 HPX_FN_SRIOV_PHYS = BIT(1), 488 HPX_FN_SRIOV_VIRT = BIT(2), 489 }; 490 491 static u8 hpx3_function_type(struct pci_dev *dev) 492 { 493 if (dev->is_virtfn) 494 return HPX_FN_SRIOV_VIRT; 495 else if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_SRIOV) > 0) 496 return HPX_FN_SRIOV_PHYS; 497 else 498 return HPX_FN_NORMAL; 499 } 500 501 static bool hpx3_cap_ver_matches(u8 pcie_cap_id, u8 hpx3_cap_id) 502 { 503 u8 cap_ver = hpx3_cap_id & 0xf; 504 505 if ((hpx3_cap_id & BIT(4)) && cap_ver >= pcie_cap_id) 506 return true; 507 else if (cap_ver == pcie_cap_id) 508 return true; 509 510 return false; 511 } 512 513 enum hpx_type3_cfg_loc { 514 HPX_CFG_PCICFG = 0, 515 HPX_CFG_PCIE_CAP = 1, 516 HPX_CFG_PCIE_CAP_EXT = 2, 517 HPX_CFG_VEND_CAP = 3, 518 HPX_CFG_DVSEC = 4, 519 HPX_CFG_MAX, 520 }; 521 522 static void program_hpx_type3_register(struct pci_dev *dev, 523 const struct hpx_type3 *reg) 524 { 525 u32 match_reg, write_reg, header, orig_value; 526 u16 pos; 527 528 if (!(hpx3_device_type(dev) & reg->device_type)) 529 return; 530 531 if (!(hpx3_function_type(dev) & reg->function_type)) 532 return; 533 534 switch (reg->config_space_location) { 535 case HPX_CFG_PCICFG: 536 pos = 0; 537 break; 538 case HPX_CFG_PCIE_CAP: 539 pos = pci_find_capability(dev, reg->pci_exp_cap_id); 540 if (pos == 0) 541 return; 542 543 break; 544 case HPX_CFG_PCIE_CAP_EXT: 545 pos = pci_find_ext_capability(dev, reg->pci_exp_cap_id); 546 if (pos == 0) 547 return; 548 549 pci_read_config_dword(dev, pos, &header); 550 if (!hpx3_cap_ver_matches(PCI_EXT_CAP_VER(header), 551 reg->pci_exp_cap_ver)) 552 return; 553 554 break; 555 case HPX_CFG_VEND_CAP: 556 case HPX_CFG_DVSEC: 557 default: 558 pci_warn(dev, "Encountered _HPX type 3 with unsupported config space location"); 559 return; 560 } 561 562 pci_read_config_dword(dev, pos + reg->match_offset, &match_reg); 563 564 if ((match_reg & reg->match_mask_and) != reg->match_value) 565 return; 566 567 pci_read_config_dword(dev, pos + reg->reg_offset, &write_reg); 568 orig_value = write_reg; 569 write_reg &= reg->reg_mask_and; 570 write_reg |= reg->reg_mask_or; 571 572 if (orig_value == write_reg) 573 return; 574 575 pci_write_config_dword(dev, pos + reg->reg_offset, write_reg); 576 577 pci_dbg(dev, "Applied _HPX3 at [0x%x]: 0x%08x -> 0x%08x", 578 pos, orig_value, write_reg); 579 } 580 581 static void program_hpx_type3(struct pci_dev *dev, struct hpx_type3 *hpx) 582 { 583 if (!hpx) 584 return; 585 586 if (!pci_is_pcie(dev)) 587 return; 588 589 program_hpx_type3_register(dev, hpx); 590 } 591 592 static void parse_hpx3_register(struct hpx_type3 *hpx3_reg, 593 union acpi_object *reg_fields) 594 { 595 hpx3_reg->device_type = reg_fields[0].integer.value; 596 hpx3_reg->function_type = reg_fields[1].integer.value; 597 hpx3_reg->config_space_location = reg_fields[2].integer.value; 598 hpx3_reg->pci_exp_cap_id = reg_fields[3].integer.value; 599 hpx3_reg->pci_exp_cap_ver = reg_fields[4].integer.value; 600 hpx3_reg->pci_exp_vendor_id = reg_fields[5].integer.value; 601 hpx3_reg->dvsec_id = reg_fields[6].integer.value; 602 hpx3_reg->dvsec_rev = reg_fields[7].integer.value; 603 hpx3_reg->match_offset = reg_fields[8].integer.value; 604 hpx3_reg->match_mask_and = reg_fields[9].integer.value; 605 hpx3_reg->match_value = reg_fields[10].integer.value; 606 hpx3_reg->reg_offset = reg_fields[11].integer.value; 607 hpx3_reg->reg_mask_and = reg_fields[12].integer.value; 608 hpx3_reg->reg_mask_or = reg_fields[13].integer.value; 609 } 610 611 static acpi_status program_type3_hpx_record(struct pci_dev *dev, 612 union acpi_object *record) 613 { 614 union acpi_object *fields = record->package.elements; 615 u32 desc_count, expected_length, revision; 616 union acpi_object *reg_fields; 617 struct hpx_type3 hpx3; 618 int i; 619 620 revision = fields[1].integer.value; 621 switch (revision) { 622 case 1: 623 desc_count = fields[2].integer.value; 624 expected_length = 3 + desc_count * 14; 625 626 if (record->package.count != expected_length) 627 return AE_ERROR; 628 629 for (i = 2; i < expected_length; i++) 630 if (fields[i].type != ACPI_TYPE_INTEGER) 631 return AE_ERROR; 632 633 for (i = 0; i < desc_count; i++) { 634 reg_fields = fields + 3 + i * 14; 635 parse_hpx3_register(&hpx3, reg_fields); 636 program_hpx_type3(dev, &hpx3); 637 } 638 639 break; 640 default: 641 printk(KERN_WARNING 642 "%s: Type 3 Revision %d record not supported\n", 643 __func__, revision); 644 return AE_ERROR; 645 } 646 return AE_OK; 647 } 648 649 static acpi_status acpi_run_hpx(struct pci_dev *dev, acpi_handle handle) 650 { 651 acpi_status status; 652 struct acpi_buffer buffer = {ACPI_ALLOCATE_BUFFER, NULL}; 653 union acpi_object *package, *record, *fields; 654 struct hpx_type0 hpx0; 655 struct hpx_type1 hpx1; 656 struct hpx_type2 hpx2; 657 u32 type; 658 int i; 659 660 status = acpi_evaluate_object(handle, "_HPX", NULL, &buffer); 661 if (ACPI_FAILURE(status)) 662 return status; 663 664 package = (union acpi_object *)buffer.pointer; 665 if (package->type != ACPI_TYPE_PACKAGE) { 666 status = AE_ERROR; 667 goto exit; 668 } 669 670 for (i = 0; i < package->package.count; i++) { 671 record = &package->package.elements[i]; 672 if (record->type != ACPI_TYPE_PACKAGE) { 673 status = AE_ERROR; 674 goto exit; 675 } 676 677 fields = record->package.elements; 678 if (fields[0].type != ACPI_TYPE_INTEGER || 679 fields[1].type != ACPI_TYPE_INTEGER) { 680 status = AE_ERROR; 681 goto exit; 682 } 683 684 type = fields[0].integer.value; 685 switch (type) { 686 case 0: 687 memset(&hpx0, 0, sizeof(hpx0)); 688 status = decode_type0_hpx_record(record, &hpx0); 689 if (ACPI_FAILURE(status)) 690 goto exit; 691 program_hpx_type0(dev, &hpx0); 692 break; 693 case 1: 694 memset(&hpx1, 0, sizeof(hpx1)); 695 status = decode_type1_hpx_record(record, &hpx1); 696 if (ACPI_FAILURE(status)) 697 goto exit; 698 program_hpx_type1(dev, &hpx1); 699 break; 700 case 2: 701 memset(&hpx2, 0, sizeof(hpx2)); 702 status = decode_type2_hpx_record(record, &hpx2); 703 if (ACPI_FAILURE(status)) 704 goto exit; 705 program_hpx_type2(dev, &hpx2); 706 break; 707 case 3: 708 status = program_type3_hpx_record(dev, record); 709 if (ACPI_FAILURE(status)) 710 goto exit; 711 break; 712 default: 713 pr_err("%s: Type %d record not supported\n", 714 __func__, type); 715 status = AE_ERROR; 716 goto exit; 717 } 718 } 719 exit: 720 kfree(buffer.pointer); 721 return status; 722 } 723 724 static acpi_status acpi_run_hpp(struct pci_dev *dev, acpi_handle handle) 725 { 726 acpi_status status; 727 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; 728 union acpi_object *package, *fields; 729 struct hpx_type0 hpx0; 730 int i; 731 732 memset(&hpx0, 0, sizeof(hpx0)); 733 734 status = acpi_evaluate_object(handle, "_HPP", NULL, &buffer); 735 if (ACPI_FAILURE(status)) 736 return status; 737 738 package = (union acpi_object *) buffer.pointer; 739 if (package->type != ACPI_TYPE_PACKAGE || 740 package->package.count != 4) { 741 status = AE_ERROR; 742 goto exit; 743 } 744 745 fields = package->package.elements; 746 for (i = 0; i < 4; i++) { 747 if (fields[i].type != ACPI_TYPE_INTEGER) { 748 status = AE_ERROR; 749 goto exit; 750 } 751 } 752 753 hpx0.revision = 1; 754 hpx0.cache_line_size = fields[0].integer.value; 755 hpx0.latency_timer = fields[1].integer.value; 756 hpx0.enable_serr = fields[2].integer.value; 757 hpx0.enable_perr = fields[3].integer.value; 758 759 program_hpx_type0(dev, &hpx0); 760 761 exit: 762 kfree(buffer.pointer); 763 return status; 764 } 765 766 /* pci_acpi_program_hp_params 767 * 768 * @dev - the pci_dev for which we want parameters 769 */ 770 int pci_acpi_program_hp_params(struct pci_dev *dev) 771 { 772 acpi_status status; 773 acpi_handle handle, phandle; 774 struct pci_bus *pbus; 775 776 if (acpi_pci_disabled) 777 return -ENODEV; 778 779 handle = NULL; 780 for (pbus = dev->bus; pbus; pbus = pbus->parent) { 781 handle = acpi_pci_get_bridge_handle(pbus); 782 if (handle) 783 break; 784 } 785 786 /* 787 * _HPP settings apply to all child buses, until another _HPP is 788 * encountered. If we don't find an _HPP for the input pci dev, 789 * look for it in the parent device scope since that would apply to 790 * this pci dev. 791 */ 792 while (handle) { 793 status = acpi_run_hpx(dev, handle); 794 if (ACPI_SUCCESS(status)) 795 return 0; 796 status = acpi_run_hpp(dev, handle); 797 if (ACPI_SUCCESS(status)) 798 return 0; 799 if (acpi_is_root_bridge(handle)) 800 break; 801 status = acpi_get_parent(handle, &phandle); 802 if (ACPI_FAILURE(status)) 803 break; 804 handle = phandle; 805 } 806 return -ENODEV; 807 } 808 809 /** 810 * pciehp_is_native - Check whether a hotplug port is handled by the OS 811 * @bridge: Hotplug port to check 812 * 813 * Returns true if the given @bridge is handled by the native PCIe hotplug 814 * driver. 815 */ 816 bool pciehp_is_native(struct pci_dev *bridge) 817 { 818 const struct pci_host_bridge *host; 819 u32 slot_cap; 820 821 if (!IS_ENABLED(CONFIG_HOTPLUG_PCI_PCIE)) 822 return false; 823 824 pcie_capability_read_dword(bridge, PCI_EXP_SLTCAP, &slot_cap); 825 if (!(slot_cap & PCI_EXP_SLTCAP_HPC)) 826 return false; 827 828 if (pcie_ports_native) 829 return true; 830 831 host = pci_find_host_bridge(bridge->bus); 832 return host->native_pcie_hotplug; 833 } 834 835 /** 836 * shpchp_is_native - Check whether a hotplug port is handled by the OS 837 * @bridge: Hotplug port to check 838 * 839 * Returns true if the given @bridge is handled by the native SHPC hotplug 840 * driver. 841 */ 842 bool shpchp_is_native(struct pci_dev *bridge) 843 { 844 return bridge->shpc_managed; 845 } 846 847 /** 848 * pci_acpi_wake_bus - Root bus wakeup notification fork function. 849 * @context: Device wakeup context. 850 */ 851 static void pci_acpi_wake_bus(struct acpi_device_wakeup_context *context) 852 { 853 struct acpi_device *adev; 854 struct acpi_pci_root *root; 855 856 adev = container_of(context, struct acpi_device, wakeup.context); 857 root = acpi_driver_data(adev); 858 pci_pme_wakeup_bus(root->bus); 859 } 860 861 /** 862 * pci_acpi_wake_dev - PCI device wakeup notification work function. 863 * @context: Device wakeup context. 864 */ 865 static void pci_acpi_wake_dev(struct acpi_device_wakeup_context *context) 866 { 867 struct pci_dev *pci_dev; 868 869 pci_dev = to_pci_dev(context->dev); 870 871 if (pci_dev->pme_poll) 872 pci_dev->pme_poll = false; 873 874 if (pci_dev->current_state == PCI_D3cold) { 875 pci_wakeup_event(pci_dev); 876 pm_request_resume(&pci_dev->dev); 877 return; 878 } 879 880 /* Clear PME Status if set. */ 881 if (pci_dev->pme_support) 882 pci_check_pme_status(pci_dev); 883 884 pci_wakeup_event(pci_dev); 885 pm_request_resume(&pci_dev->dev); 886 887 pci_pme_wakeup_bus(pci_dev->subordinate); 888 } 889 890 /** 891 * pci_acpi_add_bus_pm_notifier - Register PM notifier for root PCI bus. 892 * @dev: PCI root bridge ACPI device. 893 */ 894 acpi_status pci_acpi_add_bus_pm_notifier(struct acpi_device *dev) 895 { 896 return acpi_add_pm_notifier(dev, NULL, pci_acpi_wake_bus); 897 } 898 899 /** 900 * pci_acpi_add_pm_notifier - Register PM notifier for given PCI device. 901 * @dev: ACPI device to add the notifier for. 902 * @pci_dev: PCI device to check for the PME status if an event is signaled. 903 */ 904 acpi_status pci_acpi_add_pm_notifier(struct acpi_device *dev, 905 struct pci_dev *pci_dev) 906 { 907 return acpi_add_pm_notifier(dev, &pci_dev->dev, pci_acpi_wake_dev); 908 } 909 910 /* 911 * _SxD returns the D-state with the highest power 912 * (lowest D-state number) supported in the S-state "x". 913 * 914 * If the devices does not have a _PRW 915 * (Power Resources for Wake) supporting system wakeup from "x" 916 * then the OS is free to choose a lower power (higher number 917 * D-state) than the return value from _SxD. 918 * 919 * But if _PRW is enabled at S-state "x", the OS 920 * must not choose a power lower than _SxD -- 921 * unless the device has an _SxW method specifying 922 * the lowest power (highest D-state number) the device 923 * may enter while still able to wake the system. 924 * 925 * ie. depending on global OS policy: 926 * 927 * if (_PRW at S-state x) 928 * choose from highest power _SxD to lowest power _SxW 929 * else // no _PRW at S-state x 930 * choose highest power _SxD or any lower power 931 */ 932 933 pci_power_t acpi_pci_choose_state(struct pci_dev *pdev) 934 { 935 int acpi_state, d_max; 936 937 if (pdev->no_d3cold || !pdev->d3cold_allowed) 938 d_max = ACPI_STATE_D3_HOT; 939 else 940 d_max = ACPI_STATE_D3_COLD; 941 acpi_state = acpi_pm_device_sleep_state(&pdev->dev, NULL, d_max); 942 if (acpi_state < 0) 943 return PCI_POWER_ERROR; 944 945 switch (acpi_state) { 946 case ACPI_STATE_D0: 947 return PCI_D0; 948 case ACPI_STATE_D1: 949 return PCI_D1; 950 case ACPI_STATE_D2: 951 return PCI_D2; 952 case ACPI_STATE_D3_HOT: 953 return PCI_D3hot; 954 case ACPI_STATE_D3_COLD: 955 return PCI_D3cold; 956 } 957 return PCI_POWER_ERROR; 958 } 959 960 static struct acpi_device *acpi_pci_find_companion(struct device *dev); 961 962 void pci_set_acpi_fwnode(struct pci_dev *dev) 963 { 964 if (!dev_fwnode(&dev->dev) && !pci_dev_is_added(dev)) 965 ACPI_COMPANION_SET(&dev->dev, 966 acpi_pci_find_companion(&dev->dev)); 967 } 968 969 /** 970 * pci_dev_acpi_reset - do a function level reset using _RST method 971 * @dev: device to reset 972 * @probe: if true, return 0 if device supports _RST 973 */ 974 int pci_dev_acpi_reset(struct pci_dev *dev, bool probe) 975 { 976 acpi_handle handle = ACPI_HANDLE(&dev->dev); 977 978 if (!handle || !acpi_has_method(handle, "_RST")) 979 return -ENOTTY; 980 981 if (probe) 982 return 0; 983 984 if (ACPI_FAILURE(acpi_evaluate_object(handle, "_RST", NULL, NULL))) { 985 pci_warn(dev, "ACPI _RST failed\n"); 986 return -ENOTTY; 987 } 988 989 return 0; 990 } 991 992 bool acpi_pci_power_manageable(struct pci_dev *dev) 993 { 994 struct acpi_device *adev = ACPI_COMPANION(&dev->dev); 995 996 return adev && acpi_device_power_manageable(adev); 997 } 998 999 bool acpi_pci_bridge_d3(struct pci_dev *dev) 1000 { 1001 struct pci_dev *rpdev; 1002 struct acpi_device *adev, *rpadev; 1003 const union acpi_object *obj; 1004 1005 if (acpi_pci_disabled || !dev->is_hotplug_bridge) 1006 return false; 1007 1008 adev = ACPI_COMPANION(&dev->dev); 1009 if (adev) { 1010 /* 1011 * If the bridge has _S0W, whether or not it can go into D3 1012 * depends on what is returned by that object. In particular, 1013 * if the power state returned by _S0W is D2 or shallower, 1014 * entering D3 should not be allowed. 1015 */ 1016 if (acpi_dev_power_state_for_wake(adev) <= ACPI_STATE_D2) 1017 return false; 1018 1019 /* 1020 * Otherwise, assume that the bridge can enter D3 so long as it 1021 * is power-manageable via ACPI. 1022 */ 1023 if (acpi_device_power_manageable(adev)) 1024 return true; 1025 } 1026 1027 rpdev = pcie_find_root_port(dev); 1028 if (!rpdev) 1029 return false; 1030 1031 if (rpdev == dev) 1032 rpadev = adev; 1033 else 1034 rpadev = ACPI_COMPANION(&rpdev->dev); 1035 1036 if (!rpadev) 1037 return false; 1038 1039 /* 1040 * If the Root Port cannot signal wakeup signals at all, i.e., it 1041 * doesn't supply a wakeup GPE via _PRW, it cannot signal hotplug 1042 * events from low-power states including D3hot and D3cold. 1043 */ 1044 if (!rpadev->wakeup.flags.valid) 1045 return false; 1046 1047 /* 1048 * In the bridge-below-a-Root-Port case, evaluate _S0W for the Root Port 1049 * to verify whether or not it can signal wakeup from D3. 1050 */ 1051 if (rpadev != adev && 1052 acpi_dev_power_state_for_wake(rpadev) <= ACPI_STATE_D2) 1053 return false; 1054 1055 /* 1056 * The "HotPlugSupportInD3" property in a Root Port _DSD indicates 1057 * the Port can signal hotplug events while in D3. We assume any 1058 * bridges *below* that Root Port can also signal hotplug events 1059 * while in D3. 1060 */ 1061 if (!acpi_dev_get_property(rpadev, "HotPlugSupportInD3", 1062 ACPI_TYPE_INTEGER, &obj) && 1063 obj->integer.value == 1) 1064 return true; 1065 1066 return false; 1067 } 1068 1069 static void acpi_pci_config_space_access(struct pci_dev *dev, bool enable) 1070 { 1071 int val = enable ? ACPI_REG_CONNECT : ACPI_REG_DISCONNECT; 1072 int ret = acpi_evaluate_reg(ACPI_HANDLE(&dev->dev), 1073 ACPI_ADR_SPACE_PCI_CONFIG, val); 1074 if (ret) 1075 pci_dbg(dev, "ACPI _REG %s evaluation failed (%d)\n", 1076 enable ? "connect" : "disconnect", ret); 1077 } 1078 1079 int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state) 1080 { 1081 struct acpi_device *adev = ACPI_COMPANION(&dev->dev); 1082 static const u8 state_conv[] = { 1083 [PCI_D0] = ACPI_STATE_D0, 1084 [PCI_D1] = ACPI_STATE_D1, 1085 [PCI_D2] = ACPI_STATE_D2, 1086 [PCI_D3hot] = ACPI_STATE_D3_HOT, 1087 [PCI_D3cold] = ACPI_STATE_D3_COLD, 1088 }; 1089 int error; 1090 1091 /* If the ACPI device has _EJ0, ignore the device */ 1092 if (!adev || acpi_has_method(adev->handle, "_EJ0")) 1093 return -ENODEV; 1094 1095 switch (state) { 1096 case PCI_D0: 1097 case PCI_D1: 1098 case PCI_D2: 1099 case PCI_D3hot: 1100 case PCI_D3cold: 1101 break; 1102 default: 1103 return -EINVAL; 1104 } 1105 1106 if (state == PCI_D3cold) { 1107 if (dev_pm_qos_flags(&dev->dev, PM_QOS_FLAG_NO_POWER_OFF) == 1108 PM_QOS_FLAGS_ALL) 1109 return -EBUSY; 1110 1111 /* Notify AML lack of PCI config space availability */ 1112 acpi_pci_config_space_access(dev, false); 1113 } 1114 1115 error = acpi_device_set_power(adev, state_conv[state]); 1116 if (error) 1117 return error; 1118 1119 pci_dbg(dev, "power state changed by ACPI to %s\n", 1120 acpi_power_state_string(adev->power.state)); 1121 1122 /* 1123 * Notify AML of PCI config space availability. Config space is 1124 * accessible in all states except D3cold; the only transitions 1125 * that change availability are transitions to D3cold and from 1126 * D3cold to D0. 1127 */ 1128 if (state == PCI_D0) 1129 acpi_pci_config_space_access(dev, true); 1130 1131 return 0; 1132 } 1133 1134 pci_power_t acpi_pci_get_power_state(struct pci_dev *dev) 1135 { 1136 struct acpi_device *adev = ACPI_COMPANION(&dev->dev); 1137 static const pci_power_t state_conv[] = { 1138 [ACPI_STATE_D0] = PCI_D0, 1139 [ACPI_STATE_D1] = PCI_D1, 1140 [ACPI_STATE_D2] = PCI_D2, 1141 [ACPI_STATE_D3_HOT] = PCI_D3hot, 1142 [ACPI_STATE_D3_COLD] = PCI_D3cold, 1143 }; 1144 int state; 1145 1146 if (!adev || !acpi_device_power_manageable(adev)) 1147 return PCI_UNKNOWN; 1148 1149 state = adev->power.state; 1150 if (state == ACPI_STATE_UNKNOWN) 1151 return PCI_UNKNOWN; 1152 1153 return state_conv[state]; 1154 } 1155 1156 void acpi_pci_refresh_power_state(struct pci_dev *dev) 1157 { 1158 struct acpi_device *adev = ACPI_COMPANION(&dev->dev); 1159 1160 if (adev && acpi_device_power_manageable(adev)) 1161 acpi_device_update_power(adev, NULL); 1162 } 1163 1164 static int acpi_pci_propagate_wakeup(struct pci_bus *bus, bool enable) 1165 { 1166 while (bus->parent) { 1167 if (acpi_pm_device_can_wakeup(&bus->self->dev)) 1168 return acpi_pm_set_device_wakeup(&bus->self->dev, enable); 1169 1170 bus = bus->parent; 1171 } 1172 1173 /* We have reached the root bus. */ 1174 if (bus->bridge) { 1175 if (acpi_pm_device_can_wakeup(bus->bridge)) 1176 return acpi_pm_set_device_wakeup(bus->bridge, enable); 1177 } 1178 return 0; 1179 } 1180 1181 int acpi_pci_wakeup(struct pci_dev *dev, bool enable) 1182 { 1183 if (acpi_pci_disabled) 1184 return 0; 1185 1186 if (acpi_pm_device_can_wakeup(&dev->dev)) 1187 return acpi_pm_set_device_wakeup(&dev->dev, enable); 1188 1189 return acpi_pci_propagate_wakeup(dev->bus, enable); 1190 } 1191 1192 bool acpi_pci_need_resume(struct pci_dev *dev) 1193 { 1194 struct acpi_device *adev; 1195 1196 if (acpi_pci_disabled) 1197 return false; 1198 1199 /* 1200 * In some cases (eg. Samsung 305V4A) leaving a bridge in suspend over 1201 * system-wide suspend/resume confuses the platform firmware, so avoid 1202 * doing that. According to Section 16.1.6 of ACPI 6.2, endpoint 1203 * devices are expected to be in D3 before invoking the S3 entry path 1204 * from the firmware, so they should not be affected by this issue. 1205 */ 1206 if (pci_is_bridge(dev) && acpi_target_system_state() != ACPI_STATE_S0) 1207 return true; 1208 1209 adev = ACPI_COMPANION(&dev->dev); 1210 if (!adev || !acpi_device_power_manageable(adev)) 1211 return false; 1212 1213 if (adev->wakeup.flags.valid && 1214 device_may_wakeup(&dev->dev) != !!adev->wakeup.prepare_count) 1215 return true; 1216 1217 if (acpi_target_system_state() == ACPI_STATE_S0) 1218 return false; 1219 1220 return !!adev->power.flags.dsw_present; 1221 } 1222 1223 void acpi_pci_add_bus(struct pci_bus *bus) 1224 { 1225 union acpi_object *obj; 1226 struct pci_host_bridge *bridge; 1227 1228 if (acpi_pci_disabled || !bus->bridge || !ACPI_HANDLE(bus->bridge)) 1229 return; 1230 1231 acpi_pci_slot_enumerate(bus); 1232 acpiphp_enumerate_slots(bus); 1233 1234 /* 1235 * For a host bridge, check its _DSM for function 8 and if 1236 * that is available, mark it in pci_host_bridge. 1237 */ 1238 if (!pci_is_root_bus(bus)) 1239 return; 1240 1241 obj = acpi_evaluate_dsm_typed(ACPI_HANDLE(bus->bridge), &pci_acpi_dsm_guid, 3, 1242 DSM_PCI_POWER_ON_RESET_DELAY, NULL, ACPI_TYPE_INTEGER); 1243 if (!obj) 1244 return; 1245 1246 if (obj->integer.value == 1) { 1247 bridge = pci_find_host_bridge(bus); 1248 bridge->ignore_reset_delay = 1; 1249 } 1250 ACPI_FREE(obj); 1251 } 1252 1253 void acpi_pci_remove_bus(struct pci_bus *bus) 1254 { 1255 if (acpi_pci_disabled || !bus->bridge) 1256 return; 1257 1258 acpiphp_remove_slots(bus); 1259 acpi_pci_slot_remove(bus); 1260 } 1261 1262 /* ACPI bus type */ 1263 1264 1265 static DECLARE_RWSEM(pci_acpi_companion_lookup_sem); 1266 static struct acpi_device *(*pci_acpi_find_companion_hook)(struct pci_dev *); 1267 1268 /** 1269 * pci_acpi_set_companion_lookup_hook - Set ACPI companion lookup callback. 1270 * @func: ACPI companion lookup callback pointer or NULL. 1271 * 1272 * Set a special ACPI companion lookup callback for PCI devices whose companion 1273 * objects in the ACPI namespace have _ADR with non-standard bus-device-function 1274 * encodings. 1275 * 1276 * Return 0 on success or a negative error code on failure (in which case no 1277 * changes are made). 1278 * 1279 * The caller is responsible for the appropriate ordering of the invocations of 1280 * this function with respect to the enumeration of the PCI devices needing the 1281 * callback installed by it. 1282 */ 1283 int pci_acpi_set_companion_lookup_hook(struct acpi_device *(*func)(struct pci_dev *)) 1284 { 1285 int ret; 1286 1287 if (!func) 1288 return -EINVAL; 1289 1290 down_write(&pci_acpi_companion_lookup_sem); 1291 1292 if (pci_acpi_find_companion_hook) { 1293 ret = -EBUSY; 1294 } else { 1295 pci_acpi_find_companion_hook = func; 1296 ret = 0; 1297 } 1298 1299 up_write(&pci_acpi_companion_lookup_sem); 1300 1301 return ret; 1302 } 1303 EXPORT_SYMBOL_GPL(pci_acpi_set_companion_lookup_hook); 1304 1305 /** 1306 * pci_acpi_clear_companion_lookup_hook - Clear ACPI companion lookup callback. 1307 * 1308 * Clear the special ACPI companion lookup callback previously set by 1309 * pci_acpi_set_companion_lookup_hook(). Block until the last running instance 1310 * of the callback returns before clearing it. 1311 * 1312 * The caller is responsible for the appropriate ordering of the invocations of 1313 * this function with respect to the enumeration of the PCI devices needing the 1314 * callback cleared by it. 1315 */ 1316 void pci_acpi_clear_companion_lookup_hook(void) 1317 { 1318 down_write(&pci_acpi_companion_lookup_sem); 1319 1320 pci_acpi_find_companion_hook = NULL; 1321 1322 up_write(&pci_acpi_companion_lookup_sem); 1323 } 1324 EXPORT_SYMBOL_GPL(pci_acpi_clear_companion_lookup_hook); 1325 1326 static struct acpi_device *acpi_pci_find_companion(struct device *dev) 1327 { 1328 struct pci_dev *pci_dev = to_pci_dev(dev); 1329 struct acpi_device *adev; 1330 bool check_children; 1331 u64 addr; 1332 1333 if (!dev->parent) 1334 return NULL; 1335 1336 down_read(&pci_acpi_companion_lookup_sem); 1337 1338 adev = pci_acpi_find_companion_hook ? 1339 pci_acpi_find_companion_hook(pci_dev) : NULL; 1340 1341 up_read(&pci_acpi_companion_lookup_sem); 1342 1343 if (adev) 1344 return adev; 1345 1346 check_children = pci_is_bridge(pci_dev); 1347 /* Please ref to ACPI spec for the syntax of _ADR */ 1348 addr = (PCI_SLOT(pci_dev->devfn) << 16) | PCI_FUNC(pci_dev->devfn); 1349 adev = acpi_find_child_device(ACPI_COMPANION(dev->parent), addr, 1350 check_children); 1351 1352 /* 1353 * There may be ACPI device objects in the ACPI namespace that are 1354 * children of the device object representing the host bridge, but don't 1355 * represent PCI devices. Both _HID and _ADR may be present for them, 1356 * even though that is against the specification (for example, see 1357 * Section 6.1 of ACPI 6.3), but in many cases the _ADR returns 0 which 1358 * appears to indicate that they should not be taken into consideration 1359 * as potential companions of PCI devices on the root bus. 1360 * 1361 * To catch this special case, disregard the returned device object if 1362 * it has a valid _HID, addr is 0 and the PCI device at hand is on the 1363 * root bus. 1364 */ 1365 if (adev && adev->pnp.type.platform_id && !addr && 1366 pci_is_root_bus(pci_dev->bus)) 1367 return NULL; 1368 1369 return adev; 1370 } 1371 1372 /** 1373 * pci_acpi_optimize_delay - optimize PCI D3 and D3cold delay from ACPI 1374 * @pdev: the PCI device whose delay is to be updated 1375 * @handle: ACPI handle of this device 1376 * 1377 * Update the d3hot_delay and d3cold_delay of a PCI device from the ACPI _DSM 1378 * control method of either the device itself or the PCI host bridge. 1379 * 1380 * Function 8, "Reset Delay," applies to the entire hierarchy below a PCI 1381 * host bridge. If it returns one, the OS may assume that all devices in 1382 * the hierarchy have already completed power-on reset delays. 1383 * 1384 * Function 9, "Device Readiness Durations," applies only to the object 1385 * where it is located. It returns delay durations required after various 1386 * events if the device requires less time than the spec requires. Delays 1387 * from this function take precedence over the Reset Delay function. 1388 * 1389 * These _DSM functions are defined by the draft ECN of January 28, 2014, 1390 * titled "ACPI additions for FW latency optimizations." 1391 */ 1392 static void pci_acpi_optimize_delay(struct pci_dev *pdev, 1393 acpi_handle handle) 1394 { 1395 struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus); 1396 int value; 1397 union acpi_object *obj, *elements; 1398 1399 if (bridge->ignore_reset_delay) 1400 pdev->d3cold_delay = 0; 1401 1402 obj = acpi_evaluate_dsm_typed(handle, &pci_acpi_dsm_guid, 3, 1403 DSM_PCI_DEVICE_READINESS_DURATIONS, NULL, 1404 ACPI_TYPE_PACKAGE); 1405 if (!obj) 1406 return; 1407 1408 if (obj->package.count == 5) { 1409 elements = obj->package.elements; 1410 if (elements[0].type == ACPI_TYPE_INTEGER) { 1411 value = (int)elements[0].integer.value / 1000; 1412 if (value < PCI_PM_D3COLD_WAIT) 1413 pdev->d3cold_delay = value; 1414 } 1415 if (elements[3].type == ACPI_TYPE_INTEGER) { 1416 value = (int)elements[3].integer.value / 1000; 1417 if (value < PCI_PM_D3HOT_WAIT) 1418 pdev->d3hot_delay = value; 1419 } 1420 } 1421 ACPI_FREE(obj); 1422 } 1423 1424 static void pci_acpi_set_external_facing(struct pci_dev *dev) 1425 { 1426 u8 val; 1427 1428 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 1429 return; 1430 if (device_property_read_u8(&dev->dev, "ExternalFacingPort", &val)) 1431 return; 1432 1433 /* 1434 * These root ports expose PCIe (including DMA) outside of the 1435 * system. Everything downstream from them is external. 1436 */ 1437 if (val) 1438 dev->external_facing = 1; 1439 } 1440 1441 void pci_acpi_setup(struct device *dev, struct acpi_device *adev) 1442 { 1443 struct pci_dev *pci_dev = to_pci_dev(dev); 1444 1445 pci_acpi_optimize_delay(pci_dev, adev->handle); 1446 pci_acpi_set_external_facing(pci_dev); 1447 pci_acpi_add_edr_notifier(pci_dev); 1448 1449 pci_acpi_add_pm_notifier(adev, pci_dev); 1450 if (!adev->wakeup.flags.valid) 1451 return; 1452 1453 device_set_wakeup_capable(dev, true); 1454 /* 1455 * For bridges that can do D3 we enable wake automatically (as 1456 * we do for the power management itself in that case). The 1457 * reason is that the bridge may have additional methods such as 1458 * _DSW that need to be called. 1459 */ 1460 if (pci_dev->bridge_d3) 1461 device_wakeup_enable(dev); 1462 1463 acpi_pci_wakeup(pci_dev, false); 1464 acpi_device_power_add_dependent(adev, dev); 1465 1466 if (pci_is_bridge(pci_dev)) 1467 acpi_dev_power_up_children_with_adr(adev); 1468 } 1469 1470 void pci_acpi_cleanup(struct device *dev, struct acpi_device *adev) 1471 { 1472 struct pci_dev *pci_dev = to_pci_dev(dev); 1473 1474 pci_acpi_remove_edr_notifier(pci_dev); 1475 pci_acpi_remove_pm_notifier(adev); 1476 if (adev->wakeup.flags.valid) { 1477 acpi_device_power_remove_dependent(adev, dev); 1478 if (pci_dev->bridge_d3) 1479 device_wakeup_disable(dev); 1480 1481 device_set_wakeup_capable(dev, false); 1482 } 1483 } 1484 1485 static struct fwnode_handle *(*pci_msi_get_fwnode_cb)(struct device *dev); 1486 1487 /** 1488 * pci_msi_register_fwnode_provider - Register callback to retrieve fwnode 1489 * @fn: Callback matching a device to a fwnode that identifies a PCI 1490 * MSI domain. 1491 * 1492 * This should be called by irqchip driver, which is the parent of 1493 * the MSI domain to provide callback interface to query fwnode. 1494 */ 1495 void 1496 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *)) 1497 { 1498 pci_msi_get_fwnode_cb = fn; 1499 } 1500 1501 /** 1502 * pci_host_bridge_acpi_msi_domain - Retrieve MSI domain of a PCI host bridge 1503 * @bus: The PCI host bridge bus. 1504 * 1505 * This function uses the callback function registered by 1506 * pci_msi_register_fwnode_provider() to retrieve the irq_domain with 1507 * type DOMAIN_BUS_PCI_MSI of the specified host bridge bus. 1508 * This returns NULL on error or when the domain is not found. 1509 */ 1510 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) 1511 { 1512 struct fwnode_handle *fwnode; 1513 1514 if (!pci_msi_get_fwnode_cb) 1515 return NULL; 1516 1517 fwnode = pci_msi_get_fwnode_cb(&bus->dev); 1518 if (!fwnode) 1519 return NULL; 1520 1521 return irq_find_matching_fwnode(fwnode, DOMAIN_BUS_PCI_MSI); 1522 } 1523 1524 static int __init acpi_pci_init(void) 1525 { 1526 if (acpi_gbl_FADT.boot_flags & ACPI_FADT_NO_MSI) { 1527 pr_info("ACPI FADT declares the system doesn't support MSI, so disable it\n"); 1528 pci_no_msi(); 1529 } 1530 1531 if (acpi_gbl_FADT.boot_flags & ACPI_FADT_NO_ASPM) { 1532 pr_info("ACPI FADT declares the system doesn't support PCIe ASPM, so disable it\n"); 1533 pcie_no_aspm(); 1534 } 1535 1536 if (acpi_pci_disabled) 1537 return 0; 1538 1539 acpi_pci_slot_init(); 1540 acpiphp_init(); 1541 1542 return 0; 1543 } 1544 arch_initcall(acpi_pci_init); 1545 1546 #if defined(CONFIG_ARM64) || defined(CONFIG_RISCV) 1547 1548 /* 1549 * Try to assign the IRQ number when probing a new device 1550 */ 1551 int pcibios_alloc_irq(struct pci_dev *dev) 1552 { 1553 if (!acpi_disabled) 1554 acpi_pci_irq_enable(dev); 1555 1556 return 0; 1557 } 1558 1559 struct acpi_pci_generic_root_info { 1560 struct acpi_pci_root_info common; 1561 struct pci_config_window *cfg; /* config space mapping */ 1562 }; 1563 1564 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus) 1565 { 1566 struct pci_config_window *cfg = bus->sysdata; 1567 struct acpi_device *adev = to_acpi_device(cfg->parent); 1568 struct acpi_pci_root *root = acpi_driver_data(adev); 1569 1570 return root->segment; 1571 } 1572 1573 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge) 1574 { 1575 struct pci_config_window *cfg; 1576 struct acpi_device *adev; 1577 struct device *bus_dev; 1578 1579 if (acpi_disabled) 1580 return 0; 1581 1582 cfg = bridge->bus->sysdata; 1583 1584 /* 1585 * On Hyper-V there is no corresponding ACPI device for a root bridge, 1586 * therefore ->parent is set as NULL by the driver. And set 'adev' as 1587 * NULL in this case because there is no proper ACPI device. 1588 */ 1589 if (!cfg->parent) 1590 adev = NULL; 1591 else 1592 adev = to_acpi_device(cfg->parent); 1593 1594 bus_dev = &bridge->bus->dev; 1595 1596 ACPI_COMPANION_SET(&bridge->dev, adev); 1597 set_dev_node(bus_dev, acpi_get_node(acpi_device_handle(adev))); 1598 1599 return 0; 1600 } 1601 1602 static int pci_acpi_root_prepare_resources(struct acpi_pci_root_info *ci) 1603 { 1604 struct resource_entry *entry, *tmp; 1605 int status; 1606 1607 status = acpi_pci_probe_root_resources(ci); 1608 resource_list_for_each_entry_safe(entry, tmp, &ci->resources) { 1609 if (!(entry->res->flags & IORESOURCE_WINDOW)) 1610 resource_list_destroy_entry(entry); 1611 } 1612 return status; 1613 } 1614 1615 /* 1616 * Lookup the bus range for the domain in MCFG, and set up config space 1617 * mapping. 1618 */ 1619 static struct pci_config_window * 1620 pci_acpi_setup_ecam_mapping(struct acpi_pci_root *root) 1621 { 1622 struct device *dev = &root->device->dev; 1623 struct resource *bus_res = &root->secondary; 1624 u16 seg = root->segment; 1625 const struct pci_ecam_ops *ecam_ops; 1626 struct resource cfgres; 1627 struct acpi_device *adev; 1628 struct pci_config_window *cfg; 1629 int ret; 1630 1631 ret = pci_mcfg_lookup(root, &cfgres, &ecam_ops); 1632 if (ret) { 1633 dev_err(dev, "%04x:%pR ECAM region not found\n", seg, bus_res); 1634 return NULL; 1635 } 1636 1637 adev = acpi_resource_consumer(&cfgres); 1638 if (adev) 1639 dev_info(dev, "ECAM area %pR reserved by %s\n", &cfgres, 1640 dev_name(&adev->dev)); 1641 else 1642 dev_warn(dev, FW_BUG "ECAM area %pR not reserved in ACPI namespace\n", 1643 &cfgres); 1644 1645 cfg = pci_ecam_create(dev, &cfgres, bus_res, ecam_ops); 1646 if (IS_ERR(cfg)) { 1647 dev_err(dev, "%04x:%pR error %ld mapping ECAM\n", seg, bus_res, 1648 PTR_ERR(cfg)); 1649 return NULL; 1650 } 1651 1652 return cfg; 1653 } 1654 1655 /* release_info: free resources allocated by init_info */ 1656 static void pci_acpi_generic_release_info(struct acpi_pci_root_info *ci) 1657 { 1658 struct acpi_pci_generic_root_info *ri; 1659 1660 ri = container_of(ci, struct acpi_pci_generic_root_info, common); 1661 pci_ecam_free(ri->cfg); 1662 kfree(ci->ops); 1663 kfree(ri); 1664 } 1665 1666 /* Interface called from ACPI code to setup PCI host controller */ 1667 struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root) 1668 { 1669 struct acpi_pci_generic_root_info *ri; 1670 struct pci_bus *bus, *child; 1671 struct acpi_pci_root_ops *root_ops; 1672 struct pci_host_bridge *host; 1673 1674 ri = kzalloc(sizeof(*ri), GFP_KERNEL); 1675 if (!ri) 1676 return NULL; 1677 1678 root_ops = kzalloc(sizeof(*root_ops), GFP_KERNEL); 1679 if (!root_ops) { 1680 kfree(ri); 1681 return NULL; 1682 } 1683 1684 ri->cfg = pci_acpi_setup_ecam_mapping(root); 1685 if (!ri->cfg) { 1686 kfree(ri); 1687 kfree(root_ops); 1688 return NULL; 1689 } 1690 1691 root_ops->release_info = pci_acpi_generic_release_info; 1692 root_ops->prepare_resources = pci_acpi_root_prepare_resources; 1693 root_ops->pci_ops = (struct pci_ops *)&ri->cfg->ops->pci_ops; 1694 bus = acpi_pci_root_create(root, root_ops, &ri->common, ri->cfg); 1695 if (!bus) 1696 return NULL; 1697 1698 /* If we must preserve the resource configuration, claim now */ 1699 host = pci_find_host_bridge(bus); 1700 if (host->preserve_config) 1701 pci_bus_claim_resources(bus); 1702 1703 /* 1704 * Assign whatever was left unassigned. If we didn't claim above, 1705 * this will reassign everything. 1706 */ 1707 pci_assign_unassigned_root_bus_resources(bus); 1708 1709 list_for_each_entry(child, &bus->children, node) 1710 pcie_bus_configure_settings(child); 1711 1712 return bus; 1713 } 1714 1715 void pcibios_add_bus(struct pci_bus *bus) 1716 { 1717 acpi_pci_add_bus(bus); 1718 } 1719 1720 void pcibios_remove_bus(struct pci_bus *bus) 1721 { 1722 acpi_pci_remove_bus(bus); 1723 } 1724 1725 #endif 1726