1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2024-2025 Intel Corporation. All rights reserved. */ 3 4 /* PCIe r7.0 section 6.33 Integrity & Data Encryption (IDE) */ 5 6 #define dev_fmt(fmt) "PCI/IDE: " fmt 7 #include <linux/bitfield.h> 8 #include <linux/bitops.h> 9 #include <linux/pci.h> 10 #include <linux/pci-ide.h> 11 #include <linux/pci_regs.h> 12 #include <linux/slab.h> 13 #include <linux/sysfs.h> 14 15 #include "pci.h" 16 17 static int __sel_ide_offset(u16 ide_cap, u8 nr_link_ide, u8 stream_index, 18 u8 nr_ide_mem) 19 { 20 u32 offset = ide_cap + PCI_IDE_LINK_STREAM_0 + 21 nr_link_ide * PCI_IDE_LINK_BLOCK_SIZE; 22 23 /* 24 * Assume a constant number of address association resources per stream 25 * index 26 */ 27 return offset + stream_index * PCI_IDE_SEL_BLOCK_SIZE(nr_ide_mem); 28 } 29 30 static int sel_ide_offset(struct pci_dev *pdev, 31 struct pci_ide_partner *settings) 32 { 33 return __sel_ide_offset(pdev->ide_cap, pdev->nr_link_ide, 34 settings->stream_index, pdev->nr_ide_mem); 35 } 36 37 static bool reserve_stream_index(struct pci_dev *pdev, u8 idx) 38 { 39 int ret; 40 41 ret = ida_alloc_range(&pdev->ide_stream_ida, idx, idx, GFP_KERNEL); 42 return ret >= 0; 43 } 44 45 static bool reserve_stream_id(struct pci_host_bridge *hb, u8 id) 46 { 47 int ret; 48 49 ret = ida_alloc_range(&hb->ide_stream_ids_ida, id, id, GFP_KERNEL); 50 return ret >= 0; 51 } 52 53 static bool claim_stream(struct pci_host_bridge *hb, u8 stream_id, 54 struct pci_dev *pdev, u8 stream_idx) 55 { 56 dev_info(&hb->dev, "Stream ID %d active at init\n", stream_id); 57 if (!reserve_stream_id(hb, stream_id)) { 58 dev_info(&hb->dev, "Failed to claim %s Stream ID %d\n", 59 stream_id == PCI_IDE_RESERVED_STREAM_ID ? "reserved" : 60 "active", 61 stream_id); 62 return false; 63 } 64 65 /* No stream index to reserve in the Link IDE case */ 66 if (!pdev) 67 return true; 68 69 if (!reserve_stream_index(pdev, stream_idx)) { 70 pci_info(pdev, "Failed to claim active Selective Stream %d\n", 71 stream_idx); 72 return false; 73 } 74 75 return true; 76 } 77 78 void pci_ide_init(struct pci_dev *pdev) 79 { 80 struct pci_host_bridge *hb = pci_find_host_bridge(pdev->bus); 81 u16 nr_link_ide, nr_ide_mem, nr_streams; 82 u16 ide_cap; 83 u32 val; 84 85 /* 86 * Unconditionally init so that ida idle state is consistent with 87 * pdev->ide_cap. 88 */ 89 ida_init(&pdev->ide_stream_ida); 90 91 if (!pci_is_pcie(pdev)) 92 return; 93 94 ide_cap = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_IDE); 95 if (!ide_cap) 96 return; 97 98 pci_read_config_dword(pdev, ide_cap + PCI_IDE_CAP, &val); 99 if ((val & PCI_IDE_CAP_SELECTIVE) == 0) 100 return; 101 102 /* 103 * Require endpoint IDE capability to be paired with IDE Root Port IDE 104 * capability. 105 */ 106 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ENDPOINT) { 107 struct pci_dev *rp = pcie_find_root_port(pdev); 108 109 if (!rp->ide_cap) 110 return; 111 } 112 113 pdev->ide_cfg = FIELD_GET(PCI_IDE_CAP_SEL_CFG, val); 114 pdev->ide_tee_limit = FIELD_GET(PCI_IDE_CAP_TEE_LIMITED, val); 115 116 if (val & PCI_IDE_CAP_LINK) 117 nr_link_ide = 1 + FIELD_GET(PCI_IDE_CAP_LINK_TC_NUM, val); 118 else 119 nr_link_ide = 0; 120 121 nr_ide_mem = 0; 122 nr_streams = 1 + FIELD_GET(PCI_IDE_CAP_SEL_NUM, val); 123 for (u16 i = 0; i < nr_streams; i++) { 124 int pos = __sel_ide_offset(ide_cap, nr_link_ide, i, nr_ide_mem); 125 int nr_assoc; 126 u32 val; 127 u8 id; 128 129 pci_read_config_dword(pdev, pos + PCI_IDE_SEL_CAP, &val); 130 131 /* 132 * Let's not entertain streams that do not have a constant 133 * number of address association blocks 134 */ 135 nr_assoc = FIELD_GET(PCI_IDE_SEL_CAP_ASSOC_NUM, val); 136 if (i && (nr_assoc != nr_ide_mem)) { 137 pci_info(pdev, "Unsupported Selective Stream %d capability, SKIP the rest\n", i); 138 nr_streams = i; 139 break; 140 } 141 142 nr_ide_mem = nr_assoc; 143 144 /* 145 * Claim Stream IDs and Selective Stream blocks that are already 146 * active on the device 147 */ 148 pci_read_config_dword(pdev, pos + PCI_IDE_SEL_CTL, &val); 149 id = FIELD_GET(PCI_IDE_SEL_CTL_ID, val); 150 if ((val & PCI_IDE_SEL_CTL_EN) && 151 !claim_stream(hb, id, pdev, i)) 152 return; 153 } 154 155 /* Reserve link stream-ids that are already active on the device */ 156 for (u16 i = 0; i < nr_link_ide; ++i) { 157 int pos = ide_cap + PCI_IDE_LINK_STREAM_0 + i * PCI_IDE_LINK_BLOCK_SIZE; 158 u8 id; 159 160 pci_read_config_dword(pdev, pos + PCI_IDE_LINK_CTL_0, &val); 161 id = FIELD_GET(PCI_IDE_LINK_CTL_ID, val); 162 if ((val & PCI_IDE_LINK_CTL_EN) && 163 !claim_stream(hb, id, NULL, -1)) 164 return; 165 } 166 167 for (u16 i = 0; i < nr_streams; i++) { 168 int pos = __sel_ide_offset(ide_cap, nr_link_ide, i, nr_ide_mem); 169 170 pci_read_config_dword(pdev, pos + PCI_IDE_SEL_CTL, &val); 171 if (val & PCI_IDE_SEL_CTL_EN) 172 continue; 173 FIELD_MODIFY(PCI_IDE_SEL_CTL_ID, &val, PCI_IDE_RESERVED_STREAM_ID); 174 pci_write_config_dword(pdev, pos + PCI_IDE_SEL_CTL, val); 175 } 176 177 for (u16 i = 0; i < nr_link_ide; ++i) { 178 int pos = ide_cap + PCI_IDE_LINK_STREAM_0 + 179 i * PCI_IDE_LINK_BLOCK_SIZE; 180 181 pci_read_config_dword(pdev, pos, &val); 182 if (val & PCI_IDE_LINK_CTL_EN) 183 continue; 184 FIELD_MODIFY(PCI_IDE_LINK_CTL_ID, &val, PCI_IDE_RESERVED_STREAM_ID); 185 pci_write_config_dword(pdev, pos, val); 186 } 187 188 pdev->ide_cap = ide_cap; 189 pdev->nr_link_ide = nr_link_ide; 190 pdev->nr_sel_ide = nr_streams; 191 pdev->nr_ide_mem = nr_ide_mem; 192 } 193 194 struct stream_index { 195 struct ida *ida; 196 u8 stream_index; 197 }; 198 199 static void free_stream_index(struct stream_index *stream) 200 { 201 ida_free(stream->ida, stream->stream_index); 202 } 203 204 DEFINE_FREE(free_stream, struct stream_index *, if (_T) free_stream_index(_T)) 205 static struct stream_index *alloc_stream_index(struct ida *ida, u16 max, 206 struct stream_index *stream) 207 { 208 int id; 209 210 if (!max) 211 return NULL; 212 213 id = ida_alloc_max(ida, max - 1, GFP_KERNEL); 214 if (id < 0) 215 return NULL; 216 217 *stream = (struct stream_index) { 218 .ida = ida, 219 .stream_index = id, 220 }; 221 return stream; 222 } 223 224 /** 225 * pci_ide_stream_alloc() - Reserve stream indices and probe for settings 226 * @pdev: IDE capable PCIe Endpoint Physical Function 227 * 228 * Retrieve the Requester ID range of @pdev for programming its Root 229 * Port IDE RID Association registers, and conversely retrieve the 230 * Requester ID of the Root Port for programming @pdev's IDE RID 231 * Association registers. 232 * 233 * Allocate a Selective IDE Stream Register Block instance per port. 234 * 235 * Allocate a platform stream resource from the associated host bridge. 236 * Retrieve stream association parameters for Requester ID range and 237 * address range restrictions for the stream. 238 */ 239 struct pci_ide *pci_ide_stream_alloc(struct pci_dev *pdev) 240 { 241 /* EP, RP, + HB Stream allocation */ 242 struct stream_index __stream[PCI_IDE_HB + 1]; 243 struct pci_bus_region pref_assoc = { 0, -1 }; 244 struct pci_bus_region mem_assoc = { 0, -1 }; 245 struct resource *mem, *pref; 246 struct pci_host_bridge *hb; 247 struct pci_dev *rp, *br; 248 int num_vf, rid_end; 249 250 if (!pci_is_pcie(pdev)) 251 return NULL; 252 253 if (pci_pcie_type(pdev) != PCI_EXP_TYPE_ENDPOINT) 254 return NULL; 255 256 if (!pdev->ide_cap) 257 return NULL; 258 259 struct pci_ide *ide __free(kfree) = kzalloc_obj(*ide); 260 if (!ide) 261 return NULL; 262 263 hb = pci_find_host_bridge(pdev->bus); 264 struct stream_index *hb_stream __free(free_stream) = alloc_stream_index( 265 &hb->ide_stream_ida, hb->nr_ide_streams, &__stream[PCI_IDE_HB]); 266 if (!hb_stream) 267 return NULL; 268 269 rp = pcie_find_root_port(pdev); 270 struct stream_index *rp_stream __free(free_stream) = alloc_stream_index( 271 &rp->ide_stream_ida, rp->nr_sel_ide, &__stream[PCI_IDE_RP]); 272 if (!rp_stream) 273 return NULL; 274 275 struct stream_index *ep_stream __free(free_stream) = alloc_stream_index( 276 &pdev->ide_stream_ida, pdev->nr_sel_ide, &__stream[PCI_IDE_EP]); 277 if (!ep_stream) 278 return NULL; 279 280 /* for SR-IOV case, cover all VFs */ 281 num_vf = pci_num_vf(pdev); 282 if (num_vf) 283 rid_end = PCI_DEVID(pci_iov_virtfn_bus(pdev, num_vf - 1), 284 pci_iov_virtfn_devfn(pdev, num_vf - 1)); 285 else 286 rid_end = pci_dev_id(pdev); 287 288 br = pci_upstream_bridge(pdev); 289 if (!br) 290 return NULL; 291 292 /* 293 * Check if the device consumes memory and/or prefetch-memory. Setup 294 * downstream address association ranges for each. 295 */ 296 mem = pci_resource_n(br, PCI_BRIDGE_MEM_WINDOW); 297 pref = pci_resource_n(br, PCI_BRIDGE_PREF_MEM_WINDOW); 298 if (resource_assigned(mem)) 299 pcibios_resource_to_bus(br->bus, &mem_assoc, mem); 300 if (resource_assigned(pref)) 301 pcibios_resource_to_bus(br->bus, &pref_assoc, pref); 302 303 *ide = (struct pci_ide) { 304 .pdev = pdev, 305 .partner = { 306 [PCI_IDE_EP] = { 307 .rid_start = pci_dev_id(rp), 308 .rid_end = pci_dev_id(rp), 309 .stream_index = no_free_ptr(ep_stream)->stream_index, 310 /* Disable upstream address association */ 311 .mem_assoc = { 0, -1 }, 312 .pref_assoc = { 0, -1 }, 313 }, 314 [PCI_IDE_RP] = { 315 .rid_start = pci_dev_id(pdev), 316 .rid_end = rid_end, 317 .stream_index = no_free_ptr(rp_stream)->stream_index, 318 .mem_assoc = mem_assoc, 319 .pref_assoc = pref_assoc, 320 }, 321 }, 322 .host_bridge_stream = no_free_ptr(hb_stream)->stream_index, 323 .stream_id = -1, 324 }; 325 326 return_ptr(ide); 327 } 328 EXPORT_SYMBOL_GPL(pci_ide_stream_alloc); 329 330 /** 331 * pci_ide_stream_free() - unwind pci_ide_stream_alloc() 332 * @ide: idle IDE settings descriptor 333 * 334 * Free all of the stream index (register block) allocations acquired by 335 * pci_ide_stream_alloc(). The stream represented by @ide is assumed to 336 * be unregistered and not instantiated in any device. 337 */ 338 void pci_ide_stream_free(struct pci_ide *ide) 339 { 340 struct pci_dev *pdev = ide->pdev; 341 struct pci_dev *rp = pcie_find_root_port(pdev); 342 struct pci_host_bridge *hb = pci_find_host_bridge(pdev->bus); 343 344 ida_free(&pdev->ide_stream_ida, ide->partner[PCI_IDE_EP].stream_index); 345 ida_free(&rp->ide_stream_ida, ide->partner[PCI_IDE_RP].stream_index); 346 ida_free(&hb->ide_stream_ida, ide->host_bridge_stream); 347 kfree(ide); 348 } 349 EXPORT_SYMBOL_GPL(pci_ide_stream_free); 350 351 /** 352 * pci_ide_stream_release() - unwind and release an @ide context 353 * @ide: partially or fully registered IDE settings descriptor 354 * 355 * In support of automatic cleanup of IDE setup routines perform IDE 356 * teardown in expected reverse order of setup and with respect to which 357 * aspects of IDE setup have successfully completed. 358 * 359 * Be careful that setup order mirrors this shutdown order. Otherwise, 360 * open code releasing the IDE context. 361 */ 362 void pci_ide_stream_release(struct pci_ide *ide) 363 { 364 struct pci_dev *pdev = ide->pdev; 365 struct pci_dev *rp = pcie_find_root_port(pdev); 366 367 if (ide->partner[PCI_IDE_RP].enable) 368 pci_ide_stream_disable(rp, ide); 369 370 if (ide->partner[PCI_IDE_EP].enable) 371 pci_ide_stream_disable(pdev, ide); 372 373 if (ide->partner[PCI_IDE_RP].setup) 374 pci_ide_stream_teardown(rp, ide); 375 376 if (ide->partner[PCI_IDE_EP].setup) 377 pci_ide_stream_teardown(pdev, ide); 378 379 if (ide->name) 380 pci_ide_stream_unregister(ide); 381 382 pci_ide_stream_free(ide); 383 } 384 EXPORT_SYMBOL_GPL(pci_ide_stream_release); 385 386 struct pci_ide_stream_id { 387 struct pci_host_bridge *hb; 388 u8 stream_id; 389 }; 390 391 static struct pci_ide_stream_id * 392 request_stream_id(struct pci_host_bridge *hb, u8 stream_id, 393 struct pci_ide_stream_id *sid) 394 { 395 if (!reserve_stream_id(hb, stream_id)) 396 return NULL; 397 398 *sid = (struct pci_ide_stream_id) { 399 .hb = hb, 400 .stream_id = stream_id, 401 }; 402 403 return sid; 404 } 405 DEFINE_FREE(free_stream_id, struct pci_ide_stream_id *, 406 if (_T) ida_free(&_T->hb->ide_stream_ids_ida, _T->stream_id)) 407 408 /** 409 * pci_ide_stream_register() - Prepare to activate an IDE Stream 410 * @ide: IDE settings descriptor 411 * 412 * After a Stream ID has been acquired for @ide, record the presence of 413 * the stream in sysfs. The expectation is that @ide is immutable while 414 * registered. 415 */ 416 int pci_ide_stream_register(struct pci_ide *ide) 417 { 418 struct pci_dev *pdev = ide->pdev; 419 struct pci_host_bridge *hb = pci_find_host_bridge(pdev->bus); 420 struct pci_ide_stream_id __sid; 421 u8 ep_stream, rp_stream; 422 int rc; 423 424 if (ide->stream_id < 0 || ide->stream_id > U8_MAX) { 425 pci_err(pdev, "Setup fail: Invalid Stream ID: %d\n", ide->stream_id); 426 return -ENXIO; 427 } 428 429 struct pci_ide_stream_id *sid __free(free_stream_id) = 430 request_stream_id(hb, ide->stream_id, &__sid); 431 if (!sid) { 432 pci_err(pdev, "Setup fail: Stream ID %d in use\n", ide->stream_id); 433 return -EBUSY; 434 } 435 436 ep_stream = ide->partner[PCI_IDE_EP].stream_index; 437 rp_stream = ide->partner[PCI_IDE_RP].stream_index; 438 const char *name __free(kfree) = kasprintf(GFP_KERNEL, "stream%d.%d.%d", 439 ide->host_bridge_stream, 440 rp_stream, ep_stream); 441 if (!name) 442 return -ENOMEM; 443 444 rc = sysfs_create_link(&hb->dev.kobj, &pdev->dev.kobj, name); 445 if (rc) 446 return rc; 447 448 ide->name = no_free_ptr(name); 449 450 /* Stream ID reservation recorded in @ide is now successfully registered */ 451 retain_and_null_ptr(sid); 452 453 return 0; 454 } 455 EXPORT_SYMBOL_GPL(pci_ide_stream_register); 456 457 /** 458 * pci_ide_stream_unregister() - unwind pci_ide_stream_register() 459 * @ide: idle IDE settings descriptor 460 * 461 * In preparation for freeing @ide, remove sysfs enumeration for the 462 * stream. 463 */ 464 void pci_ide_stream_unregister(struct pci_ide *ide) 465 { 466 struct pci_dev *pdev = ide->pdev; 467 struct pci_host_bridge *hb = pci_find_host_bridge(pdev->bus); 468 469 sysfs_remove_link(&hb->dev.kobj, ide->name); 470 kfree(ide->name); 471 ida_free(&hb->ide_stream_ids_ida, ide->stream_id); 472 ide->name = NULL; 473 } 474 EXPORT_SYMBOL_GPL(pci_ide_stream_unregister); 475 476 static int pci_ide_domain(struct pci_dev *pdev) 477 { 478 if (pdev->fm_enabled) 479 return pci_domain_nr(pdev->bus); 480 return 0; 481 } 482 483 struct pci_ide_partner *pci_ide_to_settings(struct pci_dev *pdev, struct pci_ide *ide) 484 { 485 if (!pci_is_pcie(pdev)) { 486 pci_warn_once(pdev, "not a PCIe device\n"); 487 return NULL; 488 } 489 490 switch (pci_pcie_type(pdev)) { 491 case PCI_EXP_TYPE_ENDPOINT: 492 if (pdev != ide->pdev) { 493 pci_warn_once(pdev, "setup expected Endpoint: %s\n", pci_name(ide->pdev)); 494 return NULL; 495 } 496 return &ide->partner[PCI_IDE_EP]; 497 case PCI_EXP_TYPE_ROOT_PORT: { 498 struct pci_dev *rp = pcie_find_root_port(ide->pdev); 499 500 if (pdev != rp) { 501 pci_warn_once(pdev, "setup expected Root Port: %s\n", 502 pci_name(rp)); 503 return NULL; 504 } 505 return &ide->partner[PCI_IDE_RP]; 506 } 507 default: 508 pci_warn_once(pdev, "invalid device type\n"); 509 return NULL; 510 } 511 } 512 EXPORT_SYMBOL_GPL(pci_ide_to_settings); 513 514 static void set_ide_sel_ctl(struct pci_dev *pdev, struct pci_ide *ide, 515 struct pci_ide_partner *settings, int pos, 516 bool enable) 517 { 518 u32 val = FIELD_PREP(PCI_IDE_SEL_CTL_ID, ide->stream_id) | 519 FIELD_PREP(PCI_IDE_SEL_CTL_DEFAULT, settings->default_stream) | 520 FIELD_PREP(PCI_IDE_SEL_CTL_CFG_EN, pdev->ide_cfg) | 521 FIELD_PREP(PCI_IDE_SEL_CTL_TEE_LIMITED, pdev->ide_tee_limit) | 522 FIELD_PREP(PCI_IDE_SEL_CTL_EN, enable); 523 524 pci_write_config_dword(pdev, pos + PCI_IDE_SEL_CTL, val); 525 } 526 527 #define SEL_ADDR1_LOWER GENMASK(31, 20) 528 #define SEL_ADDR_UPPER GENMASK_ULL(63, 32) 529 #define PREP_PCI_IDE_SEL_ADDR1(base, limit) \ 530 (FIELD_PREP(PCI_IDE_SEL_ADDR_1_VALID, 1) | \ 531 FIELD_PREP(PCI_IDE_SEL_ADDR_1_BASE_LOW, \ 532 FIELD_GET(SEL_ADDR1_LOWER, (base))) | \ 533 FIELD_PREP(PCI_IDE_SEL_ADDR_1_LIMIT_LOW, \ 534 FIELD_GET(SEL_ADDR1_LOWER, (limit)))) 535 536 static void mem_assoc_to_regs(struct pci_bus_region *region, 537 struct pci_ide_regs *regs, int idx) 538 { 539 /* convert to u64 range for bitfield size checks */ 540 struct range r = { region->start, region->end }; 541 542 regs->addr[idx].assoc1 = PREP_PCI_IDE_SEL_ADDR1(r.start, r.end); 543 regs->addr[idx].assoc2 = FIELD_GET(SEL_ADDR_UPPER, r.end); 544 regs->addr[idx].assoc3 = FIELD_GET(SEL_ADDR_UPPER, r.start); 545 } 546 547 /** 548 * pci_ide_stream_to_regs() - convert IDE settings to association register values 549 * @pdev: PCIe device object for either a Root Port or Endpoint Partner Port 550 * @ide: registered IDE settings descriptor 551 * @regs: output register values 552 */ 553 static void pci_ide_stream_to_regs(struct pci_dev *pdev, struct pci_ide *ide, 554 struct pci_ide_regs *regs) 555 { 556 struct pci_ide_partner *settings = pci_ide_to_settings(pdev, ide); 557 int assoc_idx = 0; 558 559 memset(regs, 0, sizeof(*regs)); 560 561 if (!settings) 562 return; 563 564 regs->rid1 = FIELD_PREP(PCI_IDE_SEL_RID_1_LIMIT, settings->rid_end); 565 566 regs->rid2 = FIELD_PREP(PCI_IDE_SEL_RID_2_VALID, 1) | 567 FIELD_PREP(PCI_IDE_SEL_RID_2_BASE, settings->rid_start) | 568 FIELD_PREP(PCI_IDE_SEL_RID_2_SEG, pci_ide_domain(pdev)); 569 570 if (pdev->nr_ide_mem && pci_bus_region_size(&settings->mem_assoc)) { 571 mem_assoc_to_regs(&settings->mem_assoc, regs, assoc_idx); 572 assoc_idx++; 573 } 574 575 if (pdev->nr_ide_mem > assoc_idx && 576 pci_bus_region_size(&settings->pref_assoc)) { 577 mem_assoc_to_regs(&settings->pref_assoc, regs, assoc_idx); 578 assoc_idx++; 579 } 580 581 regs->nr_addr = assoc_idx; 582 } 583 584 /** 585 * pci_ide_stream_setup() - program settings to Selective IDE Stream registers 586 * @pdev: PCIe device object for either a Root Port or Endpoint Partner Port 587 * @ide: registered IDE settings descriptor 588 * 589 * When @pdev is a PCI_EXP_TYPE_ENDPOINT then the PCI_IDE_EP partner 590 * settings are written to @pdev's Selective IDE Stream register block, 591 * and when @pdev is a PCI_EXP_TYPE_ROOT_PORT, the PCI_IDE_RP settings 592 * are selected. 593 */ 594 void pci_ide_stream_setup(struct pci_dev *pdev, struct pci_ide *ide) 595 { 596 struct pci_ide_partner *settings = pci_ide_to_settings(pdev, ide); 597 struct pci_ide_regs regs; 598 int pos; 599 600 if (!settings) 601 return; 602 603 pci_ide_stream_to_regs(pdev, ide, ®s); 604 605 pos = sel_ide_offset(pdev, settings); 606 607 pci_write_config_dword(pdev, pos + PCI_IDE_SEL_RID_1, regs.rid1); 608 pci_write_config_dword(pdev, pos + PCI_IDE_SEL_RID_2, regs.rid2); 609 610 for (int i = 0; i < regs.nr_addr; i++) { 611 pci_write_config_dword(pdev, pos + PCI_IDE_SEL_ADDR_1(i), 612 regs.addr[i].assoc1); 613 pci_write_config_dword(pdev, pos + PCI_IDE_SEL_ADDR_2(i), 614 regs.addr[i].assoc2); 615 pci_write_config_dword(pdev, pos + PCI_IDE_SEL_ADDR_3(i), 616 regs.addr[i].assoc3); 617 } 618 619 /* clear extra unused address association blocks */ 620 for (int i = regs.nr_addr; i < pdev->nr_ide_mem; i++) { 621 pci_write_config_dword(pdev, pos + PCI_IDE_SEL_ADDR_1(i), 0); 622 pci_write_config_dword(pdev, pos + PCI_IDE_SEL_ADDR_2(i), 0); 623 pci_write_config_dword(pdev, pos + PCI_IDE_SEL_ADDR_3(i), 0); 624 } 625 626 /* 627 * Setup control register early for devices that expect 628 * stream_id is set during key programming. 629 */ 630 set_ide_sel_ctl(pdev, ide, settings, pos, false); 631 settings->setup = 1; 632 } 633 EXPORT_SYMBOL_GPL(pci_ide_stream_setup); 634 635 /** 636 * pci_ide_stream_teardown() - disable the stream and clear all settings 637 * @pdev: PCIe device object for either a Root Port or Endpoint Partner Port 638 * @ide: registered IDE settings descriptor 639 * 640 * For stream destruction, zero all registers that may have been written 641 * by pci_ide_stream_setup(). Consider pci_ide_stream_disable() to leave 642 * settings in place while temporarily disabling the stream. 643 */ 644 void pci_ide_stream_teardown(struct pci_dev *pdev, struct pci_ide *ide) 645 { 646 struct pci_ide_partner *settings = pci_ide_to_settings(pdev, ide); 647 int pos, i; 648 649 if (!settings) 650 return; 651 652 pos = sel_ide_offset(pdev, settings); 653 654 pci_write_config_dword(pdev, pos + PCI_IDE_SEL_CTL, 0); 655 656 for (i = 0; i < pdev->nr_ide_mem; i++) { 657 pci_write_config_dword(pdev, pos + PCI_IDE_SEL_ADDR_1(i), 0); 658 pci_write_config_dword(pdev, pos + PCI_IDE_SEL_ADDR_2(i), 0); 659 pci_write_config_dword(pdev, pos + PCI_IDE_SEL_ADDR_3(i), 0); 660 } 661 662 pci_write_config_dword(pdev, pos + PCI_IDE_SEL_RID_2, 0); 663 pci_write_config_dword(pdev, pos + PCI_IDE_SEL_RID_1, 0); 664 settings->setup = 0; 665 } 666 EXPORT_SYMBOL_GPL(pci_ide_stream_teardown); 667 668 /** 669 * pci_ide_stream_enable() - enable a Selective IDE Stream 670 * @pdev: PCIe device object for either a Root Port or Endpoint Partner Port 671 * @ide: registered and setup IDE settings descriptor 672 * 673 * Activate the stream by writing to the Selective IDE Stream Control 674 * Register. 675 * 676 * Return: 0 if the stream successfully entered the "secure" state, and -EINVAL 677 * if @ide is invalid, and -ENXIO if the stream fails to enter the secure state. 678 * 679 * Note that the state may go "insecure" at any point after returning 0, but 680 * those events are equivalent to a "link down" event and handled via 681 * asynchronous error reporting. 682 * 683 * Caller is responsible to clear the enable bit in the -ENXIO case. 684 */ 685 int pci_ide_stream_enable(struct pci_dev *pdev, struct pci_ide *ide) 686 { 687 struct pci_ide_partner *settings = pci_ide_to_settings(pdev, ide); 688 int pos; 689 u32 val; 690 691 if (!settings) 692 return -EINVAL; 693 694 pos = sel_ide_offset(pdev, settings); 695 696 set_ide_sel_ctl(pdev, ide, settings, pos, true); 697 settings->enable = 1; 698 699 pci_read_config_dword(pdev, pos + PCI_IDE_SEL_STS, &val); 700 if (FIELD_GET(PCI_IDE_SEL_STS_STATE, val) != 701 PCI_IDE_SEL_STS_STATE_SECURE) 702 return -ENXIO; 703 704 return 0; 705 } 706 EXPORT_SYMBOL_GPL(pci_ide_stream_enable); 707 708 /** 709 * pci_ide_stream_disable() - disable a Selective IDE Stream 710 * @pdev: PCIe device object for either a Root Port or Endpoint Partner Port 711 * @ide: registered and setup IDE settings descriptor 712 * 713 * Clear the Selective IDE Stream Control Register, but leave all other 714 * registers untouched. 715 */ 716 void pci_ide_stream_disable(struct pci_dev *pdev, struct pci_ide *ide) 717 { 718 struct pci_ide_partner *settings = pci_ide_to_settings(pdev, ide); 719 int pos; 720 721 if (!settings) 722 return; 723 724 pos = sel_ide_offset(pdev, settings); 725 726 pci_write_config_dword(pdev, pos + PCI_IDE_SEL_CTL, 0); 727 settings->enable = 0; 728 } 729 EXPORT_SYMBOL_GPL(pci_ide_stream_disable); 730 731 void pci_ide_init_host_bridge(struct pci_host_bridge *hb) 732 { 733 hb->nr_ide_streams = 256; 734 ida_init(&hb->ide_stream_ida); 735 ida_init(&hb->ide_stream_ids_ida); 736 reserve_stream_id(hb, PCI_IDE_RESERVED_STREAM_ID); 737 } 738 739 static ssize_t available_secure_streams_show(struct device *dev, 740 struct device_attribute *attr, 741 char *buf) 742 { 743 struct pci_host_bridge *hb = to_pci_host_bridge(dev); 744 int nr = READ_ONCE(hb->nr_ide_streams); 745 int avail = nr; 746 747 if (!nr) 748 return -ENXIO; 749 750 /* 751 * Yes, this is inefficient and racy, but it is only for occasional 752 * platform resource surveys. Worst case is bounded to 256 streams. 753 */ 754 for (int i = 0; i < nr; i++) 755 if (ida_exists(&hb->ide_stream_ida, i)) 756 avail--; 757 return sysfs_emit(buf, "%d\n", avail); 758 } 759 static DEVICE_ATTR_RO(available_secure_streams); 760 761 static struct attribute *pci_ide_attrs[] = { 762 &dev_attr_available_secure_streams.attr, 763 NULL 764 }; 765 766 static umode_t pci_ide_attr_visible(struct kobject *kobj, struct attribute *a, int n) 767 { 768 struct device *dev = kobj_to_dev(kobj); 769 struct pci_host_bridge *hb = to_pci_host_bridge(dev); 770 771 if (a == &dev_attr_available_secure_streams.attr) 772 if (!hb->nr_ide_streams) 773 return 0; 774 775 return a->mode; 776 } 777 778 const struct attribute_group pci_ide_attr_group = { 779 .attrs = pci_ide_attrs, 780 .is_visible = pci_ide_attr_visible, 781 }; 782 783 /** 784 * pci_ide_set_nr_streams() - sets size of the pool of IDE Stream resources 785 * @hb: host bridge boundary for the stream pool 786 * @nr: number of streams 787 * 788 * Platform PCI init and/or expert test module use only. Limit IDE 789 * Stream establishment by setting the number of stream resources 790 * available at the host bridge. Platform init code must set this before 791 * the first pci_ide_stream_alloc() call if the platform has less than the 792 * default of 256 streams per host-bridge. 793 * 794 * The "PCI_IDE" symbol namespace is required because this is typically 795 * a detail that is settled in early PCI init. I.e. this export is not 796 * for endpoint drivers. 797 */ 798 void pci_ide_set_nr_streams(struct pci_host_bridge *hb, u16 nr) 799 { 800 hb->nr_ide_streams = min(nr, 256); 801 WARN_ON_ONCE(!ida_is_empty(&hb->ide_stream_ida)); 802 sysfs_update_group(&hb->dev.kobj, &pci_ide_attr_group); 803 } 804 EXPORT_SYMBOL_NS_GPL(pci_ide_set_nr_streams, "PCI_IDE"); 805 806 void pci_ide_destroy(struct pci_dev *pdev) 807 { 808 ida_destroy(&pdev->ide_stream_ida); 809 } 810