1 /* 2 * Standard PCI Hot Plug Driver 3 * 4 * Copyright (C) 1995,2001 Compaq Computer Corporation 5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com) 6 * Copyright (C) 2001 IBM Corp. 7 * Copyright (C) 2003-2004 Intel Corporation 8 * 9 * All rights reserved. 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or (at 14 * your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 19 * NON INFRINGEMENT. See the GNU General Public License for more 20 * details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 25 * 26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com> 27 * 28 */ 29 30 #include <linux/kernel.h> 31 #include <linux/module.h> 32 #include <linux/types.h> 33 #include <linux/pci.h> 34 #include <linux/interrupt.h> 35 36 #include "shpchp.h" 37 38 /* Slot Available Register I field definition */ 39 #define SLOT_33MHZ 0x0000001f 40 #define SLOT_66MHZ_PCIX 0x00001f00 41 #define SLOT_100MHZ_PCIX 0x001f0000 42 #define SLOT_133MHZ_PCIX 0x1f000000 43 44 /* Slot Available Register II field definition */ 45 #define SLOT_66MHZ 0x0000001f 46 #define SLOT_66MHZ_PCIX_266 0x00000f00 47 #define SLOT_100MHZ_PCIX_266 0x0000f000 48 #define SLOT_133MHZ_PCIX_266 0x000f0000 49 #define SLOT_66MHZ_PCIX_533 0x00f00000 50 #define SLOT_100MHZ_PCIX_533 0x0f000000 51 #define SLOT_133MHZ_PCIX_533 0xf0000000 52 53 /* Slot Configuration */ 54 #define SLOT_NUM 0x0000001F 55 #define FIRST_DEV_NUM 0x00001F00 56 #define PSN 0x07FF0000 57 #define UPDOWN 0x20000000 58 #define MRLSENSOR 0x40000000 59 #define ATTN_BUTTON 0x80000000 60 61 /* 62 * Interrupt Locator Register definitions 63 */ 64 #define CMD_INTR_PENDING (1 << 0) 65 #define SLOT_INTR_PENDING(i) (1 << (i + 1)) 66 67 /* 68 * Controller SERR-INT Register 69 */ 70 #define GLOBAL_INTR_MASK (1 << 0) 71 #define GLOBAL_SERR_MASK (1 << 1) 72 #define COMMAND_INTR_MASK (1 << 2) 73 #define ARBITER_SERR_MASK (1 << 3) 74 #define COMMAND_DETECTED (1 << 16) 75 #define ARBITER_DETECTED (1 << 17) 76 #define SERR_INTR_RSVDZ_MASK 0xfffc0000 77 78 /* 79 * Logical Slot Register definitions 80 */ 81 #define SLOT_REG(i) (SLOT1 + (4 * i)) 82 83 #define SLOT_STATE_SHIFT (0) 84 #define SLOT_STATE_MASK (3 << 0) 85 #define SLOT_STATE_PWRONLY (1) 86 #define SLOT_STATE_ENABLED (2) 87 #define SLOT_STATE_DISABLED (3) 88 #define PWR_LED_STATE_SHIFT (2) 89 #define PWR_LED_STATE_MASK (3 << 2) 90 #define ATN_LED_STATE_SHIFT (4) 91 #define ATN_LED_STATE_MASK (3 << 4) 92 #define ATN_LED_STATE_ON (1) 93 #define ATN_LED_STATE_BLINK (2) 94 #define ATN_LED_STATE_OFF (3) 95 #define POWER_FAULT (1 << 6) 96 #define ATN_BUTTON (1 << 7) 97 #define MRL_SENSOR (1 << 8) 98 #define MHZ66_CAP (1 << 9) 99 #define PRSNT_SHIFT (10) 100 #define PRSNT_MASK (3 << 10) 101 #define PCIX_CAP_SHIFT (12) 102 #define PCIX_CAP_MASK_PI1 (3 << 12) 103 #define PCIX_CAP_MASK_PI2 (7 << 12) 104 #define PRSNT_CHANGE_DETECTED (1 << 16) 105 #define ISO_PFAULT_DETECTED (1 << 17) 106 #define BUTTON_PRESS_DETECTED (1 << 18) 107 #define MRL_CHANGE_DETECTED (1 << 19) 108 #define CON_PFAULT_DETECTED (1 << 20) 109 #define PRSNT_CHANGE_INTR_MASK (1 << 24) 110 #define ISO_PFAULT_INTR_MASK (1 << 25) 111 #define BUTTON_PRESS_INTR_MASK (1 << 26) 112 #define MRL_CHANGE_INTR_MASK (1 << 27) 113 #define CON_PFAULT_INTR_MASK (1 << 28) 114 #define MRL_CHANGE_SERR_MASK (1 << 29) 115 #define CON_PFAULT_SERR_MASK (1 << 30) 116 #define SLOT_REG_RSVDZ_MASK ((1 << 15) | (7 << 21)) 117 118 /* 119 * SHPC Command Code definitnions 120 * 121 * Slot Operation 00h - 3Fh 122 * Set Bus Segment Speed/Mode A 40h - 47h 123 * Power-Only All Slots 48h 124 * Enable All Slots 49h 125 * Set Bus Segment Speed/Mode B (PI=2) 50h - 5Fh 126 * Reserved Command Codes 60h - BFh 127 * Vendor Specific Commands C0h - FFh 128 */ 129 #define SET_SLOT_PWR 0x01 /* Slot Operation */ 130 #define SET_SLOT_ENABLE 0x02 131 #define SET_SLOT_DISABLE 0x03 132 #define SET_PWR_ON 0x04 133 #define SET_PWR_BLINK 0x08 134 #define SET_PWR_OFF 0x0c 135 #define SET_ATTN_ON 0x10 136 #define SET_ATTN_BLINK 0x20 137 #define SET_ATTN_OFF 0x30 138 #define SETA_PCI_33MHZ 0x40 /* Set Bus Segment Speed/Mode A */ 139 #define SETA_PCI_66MHZ 0x41 140 #define SETA_PCIX_66MHZ 0x42 141 #define SETA_PCIX_100MHZ 0x43 142 #define SETA_PCIX_133MHZ 0x44 143 #define SETA_RESERVED1 0x45 144 #define SETA_RESERVED2 0x46 145 #define SETA_RESERVED3 0x47 146 #define SET_PWR_ONLY_ALL 0x48 /* Power-Only All Slots */ 147 #define SET_ENABLE_ALL 0x49 /* Enable All Slots */ 148 #define SETB_PCI_33MHZ 0x50 /* Set Bus Segment Speed/Mode B */ 149 #define SETB_PCI_66MHZ 0x51 150 #define SETB_PCIX_66MHZ_PM 0x52 151 #define SETB_PCIX_100MHZ_PM 0x53 152 #define SETB_PCIX_133MHZ_PM 0x54 153 #define SETB_PCIX_66MHZ_EM 0x55 154 #define SETB_PCIX_100MHZ_EM 0x56 155 #define SETB_PCIX_133MHZ_EM 0x57 156 #define SETB_PCIX_66MHZ_266 0x58 157 #define SETB_PCIX_100MHZ_266 0x59 158 #define SETB_PCIX_133MHZ_266 0x5a 159 #define SETB_PCIX_66MHZ_533 0x5b 160 #define SETB_PCIX_100MHZ_533 0x5c 161 #define SETB_PCIX_133MHZ_533 0x5d 162 #define SETB_RESERVED1 0x5e 163 #define SETB_RESERVED2 0x5f 164 165 /* 166 * SHPC controller command error code 167 */ 168 #define SWITCH_OPEN 0x1 169 #define INVALID_CMD 0x2 170 #define INVALID_SPEED_MODE 0x4 171 172 /* 173 * For accessing SHPC Working Register Set via PCI Configuration Space 174 */ 175 #define DWORD_SELECT 0x2 176 #define DWORD_DATA 0x4 177 178 /* Field Offset in Logical Slot Register - byte boundary */ 179 #define SLOT_EVENT_LATCH 0x2 180 #define SLOT_SERR_INT_MASK 0x3 181 182 static atomic_t shpchp_num_controllers = ATOMIC_INIT(0); 183 184 static irqreturn_t shpc_isr(int irq, void *dev_id); 185 static void start_int_poll_timer(struct controller *ctrl, int sec); 186 static int hpc_check_cmd_status(struct controller *ctrl); 187 188 static inline u8 shpc_readb(struct controller *ctrl, int reg) 189 { 190 return readb(ctrl->creg + reg); 191 } 192 193 static inline void shpc_writeb(struct controller *ctrl, int reg, u8 val) 194 { 195 writeb(val, ctrl->creg + reg); 196 } 197 198 static inline u16 shpc_readw(struct controller *ctrl, int reg) 199 { 200 return readw(ctrl->creg + reg); 201 } 202 203 static inline void shpc_writew(struct controller *ctrl, int reg, u16 val) 204 { 205 writew(val, ctrl->creg + reg); 206 } 207 208 static inline u32 shpc_readl(struct controller *ctrl, int reg) 209 { 210 return readl(ctrl->creg + reg); 211 } 212 213 static inline void shpc_writel(struct controller *ctrl, int reg, u32 val) 214 { 215 writel(val, ctrl->creg + reg); 216 } 217 218 static inline int shpc_indirect_read(struct controller *ctrl, int index, 219 u32 *value) 220 { 221 int rc; 222 u32 cap_offset = ctrl->cap_offset; 223 struct pci_dev *pdev = ctrl->pci_dev; 224 225 rc = pci_write_config_byte(pdev, cap_offset + DWORD_SELECT, index); 226 if (rc) 227 return rc; 228 return pci_read_config_dword(pdev, cap_offset + DWORD_DATA, value); 229 } 230 231 /* 232 * This is the interrupt polling timeout function. 233 */ 234 static void int_poll_timeout(unsigned long data) 235 { 236 struct controller *ctrl = (struct controller *)data; 237 238 /* Poll for interrupt events. regs == NULL => polling */ 239 shpc_isr(0, ctrl); 240 241 init_timer(&ctrl->poll_timer); 242 if (!shpchp_poll_time) 243 shpchp_poll_time = 2; /* default polling interval is 2 sec */ 244 245 start_int_poll_timer(ctrl, shpchp_poll_time); 246 } 247 248 /* 249 * This function starts the interrupt polling timer. 250 */ 251 static void start_int_poll_timer(struct controller *ctrl, int sec) 252 { 253 /* Clamp to sane value */ 254 if ((sec <= 0) || (sec > 60)) 255 sec = 2; 256 257 ctrl->poll_timer.function = &int_poll_timeout; 258 ctrl->poll_timer.data = (unsigned long)ctrl; 259 ctrl->poll_timer.expires = jiffies + sec * HZ; 260 add_timer(&ctrl->poll_timer); 261 } 262 263 static inline int is_ctrl_busy(struct controller *ctrl) 264 { 265 u16 cmd_status = shpc_readw(ctrl, CMD_STATUS); 266 return cmd_status & 0x1; 267 } 268 269 /* 270 * Returns 1 if SHPC finishes executing a command within 1 sec, 271 * otherwise returns 0. 272 */ 273 static inline int shpc_poll_ctrl_busy(struct controller *ctrl) 274 { 275 int i; 276 277 if (!is_ctrl_busy(ctrl)) 278 return 1; 279 280 /* Check every 0.1 sec for a total of 1 sec */ 281 for (i = 0; i < 10; i++) { 282 msleep(100); 283 if (!is_ctrl_busy(ctrl)) 284 return 1; 285 } 286 287 return 0; 288 } 289 290 static inline int shpc_wait_cmd(struct controller *ctrl) 291 { 292 int retval = 0; 293 unsigned long timeout = msecs_to_jiffies(1000); 294 int rc; 295 296 if (shpchp_poll_mode) 297 rc = shpc_poll_ctrl_busy(ctrl); 298 else 299 rc = wait_event_interruptible_timeout(ctrl->queue, 300 !is_ctrl_busy(ctrl), timeout); 301 if (!rc && is_ctrl_busy(ctrl)) { 302 retval = -EIO; 303 ctrl_err(ctrl, "Command not completed in 1000 msec\n"); 304 } else if (rc < 0) { 305 retval = -EINTR; 306 ctrl_info(ctrl, "Command was interrupted by a signal\n"); 307 } 308 309 return retval; 310 } 311 312 static int shpc_write_cmd(struct slot *slot, u8 t_slot, u8 cmd) 313 { 314 struct controller *ctrl = slot->ctrl; 315 u16 cmd_status; 316 int retval = 0; 317 u16 temp_word; 318 319 mutex_lock(&slot->ctrl->cmd_lock); 320 321 if (!shpc_poll_ctrl_busy(ctrl)) { 322 /* After 1 sec and and the controller is still busy */ 323 ctrl_err(ctrl, "Controller is still busy after 1 sec\n"); 324 retval = -EBUSY; 325 goto out; 326 } 327 328 ++t_slot; 329 temp_word = (t_slot << 8) | (cmd & 0xFF); 330 ctrl_dbg(ctrl, "%s: t_slot %x cmd %x\n", __func__, t_slot, cmd); 331 332 /* To make sure the Controller Busy bit is 0 before we send out the 333 * command. 334 */ 335 shpc_writew(ctrl, CMD, temp_word); 336 337 /* 338 * Wait for command completion. 339 */ 340 retval = shpc_wait_cmd(slot->ctrl); 341 if (retval) 342 goto out; 343 344 cmd_status = hpc_check_cmd_status(slot->ctrl); 345 if (cmd_status) { 346 ctrl_err(ctrl, 347 "Failed to issued command 0x%x (error code = %d)\n", 348 cmd, cmd_status); 349 retval = -EIO; 350 } 351 out: 352 mutex_unlock(&slot->ctrl->cmd_lock); 353 return retval; 354 } 355 356 static int hpc_check_cmd_status(struct controller *ctrl) 357 { 358 int retval = 0; 359 u16 cmd_status = shpc_readw(ctrl, CMD_STATUS) & 0x000F; 360 361 switch (cmd_status >> 1) { 362 case 0: 363 retval = 0; 364 break; 365 case 1: 366 retval = SWITCH_OPEN; 367 ctrl_err(ctrl, "Switch opened!\n"); 368 break; 369 case 2: 370 retval = INVALID_CMD; 371 ctrl_err(ctrl, "Invalid HPC command!\n"); 372 break; 373 case 4: 374 retval = INVALID_SPEED_MODE; 375 ctrl_err(ctrl, "Invalid bus speed/mode!\n"); 376 break; 377 default: 378 retval = cmd_status; 379 } 380 381 return retval; 382 } 383 384 385 static int hpc_get_attention_status(struct slot *slot, u8 *status) 386 { 387 struct controller *ctrl = slot->ctrl; 388 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); 389 u8 state = (slot_reg & ATN_LED_STATE_MASK) >> ATN_LED_STATE_SHIFT; 390 391 switch (state) { 392 case ATN_LED_STATE_ON: 393 *status = 1; /* On */ 394 break; 395 case ATN_LED_STATE_BLINK: 396 *status = 2; /* Blink */ 397 break; 398 case ATN_LED_STATE_OFF: 399 *status = 0; /* Off */ 400 break; 401 default: 402 *status = 0xFF; /* Reserved */ 403 break; 404 } 405 406 return 0; 407 } 408 409 static int hpc_get_power_status(struct slot * slot, u8 *status) 410 { 411 struct controller *ctrl = slot->ctrl; 412 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); 413 u8 state = (slot_reg & SLOT_STATE_MASK) >> SLOT_STATE_SHIFT; 414 415 switch (state) { 416 case SLOT_STATE_PWRONLY: 417 *status = 2; /* Powered only */ 418 break; 419 case SLOT_STATE_ENABLED: 420 *status = 1; /* Enabled */ 421 break; 422 case SLOT_STATE_DISABLED: 423 *status = 0; /* Disabled */ 424 break; 425 default: 426 *status = 0xFF; /* Reserved */ 427 break; 428 } 429 430 return 0; 431 } 432 433 434 static int hpc_get_latch_status(struct slot *slot, u8 *status) 435 { 436 struct controller *ctrl = slot->ctrl; 437 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); 438 439 *status = !!(slot_reg & MRL_SENSOR); /* 0 -> close; 1 -> open */ 440 441 return 0; 442 } 443 444 static int hpc_get_adapter_status(struct slot *slot, u8 *status) 445 { 446 struct controller *ctrl = slot->ctrl; 447 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); 448 u8 state = (slot_reg & PRSNT_MASK) >> PRSNT_SHIFT; 449 450 *status = (state != 0x3) ? 1 : 0; 451 452 return 0; 453 } 454 455 static int hpc_get_prog_int(struct slot *slot, u8 *prog_int) 456 { 457 struct controller *ctrl = slot->ctrl; 458 459 *prog_int = shpc_readb(ctrl, PROG_INTERFACE); 460 461 return 0; 462 } 463 464 static int hpc_get_adapter_speed(struct slot *slot, enum pci_bus_speed *value) 465 { 466 int retval = 0; 467 struct controller *ctrl = slot->ctrl; 468 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); 469 u8 m66_cap = !!(slot_reg & MHZ66_CAP); 470 u8 pi, pcix_cap; 471 472 if ((retval = hpc_get_prog_int(slot, &pi))) 473 return retval; 474 475 switch (pi) { 476 case 1: 477 pcix_cap = (slot_reg & PCIX_CAP_MASK_PI1) >> PCIX_CAP_SHIFT; 478 break; 479 case 2: 480 pcix_cap = (slot_reg & PCIX_CAP_MASK_PI2) >> PCIX_CAP_SHIFT; 481 break; 482 default: 483 return -ENODEV; 484 } 485 486 ctrl_dbg(ctrl, "%s: slot_reg = %x, pcix_cap = %x, m66_cap = %x\n", 487 __func__, slot_reg, pcix_cap, m66_cap); 488 489 switch (pcix_cap) { 490 case 0x0: 491 *value = m66_cap ? PCI_SPEED_66MHz : PCI_SPEED_33MHz; 492 break; 493 case 0x1: 494 *value = PCI_SPEED_66MHz_PCIX; 495 break; 496 case 0x3: 497 *value = PCI_SPEED_133MHz_PCIX; 498 break; 499 case 0x4: 500 *value = PCI_SPEED_133MHz_PCIX_266; 501 break; 502 case 0x5: 503 *value = PCI_SPEED_133MHz_PCIX_533; 504 break; 505 case 0x2: 506 default: 507 *value = PCI_SPEED_UNKNOWN; 508 retval = -ENODEV; 509 break; 510 } 511 512 ctrl_dbg(ctrl, "Adapter speed = %d\n", *value); 513 return retval; 514 } 515 516 static int hpc_get_mode1_ECC_cap(struct slot *slot, u8 *mode) 517 { 518 int retval = 0; 519 struct controller *ctrl = slot->ctrl; 520 u16 sec_bus_status = shpc_readw(ctrl, SEC_BUS_CONFIG); 521 u8 pi = shpc_readb(ctrl, PROG_INTERFACE); 522 523 if (pi == 2) { 524 *mode = (sec_bus_status & 0x0100) >> 8; 525 } else { 526 retval = -1; 527 } 528 529 ctrl_dbg(ctrl, "Mode 1 ECC cap = %d\n", *mode); 530 return retval; 531 } 532 533 static int hpc_query_power_fault(struct slot * slot) 534 { 535 struct controller *ctrl = slot->ctrl; 536 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); 537 538 /* Note: Logic 0 => fault */ 539 return !(slot_reg & POWER_FAULT); 540 } 541 542 static int hpc_set_attention_status(struct slot *slot, u8 value) 543 { 544 u8 slot_cmd = 0; 545 546 switch (value) { 547 case 0 : 548 slot_cmd = SET_ATTN_OFF; /* OFF */ 549 break; 550 case 1: 551 slot_cmd = SET_ATTN_ON; /* ON */ 552 break; 553 case 2: 554 slot_cmd = SET_ATTN_BLINK; /* BLINK */ 555 break; 556 default: 557 return -1; 558 } 559 560 return shpc_write_cmd(slot, slot->hp_slot, slot_cmd); 561 } 562 563 564 static void hpc_set_green_led_on(struct slot *slot) 565 { 566 shpc_write_cmd(slot, slot->hp_slot, SET_PWR_ON); 567 } 568 569 static void hpc_set_green_led_off(struct slot *slot) 570 { 571 shpc_write_cmd(slot, slot->hp_slot, SET_PWR_OFF); 572 } 573 574 static void hpc_set_green_led_blink(struct slot *slot) 575 { 576 shpc_write_cmd(slot, slot->hp_slot, SET_PWR_BLINK); 577 } 578 579 static void hpc_release_ctlr(struct controller *ctrl) 580 { 581 int i; 582 u32 slot_reg, serr_int; 583 584 /* 585 * Mask event interrupts and SERRs of all slots 586 */ 587 for (i = 0; i < ctrl->num_slots; i++) { 588 slot_reg = shpc_readl(ctrl, SLOT_REG(i)); 589 slot_reg |= (PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK | 590 BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK | 591 CON_PFAULT_INTR_MASK | MRL_CHANGE_SERR_MASK | 592 CON_PFAULT_SERR_MASK); 593 slot_reg &= ~SLOT_REG_RSVDZ_MASK; 594 shpc_writel(ctrl, SLOT_REG(i), slot_reg); 595 } 596 597 cleanup_slots(ctrl); 598 599 /* 600 * Mask SERR and System Interrupt generation 601 */ 602 serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE); 603 serr_int |= (GLOBAL_INTR_MASK | GLOBAL_SERR_MASK | 604 COMMAND_INTR_MASK | ARBITER_SERR_MASK); 605 serr_int &= ~SERR_INTR_RSVDZ_MASK; 606 shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int); 607 608 if (shpchp_poll_mode) 609 del_timer(&ctrl->poll_timer); 610 else { 611 free_irq(ctrl->pci_dev->irq, ctrl); 612 pci_disable_msi(ctrl->pci_dev); 613 } 614 615 iounmap(ctrl->creg); 616 release_mem_region(ctrl->mmio_base, ctrl->mmio_size); 617 618 /* 619 * If this is the last controller to be released, destroy the 620 * shpchpd work queue 621 */ 622 if (atomic_dec_and_test(&shpchp_num_controllers)) 623 destroy_workqueue(shpchp_wq); 624 } 625 626 static int hpc_power_on_slot(struct slot * slot) 627 { 628 int retval; 629 630 retval = shpc_write_cmd(slot, slot->hp_slot, SET_SLOT_PWR); 631 if (retval) 632 ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__); 633 634 return retval; 635 } 636 637 static int hpc_slot_enable(struct slot * slot) 638 { 639 int retval; 640 641 /* Slot - Enable, Power Indicator - Blink, Attention Indicator - Off */ 642 retval = shpc_write_cmd(slot, slot->hp_slot, 643 SET_SLOT_ENABLE | SET_PWR_BLINK | SET_ATTN_OFF); 644 if (retval) 645 ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__); 646 647 return retval; 648 } 649 650 static int hpc_slot_disable(struct slot * slot) 651 { 652 int retval; 653 654 /* Slot - Disable, Power Indicator - Off, Attention Indicator - On */ 655 retval = shpc_write_cmd(slot, slot->hp_slot, 656 SET_SLOT_DISABLE | SET_PWR_OFF | SET_ATTN_ON); 657 if (retval) 658 ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__); 659 660 return retval; 661 } 662 663 static int shpc_get_cur_bus_speed(struct controller *ctrl) 664 { 665 int retval = 0; 666 struct pci_bus *bus = ctrl->pci_dev->subordinate; 667 enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN; 668 u16 sec_bus_reg = shpc_readw(ctrl, SEC_BUS_CONFIG); 669 u8 pi = shpc_readb(ctrl, PROG_INTERFACE); 670 u8 speed_mode = (pi == 2) ? (sec_bus_reg & 0xF) : (sec_bus_reg & 0x7); 671 672 if ((pi == 1) && (speed_mode > 4)) { 673 retval = -ENODEV; 674 goto out; 675 } 676 677 switch (speed_mode) { 678 case 0x0: 679 bus_speed = PCI_SPEED_33MHz; 680 break; 681 case 0x1: 682 bus_speed = PCI_SPEED_66MHz; 683 break; 684 case 0x2: 685 bus_speed = PCI_SPEED_66MHz_PCIX; 686 break; 687 case 0x3: 688 bus_speed = PCI_SPEED_100MHz_PCIX; 689 break; 690 case 0x4: 691 bus_speed = PCI_SPEED_133MHz_PCIX; 692 break; 693 case 0x5: 694 bus_speed = PCI_SPEED_66MHz_PCIX_ECC; 695 break; 696 case 0x6: 697 bus_speed = PCI_SPEED_100MHz_PCIX_ECC; 698 break; 699 case 0x7: 700 bus_speed = PCI_SPEED_133MHz_PCIX_ECC; 701 break; 702 case 0x8: 703 bus_speed = PCI_SPEED_66MHz_PCIX_266; 704 break; 705 case 0x9: 706 bus_speed = PCI_SPEED_100MHz_PCIX_266; 707 break; 708 case 0xa: 709 bus_speed = PCI_SPEED_133MHz_PCIX_266; 710 break; 711 case 0xb: 712 bus_speed = PCI_SPEED_66MHz_PCIX_533; 713 break; 714 case 0xc: 715 bus_speed = PCI_SPEED_100MHz_PCIX_533; 716 break; 717 case 0xd: 718 bus_speed = PCI_SPEED_133MHz_PCIX_533; 719 break; 720 default: 721 retval = -ENODEV; 722 break; 723 } 724 725 out: 726 bus->cur_bus_speed = bus_speed; 727 dbg("Current bus speed = %d\n", bus_speed); 728 return retval; 729 } 730 731 732 static int hpc_set_bus_speed_mode(struct slot * slot, enum pci_bus_speed value) 733 { 734 int retval; 735 struct controller *ctrl = slot->ctrl; 736 u8 pi, cmd; 737 738 pi = shpc_readb(ctrl, PROG_INTERFACE); 739 if ((pi == 1) && (value > PCI_SPEED_133MHz_PCIX)) 740 return -EINVAL; 741 742 switch (value) { 743 case PCI_SPEED_33MHz: 744 cmd = SETA_PCI_33MHZ; 745 break; 746 case PCI_SPEED_66MHz: 747 cmd = SETA_PCI_66MHZ; 748 break; 749 case PCI_SPEED_66MHz_PCIX: 750 cmd = SETA_PCIX_66MHZ; 751 break; 752 case PCI_SPEED_100MHz_PCIX: 753 cmd = SETA_PCIX_100MHZ; 754 break; 755 case PCI_SPEED_133MHz_PCIX: 756 cmd = SETA_PCIX_133MHZ; 757 break; 758 case PCI_SPEED_66MHz_PCIX_ECC: 759 cmd = SETB_PCIX_66MHZ_EM; 760 break; 761 case PCI_SPEED_100MHz_PCIX_ECC: 762 cmd = SETB_PCIX_100MHZ_EM; 763 break; 764 case PCI_SPEED_133MHz_PCIX_ECC: 765 cmd = SETB_PCIX_133MHZ_EM; 766 break; 767 case PCI_SPEED_66MHz_PCIX_266: 768 cmd = SETB_PCIX_66MHZ_266; 769 break; 770 case PCI_SPEED_100MHz_PCIX_266: 771 cmd = SETB_PCIX_100MHZ_266; 772 break; 773 case PCI_SPEED_133MHz_PCIX_266: 774 cmd = SETB_PCIX_133MHZ_266; 775 break; 776 case PCI_SPEED_66MHz_PCIX_533: 777 cmd = SETB_PCIX_66MHZ_533; 778 break; 779 case PCI_SPEED_100MHz_PCIX_533: 780 cmd = SETB_PCIX_100MHZ_533; 781 break; 782 case PCI_SPEED_133MHz_PCIX_533: 783 cmd = SETB_PCIX_133MHZ_533; 784 break; 785 default: 786 return -EINVAL; 787 } 788 789 retval = shpc_write_cmd(slot, 0, cmd); 790 if (retval) 791 ctrl_err(ctrl, "%s: Write command failed!\n", __func__); 792 else 793 shpc_get_cur_bus_speed(ctrl); 794 795 return retval; 796 } 797 798 static irqreturn_t shpc_isr(int irq, void *dev_id) 799 { 800 struct controller *ctrl = (struct controller *)dev_id; 801 u32 serr_int, slot_reg, intr_loc, intr_loc2; 802 int hp_slot; 803 804 /* Check to see if it was our interrupt */ 805 intr_loc = shpc_readl(ctrl, INTR_LOC); 806 if (!intr_loc) 807 return IRQ_NONE; 808 809 ctrl_dbg(ctrl, "%s: intr_loc = %x\n", __func__, intr_loc); 810 811 if(!shpchp_poll_mode) { 812 /* 813 * Mask Global Interrupt Mask - see implementation 814 * note on p. 139 of SHPC spec rev 1.0 815 */ 816 serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE); 817 serr_int |= GLOBAL_INTR_MASK; 818 serr_int &= ~SERR_INTR_RSVDZ_MASK; 819 shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int); 820 821 intr_loc2 = shpc_readl(ctrl, INTR_LOC); 822 ctrl_dbg(ctrl, "%s: intr_loc2 = %x\n", __func__, intr_loc2); 823 } 824 825 if (intr_loc & CMD_INTR_PENDING) { 826 /* 827 * Command Complete Interrupt Pending 828 * RO only - clear by writing 1 to the Command Completion 829 * Detect bit in Controller SERR-INT register 830 */ 831 serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE); 832 serr_int &= ~SERR_INTR_RSVDZ_MASK; 833 shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int); 834 835 wake_up_interruptible(&ctrl->queue); 836 } 837 838 if (!(intr_loc & ~CMD_INTR_PENDING)) 839 goto out; 840 841 for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) { 842 /* To find out which slot has interrupt pending */ 843 if (!(intr_loc & SLOT_INTR_PENDING(hp_slot))) 844 continue; 845 846 slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot)); 847 ctrl_dbg(ctrl, "Slot %x with intr, slot register = %x\n", 848 hp_slot, slot_reg); 849 850 if (slot_reg & MRL_CHANGE_DETECTED) 851 shpchp_handle_switch_change(hp_slot, ctrl); 852 853 if (slot_reg & BUTTON_PRESS_DETECTED) 854 shpchp_handle_attention_button(hp_slot, ctrl); 855 856 if (slot_reg & PRSNT_CHANGE_DETECTED) 857 shpchp_handle_presence_change(hp_slot, ctrl); 858 859 if (slot_reg & (ISO_PFAULT_DETECTED | CON_PFAULT_DETECTED)) 860 shpchp_handle_power_fault(hp_slot, ctrl); 861 862 /* Clear all slot events */ 863 slot_reg &= ~SLOT_REG_RSVDZ_MASK; 864 shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg); 865 } 866 out: 867 if (!shpchp_poll_mode) { 868 /* Unmask Global Interrupt Mask */ 869 serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE); 870 serr_int &= ~(GLOBAL_INTR_MASK | SERR_INTR_RSVDZ_MASK); 871 shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int); 872 } 873 874 return IRQ_HANDLED; 875 } 876 877 static int shpc_get_max_bus_speed(struct controller *ctrl) 878 { 879 int retval = 0; 880 struct pci_bus *bus = ctrl->pci_dev->subordinate; 881 enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN; 882 u8 pi = shpc_readb(ctrl, PROG_INTERFACE); 883 u32 slot_avail1 = shpc_readl(ctrl, SLOT_AVAIL1); 884 u32 slot_avail2 = shpc_readl(ctrl, SLOT_AVAIL2); 885 886 if (pi == 2) { 887 if (slot_avail2 & SLOT_133MHZ_PCIX_533) 888 bus_speed = PCI_SPEED_133MHz_PCIX_533; 889 else if (slot_avail2 & SLOT_100MHZ_PCIX_533) 890 bus_speed = PCI_SPEED_100MHz_PCIX_533; 891 else if (slot_avail2 & SLOT_66MHZ_PCIX_533) 892 bus_speed = PCI_SPEED_66MHz_PCIX_533; 893 else if (slot_avail2 & SLOT_133MHZ_PCIX_266) 894 bus_speed = PCI_SPEED_133MHz_PCIX_266; 895 else if (slot_avail2 & SLOT_100MHZ_PCIX_266) 896 bus_speed = PCI_SPEED_100MHz_PCIX_266; 897 else if (slot_avail2 & SLOT_66MHZ_PCIX_266) 898 bus_speed = PCI_SPEED_66MHz_PCIX_266; 899 } 900 901 if (bus_speed == PCI_SPEED_UNKNOWN) { 902 if (slot_avail1 & SLOT_133MHZ_PCIX) 903 bus_speed = PCI_SPEED_133MHz_PCIX; 904 else if (slot_avail1 & SLOT_100MHZ_PCIX) 905 bus_speed = PCI_SPEED_100MHz_PCIX; 906 else if (slot_avail1 & SLOT_66MHZ_PCIX) 907 bus_speed = PCI_SPEED_66MHz_PCIX; 908 else if (slot_avail2 & SLOT_66MHZ) 909 bus_speed = PCI_SPEED_66MHz; 910 else if (slot_avail1 & SLOT_33MHZ) 911 bus_speed = PCI_SPEED_33MHz; 912 else 913 retval = -ENODEV; 914 } 915 916 bus->max_bus_speed = bus_speed; 917 ctrl_dbg(ctrl, "Max bus speed = %d\n", bus_speed); 918 919 return retval; 920 } 921 922 static struct hpc_ops shpchp_hpc_ops = { 923 .power_on_slot = hpc_power_on_slot, 924 .slot_enable = hpc_slot_enable, 925 .slot_disable = hpc_slot_disable, 926 .set_bus_speed_mode = hpc_set_bus_speed_mode, 927 .set_attention_status = hpc_set_attention_status, 928 .get_power_status = hpc_get_power_status, 929 .get_attention_status = hpc_get_attention_status, 930 .get_latch_status = hpc_get_latch_status, 931 .get_adapter_status = hpc_get_adapter_status, 932 933 .get_adapter_speed = hpc_get_adapter_speed, 934 .get_mode1_ECC_cap = hpc_get_mode1_ECC_cap, 935 .get_prog_int = hpc_get_prog_int, 936 937 .query_power_fault = hpc_query_power_fault, 938 .green_led_on = hpc_set_green_led_on, 939 .green_led_off = hpc_set_green_led_off, 940 .green_led_blink = hpc_set_green_led_blink, 941 942 .release_ctlr = hpc_release_ctlr, 943 }; 944 945 int shpc_init(struct controller *ctrl, struct pci_dev *pdev) 946 { 947 int rc = -1, num_slots = 0; 948 u8 hp_slot; 949 u32 shpc_base_offset; 950 u32 tempdword, slot_reg, slot_config; 951 u8 i; 952 953 ctrl->pci_dev = pdev; /* pci_dev of the P2P bridge */ 954 ctrl_dbg(ctrl, "Hotplug Controller:\n"); 955 956 if ((pdev->vendor == PCI_VENDOR_ID_AMD) || (pdev->device == 957 PCI_DEVICE_ID_AMD_GOLAM_7450)) { 958 /* amd shpc driver doesn't use Base Offset; assume 0 */ 959 ctrl->mmio_base = pci_resource_start(pdev, 0); 960 ctrl->mmio_size = pci_resource_len(pdev, 0); 961 } else { 962 ctrl->cap_offset = pci_find_capability(pdev, PCI_CAP_ID_SHPC); 963 if (!ctrl->cap_offset) { 964 ctrl_err(ctrl, "Cannot find PCI capability\n"); 965 goto abort; 966 } 967 ctrl_dbg(ctrl, " cap_offset = %x\n", ctrl->cap_offset); 968 969 rc = shpc_indirect_read(ctrl, 0, &shpc_base_offset); 970 if (rc) { 971 ctrl_err(ctrl, "Cannot read base_offset\n"); 972 goto abort; 973 } 974 975 rc = shpc_indirect_read(ctrl, 3, &tempdword); 976 if (rc) { 977 ctrl_err(ctrl, "Cannot read slot config\n"); 978 goto abort; 979 } 980 num_slots = tempdword & SLOT_NUM; 981 ctrl_dbg(ctrl, " num_slots (indirect) %x\n", num_slots); 982 983 for (i = 0; i < 9 + num_slots; i++) { 984 rc = shpc_indirect_read(ctrl, i, &tempdword); 985 if (rc) { 986 ctrl_err(ctrl, 987 "Cannot read creg (index = %d)\n", i); 988 goto abort; 989 } 990 ctrl_dbg(ctrl, " offset %d: value %x\n", i, tempdword); 991 } 992 993 ctrl->mmio_base = 994 pci_resource_start(pdev, 0) + shpc_base_offset; 995 ctrl->mmio_size = 0x24 + 0x4 * num_slots; 996 } 997 998 ctrl_info(ctrl, "HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", 999 pdev->vendor, pdev->device, pdev->subsystem_vendor, 1000 pdev->subsystem_device); 1001 1002 rc = pci_enable_device(pdev); 1003 if (rc) { 1004 ctrl_err(ctrl, "pci_enable_device failed\n"); 1005 goto abort; 1006 } 1007 1008 if (!request_mem_region(ctrl->mmio_base, ctrl->mmio_size, MY_NAME)) { 1009 ctrl_err(ctrl, "Cannot reserve MMIO region\n"); 1010 rc = -1; 1011 goto abort; 1012 } 1013 1014 ctrl->creg = ioremap(ctrl->mmio_base, ctrl->mmio_size); 1015 if (!ctrl->creg) { 1016 ctrl_err(ctrl, "Cannot remap MMIO region %lx @ %lx\n", 1017 ctrl->mmio_size, ctrl->mmio_base); 1018 release_mem_region(ctrl->mmio_base, ctrl->mmio_size); 1019 rc = -1; 1020 goto abort; 1021 } 1022 ctrl_dbg(ctrl, "ctrl->creg %p\n", ctrl->creg); 1023 1024 mutex_init(&ctrl->crit_sect); 1025 mutex_init(&ctrl->cmd_lock); 1026 1027 /* Setup wait queue */ 1028 init_waitqueue_head(&ctrl->queue); 1029 1030 ctrl->hpc_ops = &shpchp_hpc_ops; 1031 1032 /* Return PCI Controller Info */ 1033 slot_config = shpc_readl(ctrl, SLOT_CONFIG); 1034 ctrl->slot_device_offset = (slot_config & FIRST_DEV_NUM) >> 8; 1035 ctrl->num_slots = slot_config & SLOT_NUM; 1036 ctrl->first_slot = (slot_config & PSN) >> 16; 1037 ctrl->slot_num_inc = ((slot_config & UPDOWN) >> 29) ? 1 : -1; 1038 1039 /* Mask Global Interrupt Mask & Command Complete Interrupt Mask */ 1040 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE); 1041 ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword); 1042 tempdword |= (GLOBAL_INTR_MASK | GLOBAL_SERR_MASK | 1043 COMMAND_INTR_MASK | ARBITER_SERR_MASK); 1044 tempdword &= ~SERR_INTR_RSVDZ_MASK; 1045 shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword); 1046 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE); 1047 ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword); 1048 1049 /* Mask the MRL sensor SERR Mask of individual slot in 1050 * Slot SERR-INT Mask & clear all the existing event if any 1051 */ 1052 for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) { 1053 slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot)); 1054 ctrl_dbg(ctrl, "Default Logical Slot Register %d value %x\n", 1055 hp_slot, slot_reg); 1056 slot_reg |= (PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK | 1057 BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK | 1058 CON_PFAULT_INTR_MASK | MRL_CHANGE_SERR_MASK | 1059 CON_PFAULT_SERR_MASK); 1060 slot_reg &= ~SLOT_REG_RSVDZ_MASK; 1061 shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg); 1062 } 1063 1064 if (shpchp_poll_mode) { 1065 /* Install interrupt polling timer. Start with 10 sec delay */ 1066 init_timer(&ctrl->poll_timer); 1067 start_int_poll_timer(ctrl, 10); 1068 } else { 1069 /* Installs the interrupt handler */ 1070 rc = pci_enable_msi(pdev); 1071 if (rc) { 1072 ctrl_info(ctrl, 1073 "Can't get msi for the hotplug controller\n"); 1074 ctrl_info(ctrl, 1075 "Use INTx for the hotplug controller\n"); 1076 } 1077 1078 rc = request_irq(ctrl->pci_dev->irq, shpc_isr, IRQF_SHARED, 1079 MY_NAME, (void *)ctrl); 1080 ctrl_dbg(ctrl, "request_irq %d for hpc%d (returns %d)\n", 1081 ctrl->pci_dev->irq, 1082 atomic_read(&shpchp_num_controllers), rc); 1083 if (rc) { 1084 ctrl_err(ctrl, "Can't get irq %d for the hotplug " 1085 "controller\n", ctrl->pci_dev->irq); 1086 goto abort_iounmap; 1087 } 1088 } 1089 ctrl_dbg(ctrl, "HPC at %s irq=%x\n", pci_name(pdev), pdev->irq); 1090 1091 shpc_get_max_bus_speed(ctrl); 1092 shpc_get_cur_bus_speed(ctrl); 1093 1094 /* 1095 * If this is the first controller to be initialized, 1096 * initialize the shpchpd work queue 1097 */ 1098 if (atomic_add_return(1, &shpchp_num_controllers) == 1) { 1099 shpchp_wq = create_singlethread_workqueue("shpchpd"); 1100 if (!shpchp_wq) { 1101 rc = -ENOMEM; 1102 goto abort_iounmap; 1103 } 1104 } 1105 1106 /* 1107 * Unmask all event interrupts of all slots 1108 */ 1109 for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) { 1110 slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot)); 1111 ctrl_dbg(ctrl, "Default Logical Slot Register %d value %x\n", 1112 hp_slot, slot_reg); 1113 slot_reg &= ~(PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK | 1114 BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK | 1115 CON_PFAULT_INTR_MASK | SLOT_REG_RSVDZ_MASK); 1116 shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg); 1117 } 1118 if (!shpchp_poll_mode) { 1119 /* Unmask all general input interrupts and SERR */ 1120 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE); 1121 tempdword &= ~(GLOBAL_INTR_MASK | COMMAND_INTR_MASK | 1122 SERR_INTR_RSVDZ_MASK); 1123 shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword); 1124 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE); 1125 ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword); 1126 } 1127 1128 return 0; 1129 1130 /* We end up here for the many possible ways to fail this API. */ 1131 abort_iounmap: 1132 iounmap(ctrl->creg); 1133 abort: 1134 return rc; 1135 } 1136