1 /* 2 * Standard PCI Hot Plug Driver 3 * 4 * Copyright (C) 1995,2001 Compaq Computer Corporation 5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com) 6 * Copyright (C) 2001 IBM Corp. 7 * Copyright (C) 2003-2004 Intel Corporation 8 * 9 * All rights reserved. 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or (at 14 * your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 19 * NON INFRINGEMENT. See the GNU General Public License for more 20 * details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 25 * 26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com> 27 * 28 */ 29 30 #include <linux/kernel.h> 31 #include <linux/module.h> 32 #include <linux/types.h> 33 #include <linux/pci.h> 34 #include <linux/interrupt.h> 35 36 #include "shpchp.h" 37 38 #ifdef DEBUG 39 #define DBG_K_TRACE_ENTRY ((unsigned int)0x00000001) /* On function entry */ 40 #define DBG_K_TRACE_EXIT ((unsigned int)0x00000002) /* On function exit */ 41 #define DBG_K_INFO ((unsigned int)0x00000004) /* Info messages */ 42 #define DBG_K_ERROR ((unsigned int)0x00000008) /* Error messages */ 43 #define DBG_K_TRACE (DBG_K_TRACE_ENTRY|DBG_K_TRACE_EXIT) 44 #define DBG_K_STANDARD (DBG_K_INFO|DBG_K_ERROR|DBG_K_TRACE) 45 /* Redefine this flagword to set debug level */ 46 #define DEBUG_LEVEL DBG_K_STANDARD 47 48 #define DEFINE_DBG_BUFFER char __dbg_str_buf[256]; 49 50 #define DBG_PRINT( dbg_flags, args... ) \ 51 do { \ 52 if ( DEBUG_LEVEL & ( dbg_flags ) ) \ 53 { \ 54 int len; \ 55 len = sprintf( __dbg_str_buf, "%s:%d: %s: ", \ 56 __FILE__, __LINE__, __FUNCTION__ ); \ 57 sprintf( __dbg_str_buf + len, args ); \ 58 printk( KERN_NOTICE "%s\n", __dbg_str_buf ); \ 59 } \ 60 } while (0) 61 62 #define DBG_ENTER_ROUTINE DBG_PRINT (DBG_K_TRACE_ENTRY, "%s", "[Entry]"); 63 #define DBG_LEAVE_ROUTINE DBG_PRINT (DBG_K_TRACE_EXIT, "%s", "[Exit]"); 64 #else 65 #define DEFINE_DBG_BUFFER 66 #define DBG_ENTER_ROUTINE 67 #define DBG_LEAVE_ROUTINE 68 #endif /* DEBUG */ 69 70 /* Slot Available Register I field definition */ 71 #define SLOT_33MHZ 0x0000001f 72 #define SLOT_66MHZ_PCIX 0x00001f00 73 #define SLOT_100MHZ_PCIX 0x001f0000 74 #define SLOT_133MHZ_PCIX 0x1f000000 75 76 /* Slot Available Register II field definition */ 77 #define SLOT_66MHZ 0x0000001f 78 #define SLOT_66MHZ_PCIX_266 0x00000f00 79 #define SLOT_100MHZ_PCIX_266 0x0000f000 80 #define SLOT_133MHZ_PCIX_266 0x000f0000 81 #define SLOT_66MHZ_PCIX_533 0x00f00000 82 #define SLOT_100MHZ_PCIX_533 0x0f000000 83 #define SLOT_133MHZ_PCIX_533 0xf0000000 84 85 /* Slot Configuration */ 86 #define SLOT_NUM 0x0000001F 87 #define FIRST_DEV_NUM 0x00001F00 88 #define PSN 0x07FF0000 89 #define UPDOWN 0x20000000 90 #define MRLSENSOR 0x40000000 91 #define ATTN_BUTTON 0x80000000 92 93 /* 94 * Interrupt Locator Register definitions 95 */ 96 #define CMD_INTR_PENDING (1 << 0) 97 #define SLOT_INTR_PENDING(i) (1 << (i + 1)) 98 99 /* 100 * Controller SERR-INT Register 101 */ 102 #define GLOBAL_INTR_MASK (1 << 0) 103 #define GLOBAL_SERR_MASK (1 << 1) 104 #define COMMAND_INTR_MASK (1 << 2) 105 #define ARBITER_SERR_MASK (1 << 3) 106 #define COMMAND_DETECTED (1 << 16) 107 #define ARBITER_DETECTED (1 << 17) 108 #define SERR_INTR_RSVDZ_MASK 0xfffc0000 109 110 /* 111 * Logical Slot Register definitions 112 */ 113 #define SLOT_REG(i) (SLOT1 + (4 * i)) 114 115 #define SLOT_STATE_SHIFT (0) 116 #define SLOT_STATE_MASK (3 << 0) 117 #define SLOT_STATE_PWRONLY (1) 118 #define SLOT_STATE_ENABLED (2) 119 #define SLOT_STATE_DISABLED (3) 120 #define PWR_LED_STATE_SHIFT (2) 121 #define PWR_LED_STATE_MASK (3 << 2) 122 #define ATN_LED_STATE_SHIFT (4) 123 #define ATN_LED_STATE_MASK (3 << 4) 124 #define ATN_LED_STATE_ON (1) 125 #define ATN_LED_STATE_BLINK (2) 126 #define ATN_LED_STATE_OFF (3) 127 #define POWER_FAULT (1 << 6) 128 #define ATN_BUTTON (1 << 7) 129 #define MRL_SENSOR (1 << 8) 130 #define MHZ66_CAP (1 << 9) 131 #define PRSNT_SHIFT (10) 132 #define PRSNT_MASK (3 << 10) 133 #define PCIX_CAP_SHIFT (12) 134 #define PCIX_CAP_MASK_PI1 (3 << 12) 135 #define PCIX_CAP_MASK_PI2 (7 << 12) 136 #define PRSNT_CHANGE_DETECTED (1 << 16) 137 #define ISO_PFAULT_DETECTED (1 << 17) 138 #define BUTTON_PRESS_DETECTED (1 << 18) 139 #define MRL_CHANGE_DETECTED (1 << 19) 140 #define CON_PFAULT_DETECTED (1 << 20) 141 #define PRSNT_CHANGE_INTR_MASK (1 << 24) 142 #define ISO_PFAULT_INTR_MASK (1 << 25) 143 #define BUTTON_PRESS_INTR_MASK (1 << 26) 144 #define MRL_CHANGE_INTR_MASK (1 << 27) 145 #define CON_PFAULT_INTR_MASK (1 << 28) 146 #define MRL_CHANGE_SERR_MASK (1 << 29) 147 #define CON_PFAULT_SERR_MASK (1 << 30) 148 #define SLOT_REG_RSVDZ_MASK (1 << 15) | (7 << 21) 149 150 /* 151 * SHPC Command Code definitnions 152 * 153 * Slot Operation 00h - 3Fh 154 * Set Bus Segment Speed/Mode A 40h - 47h 155 * Power-Only All Slots 48h 156 * Enable All Slots 49h 157 * Set Bus Segment Speed/Mode B (PI=2) 50h - 5Fh 158 * Reserved Command Codes 60h - BFh 159 * Vendor Specific Commands C0h - FFh 160 */ 161 #define SET_SLOT_PWR 0x01 /* Slot Operation */ 162 #define SET_SLOT_ENABLE 0x02 163 #define SET_SLOT_DISABLE 0x03 164 #define SET_PWR_ON 0x04 165 #define SET_PWR_BLINK 0x08 166 #define SET_PWR_OFF 0x0c 167 #define SET_ATTN_ON 0x10 168 #define SET_ATTN_BLINK 0x20 169 #define SET_ATTN_OFF 0x30 170 #define SETA_PCI_33MHZ 0x40 /* Set Bus Segment Speed/Mode A */ 171 #define SETA_PCI_66MHZ 0x41 172 #define SETA_PCIX_66MHZ 0x42 173 #define SETA_PCIX_100MHZ 0x43 174 #define SETA_PCIX_133MHZ 0x44 175 #define SETA_RESERVED1 0x45 176 #define SETA_RESERVED2 0x46 177 #define SETA_RESERVED3 0x47 178 #define SET_PWR_ONLY_ALL 0x48 /* Power-Only All Slots */ 179 #define SET_ENABLE_ALL 0x49 /* Enable All Slots */ 180 #define SETB_PCI_33MHZ 0x50 /* Set Bus Segment Speed/Mode B */ 181 #define SETB_PCI_66MHZ 0x51 182 #define SETB_PCIX_66MHZ_PM 0x52 183 #define SETB_PCIX_100MHZ_PM 0x53 184 #define SETB_PCIX_133MHZ_PM 0x54 185 #define SETB_PCIX_66MHZ_EM 0x55 186 #define SETB_PCIX_100MHZ_EM 0x56 187 #define SETB_PCIX_133MHZ_EM 0x57 188 #define SETB_PCIX_66MHZ_266 0x58 189 #define SETB_PCIX_100MHZ_266 0x59 190 #define SETB_PCIX_133MHZ_266 0x5a 191 #define SETB_PCIX_66MHZ_533 0x5b 192 #define SETB_PCIX_100MHZ_533 0x5c 193 #define SETB_PCIX_133MHZ_533 0x5d 194 #define SETB_RESERVED1 0x5e 195 #define SETB_RESERVED2 0x5f 196 197 /* 198 * SHPC controller command error code 199 */ 200 #define SWITCH_OPEN 0x1 201 #define INVALID_CMD 0x2 202 #define INVALID_SPEED_MODE 0x4 203 204 /* 205 * For accessing SHPC Working Register Set via PCI Configuration Space 206 */ 207 #define DWORD_SELECT 0x2 208 #define DWORD_DATA 0x4 209 210 /* Field Offset in Logical Slot Register - byte boundary */ 211 #define SLOT_EVENT_LATCH 0x2 212 #define SLOT_SERR_INT_MASK 0x3 213 214 DEFINE_DBG_BUFFER /* Debug string buffer for entire HPC defined here */ 215 static struct php_ctlr_state_s *php_ctlr_list_head; /* HPC state linked list */ 216 static int ctlr_seq_num = 0; /* Controller sequenc # */ 217 static spinlock_t list_lock; 218 219 static atomic_t shpchp_num_controllers = ATOMIC_INIT(0); 220 221 static irqreturn_t shpc_isr(int irq, void *dev_id, struct pt_regs *regs); 222 static void start_int_poll_timer(struct php_ctlr_state_s *php_ctlr, int sec); 223 static int hpc_check_cmd_status(struct controller *ctrl); 224 225 static inline u8 shpc_readb(struct controller *ctrl, int reg) 226 { 227 return readb(ctrl->hpc_ctlr_handle->creg + reg); 228 } 229 230 static inline void shpc_writeb(struct controller *ctrl, int reg, u8 val) 231 { 232 writeb(val, ctrl->hpc_ctlr_handle->creg + reg); 233 } 234 235 static inline u16 shpc_readw(struct controller *ctrl, int reg) 236 { 237 return readw(ctrl->hpc_ctlr_handle->creg + reg); 238 } 239 240 static inline void shpc_writew(struct controller *ctrl, int reg, u16 val) 241 { 242 writew(val, ctrl->hpc_ctlr_handle->creg + reg); 243 } 244 245 static inline u32 shpc_readl(struct controller *ctrl, int reg) 246 { 247 return readl(ctrl->hpc_ctlr_handle->creg + reg); 248 } 249 250 static inline void shpc_writel(struct controller *ctrl, int reg, u32 val) 251 { 252 writel(val, ctrl->hpc_ctlr_handle->creg + reg); 253 } 254 255 static inline int shpc_indirect_read(struct controller *ctrl, int index, 256 u32 *value) 257 { 258 int rc; 259 u32 cap_offset = ctrl->cap_offset; 260 struct pci_dev *pdev = ctrl->pci_dev; 261 262 rc = pci_write_config_byte(pdev, cap_offset + DWORD_SELECT, index); 263 if (rc) 264 return rc; 265 return pci_read_config_dword(pdev, cap_offset + DWORD_DATA, value); 266 } 267 268 /* 269 * This is the interrupt polling timeout function. 270 */ 271 static void int_poll_timeout(unsigned long lphp_ctlr) 272 { 273 struct php_ctlr_state_s *php_ctlr = 274 (struct php_ctlr_state_s *)lphp_ctlr; 275 276 DBG_ENTER_ROUTINE 277 278 /* Poll for interrupt events. regs == NULL => polling */ 279 shpc_isr(0, php_ctlr->callback_instance_id, NULL); 280 281 init_timer(&php_ctlr->int_poll_timer); 282 if (!shpchp_poll_time) 283 shpchp_poll_time = 2; /* default polling interval is 2 sec */ 284 285 start_int_poll_timer(php_ctlr, shpchp_poll_time); 286 287 DBG_LEAVE_ROUTINE 288 } 289 290 /* 291 * This function starts the interrupt polling timer. 292 */ 293 static void start_int_poll_timer(struct php_ctlr_state_s *php_ctlr, int sec) 294 { 295 /* Clamp to sane value */ 296 if ((sec <= 0) || (sec > 60)) 297 sec = 2; 298 299 php_ctlr->int_poll_timer.function = &int_poll_timeout; 300 php_ctlr->int_poll_timer.data = (unsigned long)php_ctlr; 301 php_ctlr->int_poll_timer.expires = jiffies + sec * HZ; 302 add_timer(&php_ctlr->int_poll_timer); 303 } 304 305 static inline int shpc_wait_cmd(struct controller *ctrl) 306 { 307 int retval = 0; 308 unsigned int timeout_msec = shpchp_poll_mode ? 2000 : 1000; 309 unsigned long timeout = msecs_to_jiffies(timeout_msec); 310 int rc = wait_event_interruptible_timeout(ctrl->queue, 311 !ctrl->cmd_busy, timeout); 312 if (!rc) { 313 retval = -EIO; 314 err("Command not completed in %d msec\n", timeout_msec); 315 } else if (rc < 0) { 316 retval = -EINTR; 317 info("Command was interrupted by a signal\n"); 318 } 319 ctrl->cmd_busy = 0; 320 321 return retval; 322 } 323 324 static int shpc_write_cmd(struct slot *slot, u8 t_slot, u8 cmd) 325 { 326 struct controller *ctrl = slot->ctrl; 327 u16 cmd_status; 328 int retval = 0; 329 u16 temp_word; 330 int i; 331 332 DBG_ENTER_ROUTINE 333 334 mutex_lock(&slot->ctrl->cmd_lock); 335 336 for (i = 0; i < 10; i++) { 337 cmd_status = shpc_readw(ctrl, CMD_STATUS); 338 339 if (!(cmd_status & 0x1)) 340 break; 341 /* Check every 0.1 sec for a total of 1 sec*/ 342 msleep(100); 343 } 344 345 cmd_status = shpc_readw(ctrl, CMD_STATUS); 346 347 if (cmd_status & 0x1) { 348 /* After 1 sec and and the controller is still busy */ 349 err("%s : Controller is still busy after 1 sec.\n", __FUNCTION__); 350 retval = -EBUSY; 351 goto out; 352 } 353 354 ++t_slot; 355 temp_word = (t_slot << 8) | (cmd & 0xFF); 356 dbg("%s: t_slot %x cmd %x\n", __FUNCTION__, t_slot, cmd); 357 358 /* To make sure the Controller Busy bit is 0 before we send out the 359 * command. 360 */ 361 slot->ctrl->cmd_busy = 1; 362 shpc_writew(ctrl, CMD, temp_word); 363 364 /* 365 * Wait for command completion. 366 */ 367 retval = shpc_wait_cmd(slot->ctrl); 368 if (retval) 369 goto out; 370 371 cmd_status = hpc_check_cmd_status(slot->ctrl); 372 if (cmd_status) { 373 err("%s: Failed to issued command 0x%x (error code = %d)\n", 374 __FUNCTION__, cmd, cmd_status); 375 retval = -EIO; 376 } 377 out: 378 mutex_unlock(&slot->ctrl->cmd_lock); 379 380 DBG_LEAVE_ROUTINE 381 return retval; 382 } 383 384 static int hpc_check_cmd_status(struct controller *ctrl) 385 { 386 u16 cmd_status; 387 int retval = 0; 388 389 DBG_ENTER_ROUTINE 390 391 cmd_status = shpc_readw(ctrl, CMD_STATUS) & 0x000F; 392 393 switch (cmd_status >> 1) { 394 case 0: 395 retval = 0; 396 break; 397 case 1: 398 retval = SWITCH_OPEN; 399 err("%s: Switch opened!\n", __FUNCTION__); 400 break; 401 case 2: 402 retval = INVALID_CMD; 403 err("%s: Invalid HPC command!\n", __FUNCTION__); 404 break; 405 case 4: 406 retval = INVALID_SPEED_MODE; 407 err("%s: Invalid bus speed/mode!\n", __FUNCTION__); 408 break; 409 default: 410 retval = cmd_status; 411 } 412 413 DBG_LEAVE_ROUTINE 414 return retval; 415 } 416 417 418 static int hpc_get_attention_status(struct slot *slot, u8 *status) 419 { 420 struct controller *ctrl = slot->ctrl; 421 u32 slot_reg; 422 u8 state; 423 424 DBG_ENTER_ROUTINE 425 426 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); 427 state = (slot_reg & ATN_LED_STATE_MASK) >> ATN_LED_STATE_SHIFT; 428 429 switch (state) { 430 case ATN_LED_STATE_ON: 431 *status = 1; /* On */ 432 break; 433 case ATN_LED_STATE_BLINK: 434 *status = 2; /* Blink */ 435 break; 436 case ATN_LED_STATE_OFF: 437 *status = 0; /* Off */ 438 break; 439 default: 440 *status = 0xFF; /* Reserved */ 441 break; 442 } 443 444 DBG_LEAVE_ROUTINE 445 return 0; 446 } 447 448 static int hpc_get_power_status(struct slot * slot, u8 *status) 449 { 450 struct controller *ctrl = slot->ctrl; 451 u32 slot_reg; 452 u8 state; 453 454 DBG_ENTER_ROUTINE 455 456 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); 457 state = (slot_reg & SLOT_STATE_MASK) >> SLOT_STATE_SHIFT; 458 459 switch (state) { 460 case SLOT_STATE_PWRONLY: 461 *status = 2; /* Powered only */ 462 break; 463 case SLOT_STATE_ENABLED: 464 *status = 1; /* Enabled */ 465 break; 466 case SLOT_STATE_DISABLED: 467 *status = 0; /* Disabled */ 468 break; 469 default: 470 *status = 0xFF; /* Reserved */ 471 break; 472 } 473 474 DBG_LEAVE_ROUTINE 475 return 0; 476 } 477 478 479 static int hpc_get_latch_status(struct slot *slot, u8 *status) 480 { 481 struct controller *ctrl = slot->ctrl; 482 u32 slot_reg; 483 484 DBG_ENTER_ROUTINE 485 486 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); 487 *status = !!(slot_reg & MRL_SENSOR); /* 0 -> close; 1 -> open */ 488 489 DBG_LEAVE_ROUTINE 490 return 0; 491 } 492 493 static int hpc_get_adapter_status(struct slot *slot, u8 *status) 494 { 495 struct controller *ctrl = slot->ctrl; 496 u32 slot_reg; 497 u8 state; 498 499 DBG_ENTER_ROUTINE 500 501 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); 502 state = (slot_reg & PRSNT_MASK) >> PRSNT_SHIFT; 503 *status = (state != 0x3) ? 1 : 0; 504 505 DBG_LEAVE_ROUTINE 506 return 0; 507 } 508 509 static int hpc_get_prog_int(struct slot *slot, u8 *prog_int) 510 { 511 struct controller *ctrl = slot->ctrl; 512 513 DBG_ENTER_ROUTINE 514 515 *prog_int = shpc_readb(ctrl, PROG_INTERFACE); 516 517 DBG_LEAVE_ROUTINE 518 return 0; 519 } 520 521 static int hpc_get_adapter_speed(struct slot *slot, enum pci_bus_speed *value) 522 { 523 int retval = 0; 524 struct controller *ctrl = slot->ctrl; 525 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); 526 u8 m66_cap = !!(slot_reg & MHZ66_CAP); 527 u8 pi, pcix_cap; 528 529 DBG_ENTER_ROUTINE 530 531 if ((retval = hpc_get_prog_int(slot, &pi))) 532 return retval; 533 534 switch (pi) { 535 case 1: 536 pcix_cap = (slot_reg & PCIX_CAP_MASK_PI1) >> PCIX_CAP_SHIFT; 537 break; 538 case 2: 539 pcix_cap = (slot_reg & PCIX_CAP_MASK_PI2) >> PCIX_CAP_SHIFT; 540 break; 541 default: 542 return -ENODEV; 543 } 544 545 dbg("%s: slot_reg = %x, pcix_cap = %x, m66_cap = %x\n", 546 __FUNCTION__, slot_reg, pcix_cap, m66_cap); 547 548 switch (pcix_cap) { 549 case 0x0: 550 *value = m66_cap ? PCI_SPEED_66MHz : PCI_SPEED_33MHz; 551 break; 552 case 0x1: 553 *value = PCI_SPEED_66MHz_PCIX; 554 break; 555 case 0x3: 556 *value = PCI_SPEED_133MHz_PCIX; 557 break; 558 case 0x4: 559 *value = PCI_SPEED_133MHz_PCIX_266; 560 break; 561 case 0x5: 562 *value = PCI_SPEED_133MHz_PCIX_533; 563 break; 564 case 0x2: 565 default: 566 *value = PCI_SPEED_UNKNOWN; 567 retval = -ENODEV; 568 break; 569 } 570 571 dbg("Adapter speed = %d\n", *value); 572 DBG_LEAVE_ROUTINE 573 return retval; 574 } 575 576 static int hpc_get_mode1_ECC_cap(struct slot *slot, u8 *mode) 577 { 578 struct controller *ctrl = slot->ctrl; 579 u16 sec_bus_status; 580 u8 pi; 581 int retval = 0; 582 583 DBG_ENTER_ROUTINE 584 585 pi = shpc_readb(ctrl, PROG_INTERFACE); 586 sec_bus_status = shpc_readw(ctrl, SEC_BUS_CONFIG); 587 588 if (pi == 2) { 589 *mode = (sec_bus_status & 0x0100) >> 8; 590 } else { 591 retval = -1; 592 } 593 594 dbg("Mode 1 ECC cap = %d\n", *mode); 595 596 DBG_LEAVE_ROUTINE 597 return retval; 598 } 599 600 static int hpc_query_power_fault(struct slot * slot) 601 { 602 struct controller *ctrl = slot->ctrl; 603 u32 slot_reg; 604 605 DBG_ENTER_ROUTINE 606 607 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); 608 609 DBG_LEAVE_ROUTINE 610 /* Note: Logic 0 => fault */ 611 return !(slot_reg & POWER_FAULT); 612 } 613 614 static int hpc_set_attention_status(struct slot *slot, u8 value) 615 { 616 u8 slot_cmd = 0; 617 618 switch (value) { 619 case 0 : 620 slot_cmd = SET_ATTN_OFF; /* OFF */ 621 break; 622 case 1: 623 slot_cmd = SET_ATTN_ON; /* ON */ 624 break; 625 case 2: 626 slot_cmd = SET_ATTN_BLINK; /* BLINK */ 627 break; 628 default: 629 return -1; 630 } 631 632 return shpc_write_cmd(slot, slot->hp_slot, slot_cmd); 633 } 634 635 636 static void hpc_set_green_led_on(struct slot *slot) 637 { 638 shpc_write_cmd(slot, slot->hp_slot, SET_PWR_ON); 639 } 640 641 static void hpc_set_green_led_off(struct slot *slot) 642 { 643 shpc_write_cmd(slot, slot->hp_slot, SET_PWR_OFF); 644 } 645 646 static void hpc_set_green_led_blink(struct slot *slot) 647 { 648 shpc_write_cmd(slot, slot->hp_slot, SET_PWR_BLINK); 649 } 650 651 int shpc_get_ctlr_slot_config(struct controller *ctrl, 652 int *num_ctlr_slots, /* number of slots in this HPC */ 653 int *first_device_num, /* PCI dev num of the first slot in this SHPC */ 654 int *physical_slot_num, /* phy slot num of the first slot in this SHPC */ 655 int *updown, /* physical_slot_num increament: 1 or -1 */ 656 int *flags) 657 { 658 u32 slot_config; 659 660 DBG_ENTER_ROUTINE 661 662 slot_config = shpc_readl(ctrl, SLOT_CONFIG); 663 *first_device_num = (slot_config & FIRST_DEV_NUM) >> 8; 664 *num_ctlr_slots = slot_config & SLOT_NUM; 665 *physical_slot_num = (slot_config & PSN) >> 16; 666 *updown = ((slot_config & UPDOWN) >> 29) ? 1 : -1; 667 668 dbg("%s: physical_slot_num = %x\n", __FUNCTION__, *physical_slot_num); 669 670 DBG_LEAVE_ROUTINE 671 return 0; 672 } 673 674 static void hpc_release_ctlr(struct controller *ctrl) 675 { 676 struct php_ctlr_state_s *php_ctlr = ctrl->hpc_ctlr_handle; 677 struct php_ctlr_state_s *p, *p_prev; 678 int i; 679 u32 slot_reg, serr_int; 680 681 DBG_ENTER_ROUTINE 682 683 /* 684 * Mask event interrupts and SERRs of all slots 685 */ 686 for (i = 0; i < ctrl->num_slots; i++) { 687 slot_reg = shpc_readl(ctrl, SLOT_REG(i)); 688 slot_reg |= (PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK | 689 BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK | 690 CON_PFAULT_INTR_MASK | MRL_CHANGE_SERR_MASK | 691 CON_PFAULT_SERR_MASK); 692 slot_reg &= ~SLOT_REG_RSVDZ_MASK; 693 shpc_writel(ctrl, SLOT_REG(i), slot_reg); 694 } 695 696 cleanup_slots(ctrl); 697 698 /* 699 * Mask SERR and System Interrut generation 700 */ 701 serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE); 702 serr_int |= (GLOBAL_INTR_MASK | GLOBAL_SERR_MASK | 703 COMMAND_INTR_MASK | ARBITER_SERR_MASK); 704 serr_int &= ~SERR_INTR_RSVDZ_MASK; 705 shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int); 706 707 if (shpchp_poll_mode) { 708 del_timer(&php_ctlr->int_poll_timer); 709 } else { 710 if (php_ctlr->irq) { 711 free_irq(php_ctlr->irq, ctrl); 712 php_ctlr->irq = 0; 713 pci_disable_msi(php_ctlr->pci_dev); 714 } 715 } 716 717 if (php_ctlr->pci_dev) { 718 iounmap(php_ctlr->creg); 719 release_mem_region(ctrl->mmio_base, ctrl->mmio_size); 720 php_ctlr->pci_dev = NULL; 721 } 722 723 spin_lock(&list_lock); 724 p = php_ctlr_list_head; 725 p_prev = NULL; 726 while (p) { 727 if (p == php_ctlr) { 728 if (p_prev) 729 p_prev->pnext = p->pnext; 730 else 731 php_ctlr_list_head = p->pnext; 732 break; 733 } else { 734 p_prev = p; 735 p = p->pnext; 736 } 737 } 738 spin_unlock(&list_lock); 739 740 kfree(php_ctlr); 741 742 /* 743 * If this is the last controller to be released, destroy the 744 * shpchpd work queue 745 */ 746 if (atomic_dec_and_test(&shpchp_num_controllers)) 747 destroy_workqueue(shpchp_wq); 748 749 DBG_LEAVE_ROUTINE 750 751 } 752 753 static int hpc_power_on_slot(struct slot * slot) 754 { 755 int retval; 756 757 DBG_ENTER_ROUTINE 758 759 retval = shpc_write_cmd(slot, slot->hp_slot, SET_SLOT_PWR); 760 if (retval) { 761 err("%s: Write command failed!\n", __FUNCTION__); 762 return retval; 763 } 764 765 DBG_LEAVE_ROUTINE 766 767 return 0; 768 } 769 770 static int hpc_slot_enable(struct slot * slot) 771 { 772 int retval; 773 774 DBG_ENTER_ROUTINE 775 776 /* Slot - Enable, Power Indicator - Blink, Attention Indicator - Off */ 777 retval = shpc_write_cmd(slot, slot->hp_slot, 778 SET_SLOT_ENABLE | SET_PWR_BLINK | SET_ATTN_OFF); 779 if (retval) { 780 err("%s: Write command failed!\n", __FUNCTION__); 781 return retval; 782 } 783 784 DBG_LEAVE_ROUTINE 785 return 0; 786 } 787 788 static int hpc_slot_disable(struct slot * slot) 789 { 790 int retval; 791 792 DBG_ENTER_ROUTINE 793 794 /* Slot - Disable, Power Indicator - Off, Attention Indicator - On */ 795 retval = shpc_write_cmd(slot, slot->hp_slot, 796 SET_SLOT_DISABLE | SET_PWR_OFF | SET_ATTN_ON); 797 if (retval) { 798 err("%s: Write command failed!\n", __FUNCTION__); 799 return retval; 800 } 801 802 DBG_LEAVE_ROUTINE 803 return 0; 804 } 805 806 static int hpc_set_bus_speed_mode(struct slot * slot, enum pci_bus_speed value) 807 { 808 int retval; 809 struct controller *ctrl = slot->ctrl; 810 u8 pi, cmd; 811 812 DBG_ENTER_ROUTINE 813 814 pi = shpc_readb(ctrl, PROG_INTERFACE); 815 if ((pi == 1) && (value > PCI_SPEED_133MHz_PCIX)) 816 return -EINVAL; 817 818 switch (value) { 819 case PCI_SPEED_33MHz: 820 cmd = SETA_PCI_33MHZ; 821 break; 822 case PCI_SPEED_66MHz: 823 cmd = SETA_PCI_66MHZ; 824 break; 825 case PCI_SPEED_66MHz_PCIX: 826 cmd = SETA_PCIX_66MHZ; 827 break; 828 case PCI_SPEED_100MHz_PCIX: 829 cmd = SETA_PCIX_100MHZ; 830 break; 831 case PCI_SPEED_133MHz_PCIX: 832 cmd = SETA_PCIX_133MHZ; 833 break; 834 case PCI_SPEED_66MHz_PCIX_ECC: 835 cmd = SETB_PCIX_66MHZ_EM; 836 break; 837 case PCI_SPEED_100MHz_PCIX_ECC: 838 cmd = SETB_PCIX_100MHZ_EM; 839 break; 840 case PCI_SPEED_133MHz_PCIX_ECC: 841 cmd = SETB_PCIX_133MHZ_EM; 842 break; 843 case PCI_SPEED_66MHz_PCIX_266: 844 cmd = SETB_PCIX_66MHZ_266; 845 break; 846 case PCI_SPEED_100MHz_PCIX_266: 847 cmd = SETB_PCIX_100MHZ_266; 848 break; 849 case PCI_SPEED_133MHz_PCIX_266: 850 cmd = SETB_PCIX_133MHZ_266; 851 break; 852 case PCI_SPEED_66MHz_PCIX_533: 853 cmd = SETB_PCIX_66MHZ_533; 854 break; 855 case PCI_SPEED_100MHz_PCIX_533: 856 cmd = SETB_PCIX_100MHZ_533; 857 break; 858 case PCI_SPEED_133MHz_PCIX_533: 859 cmd = SETB_PCIX_133MHZ_533; 860 break; 861 default: 862 return -EINVAL; 863 } 864 865 retval = shpc_write_cmd(slot, 0, cmd); 866 if (retval) 867 err("%s: Write command failed!\n", __FUNCTION__); 868 869 DBG_LEAVE_ROUTINE 870 return retval; 871 } 872 873 static irqreturn_t shpc_isr(int irq, void *dev_id, struct pt_regs *regs) 874 { 875 struct controller *ctrl = (struct controller *)dev_id; 876 struct php_ctlr_state_s *php_ctlr = ctrl->hpc_ctlr_handle; 877 u32 serr_int, slot_reg, intr_loc, intr_loc2; 878 int hp_slot; 879 880 /* Check to see if it was our interrupt */ 881 intr_loc = shpc_readl(ctrl, INTR_LOC); 882 if (!intr_loc) 883 return IRQ_NONE; 884 885 dbg("%s: intr_loc = %x\n",__FUNCTION__, intr_loc); 886 887 if(!shpchp_poll_mode) { 888 /* 889 * Mask Global Interrupt Mask - see implementation 890 * note on p. 139 of SHPC spec rev 1.0 891 */ 892 serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE); 893 serr_int |= GLOBAL_INTR_MASK; 894 serr_int &= ~SERR_INTR_RSVDZ_MASK; 895 shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int); 896 897 intr_loc2 = shpc_readl(ctrl, INTR_LOC); 898 dbg("%s: intr_loc2 = %x\n",__FUNCTION__, intr_loc2); 899 } 900 901 if (intr_loc & CMD_INTR_PENDING) { 902 /* 903 * Command Complete Interrupt Pending 904 * RO only - clear by writing 1 to the Command Completion 905 * Detect bit in Controller SERR-INT register 906 */ 907 serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE); 908 serr_int &= ~SERR_INTR_RSVDZ_MASK; 909 shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int); 910 911 ctrl->cmd_busy = 0; 912 wake_up_interruptible(&ctrl->queue); 913 } 914 915 if (!(intr_loc & ~CMD_INTR_PENDING)) 916 goto out; 917 918 for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) { 919 /* To find out which slot has interrupt pending */ 920 if (!(intr_loc & SLOT_INTR_PENDING(hp_slot))) 921 continue; 922 923 slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot)); 924 dbg("%s: Slot %x with intr, slot register = %x\n", 925 __FUNCTION__, hp_slot, slot_reg); 926 927 if (slot_reg & MRL_CHANGE_DETECTED) 928 php_ctlr->switch_change_callback( 929 hp_slot, php_ctlr->callback_instance_id); 930 931 if (slot_reg & BUTTON_PRESS_DETECTED) 932 php_ctlr->attention_button_callback( 933 hp_slot, php_ctlr->callback_instance_id); 934 935 if (slot_reg & PRSNT_CHANGE_DETECTED) 936 php_ctlr->presence_change_callback( 937 hp_slot , php_ctlr->callback_instance_id); 938 939 if (slot_reg & (ISO_PFAULT_DETECTED | CON_PFAULT_DETECTED)) 940 php_ctlr->power_fault_callback( 941 hp_slot, php_ctlr->callback_instance_id); 942 943 /* Clear all slot events */ 944 slot_reg &= ~SLOT_REG_RSVDZ_MASK; 945 shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg); 946 } 947 out: 948 if (!shpchp_poll_mode) { 949 /* Unmask Global Interrupt Mask */ 950 serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE); 951 serr_int &= ~(GLOBAL_INTR_MASK | SERR_INTR_RSVDZ_MASK); 952 shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int); 953 } 954 955 return IRQ_HANDLED; 956 } 957 958 static int hpc_get_max_bus_speed (struct slot *slot, enum pci_bus_speed *value) 959 { 960 int retval = 0; 961 struct controller *ctrl = slot->ctrl; 962 enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN; 963 u8 pi = shpc_readb(ctrl, PROG_INTERFACE); 964 u32 slot_avail1 = shpc_readl(ctrl, SLOT_AVAIL1); 965 u32 slot_avail2 = shpc_readl(ctrl, SLOT_AVAIL2); 966 967 DBG_ENTER_ROUTINE 968 969 if (pi == 2) { 970 if (slot_avail2 & SLOT_133MHZ_PCIX_533) 971 bus_speed = PCI_SPEED_133MHz_PCIX_533; 972 else if (slot_avail2 & SLOT_100MHZ_PCIX_533) 973 bus_speed = PCI_SPEED_100MHz_PCIX_533; 974 else if (slot_avail2 & SLOT_66MHZ_PCIX_533) 975 bus_speed = PCI_SPEED_66MHz_PCIX_533; 976 else if (slot_avail2 & SLOT_133MHZ_PCIX_266) 977 bus_speed = PCI_SPEED_133MHz_PCIX_266; 978 else if (slot_avail2 & SLOT_100MHZ_PCIX_266) 979 bus_speed = PCI_SPEED_100MHz_PCIX_266; 980 else if (slot_avail2 & SLOT_66MHZ_PCIX_266) 981 bus_speed = PCI_SPEED_66MHz_PCIX_266; 982 } 983 984 if (bus_speed == PCI_SPEED_UNKNOWN) { 985 if (slot_avail1 & SLOT_133MHZ_PCIX) 986 bus_speed = PCI_SPEED_133MHz_PCIX; 987 else if (slot_avail1 & SLOT_100MHZ_PCIX) 988 bus_speed = PCI_SPEED_100MHz_PCIX; 989 else if (slot_avail1 & SLOT_66MHZ_PCIX) 990 bus_speed = PCI_SPEED_66MHz_PCIX; 991 else if (slot_avail2 & SLOT_66MHZ) 992 bus_speed = PCI_SPEED_66MHz; 993 else if (slot_avail1 & SLOT_33MHZ) 994 bus_speed = PCI_SPEED_33MHz; 995 else 996 retval = -ENODEV; 997 } 998 999 *value = bus_speed; 1000 dbg("Max bus speed = %d\n", bus_speed); 1001 DBG_LEAVE_ROUTINE 1002 return retval; 1003 } 1004 1005 static int hpc_get_cur_bus_speed (struct slot *slot, enum pci_bus_speed *value) 1006 { 1007 int retval = 0; 1008 struct controller *ctrl = slot->ctrl; 1009 enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN; 1010 u16 sec_bus_reg = shpc_readw(ctrl, SEC_BUS_CONFIG); 1011 u8 pi = shpc_readb(ctrl, PROG_INTERFACE); 1012 u8 speed_mode = (pi == 2) ? (sec_bus_reg & 0xF) : (sec_bus_reg & 0x7); 1013 1014 DBG_ENTER_ROUTINE 1015 1016 if ((pi == 1) && (speed_mode > 4)) { 1017 *value = PCI_SPEED_UNKNOWN; 1018 return -ENODEV; 1019 } 1020 1021 switch (speed_mode) { 1022 case 0x0: 1023 *value = PCI_SPEED_33MHz; 1024 break; 1025 case 0x1: 1026 *value = PCI_SPEED_66MHz; 1027 break; 1028 case 0x2: 1029 *value = PCI_SPEED_66MHz_PCIX; 1030 break; 1031 case 0x3: 1032 *value = PCI_SPEED_100MHz_PCIX; 1033 break; 1034 case 0x4: 1035 *value = PCI_SPEED_133MHz_PCIX; 1036 break; 1037 case 0x5: 1038 *value = PCI_SPEED_66MHz_PCIX_ECC; 1039 break; 1040 case 0x6: 1041 *value = PCI_SPEED_100MHz_PCIX_ECC; 1042 break; 1043 case 0x7: 1044 *value = PCI_SPEED_133MHz_PCIX_ECC; 1045 break; 1046 case 0x8: 1047 *value = PCI_SPEED_66MHz_PCIX_266; 1048 break; 1049 case 0x9: 1050 *value = PCI_SPEED_100MHz_PCIX_266; 1051 break; 1052 case 0xa: 1053 *value = PCI_SPEED_133MHz_PCIX_266; 1054 break; 1055 case 0xb: 1056 *value = PCI_SPEED_66MHz_PCIX_533; 1057 break; 1058 case 0xc: 1059 *value = PCI_SPEED_100MHz_PCIX_533; 1060 break; 1061 case 0xd: 1062 *value = PCI_SPEED_133MHz_PCIX_533; 1063 break; 1064 default: 1065 *value = PCI_SPEED_UNKNOWN; 1066 retval = -ENODEV; 1067 break; 1068 } 1069 1070 dbg("Current bus speed = %d\n", bus_speed); 1071 DBG_LEAVE_ROUTINE 1072 return retval; 1073 } 1074 1075 static struct hpc_ops shpchp_hpc_ops = { 1076 .power_on_slot = hpc_power_on_slot, 1077 .slot_enable = hpc_slot_enable, 1078 .slot_disable = hpc_slot_disable, 1079 .set_bus_speed_mode = hpc_set_bus_speed_mode, 1080 .set_attention_status = hpc_set_attention_status, 1081 .get_power_status = hpc_get_power_status, 1082 .get_attention_status = hpc_get_attention_status, 1083 .get_latch_status = hpc_get_latch_status, 1084 .get_adapter_status = hpc_get_adapter_status, 1085 1086 .get_max_bus_speed = hpc_get_max_bus_speed, 1087 .get_cur_bus_speed = hpc_get_cur_bus_speed, 1088 .get_adapter_speed = hpc_get_adapter_speed, 1089 .get_mode1_ECC_cap = hpc_get_mode1_ECC_cap, 1090 .get_prog_int = hpc_get_prog_int, 1091 1092 .query_power_fault = hpc_query_power_fault, 1093 .green_led_on = hpc_set_green_led_on, 1094 .green_led_off = hpc_set_green_led_off, 1095 .green_led_blink = hpc_set_green_led_blink, 1096 1097 .release_ctlr = hpc_release_ctlr, 1098 }; 1099 1100 int shpc_init(struct controller * ctrl, struct pci_dev * pdev) 1101 { 1102 struct php_ctlr_state_s *php_ctlr, *p; 1103 void *instance_id = ctrl; 1104 int rc, num_slots = 0; 1105 u8 hp_slot; 1106 u32 shpc_base_offset; 1107 u32 tempdword, slot_reg, slot_config; 1108 u8 i; 1109 1110 DBG_ENTER_ROUTINE 1111 1112 ctrl->pci_dev = pdev; /* pci_dev of the P2P bridge */ 1113 1114 spin_lock_init(&list_lock); 1115 php_ctlr = kzalloc(sizeof(*php_ctlr), GFP_KERNEL); 1116 1117 if (!php_ctlr) { /* allocate controller state data */ 1118 err("%s: HPC controller memory allocation error!\n", __FUNCTION__); 1119 goto abort; 1120 } 1121 1122 php_ctlr->pci_dev = pdev; /* save pci_dev in context */ 1123 1124 if ((pdev->vendor == PCI_VENDOR_ID_AMD) || (pdev->device == 1125 PCI_DEVICE_ID_AMD_GOLAM_7450)) { 1126 /* amd shpc driver doesn't use Base Offset; assume 0 */ 1127 ctrl->mmio_base = pci_resource_start(pdev, 0); 1128 ctrl->mmio_size = pci_resource_len(pdev, 0); 1129 } else { 1130 ctrl->cap_offset = pci_find_capability(pdev, PCI_CAP_ID_SHPC); 1131 if (!ctrl->cap_offset) { 1132 err("%s : cap_offset == 0\n", __FUNCTION__); 1133 goto abort_free_ctlr; 1134 } 1135 dbg("%s: cap_offset = %x\n", __FUNCTION__, ctrl->cap_offset); 1136 1137 rc = shpc_indirect_read(ctrl, 0, &shpc_base_offset); 1138 if (rc) { 1139 err("%s: cannot read base_offset\n", __FUNCTION__); 1140 goto abort_free_ctlr; 1141 } 1142 1143 rc = shpc_indirect_read(ctrl, 3, &tempdword); 1144 if (rc) { 1145 err("%s: cannot read slot config\n", __FUNCTION__); 1146 goto abort_free_ctlr; 1147 } 1148 num_slots = tempdword & SLOT_NUM; 1149 dbg("%s: num_slots (indirect) %x\n", __FUNCTION__, num_slots); 1150 1151 for (i = 0; i < 9 + num_slots; i++) { 1152 rc = shpc_indirect_read(ctrl, i, &tempdword); 1153 if (rc) { 1154 err("%s: cannot read creg (index = %d)\n", 1155 __FUNCTION__, i); 1156 goto abort_free_ctlr; 1157 } 1158 dbg("%s: offset %d: value %x\n", __FUNCTION__,i, 1159 tempdword); 1160 } 1161 1162 ctrl->mmio_base = 1163 pci_resource_start(pdev, 0) + shpc_base_offset; 1164 ctrl->mmio_size = 0x24 + 0x4 * num_slots; 1165 } 1166 1167 info("HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", pdev->vendor, pdev->device, pdev->subsystem_vendor, 1168 pdev->subsystem_device); 1169 1170 if (pci_enable_device(pdev)) 1171 goto abort_free_ctlr; 1172 1173 if (!request_mem_region(ctrl->mmio_base, ctrl->mmio_size, MY_NAME)) { 1174 err("%s: cannot reserve MMIO region\n", __FUNCTION__); 1175 goto abort_free_ctlr; 1176 } 1177 1178 php_ctlr->creg = ioremap(ctrl->mmio_base, ctrl->mmio_size); 1179 if (!php_ctlr->creg) { 1180 err("%s: cannot remap MMIO region %lx @ %lx\n", __FUNCTION__, 1181 ctrl->mmio_size, ctrl->mmio_base); 1182 release_mem_region(ctrl->mmio_base, ctrl->mmio_size); 1183 goto abort_free_ctlr; 1184 } 1185 dbg("%s: php_ctlr->creg %p\n", __FUNCTION__, php_ctlr->creg); 1186 1187 mutex_init(&ctrl->crit_sect); 1188 mutex_init(&ctrl->cmd_lock); 1189 1190 /* Setup wait queue */ 1191 init_waitqueue_head(&ctrl->queue); 1192 1193 /* Find the IRQ */ 1194 php_ctlr->irq = pdev->irq; 1195 php_ctlr->attention_button_callback = shpchp_handle_attention_button, 1196 php_ctlr->switch_change_callback = shpchp_handle_switch_change; 1197 php_ctlr->presence_change_callback = shpchp_handle_presence_change; 1198 php_ctlr->power_fault_callback = shpchp_handle_power_fault; 1199 php_ctlr->callback_instance_id = instance_id; 1200 1201 ctrl->hpc_ctlr_handle = php_ctlr; 1202 ctrl->hpc_ops = &shpchp_hpc_ops; 1203 1204 /* Return PCI Controller Info */ 1205 slot_config = shpc_readl(ctrl, SLOT_CONFIG); 1206 php_ctlr->slot_device_offset = (slot_config & FIRST_DEV_NUM) >> 8; 1207 php_ctlr->num_slots = slot_config & SLOT_NUM; 1208 dbg("%s: slot_device_offset %x\n", __FUNCTION__, php_ctlr->slot_device_offset); 1209 dbg("%s: num_slots %x\n", __FUNCTION__, php_ctlr->num_slots); 1210 1211 /* Mask Global Interrupt Mask & Command Complete Interrupt Mask */ 1212 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE); 1213 dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword); 1214 tempdword |= (GLOBAL_INTR_MASK | GLOBAL_SERR_MASK | 1215 COMMAND_INTR_MASK | ARBITER_SERR_MASK); 1216 tempdword &= ~SERR_INTR_RSVDZ_MASK; 1217 shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword); 1218 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE); 1219 dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword); 1220 1221 /* Mask the MRL sensor SERR Mask of individual slot in 1222 * Slot SERR-INT Mask & clear all the existing event if any 1223 */ 1224 for (hp_slot = 0; hp_slot < php_ctlr->num_slots; hp_slot++) { 1225 slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot)); 1226 dbg("%s: Default Logical Slot Register %d value %x\n", __FUNCTION__, 1227 hp_slot, slot_reg); 1228 slot_reg |= (PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK | 1229 BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK | 1230 CON_PFAULT_INTR_MASK | MRL_CHANGE_SERR_MASK | 1231 CON_PFAULT_SERR_MASK); 1232 slot_reg &= ~SLOT_REG_RSVDZ_MASK; 1233 shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg); 1234 } 1235 1236 if (shpchp_poll_mode) {/* Install interrupt polling code */ 1237 /* Install and start the interrupt polling timer */ 1238 init_timer(&php_ctlr->int_poll_timer); 1239 start_int_poll_timer( php_ctlr, 10 ); /* start with 10 second delay */ 1240 } else { 1241 /* Installs the interrupt handler */ 1242 rc = pci_enable_msi(pdev); 1243 if (rc) { 1244 info("Can't get msi for the hotplug controller\n"); 1245 info("Use INTx for the hotplug controller\n"); 1246 } else 1247 php_ctlr->irq = pdev->irq; 1248 1249 rc = request_irq(php_ctlr->irq, shpc_isr, SA_SHIRQ, MY_NAME, (void *) ctrl); 1250 dbg("%s: request_irq %d for hpc%d (returns %d)\n", __FUNCTION__, php_ctlr->irq, ctlr_seq_num, rc); 1251 if (rc) { 1252 err("Can't get irq %d for the hotplug controller\n", php_ctlr->irq); 1253 goto abort_free_ctlr; 1254 } 1255 } 1256 dbg("%s: HPC at b:d:f:irq=0x%x:%x:%x:%x\n", __FUNCTION__, 1257 pdev->bus->number, PCI_SLOT(pdev->devfn), 1258 PCI_FUNC(pdev->devfn), pdev->irq); 1259 get_hp_hw_control_from_firmware(pdev); 1260 1261 /* Add this HPC instance into the HPC list */ 1262 spin_lock(&list_lock); 1263 if (php_ctlr_list_head == 0) { 1264 php_ctlr_list_head = php_ctlr; 1265 p = php_ctlr_list_head; 1266 p->pnext = NULL; 1267 } else { 1268 p = php_ctlr_list_head; 1269 1270 while (p->pnext) 1271 p = p->pnext; 1272 1273 p->pnext = php_ctlr; 1274 } 1275 spin_unlock(&list_lock); 1276 1277 ctlr_seq_num++; 1278 1279 /* 1280 * If this is the first controller to be initialized, 1281 * initialize the shpchpd work queue 1282 */ 1283 if (atomic_add_return(1, &shpchp_num_controllers) == 1) { 1284 shpchp_wq = create_singlethread_workqueue("shpchpd"); 1285 if (!shpchp_wq) 1286 return -ENOMEM; 1287 } 1288 1289 /* 1290 * Unmask all event interrupts of all slots 1291 */ 1292 for (hp_slot = 0; hp_slot < php_ctlr->num_slots; hp_slot++) { 1293 slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot)); 1294 dbg("%s: Default Logical Slot Register %d value %x\n", __FUNCTION__, 1295 hp_slot, slot_reg); 1296 slot_reg &= ~(PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK | 1297 BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK | 1298 CON_PFAULT_INTR_MASK | SLOT_REG_RSVDZ_MASK); 1299 shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg); 1300 } 1301 if (!shpchp_poll_mode) { 1302 /* Unmask all general input interrupts and SERR */ 1303 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE); 1304 tempdword &= ~(GLOBAL_INTR_MASK | COMMAND_INTR_MASK | 1305 SERR_INTR_RSVDZ_MASK); 1306 shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword); 1307 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE); 1308 dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword); 1309 } 1310 1311 DBG_LEAVE_ROUTINE 1312 return 0; 1313 1314 /* We end up here for the many possible ways to fail this API. */ 1315 abort_free_ctlr: 1316 kfree(php_ctlr); 1317 abort: 1318 DBG_LEAVE_ROUTINE 1319 return -1; 1320 } 1321