1 /* 2 * PCI Express PCI Hot Plug Driver 3 * 4 * Copyright (C) 1995,2001 Compaq Computer Corporation 5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com) 6 * Copyright (C) 2001 IBM Corp. 7 * Copyright (C) 2003-2004 Intel Corporation 8 * 9 * All rights reserved. 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or (at 14 * your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 19 * NON INFRINGEMENT. See the GNU General Public License for more 20 * details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 25 * 26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com> 27 * 28 */ 29 30 #include <linux/kernel.h> 31 #include <linux/module.h> 32 #include <linux/types.h> 33 #include <linux/signal.h> 34 #include <linux/jiffies.h> 35 #include <linux/timer.h> 36 #include <linux/pci.h> 37 #include <linux/interrupt.h> 38 #include <linux/time.h> 39 #include <linux/slab.h> 40 41 #include "../pci.h" 42 #include "pciehp.h" 43 44 static inline int pciehp_readw(struct controller *ctrl, int reg, u16 *value) 45 { 46 struct pci_dev *dev = ctrl->pcie->port; 47 return pci_read_config_word(dev, pci_pcie_cap(dev) + reg, value); 48 } 49 50 static inline int pciehp_readl(struct controller *ctrl, int reg, u32 *value) 51 { 52 struct pci_dev *dev = ctrl->pcie->port; 53 return pci_read_config_dword(dev, pci_pcie_cap(dev) + reg, value); 54 } 55 56 static inline int pciehp_writew(struct controller *ctrl, int reg, u16 value) 57 { 58 struct pci_dev *dev = ctrl->pcie->port; 59 return pci_write_config_word(dev, pci_pcie_cap(dev) + reg, value); 60 } 61 62 static inline int pciehp_writel(struct controller *ctrl, int reg, u32 value) 63 { 64 struct pci_dev *dev = ctrl->pcie->port; 65 return pci_write_config_dword(dev, pci_pcie_cap(dev) + reg, value); 66 } 67 68 /* Power Control Command */ 69 #define POWER_ON 0 70 #define POWER_OFF PCI_EXP_SLTCTL_PCC 71 72 static irqreturn_t pcie_isr(int irq, void *dev_id); 73 static void start_int_poll_timer(struct controller *ctrl, int sec); 74 75 /* This is the interrupt polling timeout function. */ 76 static void int_poll_timeout(unsigned long data) 77 { 78 struct controller *ctrl = (struct controller *)data; 79 80 /* Poll for interrupt events. regs == NULL => polling */ 81 pcie_isr(0, ctrl); 82 83 init_timer(&ctrl->poll_timer); 84 if (!pciehp_poll_time) 85 pciehp_poll_time = 2; /* default polling interval is 2 sec */ 86 87 start_int_poll_timer(ctrl, pciehp_poll_time); 88 } 89 90 /* This function starts the interrupt polling timer. */ 91 static void start_int_poll_timer(struct controller *ctrl, int sec) 92 { 93 /* Clamp to sane value */ 94 if ((sec <= 0) || (sec > 60)) 95 sec = 2; 96 97 ctrl->poll_timer.function = &int_poll_timeout; 98 ctrl->poll_timer.data = (unsigned long)ctrl; 99 ctrl->poll_timer.expires = jiffies + sec * HZ; 100 add_timer(&ctrl->poll_timer); 101 } 102 103 static inline int pciehp_request_irq(struct controller *ctrl) 104 { 105 int retval, irq = ctrl->pcie->irq; 106 107 /* Install interrupt polling timer. Start with 10 sec delay */ 108 if (pciehp_poll_mode) { 109 init_timer(&ctrl->poll_timer); 110 start_int_poll_timer(ctrl, 10); 111 return 0; 112 } 113 114 /* Installs the interrupt handler */ 115 retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl); 116 if (retval) 117 ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n", 118 irq); 119 return retval; 120 } 121 122 static inline void pciehp_free_irq(struct controller *ctrl) 123 { 124 if (pciehp_poll_mode) 125 del_timer_sync(&ctrl->poll_timer); 126 else 127 free_irq(ctrl->pcie->irq, ctrl); 128 } 129 130 static int pcie_poll_cmd(struct controller *ctrl) 131 { 132 u16 slot_status; 133 int err, timeout = 1000; 134 135 err = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); 136 if (!err && (slot_status & PCI_EXP_SLTSTA_CC)) { 137 pciehp_writew(ctrl, PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_CC); 138 return 1; 139 } 140 while (timeout > 0) { 141 msleep(10); 142 timeout -= 10; 143 err = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); 144 if (!err && (slot_status & PCI_EXP_SLTSTA_CC)) { 145 pciehp_writew(ctrl, PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_CC); 146 return 1; 147 } 148 } 149 return 0; /* timeout */ 150 } 151 152 static void pcie_wait_cmd(struct controller *ctrl, int poll) 153 { 154 unsigned int msecs = pciehp_poll_mode ? 2500 : 1000; 155 unsigned long timeout = msecs_to_jiffies(msecs); 156 int rc; 157 158 if (poll) 159 rc = pcie_poll_cmd(ctrl); 160 else 161 rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout); 162 if (!rc) 163 ctrl_dbg(ctrl, "Command not completed in 1000 msec\n"); 164 } 165 166 /** 167 * pcie_write_cmd - Issue controller command 168 * @ctrl: controller to which the command is issued 169 * @cmd: command value written to slot control register 170 * @mask: bitmask of slot control register to be modified 171 */ 172 static int pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask) 173 { 174 int retval = 0; 175 u16 slot_status; 176 u16 slot_ctrl; 177 178 mutex_lock(&ctrl->ctrl_lock); 179 180 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); 181 if (retval) { 182 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n", 183 __func__); 184 goto out; 185 } 186 187 if (slot_status & PCI_EXP_SLTSTA_CC) { 188 if (!ctrl->no_cmd_complete) { 189 /* 190 * After 1 sec and CMD_COMPLETED still not set, just 191 * proceed forward to issue the next command according 192 * to spec. Just print out the error message. 193 */ 194 ctrl_dbg(ctrl, "CMD_COMPLETED not clear after 1 sec\n"); 195 } else if (!NO_CMD_CMPL(ctrl)) { 196 /* 197 * This controller semms to notify of command completed 198 * event even though it supports none of power 199 * controller, attention led, power led and EMI. 200 */ 201 ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Need to " 202 "wait for command completed event.\n"); 203 ctrl->no_cmd_complete = 0; 204 } else { 205 ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Maybe " 206 "the controller is broken.\n"); 207 } 208 } 209 210 retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl); 211 if (retval) { 212 ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__); 213 goto out; 214 } 215 216 slot_ctrl &= ~mask; 217 slot_ctrl |= (cmd & mask); 218 ctrl->cmd_busy = 1; 219 smp_mb(); 220 retval = pciehp_writew(ctrl, PCI_EXP_SLTCTL, slot_ctrl); 221 if (retval) 222 ctrl_err(ctrl, "Cannot write to SLOTCTRL register\n"); 223 224 /* 225 * Wait for command completion. 226 */ 227 if (!retval && !ctrl->no_cmd_complete) { 228 int poll = 0; 229 /* 230 * if hotplug interrupt is not enabled or command 231 * completed interrupt is not enabled, we need to poll 232 * command completed event. 233 */ 234 if (!(slot_ctrl & PCI_EXP_SLTCTL_HPIE) || 235 !(slot_ctrl & PCI_EXP_SLTCTL_CCIE)) 236 poll = 1; 237 pcie_wait_cmd(ctrl, poll); 238 } 239 out: 240 mutex_unlock(&ctrl->ctrl_lock); 241 return retval; 242 } 243 244 static inline int check_link_active(struct controller *ctrl) 245 { 246 u16 link_status; 247 248 if (pciehp_readw(ctrl, PCI_EXP_LNKSTA, &link_status)) 249 return 0; 250 return !!(link_status & PCI_EXP_LNKSTA_DLLLA); 251 } 252 253 static void pcie_wait_link_active(struct controller *ctrl) 254 { 255 int timeout = 1000; 256 257 if (check_link_active(ctrl)) 258 return; 259 while (timeout > 0) { 260 msleep(10); 261 timeout -= 10; 262 if (check_link_active(ctrl)) 263 return; 264 } 265 ctrl_dbg(ctrl, "Data Link Layer Link Active not set in 1000 msec\n"); 266 } 267 268 int pciehp_check_link_status(struct controller *ctrl) 269 { 270 u16 lnk_status; 271 int retval = 0; 272 273 /* 274 * Data Link Layer Link Active Reporting must be capable for 275 * hot-plug capable downstream port. But old controller might 276 * not implement it. In this case, we wait for 1000 ms. 277 */ 278 if (ctrl->link_active_reporting) 279 pcie_wait_link_active(ctrl); 280 else 281 msleep(1000); 282 283 /* 284 * Need to wait for 1000 ms after Data Link Layer Link Active 285 * (DLLLA) bit reads 1b before sending configuration request. 286 * We need it before checking Link Training (LT) bit becuase 287 * LT is still set even after DLLLA bit is set on some platform. 288 */ 289 msleep(1000); 290 291 retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status); 292 if (retval) { 293 ctrl_err(ctrl, "Cannot read LNKSTATUS register\n"); 294 return retval; 295 } 296 297 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status); 298 if ((lnk_status & PCI_EXP_LNKSTA_LT) || 299 !(lnk_status & PCI_EXP_LNKSTA_NLW)) { 300 ctrl_err(ctrl, "Link Training Error occurs \n"); 301 retval = -1; 302 return retval; 303 } 304 305 /* 306 * If the port supports Link speeds greater than 5.0 GT/s, we 307 * must wait for 100 ms after Link training completes before 308 * sending configuration request. 309 */ 310 if (ctrl->pcie->port->subordinate->max_bus_speed > PCIE_SPEED_5_0GT) 311 msleep(100); 312 313 pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status); 314 315 return retval; 316 } 317 318 int pciehp_get_attention_status(struct slot *slot, u8 *status) 319 { 320 struct controller *ctrl = slot->ctrl; 321 u16 slot_ctrl; 322 u8 atten_led_state; 323 int retval = 0; 324 325 retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl); 326 if (retval) { 327 ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__); 328 return retval; 329 } 330 331 ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__, 332 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl); 333 334 atten_led_state = (slot_ctrl & PCI_EXP_SLTCTL_AIC) >> 6; 335 336 switch (atten_led_state) { 337 case 0: 338 *status = 0xFF; /* Reserved */ 339 break; 340 case 1: 341 *status = 1; /* On */ 342 break; 343 case 2: 344 *status = 2; /* Blink */ 345 break; 346 case 3: 347 *status = 0; /* Off */ 348 break; 349 default: 350 *status = 0xFF; 351 break; 352 } 353 354 return 0; 355 } 356 357 int pciehp_get_power_status(struct slot *slot, u8 *status) 358 { 359 struct controller *ctrl = slot->ctrl; 360 u16 slot_ctrl; 361 u8 pwr_state; 362 int retval = 0; 363 364 retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl); 365 if (retval) { 366 ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__); 367 return retval; 368 } 369 ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__, 370 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl); 371 372 pwr_state = (slot_ctrl & PCI_EXP_SLTCTL_PCC) >> 10; 373 374 switch (pwr_state) { 375 case 0: 376 *status = 1; 377 break; 378 case 1: 379 *status = 0; 380 break; 381 default: 382 *status = 0xFF; 383 break; 384 } 385 386 return retval; 387 } 388 389 int pciehp_get_latch_status(struct slot *slot, u8 *status) 390 { 391 struct controller *ctrl = slot->ctrl; 392 u16 slot_status; 393 int retval; 394 395 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); 396 if (retval) { 397 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n", 398 __func__); 399 return retval; 400 } 401 *status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS); 402 return 0; 403 } 404 405 int pciehp_get_adapter_status(struct slot *slot, u8 *status) 406 { 407 struct controller *ctrl = slot->ctrl; 408 u16 slot_status; 409 int retval; 410 411 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); 412 if (retval) { 413 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n", 414 __func__); 415 return retval; 416 } 417 *status = !!(slot_status & PCI_EXP_SLTSTA_PDS); 418 return 0; 419 } 420 421 int pciehp_query_power_fault(struct slot *slot) 422 { 423 struct controller *ctrl = slot->ctrl; 424 u16 slot_status; 425 int retval; 426 427 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); 428 if (retval) { 429 ctrl_err(ctrl, "Cannot check for power fault\n"); 430 return retval; 431 } 432 return !!(slot_status & PCI_EXP_SLTSTA_PFD); 433 } 434 435 int pciehp_set_attention_status(struct slot *slot, u8 value) 436 { 437 struct controller *ctrl = slot->ctrl; 438 u16 slot_cmd; 439 u16 cmd_mask; 440 441 cmd_mask = PCI_EXP_SLTCTL_AIC; 442 switch (value) { 443 case 0 : /* turn off */ 444 slot_cmd = 0x00C0; 445 break; 446 case 1: /* turn on */ 447 slot_cmd = 0x0040; 448 break; 449 case 2: /* turn blink */ 450 slot_cmd = 0x0080; 451 break; 452 default: 453 return -EINVAL; 454 } 455 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 456 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); 457 return pcie_write_cmd(ctrl, slot_cmd, cmd_mask); 458 } 459 460 void pciehp_green_led_on(struct slot *slot) 461 { 462 struct controller *ctrl = slot->ctrl; 463 u16 slot_cmd; 464 u16 cmd_mask; 465 466 slot_cmd = 0x0100; 467 cmd_mask = PCI_EXP_SLTCTL_PIC; 468 pcie_write_cmd(ctrl, slot_cmd, cmd_mask); 469 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 470 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); 471 } 472 473 void pciehp_green_led_off(struct slot *slot) 474 { 475 struct controller *ctrl = slot->ctrl; 476 u16 slot_cmd; 477 u16 cmd_mask; 478 479 slot_cmd = 0x0300; 480 cmd_mask = PCI_EXP_SLTCTL_PIC; 481 pcie_write_cmd(ctrl, slot_cmd, cmd_mask); 482 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 483 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); 484 } 485 486 void pciehp_green_led_blink(struct slot *slot) 487 { 488 struct controller *ctrl = slot->ctrl; 489 u16 slot_cmd; 490 u16 cmd_mask; 491 492 slot_cmd = 0x0200; 493 cmd_mask = PCI_EXP_SLTCTL_PIC; 494 pcie_write_cmd(ctrl, slot_cmd, cmd_mask); 495 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 496 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); 497 } 498 499 int pciehp_power_on_slot(struct slot * slot) 500 { 501 struct controller *ctrl = slot->ctrl; 502 u16 slot_cmd; 503 u16 cmd_mask; 504 u16 slot_status; 505 int retval = 0; 506 507 /* Clear sticky power-fault bit from previous power failures */ 508 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); 509 if (retval) { 510 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n", 511 __func__); 512 return retval; 513 } 514 slot_status &= PCI_EXP_SLTSTA_PFD; 515 if (slot_status) { 516 retval = pciehp_writew(ctrl, PCI_EXP_SLTSTA, slot_status); 517 if (retval) { 518 ctrl_err(ctrl, 519 "%s: Cannot write to SLOTSTATUS register\n", 520 __func__); 521 return retval; 522 } 523 } 524 ctrl->power_fault_detected = 0; 525 526 slot_cmd = POWER_ON; 527 cmd_mask = PCI_EXP_SLTCTL_PCC; 528 retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask); 529 if (retval) { 530 ctrl_err(ctrl, "Write %x command failed!\n", slot_cmd); 531 return retval; 532 } 533 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 534 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); 535 536 return retval; 537 } 538 539 int pciehp_power_off_slot(struct slot * slot) 540 { 541 struct controller *ctrl = slot->ctrl; 542 u16 slot_cmd; 543 u16 cmd_mask; 544 int retval; 545 546 slot_cmd = POWER_OFF; 547 cmd_mask = PCI_EXP_SLTCTL_PCC; 548 retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask); 549 if (retval) { 550 ctrl_err(ctrl, "Write command failed!\n"); 551 return retval; 552 } 553 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 554 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); 555 return 0; 556 } 557 558 static irqreturn_t pcie_isr(int irq, void *dev_id) 559 { 560 struct controller *ctrl = (struct controller *)dev_id; 561 struct slot *slot = ctrl->slot; 562 u16 detected, intr_loc; 563 564 /* 565 * In order to guarantee that all interrupt events are 566 * serviced, we need to re-inspect Slot Status register after 567 * clearing what is presumed to be the last pending interrupt. 568 */ 569 intr_loc = 0; 570 do { 571 if (pciehp_readw(ctrl, PCI_EXP_SLTSTA, &detected)) { 572 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS\n", 573 __func__); 574 return IRQ_NONE; 575 } 576 577 detected &= (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD | 578 PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC | 579 PCI_EXP_SLTSTA_CC); 580 detected &= ~intr_loc; 581 intr_loc |= detected; 582 if (!intr_loc) 583 return IRQ_NONE; 584 if (detected && pciehp_writew(ctrl, PCI_EXP_SLTSTA, intr_loc)) { 585 ctrl_err(ctrl, "%s: Cannot write to SLOTSTATUS\n", 586 __func__); 587 return IRQ_NONE; 588 } 589 } while (detected); 590 591 ctrl_dbg(ctrl, "%s: intr_loc %x\n", __func__, intr_loc); 592 593 /* Check Command Complete Interrupt Pending */ 594 if (intr_loc & PCI_EXP_SLTSTA_CC) { 595 ctrl->cmd_busy = 0; 596 smp_mb(); 597 wake_up(&ctrl->queue); 598 } 599 600 if (!(intr_loc & ~PCI_EXP_SLTSTA_CC)) 601 return IRQ_HANDLED; 602 603 /* Check MRL Sensor Changed */ 604 if (intr_loc & PCI_EXP_SLTSTA_MRLSC) 605 pciehp_handle_switch_change(slot); 606 607 /* Check Attention Button Pressed */ 608 if (intr_loc & PCI_EXP_SLTSTA_ABP) 609 pciehp_handle_attention_button(slot); 610 611 /* Check Presence Detect Changed */ 612 if (intr_loc & PCI_EXP_SLTSTA_PDC) 613 pciehp_handle_presence_change(slot); 614 615 /* Check Power Fault Detected */ 616 if ((intr_loc & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) { 617 ctrl->power_fault_detected = 1; 618 pciehp_handle_power_fault(slot); 619 } 620 return IRQ_HANDLED; 621 } 622 623 int pciehp_get_max_lnk_width(struct slot *slot, 624 enum pcie_link_width *value) 625 { 626 struct controller *ctrl = slot->ctrl; 627 enum pcie_link_width lnk_wdth; 628 u32 lnk_cap; 629 int retval = 0; 630 631 retval = pciehp_readl(ctrl, PCI_EXP_LNKCAP, &lnk_cap); 632 if (retval) { 633 ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__); 634 return retval; 635 } 636 637 switch ((lnk_cap & PCI_EXP_LNKSTA_NLW) >> 4){ 638 case 0: 639 lnk_wdth = PCIE_LNK_WIDTH_RESRV; 640 break; 641 case 1: 642 lnk_wdth = PCIE_LNK_X1; 643 break; 644 case 2: 645 lnk_wdth = PCIE_LNK_X2; 646 break; 647 case 4: 648 lnk_wdth = PCIE_LNK_X4; 649 break; 650 case 8: 651 lnk_wdth = PCIE_LNK_X8; 652 break; 653 case 12: 654 lnk_wdth = PCIE_LNK_X12; 655 break; 656 case 16: 657 lnk_wdth = PCIE_LNK_X16; 658 break; 659 case 32: 660 lnk_wdth = PCIE_LNK_X32; 661 break; 662 default: 663 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; 664 break; 665 } 666 667 *value = lnk_wdth; 668 ctrl_dbg(ctrl, "Max link width = %d\n", lnk_wdth); 669 670 return retval; 671 } 672 673 int pciehp_get_cur_lnk_width(struct slot *slot, 674 enum pcie_link_width *value) 675 { 676 struct controller *ctrl = slot->ctrl; 677 enum pcie_link_width lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; 678 int retval = 0; 679 u16 lnk_status; 680 681 retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status); 682 if (retval) { 683 ctrl_err(ctrl, "%s: Cannot read LNKSTATUS register\n", 684 __func__); 685 return retval; 686 } 687 688 switch ((lnk_status & PCI_EXP_LNKSTA_NLW) >> 4){ 689 case 0: 690 lnk_wdth = PCIE_LNK_WIDTH_RESRV; 691 break; 692 case 1: 693 lnk_wdth = PCIE_LNK_X1; 694 break; 695 case 2: 696 lnk_wdth = PCIE_LNK_X2; 697 break; 698 case 4: 699 lnk_wdth = PCIE_LNK_X4; 700 break; 701 case 8: 702 lnk_wdth = PCIE_LNK_X8; 703 break; 704 case 12: 705 lnk_wdth = PCIE_LNK_X12; 706 break; 707 case 16: 708 lnk_wdth = PCIE_LNK_X16; 709 break; 710 case 32: 711 lnk_wdth = PCIE_LNK_X32; 712 break; 713 default: 714 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; 715 break; 716 } 717 718 *value = lnk_wdth; 719 ctrl_dbg(ctrl, "Current link width = %d\n", lnk_wdth); 720 721 return retval; 722 } 723 724 int pcie_enable_notification(struct controller *ctrl) 725 { 726 u16 cmd, mask; 727 728 /* 729 * TBD: Power fault detected software notification support. 730 * 731 * Power fault detected software notification is not enabled 732 * now, because it caused power fault detected interrupt storm 733 * on some machines. On those machines, power fault detected 734 * bit in the slot status register was set again immediately 735 * when it is cleared in the interrupt service routine, and 736 * next power fault detected interrupt was notified again. 737 */ 738 cmd = PCI_EXP_SLTCTL_PDCE; 739 if (ATTN_BUTTN(ctrl)) 740 cmd |= PCI_EXP_SLTCTL_ABPE; 741 if (MRL_SENS(ctrl)) 742 cmd |= PCI_EXP_SLTCTL_MRLSCE; 743 if (!pciehp_poll_mode) 744 cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE; 745 746 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE | 747 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE | 748 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE); 749 750 if (pcie_write_cmd(ctrl, cmd, mask)) { 751 ctrl_err(ctrl, "Cannot enable software notification\n"); 752 return -1; 753 } 754 return 0; 755 } 756 757 static void pcie_disable_notification(struct controller *ctrl) 758 { 759 u16 mask; 760 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE | 761 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE | 762 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE | 763 PCI_EXP_SLTCTL_DLLSCE); 764 if (pcie_write_cmd(ctrl, 0, mask)) 765 ctrl_warn(ctrl, "Cannot disable software notification\n"); 766 } 767 768 int pcie_init_notification(struct controller *ctrl) 769 { 770 if (pciehp_request_irq(ctrl)) 771 return -1; 772 if (pcie_enable_notification(ctrl)) { 773 pciehp_free_irq(ctrl); 774 return -1; 775 } 776 ctrl->notification_enabled = 1; 777 return 0; 778 } 779 780 static void pcie_shutdown_notification(struct controller *ctrl) 781 { 782 if (ctrl->notification_enabled) { 783 pcie_disable_notification(ctrl); 784 pciehp_free_irq(ctrl); 785 ctrl->notification_enabled = 0; 786 } 787 } 788 789 static int pcie_init_slot(struct controller *ctrl) 790 { 791 struct slot *slot; 792 793 slot = kzalloc(sizeof(*slot), GFP_KERNEL); 794 if (!slot) 795 return -ENOMEM; 796 797 slot->ctrl = ctrl; 798 mutex_init(&slot->lock); 799 INIT_DELAYED_WORK(&slot->work, pciehp_queue_pushbutton_work); 800 ctrl->slot = slot; 801 return 0; 802 } 803 804 static void pcie_cleanup_slot(struct controller *ctrl) 805 { 806 struct slot *slot = ctrl->slot; 807 cancel_delayed_work(&slot->work); 808 flush_workqueue(pciehp_wq); 809 kfree(slot); 810 } 811 812 static inline void dbg_ctrl(struct controller *ctrl) 813 { 814 int i; 815 u16 reg16; 816 struct pci_dev *pdev = ctrl->pcie->port; 817 818 if (!pciehp_debug) 819 return; 820 821 ctrl_info(ctrl, "Hotplug Controller:\n"); 822 ctrl_info(ctrl, " Seg/Bus/Dev/Func/IRQ : %s IRQ %d\n", 823 pci_name(pdev), pdev->irq); 824 ctrl_info(ctrl, " Vendor ID : 0x%04x\n", pdev->vendor); 825 ctrl_info(ctrl, " Device ID : 0x%04x\n", pdev->device); 826 ctrl_info(ctrl, " Subsystem ID : 0x%04x\n", 827 pdev->subsystem_device); 828 ctrl_info(ctrl, " Subsystem Vendor ID : 0x%04x\n", 829 pdev->subsystem_vendor); 830 ctrl_info(ctrl, " PCIe Cap offset : 0x%02x\n", 831 pci_pcie_cap(pdev)); 832 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { 833 if (!pci_resource_len(pdev, i)) 834 continue; 835 ctrl_info(ctrl, " PCI resource [%d] : %pR\n", 836 i, &pdev->resource[i]); 837 } 838 ctrl_info(ctrl, "Slot Capabilities : 0x%08x\n", ctrl->slot_cap); 839 ctrl_info(ctrl, " Physical Slot Number : %d\n", PSN(ctrl)); 840 ctrl_info(ctrl, " Attention Button : %3s\n", 841 ATTN_BUTTN(ctrl) ? "yes" : "no"); 842 ctrl_info(ctrl, " Power Controller : %3s\n", 843 POWER_CTRL(ctrl) ? "yes" : "no"); 844 ctrl_info(ctrl, " MRL Sensor : %3s\n", 845 MRL_SENS(ctrl) ? "yes" : "no"); 846 ctrl_info(ctrl, " Attention Indicator : %3s\n", 847 ATTN_LED(ctrl) ? "yes" : "no"); 848 ctrl_info(ctrl, " Power Indicator : %3s\n", 849 PWR_LED(ctrl) ? "yes" : "no"); 850 ctrl_info(ctrl, " Hot-Plug Surprise : %3s\n", 851 HP_SUPR_RM(ctrl) ? "yes" : "no"); 852 ctrl_info(ctrl, " EMI Present : %3s\n", 853 EMI(ctrl) ? "yes" : "no"); 854 ctrl_info(ctrl, " Command Completed : %3s\n", 855 NO_CMD_CMPL(ctrl) ? "no" : "yes"); 856 pciehp_readw(ctrl, PCI_EXP_SLTSTA, ®16); 857 ctrl_info(ctrl, "Slot Status : 0x%04x\n", reg16); 858 pciehp_readw(ctrl, PCI_EXP_SLTCTL, ®16); 859 ctrl_info(ctrl, "Slot Control : 0x%04x\n", reg16); 860 } 861 862 struct controller *pcie_init(struct pcie_device *dev) 863 { 864 struct controller *ctrl; 865 u32 slot_cap, link_cap; 866 struct pci_dev *pdev = dev->port; 867 868 ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL); 869 if (!ctrl) { 870 dev_err(&dev->device, "%s: Out of memory\n", __func__); 871 goto abort; 872 } 873 ctrl->pcie = dev; 874 if (!pci_pcie_cap(pdev)) { 875 ctrl_err(ctrl, "Cannot find PCI Express capability\n"); 876 goto abort_ctrl; 877 } 878 if (pciehp_readl(ctrl, PCI_EXP_SLTCAP, &slot_cap)) { 879 ctrl_err(ctrl, "Cannot read SLOTCAP register\n"); 880 goto abort_ctrl; 881 } 882 883 ctrl->slot_cap = slot_cap; 884 mutex_init(&ctrl->ctrl_lock); 885 init_waitqueue_head(&ctrl->queue); 886 dbg_ctrl(ctrl); 887 /* 888 * Controller doesn't notify of command completion if the "No 889 * Command Completed Support" bit is set in Slot Capability 890 * register or the controller supports none of power 891 * controller, attention led, power led and EMI. 892 */ 893 if (NO_CMD_CMPL(ctrl) || 894 !(POWER_CTRL(ctrl) | ATTN_LED(ctrl) | PWR_LED(ctrl) | EMI(ctrl))) 895 ctrl->no_cmd_complete = 1; 896 897 /* Check if Data Link Layer Link Active Reporting is implemented */ 898 if (pciehp_readl(ctrl, PCI_EXP_LNKCAP, &link_cap)) { 899 ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__); 900 goto abort_ctrl; 901 } 902 if (link_cap & PCI_EXP_LNKCAP_DLLLARC) { 903 ctrl_dbg(ctrl, "Link Active Reporting supported\n"); 904 ctrl->link_active_reporting = 1; 905 } 906 907 /* Clear all remaining event bits in Slot Status register */ 908 if (pciehp_writew(ctrl, PCI_EXP_SLTSTA, 0x1f)) 909 goto abort_ctrl; 910 911 /* Disable sotfware notification */ 912 pcie_disable_notification(ctrl); 913 914 ctrl_info(ctrl, "HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", 915 pdev->vendor, pdev->device, pdev->subsystem_vendor, 916 pdev->subsystem_device); 917 918 if (pcie_init_slot(ctrl)) 919 goto abort_ctrl; 920 921 return ctrl; 922 923 abort_ctrl: 924 kfree(ctrl); 925 abort: 926 return NULL; 927 } 928 929 void pciehp_release_ctrl(struct controller *ctrl) 930 { 931 pcie_shutdown_notification(ctrl); 932 pcie_cleanup_slot(ctrl); 933 kfree(ctrl); 934 } 935