xref: /linux/drivers/pci/hotplug/pciehp_hpc.c (revision 78964fcac47fc1525ecb4c37cd5fbc873c28320b)
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * PCI Express PCI Hot Plug Driver
4  *
5  * Copyright (C) 1995,2001 Compaq Computer Corporation
6  * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
7  * Copyright (C) 2001 IBM Corp.
8  * Copyright (C) 2003-2004 Intel Corporation
9  *
10  * All rights reserved.
11  *
12  * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
13  */
14 
15 #define dev_fmt(fmt) "pciehp: " fmt
16 
17 #include <linux/dmi.h>
18 #include <linux/kernel.h>
19 #include <linux/types.h>
20 #include <linux/jiffies.h>
21 #include <linux/kthread.h>
22 #include <linux/pci.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/interrupt.h>
25 #include <linux/slab.h>
26 
27 #include "../pci.h"
28 #include "pciehp.h"
29 
30 static const struct dmi_system_id inband_presence_disabled_dmi_table[] = {
31 	/*
32 	 * Match all Dell systems, as some Dell systems have inband
33 	 * presence disabled on NVMe slots (but don't support the bit to
34 	 * report it). Setting inband presence disabled should have no
35 	 * negative effect, except on broken hotplug slots that never
36 	 * assert presence detect--and those will still work, they will
37 	 * just have a bit of extra delay before being probed.
38 	 */
39 	{
40 		.ident = "Dell System",
41 		.matches = {
42 			DMI_MATCH(DMI_OEM_STRING, "Dell System"),
43 		},
44 	},
45 	{}
46 };
47 
48 static inline struct pci_dev *ctrl_dev(struct controller *ctrl)
49 {
50 	return ctrl->pcie->port;
51 }
52 
53 static irqreturn_t pciehp_isr(int irq, void *dev_id);
54 static irqreturn_t pciehp_ist(int irq, void *dev_id);
55 static int pciehp_poll(void *data);
56 
57 static inline int pciehp_request_irq(struct controller *ctrl)
58 {
59 	int retval, irq = ctrl->pcie->irq;
60 
61 	if (pciehp_poll_mode) {
62 		ctrl->poll_thread = kthread_run(&pciehp_poll, ctrl,
63 						"pciehp_poll-%s",
64 						slot_name(ctrl));
65 		return PTR_ERR_OR_ZERO(ctrl->poll_thread);
66 	}
67 
68 	/* Installs the interrupt handler */
69 	retval = request_threaded_irq(irq, pciehp_isr, pciehp_ist,
70 				      IRQF_SHARED, "pciehp", ctrl);
71 	if (retval)
72 		ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n",
73 			 irq);
74 	return retval;
75 }
76 
77 static inline void pciehp_free_irq(struct controller *ctrl)
78 {
79 	if (pciehp_poll_mode)
80 		kthread_stop(ctrl->poll_thread);
81 	else
82 		free_irq(ctrl->pcie->irq, ctrl);
83 }
84 
85 static int pcie_poll_cmd(struct controller *ctrl, int timeout)
86 {
87 	struct pci_dev *pdev = ctrl_dev(ctrl);
88 	u16 slot_status;
89 
90 	do {
91 		pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
92 		if (PCI_POSSIBLE_ERROR(slot_status)) {
93 			ctrl_info(ctrl, "%s: no response from device\n",
94 				  __func__);
95 			return 0;
96 		}
97 
98 		if (slot_status & PCI_EXP_SLTSTA_CC) {
99 			pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
100 						   PCI_EXP_SLTSTA_CC);
101 			ctrl->cmd_busy = 0;
102 			smp_mb();
103 			return 1;
104 		}
105 		msleep(10);
106 		timeout -= 10;
107 	} while (timeout >= 0);
108 	return 0;	/* timeout */
109 }
110 
111 static void pcie_wait_cmd(struct controller *ctrl)
112 {
113 	unsigned int msecs = pciehp_poll_mode ? 2500 : 1000;
114 	unsigned long duration = msecs_to_jiffies(msecs);
115 	unsigned long cmd_timeout = ctrl->cmd_started + duration;
116 	unsigned long now, timeout;
117 	int rc;
118 
119 	/*
120 	 * If the controller does not generate notifications for command
121 	 * completions, we never need to wait between writes.
122 	 */
123 	if (NO_CMD_CMPL(ctrl))
124 		return;
125 
126 	if (!ctrl->cmd_busy)
127 		return;
128 
129 	/*
130 	 * Even if the command has already timed out, we want to call
131 	 * pcie_poll_cmd() so it can clear PCI_EXP_SLTSTA_CC.
132 	 */
133 	now = jiffies;
134 	if (time_before_eq(cmd_timeout, now))
135 		timeout = 1;
136 	else
137 		timeout = cmd_timeout - now;
138 
139 	if (ctrl->slot_ctrl & PCI_EXP_SLTCTL_HPIE &&
140 	    ctrl->slot_ctrl & PCI_EXP_SLTCTL_CCIE)
141 		rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout);
142 	else
143 		rc = pcie_poll_cmd(ctrl, jiffies_to_msecs(timeout));
144 
145 	if (!rc)
146 		ctrl_info(ctrl, "Timeout on hotplug command %#06x (issued %u msec ago)\n",
147 			  ctrl->slot_ctrl,
148 			  jiffies_to_msecs(jiffies - ctrl->cmd_started));
149 }
150 
151 #define CC_ERRATUM_MASK		(PCI_EXP_SLTCTL_PCC |	\
152 				 PCI_EXP_SLTCTL_PIC |	\
153 				 PCI_EXP_SLTCTL_AIC |	\
154 				 PCI_EXP_SLTCTL_EIC)
155 
156 static void pcie_do_write_cmd(struct controller *ctrl, u16 cmd,
157 			      u16 mask, bool wait)
158 {
159 	struct pci_dev *pdev = ctrl_dev(ctrl);
160 	u16 slot_ctrl_orig, slot_ctrl;
161 
162 	mutex_lock(&ctrl->ctrl_lock);
163 
164 	/*
165 	 * Always wait for any previous command that might still be in progress
166 	 */
167 	pcie_wait_cmd(ctrl);
168 
169 	pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
170 	if (PCI_POSSIBLE_ERROR(slot_ctrl)) {
171 		ctrl_info(ctrl, "%s: no response from device\n", __func__);
172 		goto out;
173 	}
174 
175 	slot_ctrl_orig = slot_ctrl;
176 	slot_ctrl &= ~mask;
177 	slot_ctrl |= (cmd & mask);
178 	ctrl->cmd_busy = 1;
179 	smp_mb();
180 	ctrl->slot_ctrl = slot_ctrl;
181 	pcie_capability_write_word(pdev, PCI_EXP_SLTCTL, slot_ctrl);
182 	ctrl->cmd_started = jiffies;
183 
184 	/*
185 	 * Controllers with the Intel CF118 and similar errata advertise
186 	 * Command Completed support, but they only set Command Completed
187 	 * if we change the "Control" bits for power, power indicator,
188 	 * attention indicator, or interlock.  If we only change the
189 	 * "Enable" bits, they never set the Command Completed bit.
190 	 */
191 	if (pdev->broken_cmd_compl &&
192 	    (slot_ctrl_orig & CC_ERRATUM_MASK) == (slot_ctrl & CC_ERRATUM_MASK))
193 		ctrl->cmd_busy = 0;
194 
195 	/*
196 	 * Optionally wait for the hardware to be ready for a new command,
197 	 * indicating completion of the above issued command.
198 	 */
199 	if (wait)
200 		pcie_wait_cmd(ctrl);
201 
202 out:
203 	mutex_unlock(&ctrl->ctrl_lock);
204 }
205 
206 /**
207  * pcie_write_cmd - Issue controller command
208  * @ctrl: controller to which the command is issued
209  * @cmd:  command value written to slot control register
210  * @mask: bitmask of slot control register to be modified
211  */
212 static void pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask)
213 {
214 	pcie_do_write_cmd(ctrl, cmd, mask, true);
215 }
216 
217 /* Same as above without waiting for the hardware to latch */
218 static void pcie_write_cmd_nowait(struct controller *ctrl, u16 cmd, u16 mask)
219 {
220 	pcie_do_write_cmd(ctrl, cmd, mask, false);
221 }
222 
223 /**
224  * pciehp_check_link_active() - Is the link active
225  * @ctrl: PCIe hotplug controller
226  *
227  * Check whether the downstream link is currently active. Note it is
228  * possible that the card is removed immediately after this so the
229  * caller may need to take it into account.
230  *
231  * If the hotplug controller itself is not available anymore returns
232  * %-ENODEV.
233  */
234 int pciehp_check_link_active(struct controller *ctrl)
235 {
236 	struct pci_dev *pdev = ctrl_dev(ctrl);
237 	u16 lnk_status;
238 	int ret;
239 
240 	ret = pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
241 	if (ret == PCIBIOS_DEVICE_NOT_FOUND || PCI_POSSIBLE_ERROR(lnk_status))
242 		return -ENODEV;
243 
244 	ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA);
245 	ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
246 
247 	return ret;
248 }
249 
250 static bool pci_bus_check_dev(struct pci_bus *bus, int devfn)
251 {
252 	u32 l;
253 	int count = 0;
254 	int delay = 1000, step = 20;
255 	bool found = false;
256 
257 	do {
258 		found = pci_bus_read_dev_vendor_id(bus, devfn, &l, 0);
259 		count++;
260 
261 		if (found)
262 			break;
263 
264 		msleep(step);
265 		delay -= step;
266 	} while (delay > 0);
267 
268 	if (count > 1)
269 		pr_debug("pci %04x:%02x:%02x.%d id reading try %d times with interval %d ms to get %08x\n",
270 			pci_domain_nr(bus), bus->number, PCI_SLOT(devfn),
271 			PCI_FUNC(devfn), count, step, l);
272 
273 	return found;
274 }
275 
276 static void pcie_wait_for_presence(struct pci_dev *pdev)
277 {
278 	int timeout = 1250;
279 	u16 slot_status;
280 
281 	do {
282 		pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
283 		if (slot_status & PCI_EXP_SLTSTA_PDS)
284 			return;
285 		msleep(10);
286 		timeout -= 10;
287 	} while (timeout > 0);
288 }
289 
290 int pciehp_check_link_status(struct controller *ctrl)
291 {
292 	struct pci_dev *pdev = ctrl_dev(ctrl);
293 	bool found;
294 	u16 lnk_status;
295 
296 	if (!pcie_wait_for_link(pdev, true)) {
297 		ctrl_info(ctrl, "Slot(%s): No link\n", slot_name(ctrl));
298 		return -1;
299 	}
300 
301 	if (ctrl->inband_presence_disabled)
302 		pcie_wait_for_presence(pdev);
303 
304 	found = pci_bus_check_dev(ctrl->pcie->port->subordinate,
305 					PCI_DEVFN(0, 0));
306 
307 	/* ignore link or presence changes up to this point */
308 	if (found)
309 		atomic_and(~(PCI_EXP_SLTSTA_DLLSC | PCI_EXP_SLTSTA_PDC),
310 			   &ctrl->pending_events);
311 
312 	pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
313 	ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
314 	if ((lnk_status & PCI_EXP_LNKSTA_LT) ||
315 	    !(lnk_status & PCI_EXP_LNKSTA_NLW)) {
316 		ctrl_info(ctrl, "Slot(%s): Cannot train link: status %#06x\n",
317 			  slot_name(ctrl), lnk_status);
318 		return -1;
319 	}
320 
321 	pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status);
322 
323 	if (!found) {
324 		ctrl_info(ctrl, "Slot(%s): No device found\n",
325 			  slot_name(ctrl));
326 		return -1;
327 	}
328 
329 	return 0;
330 }
331 
332 static int __pciehp_link_set(struct controller *ctrl, bool enable)
333 {
334 	struct pci_dev *pdev = ctrl_dev(ctrl);
335 
336 	pcie_capability_clear_and_set_word(pdev, PCI_EXP_LNKCTL,
337 					   PCI_EXP_LNKCTL_LD,
338 					   enable ? 0 : PCI_EXP_LNKCTL_LD);
339 
340 	return 0;
341 }
342 
343 static int pciehp_link_enable(struct controller *ctrl)
344 {
345 	return __pciehp_link_set(ctrl, true);
346 }
347 
348 int pciehp_get_raw_indicator_status(struct hotplug_slot *hotplug_slot,
349 				    u8 *status)
350 {
351 	struct controller *ctrl = to_ctrl(hotplug_slot);
352 	struct pci_dev *pdev = ctrl_dev(ctrl);
353 	u16 slot_ctrl;
354 
355 	pci_config_pm_runtime_get(pdev);
356 	pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
357 	pci_config_pm_runtime_put(pdev);
358 	*status = (slot_ctrl & (PCI_EXP_SLTCTL_AIC | PCI_EXP_SLTCTL_PIC)) >> 6;
359 	return 0;
360 }
361 
362 int pciehp_get_attention_status(struct hotplug_slot *hotplug_slot, u8 *status)
363 {
364 	struct controller *ctrl = to_ctrl(hotplug_slot);
365 	struct pci_dev *pdev = ctrl_dev(ctrl);
366 	u16 slot_ctrl;
367 
368 	pci_config_pm_runtime_get(pdev);
369 	pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
370 	pci_config_pm_runtime_put(pdev);
371 	ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__,
372 		 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
373 
374 	switch (slot_ctrl & PCI_EXP_SLTCTL_AIC) {
375 	case PCI_EXP_SLTCTL_ATTN_IND_ON:
376 		*status = 1;	/* On */
377 		break;
378 	case PCI_EXP_SLTCTL_ATTN_IND_BLINK:
379 		*status = 2;	/* Blink */
380 		break;
381 	case PCI_EXP_SLTCTL_ATTN_IND_OFF:
382 		*status = 0;	/* Off */
383 		break;
384 	default:
385 		*status = 0xFF;
386 		break;
387 	}
388 
389 	return 0;
390 }
391 
392 void pciehp_get_power_status(struct controller *ctrl, u8 *status)
393 {
394 	struct pci_dev *pdev = ctrl_dev(ctrl);
395 	u16 slot_ctrl;
396 
397 	pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
398 	ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__,
399 		 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
400 
401 	switch (slot_ctrl & PCI_EXP_SLTCTL_PCC) {
402 	case PCI_EXP_SLTCTL_PWR_ON:
403 		*status = 1;	/* On */
404 		break;
405 	case PCI_EXP_SLTCTL_PWR_OFF:
406 		*status = 0;	/* Off */
407 		break;
408 	default:
409 		*status = 0xFF;
410 		break;
411 	}
412 }
413 
414 void pciehp_get_latch_status(struct controller *ctrl, u8 *status)
415 {
416 	struct pci_dev *pdev = ctrl_dev(ctrl);
417 	u16 slot_status;
418 
419 	pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
420 	*status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS);
421 }
422 
423 /**
424  * pciehp_card_present() - Is the card present
425  * @ctrl: PCIe hotplug controller
426  *
427  * Function checks whether the card is currently present in the slot and
428  * in that case returns true. Note it is possible that the card is
429  * removed immediately after the check so the caller may need to take
430  * this into account.
431  *
432  * It the hotplug controller itself is not available anymore returns
433  * %-ENODEV.
434  */
435 int pciehp_card_present(struct controller *ctrl)
436 {
437 	struct pci_dev *pdev = ctrl_dev(ctrl);
438 	u16 slot_status;
439 	int ret;
440 
441 	ret = pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
442 	if (ret == PCIBIOS_DEVICE_NOT_FOUND || PCI_POSSIBLE_ERROR(slot_status))
443 		return -ENODEV;
444 
445 	return !!(slot_status & PCI_EXP_SLTSTA_PDS);
446 }
447 
448 /**
449  * pciehp_card_present_or_link_active() - whether given slot is occupied
450  * @ctrl: PCIe hotplug controller
451  *
452  * Unlike pciehp_card_present(), which determines presence solely from the
453  * Presence Detect State bit, this helper also returns true if the Link Active
454  * bit is set.  This is a concession to broken hotplug ports which hardwire
455  * Presence Detect State to zero, such as Wilocity's [1ae9:0200].
456  *
457  * Returns: %1 if the slot is occupied and %0 if it is not. If the hotplug
458  *	    port is not present anymore returns %-ENODEV.
459  */
460 int pciehp_card_present_or_link_active(struct controller *ctrl)
461 {
462 	int ret;
463 
464 	ret = pciehp_card_present(ctrl);
465 	if (ret)
466 		return ret;
467 
468 	return pciehp_check_link_active(ctrl);
469 }
470 
471 int pciehp_query_power_fault(struct controller *ctrl)
472 {
473 	struct pci_dev *pdev = ctrl_dev(ctrl);
474 	u16 slot_status;
475 
476 	pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
477 	return !!(slot_status & PCI_EXP_SLTSTA_PFD);
478 }
479 
480 int pciehp_set_raw_indicator_status(struct hotplug_slot *hotplug_slot,
481 				    u8 status)
482 {
483 	struct controller *ctrl = to_ctrl(hotplug_slot);
484 	struct pci_dev *pdev = ctrl_dev(ctrl);
485 
486 	pci_config_pm_runtime_get(pdev);
487 	pcie_write_cmd_nowait(ctrl, status << 6,
488 			      PCI_EXP_SLTCTL_AIC | PCI_EXP_SLTCTL_PIC);
489 	pci_config_pm_runtime_put(pdev);
490 	return 0;
491 }
492 
493 /**
494  * pciehp_set_indicators() - set attention indicator, power indicator, or both
495  * @ctrl: PCIe hotplug controller
496  * @pwr: one of:
497  *	PCI_EXP_SLTCTL_PWR_IND_ON
498  *	PCI_EXP_SLTCTL_PWR_IND_BLINK
499  *	PCI_EXP_SLTCTL_PWR_IND_OFF
500  * @attn: one of:
501  *	PCI_EXP_SLTCTL_ATTN_IND_ON
502  *	PCI_EXP_SLTCTL_ATTN_IND_BLINK
503  *	PCI_EXP_SLTCTL_ATTN_IND_OFF
504  *
505  * Either @pwr or @attn can also be INDICATOR_NOOP to leave that indicator
506  * unchanged.
507  */
508 void pciehp_set_indicators(struct controller *ctrl, int pwr, int attn)
509 {
510 	u16 cmd = 0, mask = 0;
511 
512 	if (PWR_LED(ctrl) && pwr != INDICATOR_NOOP) {
513 		cmd |= (pwr & PCI_EXP_SLTCTL_PIC);
514 		mask |= PCI_EXP_SLTCTL_PIC;
515 	}
516 
517 	if (ATTN_LED(ctrl) && attn != INDICATOR_NOOP) {
518 		cmd |= (attn & PCI_EXP_SLTCTL_AIC);
519 		mask |= PCI_EXP_SLTCTL_AIC;
520 	}
521 
522 	if (cmd) {
523 		pcie_write_cmd_nowait(ctrl, cmd, mask);
524 		ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
525 			 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, cmd);
526 	}
527 }
528 
529 int pciehp_power_on_slot(struct controller *ctrl)
530 {
531 	struct pci_dev *pdev = ctrl_dev(ctrl);
532 	u16 slot_status;
533 	int retval;
534 
535 	/* Clear power-fault bit from previous power failures */
536 	pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
537 	if (slot_status & PCI_EXP_SLTSTA_PFD)
538 		pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
539 					   PCI_EXP_SLTSTA_PFD);
540 	ctrl->power_fault_detected = 0;
541 
542 	pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_ON, PCI_EXP_SLTCTL_PCC);
543 	ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
544 		 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
545 		 PCI_EXP_SLTCTL_PWR_ON);
546 
547 	retval = pciehp_link_enable(ctrl);
548 	if (retval)
549 		ctrl_err(ctrl, "%s: Can not enable the link!\n", __func__);
550 
551 	return retval;
552 }
553 
554 void pciehp_power_off_slot(struct controller *ctrl)
555 {
556 	pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_OFF, PCI_EXP_SLTCTL_PCC);
557 	ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
558 		 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
559 		 PCI_EXP_SLTCTL_PWR_OFF);
560 }
561 
562 static void pciehp_ignore_dpc_link_change(struct controller *ctrl,
563 					  struct pci_dev *pdev, int irq)
564 {
565 	/*
566 	 * Ignore link changes which occurred while waiting for DPC recovery.
567 	 * Could be several if DPC triggered multiple times consecutively.
568 	 */
569 	synchronize_hardirq(irq);
570 	atomic_and(~PCI_EXP_SLTSTA_DLLSC, &ctrl->pending_events);
571 	if (pciehp_poll_mode)
572 		pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
573 					   PCI_EXP_SLTSTA_DLLSC);
574 	ctrl_info(ctrl, "Slot(%s): Link Down/Up ignored (recovered by DPC)\n",
575 		  slot_name(ctrl));
576 
577 	/*
578 	 * If the link is unexpectedly down after successful recovery,
579 	 * the corresponding link change may have been ignored above.
580 	 * Synthesize it to ensure that it is acted on.
581 	 */
582 	down_read_nested(&ctrl->reset_lock, ctrl->depth);
583 	if (!pciehp_check_link_active(ctrl))
584 		pciehp_request(ctrl, PCI_EXP_SLTSTA_DLLSC);
585 	up_read(&ctrl->reset_lock);
586 }
587 
588 static irqreturn_t pciehp_isr(int irq, void *dev_id)
589 {
590 	struct controller *ctrl = (struct controller *)dev_id;
591 	struct pci_dev *pdev = ctrl_dev(ctrl);
592 	struct device *parent = pdev->dev.parent;
593 	u16 status, events = 0;
594 
595 	/*
596 	 * Interrupts only occur in D3hot or shallower and only if enabled
597 	 * in the Slot Control register (PCIe r4.0, sec 6.7.3.4).
598 	 */
599 	if (pdev->current_state == PCI_D3cold ||
600 	    (!(ctrl->slot_ctrl & PCI_EXP_SLTCTL_HPIE) && !pciehp_poll_mode))
601 		return IRQ_NONE;
602 
603 	/*
604 	 * Keep the port accessible by holding a runtime PM ref on its parent.
605 	 * Defer resume of the parent to the IRQ thread if it's suspended.
606 	 * Mask the interrupt until then.
607 	 */
608 	if (parent) {
609 		pm_runtime_get_noresume(parent);
610 		if (!pm_runtime_active(parent)) {
611 			pm_runtime_put(parent);
612 			disable_irq_nosync(irq);
613 			atomic_or(RERUN_ISR, &ctrl->pending_events);
614 			return IRQ_WAKE_THREAD;
615 		}
616 	}
617 
618 read_status:
619 	pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &status);
620 	if (PCI_POSSIBLE_ERROR(status)) {
621 		ctrl_info(ctrl, "%s: no response from device\n", __func__);
622 		if (parent)
623 			pm_runtime_put(parent);
624 		return IRQ_NONE;
625 	}
626 
627 	/*
628 	 * Slot Status contains plain status bits as well as event
629 	 * notification bits; right now we only want the event bits.
630 	 */
631 	status &= PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
632 		  PCI_EXP_SLTSTA_PDC | PCI_EXP_SLTSTA_CC |
633 		  PCI_EXP_SLTSTA_DLLSC;
634 
635 	/*
636 	 * If we've already reported a power fault, don't report it again
637 	 * until we've done something to handle it.
638 	 */
639 	if (ctrl->power_fault_detected)
640 		status &= ~PCI_EXP_SLTSTA_PFD;
641 	else if (status & PCI_EXP_SLTSTA_PFD)
642 		ctrl->power_fault_detected = true;
643 
644 	events |= status;
645 	if (!events) {
646 		if (parent)
647 			pm_runtime_put(parent);
648 		return IRQ_NONE;
649 	}
650 
651 	if (status) {
652 		pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, status);
653 
654 		/*
655 		 * In MSI mode, all event bits must be zero before the port
656 		 * will send a new interrupt (PCIe Base Spec r5.0 sec 6.7.3.4).
657 		 * So re-read the Slot Status register in case a bit was set
658 		 * between read and write.
659 		 */
660 		if (pci_dev_msi_enabled(pdev) && !pciehp_poll_mode)
661 			goto read_status;
662 	}
663 
664 	ctrl_dbg(ctrl, "pending interrupts %#06x from Slot Status\n", events);
665 	if (parent)
666 		pm_runtime_put(parent);
667 
668 	/*
669 	 * Command Completed notifications are not deferred to the
670 	 * IRQ thread because it may be waiting for their arrival.
671 	 */
672 	if (events & PCI_EXP_SLTSTA_CC) {
673 		ctrl->cmd_busy = 0;
674 		smp_mb();
675 		wake_up(&ctrl->queue);
676 
677 		if (events == PCI_EXP_SLTSTA_CC)
678 			return IRQ_HANDLED;
679 
680 		events &= ~PCI_EXP_SLTSTA_CC;
681 	}
682 
683 	if (pdev->ignore_hotplug) {
684 		ctrl_dbg(ctrl, "ignoring hotplug event %#06x\n", events);
685 		return IRQ_HANDLED;
686 	}
687 
688 	/* Save pending events for consumption by IRQ thread. */
689 	atomic_or(events, &ctrl->pending_events);
690 	return IRQ_WAKE_THREAD;
691 }
692 
693 static irqreturn_t pciehp_ist(int irq, void *dev_id)
694 {
695 	struct controller *ctrl = (struct controller *)dev_id;
696 	struct pci_dev *pdev = ctrl_dev(ctrl);
697 	irqreturn_t ret;
698 	u32 events;
699 
700 	ctrl->ist_running = true;
701 	pci_config_pm_runtime_get(pdev);
702 
703 	/* rerun pciehp_isr() if the port was inaccessible on interrupt */
704 	if (atomic_fetch_and(~RERUN_ISR, &ctrl->pending_events) & RERUN_ISR) {
705 		ret = pciehp_isr(irq, dev_id);
706 		enable_irq(irq);
707 		if (ret != IRQ_WAKE_THREAD)
708 			goto out;
709 	}
710 
711 	synchronize_hardirq(irq);
712 	events = atomic_xchg(&ctrl->pending_events, 0);
713 	if (!events) {
714 		ret = IRQ_NONE;
715 		goto out;
716 	}
717 
718 	/* Check Attention Button Pressed */
719 	if (events & PCI_EXP_SLTSTA_ABP)
720 		pciehp_handle_button_press(ctrl);
721 
722 	/* Check Power Fault Detected */
723 	if (events & PCI_EXP_SLTSTA_PFD) {
724 		ctrl_err(ctrl, "Slot(%s): Power fault\n", slot_name(ctrl));
725 		pciehp_set_indicators(ctrl, PCI_EXP_SLTCTL_PWR_IND_OFF,
726 				      PCI_EXP_SLTCTL_ATTN_IND_ON);
727 	}
728 
729 	/*
730 	 * Ignore Link Down/Up events caused by Downstream Port Containment
731 	 * if recovery from the error succeeded.
732 	 */
733 	if ((events & PCI_EXP_SLTSTA_DLLSC) && pci_dpc_recovered(pdev) &&
734 	    ctrl->state == ON_STATE) {
735 		events &= ~PCI_EXP_SLTSTA_DLLSC;
736 		pciehp_ignore_dpc_link_change(ctrl, pdev, irq);
737 	}
738 
739 	/*
740 	 * Disable requests have higher priority than Presence Detect Changed
741 	 * or Data Link Layer State Changed events.
742 	 */
743 	down_read_nested(&ctrl->reset_lock, ctrl->depth);
744 	if (events & DISABLE_SLOT)
745 		pciehp_handle_disable_request(ctrl);
746 	else if (events & (PCI_EXP_SLTSTA_PDC | PCI_EXP_SLTSTA_DLLSC))
747 		pciehp_handle_presence_or_link_change(ctrl, events);
748 	up_read(&ctrl->reset_lock);
749 
750 	ret = IRQ_HANDLED;
751 out:
752 	pci_config_pm_runtime_put(pdev);
753 	ctrl->ist_running = false;
754 	wake_up(&ctrl->requester);
755 	return ret;
756 }
757 
758 static int pciehp_poll(void *data)
759 {
760 	struct controller *ctrl = data;
761 
762 	schedule_timeout_idle(10 * HZ); /* start with 10 sec delay */
763 
764 	while (!kthread_should_stop()) {
765 		/* poll for interrupt events or user requests */
766 		while (pciehp_isr(IRQ_NOTCONNECTED, ctrl) == IRQ_WAKE_THREAD ||
767 		       atomic_read(&ctrl->pending_events))
768 			pciehp_ist(IRQ_NOTCONNECTED, ctrl);
769 
770 		if (pciehp_poll_time <= 0 || pciehp_poll_time > 60)
771 			pciehp_poll_time = 2; /* clamp to sane value */
772 
773 		schedule_timeout_idle(pciehp_poll_time * HZ);
774 	}
775 
776 	return 0;
777 }
778 
779 static void pcie_enable_notification(struct controller *ctrl)
780 {
781 	u16 cmd, mask;
782 
783 	/*
784 	 * TBD: Power fault detected software notification support.
785 	 *
786 	 * Power fault detected software notification is not enabled
787 	 * now, because it caused power fault detected interrupt storm
788 	 * on some machines. On those machines, power fault detected
789 	 * bit in the slot status register was set again immediately
790 	 * when it is cleared in the interrupt service routine, and
791 	 * next power fault detected interrupt was notified again.
792 	 */
793 
794 	/*
795 	 * Always enable link events: thus link-up and link-down shall
796 	 * always be treated as hotplug and unplug respectively. Enable
797 	 * presence detect only if Attention Button is not present.
798 	 */
799 	cmd = PCI_EXP_SLTCTL_DLLSCE;
800 	if (ATTN_BUTTN(ctrl))
801 		cmd |= PCI_EXP_SLTCTL_ABPE;
802 	else
803 		cmd |= PCI_EXP_SLTCTL_PDCE;
804 	if (!pciehp_poll_mode)
805 		cmd |= PCI_EXP_SLTCTL_HPIE;
806 	if (!pciehp_poll_mode && !NO_CMD_CMPL(ctrl))
807 		cmd |= PCI_EXP_SLTCTL_CCIE;
808 
809 	mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
810 		PCI_EXP_SLTCTL_PFDE |
811 		PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
812 		PCI_EXP_SLTCTL_DLLSCE);
813 
814 	pcie_write_cmd_nowait(ctrl, cmd, mask);
815 	ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
816 		 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, cmd);
817 }
818 
819 static void pcie_disable_notification(struct controller *ctrl)
820 {
821 	u16 mask;
822 
823 	mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
824 		PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
825 		PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
826 		PCI_EXP_SLTCTL_DLLSCE);
827 	pcie_write_cmd(ctrl, 0, mask);
828 	ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
829 		 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0);
830 }
831 
832 void pcie_clear_hotplug_events(struct controller *ctrl)
833 {
834 	pcie_capability_write_word(ctrl_dev(ctrl), PCI_EXP_SLTSTA,
835 				   PCI_EXP_SLTSTA_PDC | PCI_EXP_SLTSTA_DLLSC);
836 }
837 
838 void pcie_enable_interrupt(struct controller *ctrl)
839 {
840 	u16 mask;
841 
842 	mask = PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_DLLSCE;
843 	pcie_write_cmd(ctrl, mask, mask);
844 }
845 
846 void pcie_disable_interrupt(struct controller *ctrl)
847 {
848 	u16 mask;
849 
850 	/*
851 	 * Mask hot-plug interrupt to prevent it triggering immediately
852 	 * when the link goes inactive (we still get PME when any of the
853 	 * enabled events is detected). Same goes with Link Layer State
854 	 * changed event which generates PME immediately when the link goes
855 	 * inactive so mask it as well.
856 	 */
857 	mask = PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_DLLSCE;
858 	pcie_write_cmd(ctrl, 0, mask);
859 }
860 
861 /**
862  * pciehp_slot_reset() - ignore link event caused by error-induced hot reset
863  * @dev: PCI Express port service device
864  *
865  * Called from pcie_portdrv_slot_reset() after AER or DPC initiated a reset
866  * further up in the hierarchy to recover from an error.  The reset was
867  * propagated down to this hotplug port.  Ignore the resulting link flap.
868  * If the link failed to retrain successfully, synthesize the ignored event.
869  * Surprise removal during reset is detected through Presence Detect Changed.
870  */
871 int pciehp_slot_reset(struct pcie_device *dev)
872 {
873 	struct controller *ctrl = get_service_data(dev);
874 
875 	if (ctrl->state != ON_STATE)
876 		return 0;
877 
878 	pcie_capability_write_word(dev->port, PCI_EXP_SLTSTA,
879 				   PCI_EXP_SLTSTA_DLLSC);
880 
881 	if (!pciehp_check_link_active(ctrl))
882 		pciehp_request(ctrl, PCI_EXP_SLTSTA_DLLSC);
883 
884 	return 0;
885 }
886 
887 /*
888  * pciehp has a 1:1 bus:slot relationship so we ultimately want a secondary
889  * bus reset of the bridge, but at the same time we want to ensure that it is
890  * not seen as a hot-unplug, followed by the hot-plug of the device. Thus,
891  * disable link state notification and presence detection change notification
892  * momentarily, if we see that they could interfere. Also, clear any spurious
893  * events after.
894  */
895 int pciehp_reset_slot(struct hotplug_slot *hotplug_slot, bool probe)
896 {
897 	struct controller *ctrl = to_ctrl(hotplug_slot);
898 	struct pci_dev *pdev = ctrl_dev(ctrl);
899 	u16 stat_mask = 0, ctrl_mask = 0;
900 	int rc;
901 
902 	if (probe)
903 		return 0;
904 
905 	down_write_nested(&ctrl->reset_lock, ctrl->depth);
906 
907 	if (!ATTN_BUTTN(ctrl)) {
908 		ctrl_mask |= PCI_EXP_SLTCTL_PDCE;
909 		stat_mask |= PCI_EXP_SLTSTA_PDC;
910 	}
911 	ctrl_mask |= PCI_EXP_SLTCTL_DLLSCE;
912 	stat_mask |= PCI_EXP_SLTSTA_DLLSC;
913 
914 	pcie_write_cmd(ctrl, 0, ctrl_mask);
915 	ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
916 		 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0);
917 
918 	rc = pci_bridge_secondary_bus_reset(ctrl->pcie->port);
919 
920 	pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, stat_mask);
921 	pcie_write_cmd_nowait(ctrl, ctrl_mask, ctrl_mask);
922 	ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
923 		 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, ctrl_mask);
924 
925 	up_write(&ctrl->reset_lock);
926 	return rc;
927 }
928 
929 int pcie_init_notification(struct controller *ctrl)
930 {
931 	if (pciehp_request_irq(ctrl))
932 		return -1;
933 	pcie_enable_notification(ctrl);
934 	ctrl->notification_enabled = 1;
935 	return 0;
936 }
937 
938 void pcie_shutdown_notification(struct controller *ctrl)
939 {
940 	if (ctrl->notification_enabled) {
941 		pcie_disable_notification(ctrl);
942 		pciehp_free_irq(ctrl);
943 		ctrl->notification_enabled = 0;
944 	}
945 }
946 
947 static inline void dbg_ctrl(struct controller *ctrl)
948 {
949 	struct pci_dev *pdev = ctrl->pcie->port;
950 	u16 reg16;
951 
952 	ctrl_dbg(ctrl, "Slot Capabilities      : 0x%08x\n", ctrl->slot_cap);
953 	pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &reg16);
954 	ctrl_dbg(ctrl, "Slot Status            : 0x%04x\n", reg16);
955 	pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &reg16);
956 	ctrl_dbg(ctrl, "Slot Control           : 0x%04x\n", reg16);
957 }
958 
959 #define FLAG(x, y)	(((x) & (y)) ? '+' : '-')
960 
961 static inline int pcie_hotplug_depth(struct pci_dev *dev)
962 {
963 	struct pci_bus *bus = dev->bus;
964 	int depth = 0;
965 
966 	while (bus->parent) {
967 		bus = bus->parent;
968 		if (bus->self && bus->self->is_hotplug_bridge)
969 			depth++;
970 	}
971 
972 	return depth;
973 }
974 
975 struct controller *pcie_init(struct pcie_device *dev)
976 {
977 	struct controller *ctrl;
978 	u32 slot_cap, slot_cap2;
979 	u8 poweron;
980 	struct pci_dev *pdev = dev->port;
981 	struct pci_bus *subordinate = pdev->subordinate;
982 
983 	ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
984 	if (!ctrl)
985 		return NULL;
986 
987 	ctrl->pcie = dev;
988 	ctrl->depth = pcie_hotplug_depth(dev->port);
989 	pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap);
990 
991 	if (pdev->hotplug_user_indicators)
992 		slot_cap &= ~(PCI_EXP_SLTCAP_AIP | PCI_EXP_SLTCAP_PIP);
993 
994 	/*
995 	 * We assume no Thunderbolt controllers support Command Complete events,
996 	 * but some controllers falsely claim they do.
997 	 */
998 	if (pdev->is_thunderbolt)
999 		slot_cap |= PCI_EXP_SLTCAP_NCCS;
1000 
1001 	ctrl->slot_cap = slot_cap;
1002 	mutex_init(&ctrl->ctrl_lock);
1003 	mutex_init(&ctrl->state_lock);
1004 	init_rwsem(&ctrl->reset_lock);
1005 	init_waitqueue_head(&ctrl->requester);
1006 	init_waitqueue_head(&ctrl->queue);
1007 	INIT_DELAYED_WORK(&ctrl->button_work, pciehp_queue_pushbutton_work);
1008 	dbg_ctrl(ctrl);
1009 
1010 	down_read(&pci_bus_sem);
1011 	ctrl->state = list_empty(&subordinate->devices) ? OFF_STATE : ON_STATE;
1012 	up_read(&pci_bus_sem);
1013 
1014 	pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP2, &slot_cap2);
1015 	if (slot_cap2 & PCI_EXP_SLTCAP2_IBPD) {
1016 		pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_IBPD_DISABLE,
1017 				      PCI_EXP_SLTCTL_IBPD_DISABLE);
1018 		ctrl->inband_presence_disabled = 1;
1019 	}
1020 
1021 	if (dmi_first_match(inband_presence_disabled_dmi_table))
1022 		ctrl->inband_presence_disabled = 1;
1023 
1024 	/* Clear all remaining event bits in Slot Status register. */
1025 	pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
1026 		PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
1027 		PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_CC |
1028 		PCI_EXP_SLTSTA_DLLSC | PCI_EXP_SLTSTA_PDC);
1029 
1030 	ctrl_info(ctrl, "Slot #%d AttnBtn%c PwrCtrl%c MRL%c AttnInd%c PwrInd%c HotPlug%c Surprise%c Interlock%c NoCompl%c IbPresDis%c LLActRep%c%s\n",
1031 		(slot_cap & PCI_EXP_SLTCAP_PSN) >> 19,
1032 		FLAG(slot_cap, PCI_EXP_SLTCAP_ABP),
1033 		FLAG(slot_cap, PCI_EXP_SLTCAP_PCP),
1034 		FLAG(slot_cap, PCI_EXP_SLTCAP_MRLSP),
1035 		FLAG(slot_cap, PCI_EXP_SLTCAP_AIP),
1036 		FLAG(slot_cap, PCI_EXP_SLTCAP_PIP),
1037 		FLAG(slot_cap, PCI_EXP_SLTCAP_HPC),
1038 		FLAG(slot_cap, PCI_EXP_SLTCAP_HPS),
1039 		FLAG(slot_cap, PCI_EXP_SLTCAP_EIP),
1040 		FLAG(slot_cap, PCI_EXP_SLTCAP_NCCS),
1041 		FLAG(slot_cap2, PCI_EXP_SLTCAP2_IBPD),
1042 		FLAG(pdev->link_active_reporting, true),
1043 		pdev->broken_cmd_compl ? " (with Cmd Compl erratum)" : "");
1044 
1045 	/*
1046 	 * If empty slot's power status is on, turn power off.  The IRQ isn't
1047 	 * requested yet, so avoid triggering a notification with this command.
1048 	 */
1049 	if (POWER_CTRL(ctrl)) {
1050 		pciehp_get_power_status(ctrl, &poweron);
1051 		if (!pciehp_card_present_or_link_active(ctrl) && poweron) {
1052 			pcie_disable_notification(ctrl);
1053 			pciehp_power_off_slot(ctrl);
1054 		}
1055 	}
1056 
1057 	return ctrl;
1058 }
1059 
1060 void pciehp_release_ctrl(struct controller *ctrl)
1061 {
1062 	cancel_delayed_work_sync(&ctrl->button_work);
1063 	kfree(ctrl);
1064 }
1065 
1066 static void quirk_cmd_compl(struct pci_dev *pdev)
1067 {
1068 	u32 slot_cap;
1069 
1070 	if (pci_is_pcie(pdev)) {
1071 		pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap);
1072 		if (slot_cap & PCI_EXP_SLTCAP_HPC &&
1073 		    !(slot_cap & PCI_EXP_SLTCAP_NCCS))
1074 			pdev->broken_cmd_compl = 1;
1075 	}
1076 }
1077 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
1078 			      PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl);
1079 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_QCOM, 0x010e,
1080 			      PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl);
1081 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_QCOM, 0x0110,
1082 			      PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl);
1083 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_QCOM, 0x0400,
1084 			      PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl);
1085 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_QCOM, 0x0401,
1086 			      PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl);
1087 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_HXT, 0x0401,
1088 			      PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl);
1089