1 /* 2 * Compaq Hot Plug Controller Driver 3 * 4 * Copyright (C) 1995,2001 Compaq Computer Corporation 5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com) 6 * Copyright (C) 2001 IBM Corp. 7 * 8 * All rights reserved. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or (at 13 * your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, but 16 * WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 18 * NON INFRINGEMENT. See the GNU General Public License for more 19 * details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 24 * 25 * Send feedback to <greg@kroah.com> 26 * 27 */ 28 29 #include <linux/module.h> 30 #include <linux/kernel.h> 31 #include <linux/types.h> 32 #include <linux/slab.h> 33 #include <linux/workqueue.h> 34 #include <linux/proc_fs.h> 35 #include <linux/pci.h> 36 #include <linux/pci_hotplug.h> 37 #include "../pci.h" 38 #include "cpqphp.h" 39 #include "cpqphp_nvram.h" 40 41 42 u8 cpqhp_nic_irq; 43 u8 cpqhp_disk_irq; 44 45 static u16 unused_IRQ; 46 47 /* 48 * detect_HRT_floating_pointer 49 * 50 * find the Hot Plug Resource Table in the specified region of memory. 51 * 52 */ 53 static void __iomem *detect_HRT_floating_pointer(void __iomem *begin, void __iomem *end) 54 { 55 void __iomem *fp; 56 void __iomem *endp; 57 u8 temp1, temp2, temp3, temp4; 58 int status = 0; 59 60 endp = (end - sizeof(struct hrt) + 1); 61 62 for (fp = begin; fp <= endp; fp += 16) { 63 temp1 = readb(fp + SIG0); 64 temp2 = readb(fp + SIG1); 65 temp3 = readb(fp + SIG2); 66 temp4 = readb(fp + SIG3); 67 if (temp1 == '$' && 68 temp2 == 'H' && 69 temp3 == 'R' && 70 temp4 == 'T') { 71 status = 1; 72 break; 73 } 74 } 75 76 if (!status) 77 fp = NULL; 78 79 dbg("Discovered Hotplug Resource Table at %p\n", fp); 80 return fp; 81 } 82 83 84 int cpqhp_configure_device(struct controller *ctrl, struct pci_func *func) 85 { 86 struct pci_bus *child; 87 int num; 88 89 pci_lock_rescan_remove(); 90 91 if (func->pci_dev == NULL) 92 func->pci_dev = pci_get_domain_bus_and_slot(0, func->bus, 93 PCI_DEVFN(func->device, 94 func->function)); 95 96 /* No pci device, we need to create it then */ 97 if (func->pci_dev == NULL) { 98 dbg("INFO: pci_dev still null\n"); 99 100 num = pci_scan_slot(ctrl->pci_dev->bus, PCI_DEVFN(func->device, func->function)); 101 if (num) 102 pci_bus_add_devices(ctrl->pci_dev->bus); 103 104 func->pci_dev = pci_get_domain_bus_and_slot(0, func->bus, 105 PCI_DEVFN(func->device, 106 func->function)); 107 if (func->pci_dev == NULL) { 108 dbg("ERROR: pci_dev still null\n"); 109 goto out; 110 } 111 } 112 113 if (func->pci_dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { 114 pci_hp_add_bridge(func->pci_dev); 115 child = func->pci_dev->subordinate; 116 if (child) 117 pci_bus_add_devices(child); 118 } 119 120 pci_dev_put(func->pci_dev); 121 122 out: 123 pci_unlock_rescan_remove(); 124 return 0; 125 } 126 127 128 int cpqhp_unconfigure_device(struct pci_func *func) 129 { 130 int j; 131 132 dbg("%s: bus/dev/func = %x/%x/%x\n", __func__, func->bus, func->device, func->function); 133 134 pci_lock_rescan_remove(); 135 for (j = 0; j < 8 ; j++) { 136 struct pci_dev *temp = pci_get_domain_bus_and_slot(0, 137 func->bus, 138 PCI_DEVFN(func->device, 139 j)); 140 if (temp) { 141 pci_dev_put(temp); 142 pci_stop_and_remove_bus_device(temp); 143 } 144 } 145 pci_unlock_rescan_remove(); 146 return 0; 147 } 148 149 static int PCI_RefinedAccessConfig(struct pci_bus *bus, unsigned int devfn, u8 offset, u32 *value) 150 { 151 u32 vendID = 0; 152 153 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &vendID) == -1) 154 return -1; 155 if (vendID == 0xffffffff) 156 return -1; 157 return pci_bus_read_config_dword(bus, devfn, offset, value); 158 } 159 160 161 /* 162 * cpqhp_set_irq 163 * 164 * @bus_num: bus number of PCI device 165 * @dev_num: device number of PCI device 166 * @slot: pointer to u8 where slot number will be returned 167 */ 168 int cpqhp_set_irq(u8 bus_num, u8 dev_num, u8 int_pin, u8 irq_num) 169 { 170 int rc = 0; 171 172 if (cpqhp_legacy_mode) { 173 struct pci_dev *fakedev; 174 struct pci_bus *fakebus; 175 u16 temp_word; 176 177 fakedev = kmalloc(sizeof(*fakedev), GFP_KERNEL); 178 fakebus = kmalloc(sizeof(*fakebus), GFP_KERNEL); 179 if (!fakedev || !fakebus) { 180 kfree(fakedev); 181 kfree(fakebus); 182 return -ENOMEM; 183 } 184 185 fakedev->devfn = dev_num << 3; 186 fakedev->bus = fakebus; 187 fakebus->number = bus_num; 188 dbg("%s: dev %d, bus %d, pin %d, num %d\n", 189 __func__, dev_num, bus_num, int_pin, irq_num); 190 rc = pcibios_set_irq_routing(fakedev, int_pin - 1, irq_num); 191 kfree(fakedev); 192 kfree(fakebus); 193 dbg("%s: rc %d\n", __func__, rc); 194 if (!rc) 195 return !rc; 196 197 /* set the Edge Level Control Register (ELCR) */ 198 temp_word = inb(0x4d0); 199 temp_word |= inb(0x4d1) << 8; 200 201 temp_word |= 0x01 << irq_num; 202 203 /* This should only be for x86 as it sets the Edge Level 204 * Control Register 205 */ 206 outb((u8) (temp_word & 0xFF), 0x4d0); outb((u8) ((temp_word & 207 0xFF00) >> 8), 0x4d1); rc = 0; } 208 209 return rc; 210 } 211 212 213 static int PCI_ScanBusForNonBridge(struct controller *ctrl, u8 bus_num, u8 *dev_num) 214 { 215 u16 tdevice; 216 u32 work; 217 u8 tbus; 218 219 ctrl->pci_bus->number = bus_num; 220 221 for (tdevice = 0; tdevice < 0xFF; tdevice++) { 222 /* Scan for access first */ 223 if (PCI_RefinedAccessConfig(ctrl->pci_bus, tdevice, 0x08, &work) == -1) 224 continue; 225 dbg("Looking for nonbridge bus_num %d dev_num %d\n", bus_num, tdevice); 226 /* Yep we got one. Not a bridge ? */ 227 if ((work >> 8) != PCI_TO_PCI_BRIDGE_CLASS) { 228 *dev_num = tdevice; 229 dbg("found it !\n"); 230 return 0; 231 } 232 } 233 for (tdevice = 0; tdevice < 0xFF; tdevice++) { 234 /* Scan for access first */ 235 if (PCI_RefinedAccessConfig(ctrl->pci_bus, tdevice, 0x08, &work) == -1) 236 continue; 237 dbg("Looking for bridge bus_num %d dev_num %d\n", bus_num, tdevice); 238 /* Yep we got one. bridge ? */ 239 if ((work >> 8) == PCI_TO_PCI_BRIDGE_CLASS) { 240 pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(tdevice, 0), PCI_SECONDARY_BUS, &tbus); 241 /* XXX: no recursion, wtf? */ 242 dbg("Recurse on bus_num %d tdevice %d\n", tbus, tdevice); 243 return 0; 244 } 245 } 246 247 return -1; 248 } 249 250 251 static int PCI_GetBusDevHelper(struct controller *ctrl, u8 *bus_num, u8 *dev_num, u8 slot, u8 nobridge) 252 { 253 int loop, len; 254 u32 work; 255 u8 tbus, tdevice, tslot; 256 257 len = cpqhp_routing_table_length(); 258 for (loop = 0; loop < len; ++loop) { 259 tbus = cpqhp_routing_table->slots[loop].bus; 260 tdevice = cpqhp_routing_table->slots[loop].devfn; 261 tslot = cpqhp_routing_table->slots[loop].slot; 262 263 if (tslot == slot) { 264 *bus_num = tbus; 265 *dev_num = tdevice; 266 ctrl->pci_bus->number = tbus; 267 pci_bus_read_config_dword(ctrl->pci_bus, *dev_num, PCI_VENDOR_ID, &work); 268 if (!nobridge || (work == 0xffffffff)) 269 return 0; 270 271 dbg("bus_num %d devfn %d\n", *bus_num, *dev_num); 272 pci_bus_read_config_dword(ctrl->pci_bus, *dev_num, PCI_CLASS_REVISION, &work); 273 dbg("work >> 8 (%x) = BRIDGE (%x)\n", work >> 8, PCI_TO_PCI_BRIDGE_CLASS); 274 275 if ((work >> 8) == PCI_TO_PCI_BRIDGE_CLASS) { 276 pci_bus_read_config_byte(ctrl->pci_bus, *dev_num, PCI_SECONDARY_BUS, &tbus); 277 dbg("Scan bus for Non Bridge: bus %d\n", tbus); 278 if (PCI_ScanBusForNonBridge(ctrl, tbus, dev_num) == 0) { 279 *bus_num = tbus; 280 return 0; 281 } 282 } else 283 return 0; 284 } 285 } 286 return -1; 287 } 288 289 290 int cpqhp_get_bus_dev(struct controller *ctrl, u8 *bus_num, u8 *dev_num, u8 slot) 291 { 292 /* plain (bridges allowed) */ 293 return PCI_GetBusDevHelper(ctrl, bus_num, dev_num, slot, 0); 294 } 295 296 297 /* More PCI configuration routines; this time centered around hotplug 298 * controller 299 */ 300 301 302 /* 303 * cpqhp_save_config 304 * 305 * Reads configuration for all slots in a PCI bus and saves info. 306 * 307 * Note: For non-hot plug buses, the slot # saved is the device # 308 * 309 * returns 0 if success 310 */ 311 int cpqhp_save_config(struct controller *ctrl, int busnumber, int is_hot_plug) 312 { 313 long rc; 314 u8 class_code; 315 u8 header_type; 316 u32 ID; 317 u8 secondary_bus; 318 struct pci_func *new_slot; 319 int sub_bus; 320 int FirstSupported; 321 int LastSupported; 322 int max_functions; 323 int function; 324 u8 DevError; 325 int device = 0; 326 int cloop = 0; 327 int stop_it; 328 int index; 329 u16 devfn; 330 331 /* Decide which slots are supported */ 332 333 if (is_hot_plug) { 334 /* 335 * is_hot_plug is the slot mask 336 */ 337 FirstSupported = is_hot_plug >> 4; 338 LastSupported = FirstSupported + (is_hot_plug & 0x0F) - 1; 339 } else { 340 FirstSupported = 0; 341 LastSupported = 0x1F; 342 } 343 344 /* Save PCI configuration space for all devices in supported slots */ 345 ctrl->pci_bus->number = busnumber; 346 for (device = FirstSupported; device <= LastSupported; device++) { 347 ID = 0xFFFFFFFF; 348 rc = pci_bus_read_config_dword(ctrl->pci_bus, PCI_DEVFN(device, 0), PCI_VENDOR_ID, &ID); 349 350 if (ID == 0xFFFFFFFF) { 351 if (is_hot_plug) { 352 /* Setup slot structure with entry for empty 353 * slot 354 */ 355 new_slot = cpqhp_slot_create(busnumber); 356 if (new_slot == NULL) 357 return 1; 358 359 new_slot->bus = (u8) busnumber; 360 new_slot->device = (u8) device; 361 new_slot->function = 0; 362 new_slot->is_a_board = 0; 363 new_slot->presence_save = 0; 364 new_slot->switch_save = 0; 365 } 366 continue; 367 } 368 369 rc = pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(device, 0), 0x0B, &class_code); 370 if (rc) 371 return rc; 372 373 rc = pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(device, 0), PCI_HEADER_TYPE, &header_type); 374 if (rc) 375 return rc; 376 377 /* If multi-function device, set max_functions to 8 */ 378 if (header_type & 0x80) 379 max_functions = 8; 380 else 381 max_functions = 1; 382 383 function = 0; 384 385 do { 386 DevError = 0; 387 if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) { 388 /* Recurse the subordinate bus 389 * get the subordinate bus number 390 */ 391 rc = pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(device, function), PCI_SECONDARY_BUS, &secondary_bus); 392 if (rc) { 393 return rc; 394 } else { 395 sub_bus = (int) secondary_bus; 396 397 /* Save secondary bus cfg spc 398 * with this recursive call. 399 */ 400 rc = cpqhp_save_config(ctrl, sub_bus, 0); 401 if (rc) 402 return rc; 403 ctrl->pci_bus->number = busnumber; 404 } 405 } 406 407 index = 0; 408 new_slot = cpqhp_slot_find(busnumber, device, index++); 409 while (new_slot && 410 (new_slot->function != (u8) function)) 411 new_slot = cpqhp_slot_find(busnumber, device, index++); 412 413 if (!new_slot) { 414 /* Setup slot structure. */ 415 new_slot = cpqhp_slot_create(busnumber); 416 if (new_slot == NULL) 417 return 1; 418 } 419 420 new_slot->bus = (u8) busnumber; 421 new_slot->device = (u8) device; 422 new_slot->function = (u8) function; 423 new_slot->is_a_board = 1; 424 new_slot->switch_save = 0x10; 425 /* In case of unsupported board */ 426 new_slot->status = DevError; 427 devfn = (new_slot->device << 3) | new_slot->function; 428 new_slot->pci_dev = pci_get_domain_bus_and_slot(0, 429 new_slot->bus, devfn); 430 431 for (cloop = 0; cloop < 0x20; cloop++) { 432 rc = pci_bus_read_config_dword(ctrl->pci_bus, PCI_DEVFN(device, function), cloop << 2, (u32 *) &(new_slot->config_space[cloop])); 433 if (rc) 434 return rc; 435 } 436 437 pci_dev_put(new_slot->pci_dev); 438 439 function++; 440 441 stop_it = 0; 442 443 /* this loop skips to the next present function 444 * reading in Class Code and Header type. 445 */ 446 while ((function < max_functions) && (!stop_it)) { 447 rc = pci_bus_read_config_dword(ctrl->pci_bus, PCI_DEVFN(device, function), PCI_VENDOR_ID, &ID); 448 if (ID == 0xFFFFFFFF) { 449 function++; 450 continue; 451 } 452 rc = pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(device, function), 0x0B, &class_code); 453 if (rc) 454 return rc; 455 456 rc = pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(device, function), PCI_HEADER_TYPE, &header_type); 457 if (rc) 458 return rc; 459 460 stop_it++; 461 } 462 463 } while (function < max_functions); 464 } /* End of FOR loop */ 465 466 return 0; 467 } 468 469 470 /* 471 * cpqhp_save_slot_config 472 * 473 * Saves configuration info for all PCI devices in a given slot 474 * including subordinate buses. 475 * 476 * returns 0 if success 477 */ 478 int cpqhp_save_slot_config(struct controller *ctrl, struct pci_func *new_slot) 479 { 480 long rc; 481 u8 class_code; 482 u8 header_type; 483 u32 ID; 484 u8 secondary_bus; 485 int sub_bus; 486 int max_functions; 487 int function = 0; 488 int cloop = 0; 489 int stop_it; 490 491 ID = 0xFFFFFFFF; 492 493 ctrl->pci_bus->number = new_slot->bus; 494 pci_bus_read_config_dword(ctrl->pci_bus, PCI_DEVFN(new_slot->device, 0), PCI_VENDOR_ID, &ID); 495 496 if (ID == 0xFFFFFFFF) 497 return 2; 498 499 pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(new_slot->device, 0), 0x0B, &class_code); 500 pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(new_slot->device, 0), PCI_HEADER_TYPE, &header_type); 501 502 if (header_type & 0x80) /* Multi-function device */ 503 max_functions = 8; 504 else 505 max_functions = 1; 506 507 while (function < max_functions) { 508 if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) { 509 /* Recurse the subordinate bus */ 510 pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(new_slot->device, function), PCI_SECONDARY_BUS, &secondary_bus); 511 512 sub_bus = (int) secondary_bus; 513 514 /* Save the config headers for the secondary 515 * bus. 516 */ 517 rc = cpqhp_save_config(ctrl, sub_bus, 0); 518 if (rc) 519 return(rc); 520 ctrl->pci_bus->number = new_slot->bus; 521 522 } 523 524 new_slot->status = 0; 525 526 for (cloop = 0; cloop < 0x20; cloop++) 527 pci_bus_read_config_dword(ctrl->pci_bus, PCI_DEVFN(new_slot->device, function), cloop << 2, (u32 *) &(new_slot->config_space[cloop])); 528 529 function++; 530 531 stop_it = 0; 532 533 /* this loop skips to the next present function 534 * reading in the Class Code and the Header type. 535 */ 536 while ((function < max_functions) && (!stop_it)) { 537 pci_bus_read_config_dword(ctrl->pci_bus, PCI_DEVFN(new_slot->device, function), PCI_VENDOR_ID, &ID); 538 539 if (ID == 0xFFFFFFFF) 540 function++; 541 else { 542 pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(new_slot->device, function), 0x0B, &class_code); 543 pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(new_slot->device, function), PCI_HEADER_TYPE, &header_type); 544 stop_it++; 545 } 546 } 547 548 } 549 550 return 0; 551 } 552 553 554 /* 555 * cpqhp_save_base_addr_length 556 * 557 * Saves the length of all base address registers for the 558 * specified slot. this is for hot plug REPLACE 559 * 560 * returns 0 if success 561 */ 562 int cpqhp_save_base_addr_length(struct controller *ctrl, struct pci_func *func) 563 { 564 u8 cloop; 565 u8 header_type; 566 u8 secondary_bus; 567 u8 type; 568 int sub_bus; 569 u32 temp_register; 570 u32 base; 571 u32 rc; 572 struct pci_func *next; 573 int index = 0; 574 struct pci_bus *pci_bus = ctrl->pci_bus; 575 unsigned int devfn; 576 577 func = cpqhp_slot_find(func->bus, func->device, index++); 578 579 while (func != NULL) { 580 pci_bus->number = func->bus; 581 devfn = PCI_DEVFN(func->device, func->function); 582 583 /* Check for Bridge */ 584 pci_bus_read_config_byte(pci_bus, devfn, PCI_HEADER_TYPE, &header_type); 585 586 if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) { 587 pci_bus_read_config_byte(pci_bus, devfn, PCI_SECONDARY_BUS, &secondary_bus); 588 589 sub_bus = (int) secondary_bus; 590 591 next = cpqhp_slot_list[sub_bus]; 592 593 while (next != NULL) { 594 rc = cpqhp_save_base_addr_length(ctrl, next); 595 if (rc) 596 return rc; 597 598 next = next->next; 599 } 600 pci_bus->number = func->bus; 601 602 /* FIXME: this loop is duplicated in the non-bridge 603 * case. The two could be rolled together Figure out 604 * IO and memory base lengths 605 */ 606 for (cloop = 0x10; cloop <= 0x14; cloop += 4) { 607 temp_register = 0xFFFFFFFF; 608 pci_bus_write_config_dword(pci_bus, devfn, cloop, temp_register); 609 pci_bus_read_config_dword(pci_bus, devfn, cloop, &base); 610 /* If this register is implemented */ 611 if (base) { 612 if (base & 0x01L) { 613 /* IO base 614 * set base = amount of IO space 615 * requested 616 */ 617 base = base & 0xFFFFFFFE; 618 base = (~base) + 1; 619 620 type = 1; 621 } else { 622 /* memory base */ 623 base = base & 0xFFFFFFF0; 624 base = (~base) + 1; 625 626 type = 0; 627 } 628 } else { 629 base = 0x0L; 630 type = 0; 631 } 632 633 /* Save information in slot structure */ 634 func->base_length[(cloop - 0x10) >> 2] = 635 base; 636 func->base_type[(cloop - 0x10) >> 2] = type; 637 638 } /* End of base register loop */ 639 640 } else if ((header_type & 0x7F) == 0x00) { 641 /* Figure out IO and memory base lengths */ 642 for (cloop = 0x10; cloop <= 0x24; cloop += 4) { 643 temp_register = 0xFFFFFFFF; 644 pci_bus_write_config_dword(pci_bus, devfn, cloop, temp_register); 645 pci_bus_read_config_dword(pci_bus, devfn, cloop, &base); 646 647 /* If this register is implemented */ 648 if (base) { 649 if (base & 0x01L) { 650 /* IO base 651 * base = amount of IO space 652 * requested 653 */ 654 base = base & 0xFFFFFFFE; 655 base = (~base) + 1; 656 657 type = 1; 658 } else { 659 /* memory base 660 * base = amount of memory 661 * space requested 662 */ 663 base = base & 0xFFFFFFF0; 664 base = (~base) + 1; 665 666 type = 0; 667 } 668 } else { 669 base = 0x0L; 670 type = 0; 671 } 672 673 /* Save information in slot structure */ 674 func->base_length[(cloop - 0x10) >> 2] = base; 675 func->base_type[(cloop - 0x10) >> 2] = type; 676 677 } /* End of base register loop */ 678 679 } else { /* Some other unknown header type */ 680 } 681 682 /* find the next device in this slot */ 683 func = cpqhp_slot_find(func->bus, func->device, index++); 684 } 685 686 return(0); 687 } 688 689 690 /* 691 * cpqhp_save_used_resources 692 * 693 * Stores used resource information for existing boards. this is 694 * for boards that were in the system when this driver was loaded. 695 * this function is for hot plug ADD 696 * 697 * returns 0 if success 698 */ 699 int cpqhp_save_used_resources(struct controller *ctrl, struct pci_func *func) 700 { 701 u8 cloop; 702 u8 header_type; 703 u8 secondary_bus; 704 u8 temp_byte; 705 u8 b_base; 706 u8 b_length; 707 u16 command; 708 u16 save_command; 709 u16 w_base; 710 u16 w_length; 711 u32 temp_register; 712 u32 save_base; 713 u32 base; 714 int index = 0; 715 struct pci_resource *mem_node; 716 struct pci_resource *p_mem_node; 717 struct pci_resource *io_node; 718 struct pci_resource *bus_node; 719 struct pci_bus *pci_bus = ctrl->pci_bus; 720 unsigned int devfn; 721 722 func = cpqhp_slot_find(func->bus, func->device, index++); 723 724 while ((func != NULL) && func->is_a_board) { 725 pci_bus->number = func->bus; 726 devfn = PCI_DEVFN(func->device, func->function); 727 728 /* Save the command register */ 729 pci_bus_read_config_word(pci_bus, devfn, PCI_COMMAND, &save_command); 730 731 /* disable card */ 732 command = 0x00; 733 pci_bus_write_config_word(pci_bus, devfn, PCI_COMMAND, command); 734 735 /* Check for Bridge */ 736 pci_bus_read_config_byte(pci_bus, devfn, PCI_HEADER_TYPE, &header_type); 737 738 if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) { 739 /* Clear Bridge Control Register */ 740 command = 0x00; 741 pci_bus_write_config_word(pci_bus, devfn, PCI_BRIDGE_CONTROL, command); 742 pci_bus_read_config_byte(pci_bus, devfn, PCI_SECONDARY_BUS, &secondary_bus); 743 pci_bus_read_config_byte(pci_bus, devfn, PCI_SUBORDINATE_BUS, &temp_byte); 744 745 bus_node = kmalloc(sizeof(*bus_node), GFP_KERNEL); 746 if (!bus_node) 747 return -ENOMEM; 748 749 bus_node->base = secondary_bus; 750 bus_node->length = temp_byte - secondary_bus + 1; 751 752 bus_node->next = func->bus_head; 753 func->bus_head = bus_node; 754 755 /* Save IO base and Limit registers */ 756 pci_bus_read_config_byte(pci_bus, devfn, PCI_IO_BASE, &b_base); 757 pci_bus_read_config_byte(pci_bus, devfn, PCI_IO_LIMIT, &b_length); 758 759 if ((b_base <= b_length) && (save_command & 0x01)) { 760 io_node = kmalloc(sizeof(*io_node), GFP_KERNEL); 761 if (!io_node) 762 return -ENOMEM; 763 764 io_node->base = (b_base & 0xF0) << 8; 765 io_node->length = (b_length - b_base + 0x10) << 8; 766 767 io_node->next = func->io_head; 768 func->io_head = io_node; 769 } 770 771 /* Save memory base and Limit registers */ 772 pci_bus_read_config_word(pci_bus, devfn, PCI_MEMORY_BASE, &w_base); 773 pci_bus_read_config_word(pci_bus, devfn, PCI_MEMORY_LIMIT, &w_length); 774 775 if ((w_base <= w_length) && (save_command & 0x02)) { 776 mem_node = kmalloc(sizeof(*mem_node), GFP_KERNEL); 777 if (!mem_node) 778 return -ENOMEM; 779 780 mem_node->base = w_base << 16; 781 mem_node->length = (w_length - w_base + 0x10) << 16; 782 783 mem_node->next = func->mem_head; 784 func->mem_head = mem_node; 785 } 786 787 /* Save prefetchable memory base and Limit registers */ 788 pci_bus_read_config_word(pci_bus, devfn, PCI_PREF_MEMORY_BASE, &w_base); 789 pci_bus_read_config_word(pci_bus, devfn, PCI_PREF_MEMORY_LIMIT, &w_length); 790 791 if ((w_base <= w_length) && (save_command & 0x02)) { 792 p_mem_node = kmalloc(sizeof(*p_mem_node), GFP_KERNEL); 793 if (!p_mem_node) 794 return -ENOMEM; 795 796 p_mem_node->base = w_base << 16; 797 p_mem_node->length = (w_length - w_base + 0x10) << 16; 798 799 p_mem_node->next = func->p_mem_head; 800 func->p_mem_head = p_mem_node; 801 } 802 /* Figure out IO and memory base lengths */ 803 for (cloop = 0x10; cloop <= 0x14; cloop += 4) { 804 pci_bus_read_config_dword(pci_bus, devfn, cloop, &save_base); 805 806 temp_register = 0xFFFFFFFF; 807 pci_bus_write_config_dword(pci_bus, devfn, cloop, temp_register); 808 pci_bus_read_config_dword(pci_bus, devfn, cloop, &base); 809 810 temp_register = base; 811 812 /* If this register is implemented */ 813 if (base) { 814 if (((base & 0x03L) == 0x01) 815 && (save_command & 0x01)) { 816 /* IO base 817 * set temp_register = amount 818 * of IO space requested 819 */ 820 temp_register = base & 0xFFFFFFFE; 821 temp_register = (~temp_register) + 1; 822 823 io_node = kmalloc(sizeof(*io_node), 824 GFP_KERNEL); 825 if (!io_node) 826 return -ENOMEM; 827 828 io_node->base = 829 save_base & (~0x03L); 830 io_node->length = temp_register; 831 832 io_node->next = func->io_head; 833 func->io_head = io_node; 834 } else 835 if (((base & 0x0BL) == 0x08) 836 && (save_command & 0x02)) { 837 /* prefetchable memory base */ 838 temp_register = base & 0xFFFFFFF0; 839 temp_register = (~temp_register) + 1; 840 841 p_mem_node = kmalloc(sizeof(*p_mem_node), 842 GFP_KERNEL); 843 if (!p_mem_node) 844 return -ENOMEM; 845 846 p_mem_node->base = save_base & (~0x0FL); 847 p_mem_node->length = temp_register; 848 849 p_mem_node->next = func->p_mem_head; 850 func->p_mem_head = p_mem_node; 851 } else 852 if (((base & 0x0BL) == 0x00) 853 && (save_command & 0x02)) { 854 /* prefetchable memory base */ 855 temp_register = base & 0xFFFFFFF0; 856 temp_register = (~temp_register) + 1; 857 858 mem_node = kmalloc(sizeof(*mem_node), 859 GFP_KERNEL); 860 if (!mem_node) 861 return -ENOMEM; 862 863 mem_node->base = save_base & (~0x0FL); 864 mem_node->length = temp_register; 865 866 mem_node->next = func->mem_head; 867 func->mem_head = mem_node; 868 } else 869 return(1); 870 } 871 } /* End of base register loop */ 872 /* Standard header */ 873 } else if ((header_type & 0x7F) == 0x00) { 874 /* Figure out IO and memory base lengths */ 875 for (cloop = 0x10; cloop <= 0x24; cloop += 4) { 876 pci_bus_read_config_dword(pci_bus, devfn, cloop, &save_base); 877 878 temp_register = 0xFFFFFFFF; 879 pci_bus_write_config_dword(pci_bus, devfn, cloop, temp_register); 880 pci_bus_read_config_dword(pci_bus, devfn, cloop, &base); 881 882 temp_register = base; 883 884 /* If this register is implemented */ 885 if (base) { 886 if (((base & 0x03L) == 0x01) 887 && (save_command & 0x01)) { 888 /* IO base 889 * set temp_register = amount 890 * of IO space requested 891 */ 892 temp_register = base & 0xFFFFFFFE; 893 temp_register = (~temp_register) + 1; 894 895 io_node = kmalloc(sizeof(*io_node), 896 GFP_KERNEL); 897 if (!io_node) 898 return -ENOMEM; 899 900 io_node->base = save_base & (~0x01L); 901 io_node->length = temp_register; 902 903 io_node->next = func->io_head; 904 func->io_head = io_node; 905 } else 906 if (((base & 0x0BL) == 0x08) 907 && (save_command & 0x02)) { 908 /* prefetchable memory base */ 909 temp_register = base & 0xFFFFFFF0; 910 temp_register = (~temp_register) + 1; 911 912 p_mem_node = kmalloc(sizeof(*p_mem_node), 913 GFP_KERNEL); 914 if (!p_mem_node) 915 return -ENOMEM; 916 917 p_mem_node->base = save_base & (~0x0FL); 918 p_mem_node->length = temp_register; 919 920 p_mem_node->next = func->p_mem_head; 921 func->p_mem_head = p_mem_node; 922 } else 923 if (((base & 0x0BL) == 0x00) 924 && (save_command & 0x02)) { 925 /* prefetchable memory base */ 926 temp_register = base & 0xFFFFFFF0; 927 temp_register = (~temp_register) + 1; 928 929 mem_node = kmalloc(sizeof(*mem_node), 930 GFP_KERNEL); 931 if (!mem_node) 932 return -ENOMEM; 933 934 mem_node->base = save_base & (~0x0FL); 935 mem_node->length = temp_register; 936 937 mem_node->next = func->mem_head; 938 func->mem_head = mem_node; 939 } else 940 return(1); 941 } 942 } /* End of base register loop */ 943 } 944 945 /* find the next device in this slot */ 946 func = cpqhp_slot_find(func->bus, func->device, index++); 947 } 948 949 return 0; 950 } 951 952 953 /* 954 * cpqhp_configure_board 955 * 956 * Copies saved configuration information to one slot. 957 * this is called recursively for bridge devices. 958 * this is for hot plug REPLACE! 959 * 960 * returns 0 if success 961 */ 962 int cpqhp_configure_board(struct controller *ctrl, struct pci_func *func) 963 { 964 int cloop; 965 u8 header_type; 966 u8 secondary_bus; 967 int sub_bus; 968 struct pci_func *next; 969 u32 temp; 970 u32 rc; 971 int index = 0; 972 struct pci_bus *pci_bus = ctrl->pci_bus; 973 unsigned int devfn; 974 975 func = cpqhp_slot_find(func->bus, func->device, index++); 976 977 while (func != NULL) { 978 pci_bus->number = func->bus; 979 devfn = PCI_DEVFN(func->device, func->function); 980 981 /* Start at the top of config space so that the control 982 * registers are programmed last 983 */ 984 for (cloop = 0x3C; cloop > 0; cloop -= 4) 985 pci_bus_write_config_dword(pci_bus, devfn, cloop, func->config_space[cloop >> 2]); 986 987 pci_bus_read_config_byte(pci_bus, devfn, PCI_HEADER_TYPE, &header_type); 988 989 /* If this is a bridge device, restore subordinate devices */ 990 if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) { 991 pci_bus_read_config_byte(pci_bus, devfn, PCI_SECONDARY_BUS, &secondary_bus); 992 993 sub_bus = (int) secondary_bus; 994 995 next = cpqhp_slot_list[sub_bus]; 996 997 while (next != NULL) { 998 rc = cpqhp_configure_board(ctrl, next); 999 if (rc) 1000 return rc; 1001 1002 next = next->next; 1003 } 1004 } else { 1005 1006 /* Check all the base Address Registers to make sure 1007 * they are the same. If not, the board is different. 1008 */ 1009 1010 for (cloop = 16; cloop < 40; cloop += 4) { 1011 pci_bus_read_config_dword(pci_bus, devfn, cloop, &temp); 1012 1013 if (temp != func->config_space[cloop >> 2]) { 1014 dbg("Config space compare failure!!! offset = %x\n", cloop); 1015 dbg("bus = %x, device = %x, function = %x\n", func->bus, func->device, func->function); 1016 dbg("temp = %x, config space = %x\n\n", temp, func->config_space[cloop >> 2]); 1017 return 1; 1018 } 1019 } 1020 } 1021 1022 func->configured = 1; 1023 1024 func = cpqhp_slot_find(func->bus, func->device, index++); 1025 } 1026 1027 return 0; 1028 } 1029 1030 1031 /* 1032 * cpqhp_valid_replace 1033 * 1034 * this function checks to see if a board is the same as the 1035 * one it is replacing. this check will detect if the device's 1036 * vendor or device id's are the same 1037 * 1038 * returns 0 if the board is the same nonzero otherwise 1039 */ 1040 int cpqhp_valid_replace(struct controller *ctrl, struct pci_func *func) 1041 { 1042 u8 cloop; 1043 u8 header_type; 1044 u8 secondary_bus; 1045 u8 type; 1046 u32 temp_register = 0; 1047 u32 base; 1048 u32 rc; 1049 struct pci_func *next; 1050 int index = 0; 1051 struct pci_bus *pci_bus = ctrl->pci_bus; 1052 unsigned int devfn; 1053 1054 if (!func->is_a_board) 1055 return(ADD_NOT_SUPPORTED); 1056 1057 func = cpqhp_slot_find(func->bus, func->device, index++); 1058 1059 while (func != NULL) { 1060 pci_bus->number = func->bus; 1061 devfn = PCI_DEVFN(func->device, func->function); 1062 1063 pci_bus_read_config_dword(pci_bus, devfn, PCI_VENDOR_ID, &temp_register); 1064 1065 /* No adapter present */ 1066 if (temp_register == 0xFFFFFFFF) 1067 return(NO_ADAPTER_PRESENT); 1068 1069 if (temp_register != func->config_space[0]) 1070 return(ADAPTER_NOT_SAME); 1071 1072 /* Check for same revision number and class code */ 1073 pci_bus_read_config_dword(pci_bus, devfn, PCI_CLASS_REVISION, &temp_register); 1074 1075 /* Adapter not the same */ 1076 if (temp_register != func->config_space[0x08 >> 2]) 1077 return(ADAPTER_NOT_SAME); 1078 1079 /* Check for Bridge */ 1080 pci_bus_read_config_byte(pci_bus, devfn, PCI_HEADER_TYPE, &header_type); 1081 1082 if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) { 1083 /* In order to continue checking, we must program the 1084 * bus registers in the bridge to respond to accesses 1085 * for its subordinate bus(es) 1086 */ 1087 1088 temp_register = func->config_space[0x18 >> 2]; 1089 pci_bus_write_config_dword(pci_bus, devfn, PCI_PRIMARY_BUS, temp_register); 1090 1091 secondary_bus = (temp_register >> 8) & 0xFF; 1092 1093 next = cpqhp_slot_list[secondary_bus]; 1094 1095 while (next != NULL) { 1096 rc = cpqhp_valid_replace(ctrl, next); 1097 if (rc) 1098 return rc; 1099 1100 next = next->next; 1101 } 1102 1103 } 1104 /* Check to see if it is a standard config header */ 1105 else if ((header_type & 0x7F) == PCI_HEADER_TYPE_NORMAL) { 1106 /* Check subsystem vendor and ID */ 1107 pci_bus_read_config_dword(pci_bus, devfn, PCI_SUBSYSTEM_VENDOR_ID, &temp_register); 1108 1109 if (temp_register != func->config_space[0x2C >> 2]) { 1110 /* If it's a SMART-2 and the register isn't 1111 * filled in, ignore the difference because 1112 * they just have an old rev of the firmware 1113 */ 1114 if (!((func->config_space[0] == 0xAE100E11) 1115 && (temp_register == 0x00L))) 1116 return(ADAPTER_NOT_SAME); 1117 } 1118 /* Figure out IO and memory base lengths */ 1119 for (cloop = 0x10; cloop <= 0x24; cloop += 4) { 1120 temp_register = 0xFFFFFFFF; 1121 pci_bus_write_config_dword(pci_bus, devfn, cloop, temp_register); 1122 pci_bus_read_config_dword(pci_bus, devfn, cloop, &base); 1123 1124 /* If this register is implemented */ 1125 if (base) { 1126 if (base & 0x01L) { 1127 /* IO base 1128 * set base = amount of IO 1129 * space requested 1130 */ 1131 base = base & 0xFFFFFFFE; 1132 base = (~base) + 1; 1133 1134 type = 1; 1135 } else { 1136 /* memory base */ 1137 base = base & 0xFFFFFFF0; 1138 base = (~base) + 1; 1139 1140 type = 0; 1141 } 1142 } else { 1143 base = 0x0L; 1144 type = 0; 1145 } 1146 1147 /* Check information in slot structure */ 1148 if (func->base_length[(cloop - 0x10) >> 2] != base) 1149 return(ADAPTER_NOT_SAME); 1150 1151 if (func->base_type[(cloop - 0x10) >> 2] != type) 1152 return(ADAPTER_NOT_SAME); 1153 1154 } /* End of base register loop */ 1155 1156 } /* End of (type 0 config space) else */ 1157 else { 1158 /* this is not a type 0 or 1 config space header so 1159 * we don't know how to do it 1160 */ 1161 return(DEVICE_TYPE_NOT_SUPPORTED); 1162 } 1163 1164 /* Get the next function */ 1165 func = cpqhp_slot_find(func->bus, func->device, index++); 1166 } 1167 1168 1169 return 0; 1170 } 1171 1172 1173 /* 1174 * cpqhp_find_available_resources 1175 * 1176 * Finds available memory, IO, and IRQ resources for programming 1177 * devices which may be added to the system 1178 * this function is for hot plug ADD! 1179 * 1180 * returns 0 if success 1181 */ 1182 int cpqhp_find_available_resources(struct controller *ctrl, void __iomem *rom_start) 1183 { 1184 u8 temp; 1185 u8 populated_slot; 1186 u8 bridged_slot; 1187 void __iomem *one_slot; 1188 void __iomem *rom_resource_table; 1189 struct pci_func *func = NULL; 1190 int i = 10, index; 1191 u32 temp_dword, rc; 1192 struct pci_resource *mem_node; 1193 struct pci_resource *p_mem_node; 1194 struct pci_resource *io_node; 1195 struct pci_resource *bus_node; 1196 1197 rom_resource_table = detect_HRT_floating_pointer(rom_start, rom_start+0xffff); 1198 dbg("rom_resource_table = %p\n", rom_resource_table); 1199 1200 if (rom_resource_table == NULL) 1201 return -ENODEV; 1202 1203 /* Sum all resources and setup resource maps */ 1204 unused_IRQ = readl(rom_resource_table + UNUSED_IRQ); 1205 dbg("unused_IRQ = %x\n", unused_IRQ); 1206 1207 temp = 0; 1208 while (unused_IRQ) { 1209 if (unused_IRQ & 1) { 1210 cpqhp_disk_irq = temp; 1211 break; 1212 } 1213 unused_IRQ = unused_IRQ >> 1; 1214 temp++; 1215 } 1216 1217 dbg("cpqhp_disk_irq= %d\n", cpqhp_disk_irq); 1218 unused_IRQ = unused_IRQ >> 1; 1219 temp++; 1220 1221 while (unused_IRQ) { 1222 if (unused_IRQ & 1) { 1223 cpqhp_nic_irq = temp; 1224 break; 1225 } 1226 unused_IRQ = unused_IRQ >> 1; 1227 temp++; 1228 } 1229 1230 dbg("cpqhp_nic_irq= %d\n", cpqhp_nic_irq); 1231 unused_IRQ = readl(rom_resource_table + PCIIRQ); 1232 1233 temp = 0; 1234 1235 if (!cpqhp_nic_irq) 1236 cpqhp_nic_irq = ctrl->cfgspc_irq; 1237 1238 if (!cpqhp_disk_irq) 1239 cpqhp_disk_irq = ctrl->cfgspc_irq; 1240 1241 dbg("cpqhp_disk_irq, cpqhp_nic_irq= %d, %d\n", cpqhp_disk_irq, cpqhp_nic_irq); 1242 1243 rc = compaq_nvram_load(rom_start, ctrl); 1244 if (rc) 1245 return rc; 1246 1247 one_slot = rom_resource_table + sizeof(struct hrt); 1248 1249 i = readb(rom_resource_table + NUMBER_OF_ENTRIES); 1250 dbg("number_of_entries = %d\n", i); 1251 1252 if (!readb(one_slot + SECONDARY_BUS)) 1253 return 1; 1254 1255 dbg("dev|IO base|length|Mem base|length|Pre base|length|PB SB MB\n"); 1256 1257 while (i && readb(one_slot + SECONDARY_BUS)) { 1258 u8 dev_func = readb(one_slot + DEV_FUNC); 1259 u8 primary_bus = readb(one_slot + PRIMARY_BUS); 1260 u8 secondary_bus = readb(one_slot + SECONDARY_BUS); 1261 u8 max_bus = readb(one_slot + MAX_BUS); 1262 u16 io_base = readw(one_slot + IO_BASE); 1263 u16 io_length = readw(one_slot + IO_LENGTH); 1264 u16 mem_base = readw(one_slot + MEM_BASE); 1265 u16 mem_length = readw(one_slot + MEM_LENGTH); 1266 u16 pre_mem_base = readw(one_slot + PRE_MEM_BASE); 1267 u16 pre_mem_length = readw(one_slot + PRE_MEM_LENGTH); 1268 1269 dbg("%2.2x | %4.4x | %4.4x | %4.4x | %4.4x | %4.4x | %4.4x |%2.2x %2.2x %2.2x\n", 1270 dev_func, io_base, io_length, mem_base, mem_length, pre_mem_base, pre_mem_length, 1271 primary_bus, secondary_bus, max_bus); 1272 1273 /* If this entry isn't for our controller's bus, ignore it */ 1274 if (primary_bus != ctrl->bus) { 1275 i--; 1276 one_slot += sizeof(struct slot_rt); 1277 continue; 1278 } 1279 /* find out if this entry is for an occupied slot */ 1280 ctrl->pci_bus->number = primary_bus; 1281 pci_bus_read_config_dword(ctrl->pci_bus, dev_func, PCI_VENDOR_ID, &temp_dword); 1282 dbg("temp_D_word = %x\n", temp_dword); 1283 1284 if (temp_dword != 0xFFFFFFFF) { 1285 index = 0; 1286 func = cpqhp_slot_find(primary_bus, dev_func >> 3, 0); 1287 1288 while (func && (func->function != (dev_func & 0x07))) { 1289 dbg("func = %p (bus, dev, fun) = (%d, %d, %d)\n", func, primary_bus, dev_func >> 3, index); 1290 func = cpqhp_slot_find(primary_bus, dev_func >> 3, index++); 1291 } 1292 1293 /* If we can't find a match, skip this table entry */ 1294 if (!func) { 1295 i--; 1296 one_slot += sizeof(struct slot_rt); 1297 continue; 1298 } 1299 /* this may not work and shouldn't be used */ 1300 if (secondary_bus != primary_bus) 1301 bridged_slot = 1; 1302 else 1303 bridged_slot = 0; 1304 1305 populated_slot = 1; 1306 } else { 1307 populated_slot = 0; 1308 bridged_slot = 0; 1309 } 1310 1311 1312 /* If we've got a valid IO base, use it */ 1313 1314 temp_dword = io_base + io_length; 1315 1316 if ((io_base) && (temp_dword < 0x10000)) { 1317 io_node = kmalloc(sizeof(*io_node), GFP_KERNEL); 1318 if (!io_node) 1319 return -ENOMEM; 1320 1321 io_node->base = io_base; 1322 io_node->length = io_length; 1323 1324 dbg("found io_node(base, length) = %x, %x\n", 1325 io_node->base, io_node->length); 1326 dbg("populated slot =%d \n", populated_slot); 1327 if (!populated_slot) { 1328 io_node->next = ctrl->io_head; 1329 ctrl->io_head = io_node; 1330 } else { 1331 io_node->next = func->io_head; 1332 func->io_head = io_node; 1333 } 1334 } 1335 1336 /* If we've got a valid memory base, use it */ 1337 temp_dword = mem_base + mem_length; 1338 if ((mem_base) && (temp_dword < 0x10000)) { 1339 mem_node = kmalloc(sizeof(*mem_node), GFP_KERNEL); 1340 if (!mem_node) 1341 return -ENOMEM; 1342 1343 mem_node->base = mem_base << 16; 1344 1345 mem_node->length = mem_length << 16; 1346 1347 dbg("found mem_node(base, length) = %x, %x\n", 1348 mem_node->base, mem_node->length); 1349 dbg("populated slot =%d \n", populated_slot); 1350 if (!populated_slot) { 1351 mem_node->next = ctrl->mem_head; 1352 ctrl->mem_head = mem_node; 1353 } else { 1354 mem_node->next = func->mem_head; 1355 func->mem_head = mem_node; 1356 } 1357 } 1358 1359 /* If we've got a valid prefetchable memory base, and 1360 * the base + length isn't greater than 0xFFFF 1361 */ 1362 temp_dword = pre_mem_base + pre_mem_length; 1363 if ((pre_mem_base) && (temp_dword < 0x10000)) { 1364 p_mem_node = kmalloc(sizeof(*p_mem_node), GFP_KERNEL); 1365 if (!p_mem_node) 1366 return -ENOMEM; 1367 1368 p_mem_node->base = pre_mem_base << 16; 1369 1370 p_mem_node->length = pre_mem_length << 16; 1371 dbg("found p_mem_node(base, length) = %x, %x\n", 1372 p_mem_node->base, p_mem_node->length); 1373 dbg("populated slot =%d \n", populated_slot); 1374 1375 if (!populated_slot) { 1376 p_mem_node->next = ctrl->p_mem_head; 1377 ctrl->p_mem_head = p_mem_node; 1378 } else { 1379 p_mem_node->next = func->p_mem_head; 1380 func->p_mem_head = p_mem_node; 1381 } 1382 } 1383 1384 /* If we've got a valid bus number, use it 1385 * The second condition is to ignore bus numbers on 1386 * populated slots that don't have PCI-PCI bridges 1387 */ 1388 if (secondary_bus && (secondary_bus != primary_bus)) { 1389 bus_node = kmalloc(sizeof(*bus_node), GFP_KERNEL); 1390 if (!bus_node) 1391 return -ENOMEM; 1392 1393 bus_node->base = secondary_bus; 1394 bus_node->length = max_bus - secondary_bus + 1; 1395 dbg("found bus_node(base, length) = %x, %x\n", 1396 bus_node->base, bus_node->length); 1397 dbg("populated slot =%d \n", populated_slot); 1398 if (!populated_slot) { 1399 bus_node->next = ctrl->bus_head; 1400 ctrl->bus_head = bus_node; 1401 } else { 1402 bus_node->next = func->bus_head; 1403 func->bus_head = bus_node; 1404 } 1405 } 1406 1407 i--; 1408 one_slot += sizeof(struct slot_rt); 1409 } 1410 1411 /* If all of the following fail, we don't have any resources for 1412 * hot plug add 1413 */ 1414 rc = 1; 1415 rc &= cpqhp_resource_sort_and_combine(&(ctrl->mem_head)); 1416 rc &= cpqhp_resource_sort_and_combine(&(ctrl->p_mem_head)); 1417 rc &= cpqhp_resource_sort_and_combine(&(ctrl->io_head)); 1418 rc &= cpqhp_resource_sort_and_combine(&(ctrl->bus_head)); 1419 1420 return rc; 1421 } 1422 1423 1424 /* 1425 * cpqhp_return_board_resources 1426 * 1427 * this routine returns all resources allocated to a board to 1428 * the available pool. 1429 * 1430 * returns 0 if success 1431 */ 1432 int cpqhp_return_board_resources(struct pci_func *func, struct resource_lists *resources) 1433 { 1434 int rc = 0; 1435 struct pci_resource *node; 1436 struct pci_resource *t_node; 1437 dbg("%s\n", __func__); 1438 1439 if (!func) 1440 return 1; 1441 1442 node = func->io_head; 1443 func->io_head = NULL; 1444 while (node) { 1445 t_node = node->next; 1446 return_resource(&(resources->io_head), node); 1447 node = t_node; 1448 } 1449 1450 node = func->mem_head; 1451 func->mem_head = NULL; 1452 while (node) { 1453 t_node = node->next; 1454 return_resource(&(resources->mem_head), node); 1455 node = t_node; 1456 } 1457 1458 node = func->p_mem_head; 1459 func->p_mem_head = NULL; 1460 while (node) { 1461 t_node = node->next; 1462 return_resource(&(resources->p_mem_head), node); 1463 node = t_node; 1464 } 1465 1466 node = func->bus_head; 1467 func->bus_head = NULL; 1468 while (node) { 1469 t_node = node->next; 1470 return_resource(&(resources->bus_head), node); 1471 node = t_node; 1472 } 1473 1474 rc |= cpqhp_resource_sort_and_combine(&(resources->mem_head)); 1475 rc |= cpqhp_resource_sort_and_combine(&(resources->p_mem_head)); 1476 rc |= cpqhp_resource_sort_and_combine(&(resources->io_head)); 1477 rc |= cpqhp_resource_sort_and_combine(&(resources->bus_head)); 1478 1479 return rc; 1480 } 1481 1482 1483 /* 1484 * cpqhp_destroy_resource_list 1485 * 1486 * Puts node back in the resource list pointed to by head 1487 */ 1488 void cpqhp_destroy_resource_list(struct resource_lists *resources) 1489 { 1490 struct pci_resource *res, *tres; 1491 1492 res = resources->io_head; 1493 resources->io_head = NULL; 1494 1495 while (res) { 1496 tres = res; 1497 res = res->next; 1498 kfree(tres); 1499 } 1500 1501 res = resources->mem_head; 1502 resources->mem_head = NULL; 1503 1504 while (res) { 1505 tres = res; 1506 res = res->next; 1507 kfree(tres); 1508 } 1509 1510 res = resources->p_mem_head; 1511 resources->p_mem_head = NULL; 1512 1513 while (res) { 1514 tres = res; 1515 res = res->next; 1516 kfree(tres); 1517 } 1518 1519 res = resources->bus_head; 1520 resources->bus_head = NULL; 1521 1522 while (res) { 1523 tres = res; 1524 res = res->next; 1525 kfree(tres); 1526 } 1527 } 1528 1529 1530 /* 1531 * cpqhp_destroy_board_resources 1532 * 1533 * Puts node back in the resource list pointed to by head 1534 */ 1535 void cpqhp_destroy_board_resources(struct pci_func *func) 1536 { 1537 struct pci_resource *res, *tres; 1538 1539 res = func->io_head; 1540 func->io_head = NULL; 1541 1542 while (res) { 1543 tres = res; 1544 res = res->next; 1545 kfree(tres); 1546 } 1547 1548 res = func->mem_head; 1549 func->mem_head = NULL; 1550 1551 while (res) { 1552 tres = res; 1553 res = res->next; 1554 kfree(tres); 1555 } 1556 1557 res = func->p_mem_head; 1558 func->p_mem_head = NULL; 1559 1560 while (res) { 1561 tres = res; 1562 res = res->next; 1563 kfree(tres); 1564 } 1565 1566 res = func->bus_head; 1567 func->bus_head = NULL; 1568 1569 while (res) { 1570 tres = res; 1571 res = res->next; 1572 kfree(tres); 1573 } 1574 } 1575