1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Compaq Hot Plug Controller Driver 4 * 5 * Copyright (C) 1995,2001 Compaq Computer Corporation 6 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com) 7 * Copyright (C) 2001 IBM Corp. 8 * 9 * All rights reserved. 10 * 11 * Send feedback to <greg@kroah.com> 12 * 13 */ 14 15 #include <linux/module.h> 16 #include <linux/kernel.h> 17 #include <linux/types.h> 18 #include <linux/slab.h> 19 #include <linux/workqueue.h> 20 #include <linux/proc_fs.h> 21 #include <linux/pci.h> 22 #include <linux/pci_hotplug.h> 23 #include "../pci.h" 24 #include "cpqphp.h" 25 #include "cpqphp_nvram.h" 26 27 28 u8 cpqhp_nic_irq; 29 u8 cpqhp_disk_irq; 30 31 static u16 unused_IRQ; 32 33 /* 34 * detect_HRT_floating_pointer 35 * 36 * find the Hot Plug Resource Table in the specified region of memory. 37 * 38 */ 39 static void __iomem *detect_HRT_floating_pointer(void __iomem *begin, void __iomem *end) 40 { 41 void __iomem *fp; 42 void __iomem *endp; 43 u8 temp1, temp2, temp3, temp4; 44 int status = 0; 45 46 endp = (end - sizeof(struct hrt) + 1); 47 48 for (fp = begin; fp <= endp; fp += 16) { 49 temp1 = readb(fp + SIG0); 50 temp2 = readb(fp + SIG1); 51 temp3 = readb(fp + SIG2); 52 temp4 = readb(fp + SIG3); 53 if (temp1 == '$' && 54 temp2 == 'H' && 55 temp3 == 'R' && 56 temp4 == 'T') { 57 status = 1; 58 break; 59 } 60 } 61 62 if (!status) 63 fp = NULL; 64 65 dbg("Discovered Hotplug Resource Table at %p\n", fp); 66 return fp; 67 } 68 69 70 int cpqhp_configure_device(struct controller *ctrl, struct pci_func *func) 71 { 72 struct pci_bus *child; 73 int num; 74 75 pci_lock_rescan_remove(); 76 77 if (func->pci_dev == NULL) 78 func->pci_dev = pci_get_domain_bus_and_slot(0, func->bus, 79 PCI_DEVFN(func->device, 80 func->function)); 81 82 /* No pci device, we need to create it then */ 83 if (func->pci_dev == NULL) { 84 dbg("INFO: pci_dev still null\n"); 85 86 num = pci_scan_slot(ctrl->pci_dev->bus, PCI_DEVFN(func->device, func->function)); 87 if (num) 88 pci_bus_add_devices(ctrl->pci_dev->bus); 89 90 func->pci_dev = pci_get_domain_bus_and_slot(0, func->bus, 91 PCI_DEVFN(func->device, 92 func->function)); 93 if (func->pci_dev == NULL) { 94 dbg("ERROR: pci_dev still null\n"); 95 goto out; 96 } 97 } 98 99 if (func->pci_dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { 100 pci_hp_add_bridge(func->pci_dev); 101 child = func->pci_dev->subordinate; 102 if (child) 103 pci_bus_add_devices(child); 104 } 105 106 pci_dev_put(func->pci_dev); 107 108 out: 109 pci_unlock_rescan_remove(); 110 return 0; 111 } 112 113 114 int cpqhp_unconfigure_device(struct pci_func *func) 115 { 116 int j; 117 118 dbg("%s: bus/dev/func = %x/%x/%x\n", __func__, func->bus, func->device, func->function); 119 120 pci_lock_rescan_remove(); 121 for (j = 0; j < 8 ; j++) { 122 struct pci_dev *temp = pci_get_domain_bus_and_slot(0, 123 func->bus, 124 PCI_DEVFN(func->device, 125 j)); 126 if (temp) { 127 pci_dev_put(temp); 128 pci_stop_and_remove_bus_device(temp); 129 } 130 } 131 pci_unlock_rescan_remove(); 132 return 0; 133 } 134 135 static int PCI_RefinedAccessConfig(struct pci_bus *bus, unsigned int devfn, u8 offset, u32 *value) 136 { 137 u32 vendID = 0; 138 139 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &vendID) == -1) 140 return -1; 141 if (vendID == 0xffffffff) 142 return -1; 143 return pci_bus_read_config_dword(bus, devfn, offset, value); 144 } 145 146 147 /* 148 * cpqhp_set_irq 149 * 150 * @bus_num: bus number of PCI device 151 * @dev_num: device number of PCI device 152 * @slot: pointer to u8 where slot number will be returned 153 */ 154 int cpqhp_set_irq(u8 bus_num, u8 dev_num, u8 int_pin, u8 irq_num) 155 { 156 int rc = 0; 157 158 if (cpqhp_legacy_mode) { 159 struct pci_dev *fakedev; 160 struct pci_bus *fakebus; 161 u16 temp_word; 162 163 fakedev = kmalloc(sizeof(*fakedev), GFP_KERNEL); 164 fakebus = kmalloc(sizeof(*fakebus), GFP_KERNEL); 165 if (!fakedev || !fakebus) { 166 kfree(fakedev); 167 kfree(fakebus); 168 return -ENOMEM; 169 } 170 171 fakedev->devfn = dev_num << 3; 172 fakedev->bus = fakebus; 173 fakebus->number = bus_num; 174 dbg("%s: dev %d, bus %d, pin %d, num %d\n", 175 __func__, dev_num, bus_num, int_pin, irq_num); 176 rc = pcibios_set_irq_routing(fakedev, int_pin - 1, irq_num); 177 kfree(fakedev); 178 kfree(fakebus); 179 dbg("%s: rc %d\n", __func__, rc); 180 if (!rc) 181 return !rc; 182 183 /* set the Edge Level Control Register (ELCR) */ 184 temp_word = inb(0x4d0); 185 temp_word |= inb(0x4d1) << 8; 186 187 temp_word |= 0x01 << irq_num; 188 189 /* This should only be for x86 as it sets the Edge Level 190 * Control Register 191 */ 192 outb((u8)(temp_word & 0xFF), 0x4d0); 193 outb((u8)((temp_word & 0xFF00) >> 8), 0x4d1); 194 rc = 0; 195 } 196 197 return rc; 198 } 199 200 201 static int PCI_ScanBusForNonBridge(struct controller *ctrl, u8 bus_num, u8 *dev_num) 202 { 203 u16 tdevice; 204 u32 work; 205 u8 tbus; 206 207 ctrl->pci_bus->number = bus_num; 208 209 for (tdevice = 0; tdevice < 0xFF; tdevice++) { 210 /* Scan for access first */ 211 if (PCI_RefinedAccessConfig(ctrl->pci_bus, tdevice, 0x08, &work) == -1) 212 continue; 213 dbg("Looking for nonbridge bus_num %d dev_num %d\n", bus_num, tdevice); 214 /* Yep we got one. Not a bridge ? */ 215 if ((work >> 8) != PCI_TO_PCI_BRIDGE_CLASS) { 216 *dev_num = tdevice; 217 dbg("found it !\n"); 218 return 0; 219 } 220 } 221 for (tdevice = 0; tdevice < 0xFF; tdevice++) { 222 /* Scan for access first */ 223 if (PCI_RefinedAccessConfig(ctrl->pci_bus, tdevice, 0x08, &work) == -1) 224 continue; 225 dbg("Looking for bridge bus_num %d dev_num %d\n", bus_num, tdevice); 226 /* Yep we got one. bridge ? */ 227 if ((work >> 8) == PCI_TO_PCI_BRIDGE_CLASS) { 228 pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(tdevice, 0), PCI_SECONDARY_BUS, &tbus); 229 /* XXX: no recursion, wtf? */ 230 dbg("Recurse on bus_num %d tdevice %d\n", tbus, tdevice); 231 return 0; 232 } 233 } 234 235 return -1; 236 } 237 238 239 static int PCI_GetBusDevHelper(struct controller *ctrl, u8 *bus_num, u8 *dev_num, u8 slot, u8 nobridge) 240 { 241 int loop, len; 242 u32 work; 243 u8 tbus, tdevice, tslot; 244 245 len = cpqhp_routing_table_length(); 246 for (loop = 0; loop < len; ++loop) { 247 tbus = cpqhp_routing_table->slots[loop].bus; 248 tdevice = cpqhp_routing_table->slots[loop].devfn; 249 tslot = cpqhp_routing_table->slots[loop].slot; 250 251 if (tslot == slot) { 252 *bus_num = tbus; 253 *dev_num = tdevice; 254 ctrl->pci_bus->number = tbus; 255 pci_bus_read_config_dword(ctrl->pci_bus, *dev_num, PCI_VENDOR_ID, &work); 256 if (!nobridge || (work == 0xffffffff)) 257 return 0; 258 259 dbg("bus_num %d devfn %d\n", *bus_num, *dev_num); 260 pci_bus_read_config_dword(ctrl->pci_bus, *dev_num, PCI_CLASS_REVISION, &work); 261 dbg("work >> 8 (%x) = BRIDGE (%x)\n", work >> 8, PCI_TO_PCI_BRIDGE_CLASS); 262 263 if ((work >> 8) == PCI_TO_PCI_BRIDGE_CLASS) { 264 pci_bus_read_config_byte(ctrl->pci_bus, *dev_num, PCI_SECONDARY_BUS, &tbus); 265 dbg("Scan bus for Non Bridge: bus %d\n", tbus); 266 if (PCI_ScanBusForNonBridge(ctrl, tbus, dev_num) == 0) { 267 *bus_num = tbus; 268 return 0; 269 } 270 } else 271 return 0; 272 } 273 } 274 return -1; 275 } 276 277 278 int cpqhp_get_bus_dev(struct controller *ctrl, u8 *bus_num, u8 *dev_num, u8 slot) 279 { 280 /* plain (bridges allowed) */ 281 return PCI_GetBusDevHelper(ctrl, bus_num, dev_num, slot, 0); 282 } 283 284 285 /* More PCI configuration routines; this time centered around hotplug 286 * controller 287 */ 288 289 290 /* 291 * cpqhp_save_config 292 * 293 * Reads configuration for all slots in a PCI bus and saves info. 294 * 295 * Note: For non-hot plug buses, the slot # saved is the device # 296 * 297 * returns 0 if success 298 */ 299 int cpqhp_save_config(struct controller *ctrl, int busnumber, int is_hot_plug) 300 { 301 long rc; 302 u8 class_code; 303 u8 header_type; 304 u32 ID; 305 u8 secondary_bus; 306 struct pci_func *new_slot; 307 int sub_bus; 308 int FirstSupported; 309 int LastSupported; 310 int max_functions; 311 int function; 312 u8 DevError; 313 int device = 0; 314 int cloop = 0; 315 int stop_it; 316 int index; 317 u16 devfn; 318 319 /* Decide which slots are supported */ 320 321 if (is_hot_plug) { 322 /* 323 * is_hot_plug is the slot mask 324 */ 325 FirstSupported = is_hot_plug >> 4; 326 LastSupported = FirstSupported + (is_hot_plug & 0x0F) - 1; 327 } else { 328 FirstSupported = 0; 329 LastSupported = 0x1F; 330 } 331 332 /* Save PCI configuration space for all devices in supported slots */ 333 ctrl->pci_bus->number = busnumber; 334 for (device = FirstSupported; device <= LastSupported; device++) { 335 ID = 0xFFFFFFFF; 336 rc = pci_bus_read_config_dword(ctrl->pci_bus, PCI_DEVFN(device, 0), PCI_VENDOR_ID, &ID); 337 338 if (ID == 0xFFFFFFFF) { 339 if (is_hot_plug) { 340 /* Setup slot structure with entry for empty 341 * slot 342 */ 343 new_slot = cpqhp_slot_create(busnumber); 344 if (new_slot == NULL) 345 return 1; 346 347 new_slot->bus = (u8) busnumber; 348 new_slot->device = (u8) device; 349 new_slot->function = 0; 350 new_slot->is_a_board = 0; 351 new_slot->presence_save = 0; 352 new_slot->switch_save = 0; 353 } 354 continue; 355 } 356 357 rc = pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(device, 0), 0x0B, &class_code); 358 if (rc) 359 return rc; 360 361 rc = pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(device, 0), PCI_HEADER_TYPE, &header_type); 362 if (rc) 363 return rc; 364 365 /* If multi-function device, set max_functions to 8 */ 366 if (header_type & PCI_HEADER_TYPE_MFD) 367 max_functions = 8; 368 else 369 max_functions = 1; 370 371 function = 0; 372 373 do { 374 DevError = 0; 375 if ((header_type & PCI_HEADER_TYPE_MASK) == PCI_HEADER_TYPE_BRIDGE) { 376 /* Recurse the subordinate bus 377 * get the subordinate bus number 378 */ 379 rc = pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(device, function), PCI_SECONDARY_BUS, &secondary_bus); 380 if (rc) { 381 return rc; 382 } else { 383 sub_bus = (int) secondary_bus; 384 385 /* Save secondary bus cfg spc 386 * with this recursive call. 387 */ 388 rc = cpqhp_save_config(ctrl, sub_bus, 0); 389 if (rc) 390 return rc; 391 ctrl->pci_bus->number = busnumber; 392 } 393 } 394 395 index = 0; 396 new_slot = cpqhp_slot_find(busnumber, device, index++); 397 while (new_slot && 398 (new_slot->function != (u8) function)) 399 new_slot = cpqhp_slot_find(busnumber, device, index++); 400 401 if (!new_slot) { 402 /* Setup slot structure. */ 403 new_slot = cpqhp_slot_create(busnumber); 404 if (new_slot == NULL) 405 return 1; 406 } 407 408 new_slot->bus = (u8) busnumber; 409 new_slot->device = (u8) device; 410 new_slot->function = (u8) function; 411 new_slot->is_a_board = 1; 412 new_slot->switch_save = 0x10; 413 /* In case of unsupported board */ 414 new_slot->status = DevError; 415 devfn = (new_slot->device << 3) | new_slot->function; 416 new_slot->pci_dev = pci_get_domain_bus_and_slot(0, 417 new_slot->bus, devfn); 418 419 for (cloop = 0; cloop < 0x20; cloop++) { 420 rc = pci_bus_read_config_dword(ctrl->pci_bus, PCI_DEVFN(device, function), cloop << 2, (u32 *) &(new_slot->config_space[cloop])); 421 if (rc) 422 return rc; 423 } 424 425 pci_dev_put(new_slot->pci_dev); 426 427 function++; 428 429 stop_it = 0; 430 431 /* this loop skips to the next present function 432 * reading in Class Code and Header type. 433 */ 434 while ((function < max_functions) && (!stop_it)) { 435 rc = pci_bus_read_config_dword(ctrl->pci_bus, PCI_DEVFN(device, function), PCI_VENDOR_ID, &ID); 436 if (ID == 0xFFFFFFFF) { 437 function++; 438 continue; 439 } 440 rc = pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(device, function), 0x0B, &class_code); 441 if (rc) 442 return rc; 443 444 rc = pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(device, function), PCI_HEADER_TYPE, &header_type); 445 if (rc) 446 return rc; 447 448 stop_it++; 449 } 450 451 } while (function < max_functions); 452 } /* End of FOR loop */ 453 454 return 0; 455 } 456 457 458 /* 459 * cpqhp_save_slot_config 460 * 461 * Saves configuration info for all PCI devices in a given slot 462 * including subordinate buses. 463 * 464 * returns 0 if success 465 */ 466 int cpqhp_save_slot_config(struct controller *ctrl, struct pci_func *new_slot) 467 { 468 long rc; 469 u8 class_code; 470 u8 header_type; 471 u32 ID; 472 u8 secondary_bus; 473 int sub_bus; 474 int max_functions; 475 int function = 0; 476 int cloop; 477 int stop_it; 478 479 ID = 0xFFFFFFFF; 480 481 ctrl->pci_bus->number = new_slot->bus; 482 pci_bus_read_config_dword(ctrl->pci_bus, PCI_DEVFN(new_slot->device, 0), PCI_VENDOR_ID, &ID); 483 484 if (ID == 0xFFFFFFFF) 485 return 2; 486 487 pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(new_slot->device, 0), 0x0B, &class_code); 488 pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(new_slot->device, 0), PCI_HEADER_TYPE, &header_type); 489 490 if (header_type & PCI_HEADER_TYPE_MFD) 491 max_functions = 8; 492 else 493 max_functions = 1; 494 495 while (function < max_functions) { 496 if ((header_type & PCI_HEADER_TYPE_MASK) == PCI_HEADER_TYPE_BRIDGE) { 497 /* Recurse the subordinate bus */ 498 pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(new_slot->device, function), PCI_SECONDARY_BUS, &secondary_bus); 499 500 sub_bus = (int) secondary_bus; 501 502 /* Save the config headers for the secondary 503 * bus. 504 */ 505 rc = cpqhp_save_config(ctrl, sub_bus, 0); 506 if (rc) 507 return(rc); 508 ctrl->pci_bus->number = new_slot->bus; 509 510 } 511 512 new_slot->status = 0; 513 514 for (cloop = 0; cloop < 0x20; cloop++) 515 pci_bus_read_config_dword(ctrl->pci_bus, PCI_DEVFN(new_slot->device, function), cloop << 2, (u32 *) &(new_slot->config_space[cloop])); 516 517 function++; 518 519 stop_it = 0; 520 521 /* this loop skips to the next present function 522 * reading in the Class Code and the Header type. 523 */ 524 while ((function < max_functions) && (!stop_it)) { 525 pci_bus_read_config_dword(ctrl->pci_bus, PCI_DEVFN(new_slot->device, function), PCI_VENDOR_ID, &ID); 526 527 if (ID == 0xFFFFFFFF) 528 function++; 529 else { 530 pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(new_slot->device, function), 0x0B, &class_code); 531 pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(new_slot->device, function), PCI_HEADER_TYPE, &header_type); 532 stop_it++; 533 } 534 } 535 536 } 537 538 return 0; 539 } 540 541 542 /* 543 * cpqhp_save_base_addr_length 544 * 545 * Saves the length of all base address registers for the 546 * specified slot. this is for hot plug REPLACE 547 * 548 * returns 0 if success 549 */ 550 int cpqhp_save_base_addr_length(struct controller *ctrl, struct pci_func *func) 551 { 552 u8 cloop; 553 u8 header_type; 554 u8 secondary_bus; 555 u8 type; 556 int sub_bus; 557 u32 temp_register; 558 u32 base; 559 u32 rc; 560 struct pci_func *next; 561 int index = 0; 562 struct pci_bus *pci_bus = ctrl->pci_bus; 563 unsigned int devfn; 564 565 func = cpqhp_slot_find(func->bus, func->device, index++); 566 567 while (func != NULL) { 568 pci_bus->number = func->bus; 569 devfn = PCI_DEVFN(func->device, func->function); 570 571 /* Check for Bridge */ 572 pci_bus_read_config_byte(pci_bus, devfn, PCI_HEADER_TYPE, &header_type); 573 574 if ((header_type & PCI_HEADER_TYPE_MASK) == PCI_HEADER_TYPE_BRIDGE) { 575 pci_bus_read_config_byte(pci_bus, devfn, PCI_SECONDARY_BUS, &secondary_bus); 576 577 sub_bus = (int) secondary_bus; 578 579 next = cpqhp_slot_list[sub_bus]; 580 581 while (next != NULL) { 582 rc = cpqhp_save_base_addr_length(ctrl, next); 583 if (rc) 584 return rc; 585 586 next = next->next; 587 } 588 pci_bus->number = func->bus; 589 590 /* FIXME: this loop is duplicated in the non-bridge 591 * case. The two could be rolled together Figure out 592 * IO and memory base lengths 593 */ 594 for (cloop = 0x10; cloop <= 0x14; cloop += 4) { 595 temp_register = 0xFFFFFFFF; 596 pci_bus_write_config_dword(pci_bus, devfn, cloop, temp_register); 597 pci_bus_read_config_dword(pci_bus, devfn, cloop, &base); 598 /* If this register is implemented */ 599 if (base) { 600 if (base & 0x01L) { 601 /* IO base 602 * set base = amount of IO space 603 * requested 604 */ 605 base = base & 0xFFFFFFFE; 606 base = (~base) + 1; 607 608 type = 1; 609 } else { 610 /* memory base */ 611 base = base & 0xFFFFFFF0; 612 base = (~base) + 1; 613 614 type = 0; 615 } 616 } else { 617 base = 0x0L; 618 type = 0; 619 } 620 621 /* Save information in slot structure */ 622 func->base_length[(cloop - 0x10) >> 2] = 623 base; 624 func->base_type[(cloop - 0x10) >> 2] = type; 625 626 } /* End of base register loop */ 627 628 } else if ((header_type & PCI_HEADER_TYPE_MASK) == PCI_HEADER_TYPE_NORMAL) { 629 /* Figure out IO and memory base lengths */ 630 for (cloop = 0x10; cloop <= 0x24; cloop += 4) { 631 temp_register = 0xFFFFFFFF; 632 pci_bus_write_config_dword(pci_bus, devfn, cloop, temp_register); 633 pci_bus_read_config_dword(pci_bus, devfn, cloop, &base); 634 635 /* If this register is implemented */ 636 if (base) { 637 if (base & 0x01L) { 638 /* IO base 639 * base = amount of IO space 640 * requested 641 */ 642 base = base & 0xFFFFFFFE; 643 base = (~base) + 1; 644 645 type = 1; 646 } else { 647 /* memory base 648 * base = amount of memory 649 * space requested 650 */ 651 base = base & 0xFFFFFFF0; 652 base = (~base) + 1; 653 654 type = 0; 655 } 656 } else { 657 base = 0x0L; 658 type = 0; 659 } 660 661 /* Save information in slot structure */ 662 func->base_length[(cloop - 0x10) >> 2] = base; 663 func->base_type[(cloop - 0x10) >> 2] = type; 664 665 } /* End of base register loop */ 666 667 } else { /* Some other unknown header type */ 668 } 669 670 /* find the next device in this slot */ 671 func = cpqhp_slot_find(func->bus, func->device, index++); 672 } 673 674 return(0); 675 } 676 677 678 /* 679 * cpqhp_save_used_resources 680 * 681 * Stores used resource information for existing boards. this is 682 * for boards that were in the system when this driver was loaded. 683 * this function is for hot plug ADD 684 * 685 * returns 0 if success 686 */ 687 int cpqhp_save_used_resources(struct controller *ctrl, struct pci_func *func) 688 { 689 u8 cloop; 690 u8 header_type; 691 u8 secondary_bus; 692 u8 temp_byte; 693 u8 b_base; 694 u8 b_length; 695 u16 command; 696 u16 save_command; 697 u16 w_base; 698 u16 w_length; 699 u32 temp_register; 700 u32 save_base; 701 u32 base; 702 int index = 0; 703 struct pci_resource *mem_node; 704 struct pci_resource *p_mem_node; 705 struct pci_resource *io_node; 706 struct pci_resource *bus_node; 707 struct pci_bus *pci_bus = ctrl->pci_bus; 708 unsigned int devfn; 709 710 func = cpqhp_slot_find(func->bus, func->device, index++); 711 712 while ((func != NULL) && func->is_a_board) { 713 pci_bus->number = func->bus; 714 devfn = PCI_DEVFN(func->device, func->function); 715 716 /* Save the command register */ 717 pci_bus_read_config_word(pci_bus, devfn, PCI_COMMAND, &save_command); 718 719 /* disable card */ 720 command = 0x00; 721 pci_bus_write_config_word(pci_bus, devfn, PCI_COMMAND, command); 722 723 /* Check for Bridge */ 724 pci_bus_read_config_byte(pci_bus, devfn, PCI_HEADER_TYPE, &header_type); 725 726 if ((header_type & PCI_HEADER_TYPE_MASK) == PCI_HEADER_TYPE_BRIDGE) { 727 /* Clear Bridge Control Register */ 728 command = 0x00; 729 pci_bus_write_config_word(pci_bus, devfn, PCI_BRIDGE_CONTROL, command); 730 pci_bus_read_config_byte(pci_bus, devfn, PCI_SECONDARY_BUS, &secondary_bus); 731 pci_bus_read_config_byte(pci_bus, devfn, PCI_SUBORDINATE_BUS, &temp_byte); 732 733 bus_node = kmalloc(sizeof(*bus_node), GFP_KERNEL); 734 if (!bus_node) 735 return -ENOMEM; 736 737 bus_node->base = secondary_bus; 738 bus_node->length = temp_byte - secondary_bus + 1; 739 740 bus_node->next = func->bus_head; 741 func->bus_head = bus_node; 742 743 /* Save IO base and Limit registers */ 744 pci_bus_read_config_byte(pci_bus, devfn, PCI_IO_BASE, &b_base); 745 pci_bus_read_config_byte(pci_bus, devfn, PCI_IO_LIMIT, &b_length); 746 747 if ((b_base <= b_length) && (save_command & 0x01)) { 748 io_node = kmalloc(sizeof(*io_node), GFP_KERNEL); 749 if (!io_node) 750 return -ENOMEM; 751 752 io_node->base = (b_base & 0xF0) << 8; 753 io_node->length = (b_length - b_base + 0x10) << 8; 754 755 io_node->next = func->io_head; 756 func->io_head = io_node; 757 } 758 759 /* Save memory base and Limit registers */ 760 pci_bus_read_config_word(pci_bus, devfn, PCI_MEMORY_BASE, &w_base); 761 pci_bus_read_config_word(pci_bus, devfn, PCI_MEMORY_LIMIT, &w_length); 762 763 if ((w_base <= w_length) && (save_command & 0x02)) { 764 mem_node = kmalloc(sizeof(*mem_node), GFP_KERNEL); 765 if (!mem_node) 766 return -ENOMEM; 767 768 mem_node->base = w_base << 16; 769 mem_node->length = (w_length - w_base + 0x10) << 16; 770 771 mem_node->next = func->mem_head; 772 func->mem_head = mem_node; 773 } 774 775 /* Save prefetchable memory base and Limit registers */ 776 pci_bus_read_config_word(pci_bus, devfn, PCI_PREF_MEMORY_BASE, &w_base); 777 pci_bus_read_config_word(pci_bus, devfn, PCI_PREF_MEMORY_LIMIT, &w_length); 778 779 if ((w_base <= w_length) && (save_command & 0x02)) { 780 p_mem_node = kmalloc(sizeof(*p_mem_node), GFP_KERNEL); 781 if (!p_mem_node) 782 return -ENOMEM; 783 784 p_mem_node->base = w_base << 16; 785 p_mem_node->length = (w_length - w_base + 0x10) << 16; 786 787 p_mem_node->next = func->p_mem_head; 788 func->p_mem_head = p_mem_node; 789 } 790 /* Figure out IO and memory base lengths */ 791 for (cloop = 0x10; cloop <= 0x14; cloop += 4) { 792 pci_bus_read_config_dword(pci_bus, devfn, cloop, &save_base); 793 794 temp_register = 0xFFFFFFFF; 795 pci_bus_write_config_dword(pci_bus, devfn, cloop, temp_register); 796 pci_bus_read_config_dword(pci_bus, devfn, cloop, &base); 797 798 temp_register = base; 799 800 /* If this register is implemented */ 801 if (base) { 802 if (((base & 0x03L) == 0x01) 803 && (save_command & 0x01)) { 804 /* IO base 805 * set temp_register = amount 806 * of IO space requested 807 */ 808 temp_register = base & 0xFFFFFFFE; 809 temp_register = (~temp_register) + 1; 810 811 io_node = kmalloc(sizeof(*io_node), 812 GFP_KERNEL); 813 if (!io_node) 814 return -ENOMEM; 815 816 io_node->base = 817 save_base & (~0x03L); 818 io_node->length = temp_register; 819 820 io_node->next = func->io_head; 821 func->io_head = io_node; 822 } else 823 if (((base & 0x0BL) == 0x08) 824 && (save_command & 0x02)) { 825 /* prefetchable memory base */ 826 temp_register = base & 0xFFFFFFF0; 827 temp_register = (~temp_register) + 1; 828 829 p_mem_node = kmalloc(sizeof(*p_mem_node), 830 GFP_KERNEL); 831 if (!p_mem_node) 832 return -ENOMEM; 833 834 p_mem_node->base = save_base & (~0x0FL); 835 p_mem_node->length = temp_register; 836 837 p_mem_node->next = func->p_mem_head; 838 func->p_mem_head = p_mem_node; 839 } else 840 if (((base & 0x0BL) == 0x00) 841 && (save_command & 0x02)) { 842 /* prefetchable memory base */ 843 temp_register = base & 0xFFFFFFF0; 844 temp_register = (~temp_register) + 1; 845 846 mem_node = kmalloc(sizeof(*mem_node), 847 GFP_KERNEL); 848 if (!mem_node) 849 return -ENOMEM; 850 851 mem_node->base = save_base & (~0x0FL); 852 mem_node->length = temp_register; 853 854 mem_node->next = func->mem_head; 855 func->mem_head = mem_node; 856 } else 857 return(1); 858 } 859 } /* End of base register loop */ 860 /* Standard header */ 861 } else if ((header_type & PCI_HEADER_TYPE_MASK) == PCI_HEADER_TYPE_NORMAL) { 862 /* Figure out IO and memory base lengths */ 863 for (cloop = 0x10; cloop <= 0x24; cloop += 4) { 864 pci_bus_read_config_dword(pci_bus, devfn, cloop, &save_base); 865 866 temp_register = 0xFFFFFFFF; 867 pci_bus_write_config_dword(pci_bus, devfn, cloop, temp_register); 868 pci_bus_read_config_dword(pci_bus, devfn, cloop, &base); 869 870 temp_register = base; 871 872 /* If this register is implemented */ 873 if (base) { 874 if (((base & 0x03L) == 0x01) 875 && (save_command & 0x01)) { 876 /* IO base 877 * set temp_register = amount 878 * of IO space requested 879 */ 880 temp_register = base & 0xFFFFFFFE; 881 temp_register = (~temp_register) + 1; 882 883 io_node = kmalloc(sizeof(*io_node), 884 GFP_KERNEL); 885 if (!io_node) 886 return -ENOMEM; 887 888 io_node->base = save_base & (~0x01L); 889 io_node->length = temp_register; 890 891 io_node->next = func->io_head; 892 func->io_head = io_node; 893 } else 894 if (((base & 0x0BL) == 0x08) 895 && (save_command & 0x02)) { 896 /* prefetchable memory base */ 897 temp_register = base & 0xFFFFFFF0; 898 temp_register = (~temp_register) + 1; 899 900 p_mem_node = kmalloc(sizeof(*p_mem_node), 901 GFP_KERNEL); 902 if (!p_mem_node) 903 return -ENOMEM; 904 905 p_mem_node->base = save_base & (~0x0FL); 906 p_mem_node->length = temp_register; 907 908 p_mem_node->next = func->p_mem_head; 909 func->p_mem_head = p_mem_node; 910 } else 911 if (((base & 0x0BL) == 0x00) 912 && (save_command & 0x02)) { 913 /* prefetchable memory base */ 914 temp_register = base & 0xFFFFFFF0; 915 temp_register = (~temp_register) + 1; 916 917 mem_node = kmalloc(sizeof(*mem_node), 918 GFP_KERNEL); 919 if (!mem_node) 920 return -ENOMEM; 921 922 mem_node->base = save_base & (~0x0FL); 923 mem_node->length = temp_register; 924 925 mem_node->next = func->mem_head; 926 func->mem_head = mem_node; 927 } else 928 return(1); 929 } 930 } /* End of base register loop */ 931 } 932 933 /* find the next device in this slot */ 934 func = cpqhp_slot_find(func->bus, func->device, index++); 935 } 936 937 return 0; 938 } 939 940 941 /* 942 * cpqhp_configure_board 943 * 944 * Copies saved configuration information to one slot. 945 * this is called recursively for bridge devices. 946 * this is for hot plug REPLACE! 947 * 948 * returns 0 if success 949 */ 950 int cpqhp_configure_board(struct controller *ctrl, struct pci_func *func) 951 { 952 int cloop; 953 u8 header_type; 954 u8 secondary_bus; 955 int sub_bus; 956 struct pci_func *next; 957 u32 temp; 958 u32 rc; 959 int index = 0; 960 struct pci_bus *pci_bus = ctrl->pci_bus; 961 unsigned int devfn; 962 963 func = cpqhp_slot_find(func->bus, func->device, index++); 964 965 while (func != NULL) { 966 pci_bus->number = func->bus; 967 devfn = PCI_DEVFN(func->device, func->function); 968 969 /* Start at the top of config space so that the control 970 * registers are programmed last 971 */ 972 for (cloop = 0x3C; cloop > 0; cloop -= 4) 973 pci_bus_write_config_dword(pci_bus, devfn, cloop, func->config_space[cloop >> 2]); 974 975 pci_bus_read_config_byte(pci_bus, devfn, PCI_HEADER_TYPE, &header_type); 976 977 /* If this is a bridge device, restore subordinate devices */ 978 if ((header_type & PCI_HEADER_TYPE_MASK) == PCI_HEADER_TYPE_BRIDGE) { 979 pci_bus_read_config_byte(pci_bus, devfn, PCI_SECONDARY_BUS, &secondary_bus); 980 981 sub_bus = (int) secondary_bus; 982 983 next = cpqhp_slot_list[sub_bus]; 984 985 while (next != NULL) { 986 rc = cpqhp_configure_board(ctrl, next); 987 if (rc) 988 return rc; 989 990 next = next->next; 991 } 992 } else { 993 994 /* Check all the base Address Registers to make sure 995 * they are the same. If not, the board is different. 996 */ 997 998 for (cloop = 16; cloop < 40; cloop += 4) { 999 pci_bus_read_config_dword(pci_bus, devfn, cloop, &temp); 1000 1001 if (temp != func->config_space[cloop >> 2]) { 1002 dbg("Config space compare failure!!! offset = %x\n", cloop); 1003 dbg("bus = %x, device = %x, function = %x\n", func->bus, func->device, func->function); 1004 dbg("temp = %x, config space = %x\n\n", temp, func->config_space[cloop >> 2]); 1005 return 1; 1006 } 1007 } 1008 } 1009 1010 func->configured = 1; 1011 1012 func = cpqhp_slot_find(func->bus, func->device, index++); 1013 } 1014 1015 return 0; 1016 } 1017 1018 1019 /* 1020 * cpqhp_valid_replace 1021 * 1022 * this function checks to see if a board is the same as the 1023 * one it is replacing. this check will detect if the device's 1024 * vendor or device id's are the same 1025 * 1026 * returns 0 if the board is the same nonzero otherwise 1027 */ 1028 int cpqhp_valid_replace(struct controller *ctrl, struct pci_func *func) 1029 { 1030 u8 cloop; 1031 u8 header_type; 1032 u8 secondary_bus; 1033 u8 type; 1034 u32 temp_register = 0; 1035 u32 base; 1036 u32 rc; 1037 struct pci_func *next; 1038 int index = 0; 1039 struct pci_bus *pci_bus = ctrl->pci_bus; 1040 unsigned int devfn; 1041 1042 if (!func->is_a_board) 1043 return(ADD_NOT_SUPPORTED); 1044 1045 func = cpqhp_slot_find(func->bus, func->device, index++); 1046 1047 while (func != NULL) { 1048 pci_bus->number = func->bus; 1049 devfn = PCI_DEVFN(func->device, func->function); 1050 1051 pci_bus_read_config_dword(pci_bus, devfn, PCI_VENDOR_ID, &temp_register); 1052 1053 /* No adapter present */ 1054 if (temp_register == 0xFFFFFFFF) 1055 return(NO_ADAPTER_PRESENT); 1056 1057 if (temp_register != func->config_space[0]) 1058 return(ADAPTER_NOT_SAME); 1059 1060 /* Check for same revision number and class code */ 1061 pci_bus_read_config_dword(pci_bus, devfn, PCI_CLASS_REVISION, &temp_register); 1062 1063 /* Adapter not the same */ 1064 if (temp_register != func->config_space[0x08 >> 2]) 1065 return(ADAPTER_NOT_SAME); 1066 1067 /* Check for Bridge */ 1068 pci_bus_read_config_byte(pci_bus, devfn, PCI_HEADER_TYPE, &header_type); 1069 1070 if ((header_type & PCI_HEADER_TYPE_MASK) == PCI_HEADER_TYPE_BRIDGE) { 1071 /* In order to continue checking, we must program the 1072 * bus registers in the bridge to respond to accesses 1073 * for its subordinate bus(es) 1074 */ 1075 1076 temp_register = func->config_space[0x18 >> 2]; 1077 pci_bus_write_config_dword(pci_bus, devfn, PCI_PRIMARY_BUS, temp_register); 1078 1079 secondary_bus = (temp_register >> 8) & 0xFF; 1080 1081 next = cpqhp_slot_list[secondary_bus]; 1082 1083 while (next != NULL) { 1084 rc = cpqhp_valid_replace(ctrl, next); 1085 if (rc) 1086 return rc; 1087 1088 next = next->next; 1089 } 1090 1091 } 1092 /* Check to see if it is a standard config header */ 1093 else if ((header_type & PCI_HEADER_TYPE_MASK) == PCI_HEADER_TYPE_NORMAL) { 1094 /* Check subsystem vendor and ID */ 1095 pci_bus_read_config_dword(pci_bus, devfn, PCI_SUBSYSTEM_VENDOR_ID, &temp_register); 1096 1097 if (temp_register != func->config_space[0x2C >> 2]) { 1098 /* If it's a SMART-2 and the register isn't 1099 * filled in, ignore the difference because 1100 * they just have an old rev of the firmware 1101 */ 1102 if (!((func->config_space[0] == 0xAE100E11) 1103 && (temp_register == 0x00L))) 1104 return(ADAPTER_NOT_SAME); 1105 } 1106 /* Figure out IO and memory base lengths */ 1107 for (cloop = 0x10; cloop <= 0x24; cloop += 4) { 1108 temp_register = 0xFFFFFFFF; 1109 pci_bus_write_config_dword(pci_bus, devfn, cloop, temp_register); 1110 pci_bus_read_config_dword(pci_bus, devfn, cloop, &base); 1111 1112 /* If this register is implemented */ 1113 if (base) { 1114 if (base & 0x01L) { 1115 /* IO base 1116 * set base = amount of IO 1117 * space requested 1118 */ 1119 base = base & 0xFFFFFFFE; 1120 base = (~base) + 1; 1121 1122 type = 1; 1123 } else { 1124 /* memory base */ 1125 base = base & 0xFFFFFFF0; 1126 base = (~base) + 1; 1127 1128 type = 0; 1129 } 1130 } else { 1131 base = 0x0L; 1132 type = 0; 1133 } 1134 1135 /* Check information in slot structure */ 1136 if (func->base_length[(cloop - 0x10) >> 2] != base) 1137 return(ADAPTER_NOT_SAME); 1138 1139 if (func->base_type[(cloop - 0x10) >> 2] != type) 1140 return(ADAPTER_NOT_SAME); 1141 1142 } /* End of base register loop */ 1143 1144 } /* End of (type 0 config space) else */ 1145 else { 1146 /* this is not a type 0 or 1 config space header so 1147 * we don't know how to do it 1148 */ 1149 return(DEVICE_TYPE_NOT_SUPPORTED); 1150 } 1151 1152 /* Get the next function */ 1153 func = cpqhp_slot_find(func->bus, func->device, index++); 1154 } 1155 1156 1157 return 0; 1158 } 1159 1160 1161 /* 1162 * cpqhp_find_available_resources 1163 * 1164 * Finds available memory, IO, and IRQ resources for programming 1165 * devices which may be added to the system 1166 * this function is for hot plug ADD! 1167 * 1168 * returns 0 if success 1169 */ 1170 int cpqhp_find_available_resources(struct controller *ctrl, void __iomem *rom_start) 1171 { 1172 u8 temp; 1173 u8 populated_slot; 1174 u8 bridged_slot; 1175 void __iomem *one_slot; 1176 void __iomem *rom_resource_table; 1177 struct pci_func *func = NULL; 1178 int i = 10, index; 1179 u32 temp_dword, rc; 1180 struct pci_resource *mem_node; 1181 struct pci_resource *p_mem_node; 1182 struct pci_resource *io_node; 1183 struct pci_resource *bus_node; 1184 1185 rom_resource_table = detect_HRT_floating_pointer(rom_start, rom_start+0xffff); 1186 dbg("rom_resource_table = %p\n", rom_resource_table); 1187 1188 if (rom_resource_table == NULL) 1189 return -ENODEV; 1190 1191 /* Sum all resources and setup resource maps */ 1192 unused_IRQ = readl(rom_resource_table + UNUSED_IRQ); 1193 dbg("unused_IRQ = %x\n", unused_IRQ); 1194 1195 temp = 0; 1196 while (unused_IRQ) { 1197 if (unused_IRQ & 1) { 1198 cpqhp_disk_irq = temp; 1199 break; 1200 } 1201 unused_IRQ = unused_IRQ >> 1; 1202 temp++; 1203 } 1204 1205 dbg("cpqhp_disk_irq= %d\n", cpqhp_disk_irq); 1206 unused_IRQ = unused_IRQ >> 1; 1207 temp++; 1208 1209 while (unused_IRQ) { 1210 if (unused_IRQ & 1) { 1211 cpqhp_nic_irq = temp; 1212 break; 1213 } 1214 unused_IRQ = unused_IRQ >> 1; 1215 temp++; 1216 } 1217 1218 dbg("cpqhp_nic_irq= %d\n", cpqhp_nic_irq); 1219 unused_IRQ = readl(rom_resource_table + PCIIRQ); 1220 1221 temp = 0; 1222 1223 if (!cpqhp_nic_irq) 1224 cpqhp_nic_irq = ctrl->cfgspc_irq; 1225 1226 if (!cpqhp_disk_irq) 1227 cpqhp_disk_irq = ctrl->cfgspc_irq; 1228 1229 dbg("cpqhp_disk_irq, cpqhp_nic_irq= %d, %d\n", cpqhp_disk_irq, cpqhp_nic_irq); 1230 1231 rc = compaq_nvram_load(rom_start, ctrl); 1232 if (rc) 1233 return rc; 1234 1235 one_slot = rom_resource_table + sizeof(struct hrt); 1236 1237 i = readb(rom_resource_table + NUMBER_OF_ENTRIES); 1238 dbg("number_of_entries = %d\n", i); 1239 1240 if (!readb(one_slot + SECONDARY_BUS)) 1241 return 1; 1242 1243 dbg("dev|IO base|length|Mem base|length|Pre base|length|PB SB MB\n"); 1244 1245 while (i && readb(one_slot + SECONDARY_BUS)) { 1246 u8 dev_func = readb(one_slot + DEV_FUNC); 1247 u8 primary_bus = readb(one_slot + PRIMARY_BUS); 1248 u8 secondary_bus = readb(one_slot + SECONDARY_BUS); 1249 u8 max_bus = readb(one_slot + MAX_BUS); 1250 u16 io_base = readw(one_slot + IO_BASE); 1251 u16 io_length = readw(one_slot + IO_LENGTH); 1252 u16 mem_base = readw(one_slot + MEM_BASE); 1253 u16 mem_length = readw(one_slot + MEM_LENGTH); 1254 u16 pre_mem_base = readw(one_slot + PRE_MEM_BASE); 1255 u16 pre_mem_length = readw(one_slot + PRE_MEM_LENGTH); 1256 1257 dbg("%2.2x | %4.4x | %4.4x | %4.4x | %4.4x | %4.4x | %4.4x |%2.2x %2.2x %2.2x\n", 1258 dev_func, io_base, io_length, mem_base, mem_length, pre_mem_base, pre_mem_length, 1259 primary_bus, secondary_bus, max_bus); 1260 1261 /* If this entry isn't for our controller's bus, ignore it */ 1262 if (primary_bus != ctrl->bus) { 1263 i--; 1264 one_slot += sizeof(struct slot_rt); 1265 continue; 1266 } 1267 /* find out if this entry is for an occupied slot */ 1268 ctrl->pci_bus->number = primary_bus; 1269 pci_bus_read_config_dword(ctrl->pci_bus, dev_func, PCI_VENDOR_ID, &temp_dword); 1270 dbg("temp_D_word = %x\n", temp_dword); 1271 1272 if (temp_dword != 0xFFFFFFFF) { 1273 index = 0; 1274 func = cpqhp_slot_find(primary_bus, dev_func >> 3, 0); 1275 1276 while (func && (func->function != (dev_func & 0x07))) { 1277 dbg("func = %p (bus, dev, fun) = (%d, %d, %d)\n", func, primary_bus, dev_func >> 3, index); 1278 func = cpqhp_slot_find(primary_bus, dev_func >> 3, index++); 1279 } 1280 1281 /* If we can't find a match, skip this table entry */ 1282 if (!func) { 1283 i--; 1284 one_slot += sizeof(struct slot_rt); 1285 continue; 1286 } 1287 /* this may not work and shouldn't be used */ 1288 if (secondary_bus != primary_bus) 1289 bridged_slot = 1; 1290 else 1291 bridged_slot = 0; 1292 1293 populated_slot = 1; 1294 } else { 1295 populated_slot = 0; 1296 bridged_slot = 0; 1297 } 1298 1299 1300 /* If we've got a valid IO base, use it */ 1301 1302 temp_dword = io_base + io_length; 1303 1304 if ((io_base) && (temp_dword < 0x10000)) { 1305 io_node = kmalloc(sizeof(*io_node), GFP_KERNEL); 1306 if (!io_node) 1307 return -ENOMEM; 1308 1309 io_node->base = io_base; 1310 io_node->length = io_length; 1311 1312 dbg("found io_node(base, length) = %x, %x\n", 1313 io_node->base, io_node->length); 1314 dbg("populated slot =%d \n", populated_slot); 1315 if (!populated_slot) { 1316 io_node->next = ctrl->io_head; 1317 ctrl->io_head = io_node; 1318 } else { 1319 io_node->next = func->io_head; 1320 func->io_head = io_node; 1321 } 1322 } 1323 1324 /* If we've got a valid memory base, use it */ 1325 temp_dword = mem_base + mem_length; 1326 if ((mem_base) && (temp_dword < 0x10000)) { 1327 mem_node = kmalloc(sizeof(*mem_node), GFP_KERNEL); 1328 if (!mem_node) 1329 return -ENOMEM; 1330 1331 mem_node->base = mem_base << 16; 1332 1333 mem_node->length = mem_length << 16; 1334 1335 dbg("found mem_node(base, length) = %x, %x\n", 1336 mem_node->base, mem_node->length); 1337 dbg("populated slot =%d \n", populated_slot); 1338 if (!populated_slot) { 1339 mem_node->next = ctrl->mem_head; 1340 ctrl->mem_head = mem_node; 1341 } else { 1342 mem_node->next = func->mem_head; 1343 func->mem_head = mem_node; 1344 } 1345 } 1346 1347 /* If we've got a valid prefetchable memory base, and 1348 * the base + length isn't greater than 0xFFFF 1349 */ 1350 temp_dword = pre_mem_base + pre_mem_length; 1351 if ((pre_mem_base) && (temp_dword < 0x10000)) { 1352 p_mem_node = kmalloc(sizeof(*p_mem_node), GFP_KERNEL); 1353 if (!p_mem_node) 1354 return -ENOMEM; 1355 1356 p_mem_node->base = pre_mem_base << 16; 1357 1358 p_mem_node->length = pre_mem_length << 16; 1359 dbg("found p_mem_node(base, length) = %x, %x\n", 1360 p_mem_node->base, p_mem_node->length); 1361 dbg("populated slot =%d \n", populated_slot); 1362 1363 if (!populated_slot) { 1364 p_mem_node->next = ctrl->p_mem_head; 1365 ctrl->p_mem_head = p_mem_node; 1366 } else { 1367 p_mem_node->next = func->p_mem_head; 1368 func->p_mem_head = p_mem_node; 1369 } 1370 } 1371 1372 /* If we've got a valid bus number, use it 1373 * The second condition is to ignore bus numbers on 1374 * populated slots that don't have PCI-PCI bridges 1375 */ 1376 if (secondary_bus && (secondary_bus != primary_bus)) { 1377 bus_node = kmalloc(sizeof(*bus_node), GFP_KERNEL); 1378 if (!bus_node) 1379 return -ENOMEM; 1380 1381 bus_node->base = secondary_bus; 1382 bus_node->length = max_bus - secondary_bus + 1; 1383 dbg("found bus_node(base, length) = %x, %x\n", 1384 bus_node->base, bus_node->length); 1385 dbg("populated slot =%d \n", populated_slot); 1386 if (!populated_slot) { 1387 bus_node->next = ctrl->bus_head; 1388 ctrl->bus_head = bus_node; 1389 } else { 1390 bus_node->next = func->bus_head; 1391 func->bus_head = bus_node; 1392 } 1393 } 1394 1395 i--; 1396 one_slot += sizeof(struct slot_rt); 1397 } 1398 1399 /* If all of the following fail, we don't have any resources for 1400 * hot plug add 1401 */ 1402 rc = 1; 1403 rc &= cpqhp_resource_sort_and_combine(&(ctrl->mem_head)); 1404 rc &= cpqhp_resource_sort_and_combine(&(ctrl->p_mem_head)); 1405 rc &= cpqhp_resource_sort_and_combine(&(ctrl->io_head)); 1406 rc &= cpqhp_resource_sort_and_combine(&(ctrl->bus_head)); 1407 1408 return rc; 1409 } 1410 1411 1412 /* 1413 * cpqhp_return_board_resources 1414 * 1415 * this routine returns all resources allocated to a board to 1416 * the available pool. 1417 * 1418 * returns 0 if success 1419 */ 1420 int cpqhp_return_board_resources(struct pci_func *func, struct resource_lists *resources) 1421 { 1422 int rc = 0; 1423 struct pci_resource *node; 1424 struct pci_resource *t_node; 1425 dbg("%s\n", __func__); 1426 1427 if (!func) 1428 return 1; 1429 1430 node = func->io_head; 1431 func->io_head = NULL; 1432 while (node) { 1433 t_node = node->next; 1434 return_resource(&(resources->io_head), node); 1435 node = t_node; 1436 } 1437 1438 node = func->mem_head; 1439 func->mem_head = NULL; 1440 while (node) { 1441 t_node = node->next; 1442 return_resource(&(resources->mem_head), node); 1443 node = t_node; 1444 } 1445 1446 node = func->p_mem_head; 1447 func->p_mem_head = NULL; 1448 while (node) { 1449 t_node = node->next; 1450 return_resource(&(resources->p_mem_head), node); 1451 node = t_node; 1452 } 1453 1454 node = func->bus_head; 1455 func->bus_head = NULL; 1456 while (node) { 1457 t_node = node->next; 1458 return_resource(&(resources->bus_head), node); 1459 node = t_node; 1460 } 1461 1462 rc |= cpqhp_resource_sort_and_combine(&(resources->mem_head)); 1463 rc |= cpqhp_resource_sort_and_combine(&(resources->p_mem_head)); 1464 rc |= cpqhp_resource_sort_and_combine(&(resources->io_head)); 1465 rc |= cpqhp_resource_sort_and_combine(&(resources->bus_head)); 1466 1467 return rc; 1468 } 1469 1470 1471 /* 1472 * cpqhp_destroy_resource_list 1473 * 1474 * Puts node back in the resource list pointed to by head 1475 */ 1476 void cpqhp_destroy_resource_list(struct resource_lists *resources) 1477 { 1478 struct pci_resource *res, *tres; 1479 1480 res = resources->io_head; 1481 resources->io_head = NULL; 1482 1483 while (res) { 1484 tres = res; 1485 res = res->next; 1486 kfree(tres); 1487 } 1488 1489 res = resources->mem_head; 1490 resources->mem_head = NULL; 1491 1492 while (res) { 1493 tres = res; 1494 res = res->next; 1495 kfree(tres); 1496 } 1497 1498 res = resources->p_mem_head; 1499 resources->p_mem_head = NULL; 1500 1501 while (res) { 1502 tres = res; 1503 res = res->next; 1504 kfree(tres); 1505 } 1506 1507 res = resources->bus_head; 1508 resources->bus_head = NULL; 1509 1510 while (res) { 1511 tres = res; 1512 res = res->next; 1513 kfree(tres); 1514 } 1515 } 1516 1517 1518 /* 1519 * cpqhp_destroy_board_resources 1520 * 1521 * Puts node back in the resource list pointed to by head 1522 */ 1523 void cpqhp_destroy_board_resources(struct pci_func *func) 1524 { 1525 struct pci_resource *res, *tres; 1526 1527 res = func->io_head; 1528 func->io_head = NULL; 1529 1530 while (res) { 1531 tres = res; 1532 res = res->next; 1533 kfree(tres); 1534 } 1535 1536 res = func->mem_head; 1537 func->mem_head = NULL; 1538 1539 while (res) { 1540 tres = res; 1541 res = res->next; 1542 kfree(tres); 1543 } 1544 1545 res = func->p_mem_head; 1546 func->p_mem_head = NULL; 1547 1548 while (res) { 1549 tres = res; 1550 res = res->next; 1551 kfree(tres); 1552 } 1553 1554 res = func->bus_head; 1555 func->bus_head = NULL; 1556 1557 while (res) { 1558 tres = res; 1559 res = res->next; 1560 kfree(tres); 1561 } 1562 } 1563