1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Volume Management Device driver 4 * Copyright (c) 2015, Intel Corporation. 5 */ 6 7 #include <linux/device.h> 8 #include <linux/interrupt.h> 9 #include <linux/irq.h> 10 #include <linux/irqchip/irq-msi-lib.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/msi.h> 14 #include <linux/pci.h> 15 #include <linux/pci-acpi.h> 16 #include <linux/pci-ecam.h> 17 #include <linux/srcu.h> 18 #include <linux/rculist.h> 19 #include <linux/rcupdate.h> 20 21 #include <xen/xen.h> 22 23 #include <asm/irqdomain.h> 24 25 #define VMD_CFGBAR 0 26 #define VMD_MEMBAR1 2 27 #define VMD_MEMBAR2 4 28 29 #define PCI_REG_VMCAP 0x40 30 #define BUS_RESTRICT_CAP(vmcap) (vmcap & 0x1) 31 #define PCI_REG_VMCONFIG 0x44 32 #define BUS_RESTRICT_CFG(vmcfg) ((vmcfg >> 8) & 0x3) 33 #define VMCONFIG_MSI_REMAP 0x2 34 #define PCI_REG_VMLOCK 0x70 35 #define MB2_SHADOW_EN(vmlock) (vmlock & 0x2) 36 37 #define MB2_SHADOW_OFFSET 0x2000 38 #define MB2_SHADOW_SIZE 16 39 40 /* DMR BAR4 register offsets */ 41 #define SHADOW_MEMBAR1_28C1 0x2818 /* MEMBAR1 physical address */ 42 #define SHADOW_MEMBAR2_28C1 0x2820 /* MEMBAR2 physical address */ 43 #define BASE_ID_REG_28C1 0x2840 44 #define MEMBAR2_OFFSET_28C1 0x30d0 45 46 enum vmd_features { 47 /* 48 * Device may contain registers which hint the physical location of the 49 * membars, in order to allow proper address translation during 50 * resource assignment to enable guest virtualization 51 */ 52 VMD_FEAT_HAS_MEMBAR_SHADOW = (1 << 0), 53 54 /* 55 * Device may provide root port configuration information which limits 56 * bus numbering 57 */ 58 VMD_FEAT_HAS_BUS_RESTRICTIONS = (1 << 1), 59 60 /* 61 * Device contains physical location shadow registers in 62 * vendor-specific capability space 63 */ 64 VMD_FEAT_HAS_MEMBAR_SHADOW_VSCAP = (1 << 2), 65 66 /* 67 * Device may use MSI-X vector 0 for software triggering and will not 68 * be used for MSI remapping 69 */ 70 VMD_FEAT_OFFSET_FIRST_VECTOR = (1 << 3), 71 72 /* 73 * Device can bypass remapping MSI-X transactions into its MSI-X table, 74 * avoiding the requirement of a VMD MSI domain for child device 75 * interrupt handling. 76 */ 77 VMD_FEAT_CAN_BYPASS_MSI_REMAP = (1 << 4), 78 79 /* 80 * Enable ASPM on the PCIE root ports and set the default LTR of the 81 * storage devices on platforms where these values are not configured by 82 * BIOS. This is needed for laptops, which require these settings for 83 * proper power management of the SoC. 84 */ 85 VMD_FEAT_BIOS_PM_QUIRK = (1 << 5), 86 87 /* 88 * Newer VMD with device ID 0x28C1 has unique settings compared to its 89 * predecessor where BIOS enumerates the entire VMD device tree and 90 * stores respective configurations including bus start range and 91 * shadow registers in VMD MMIO space in VMD BAR4/BAR5, otherwise 92 * referred to as MEMBAR2 or MSI-X BAR. 93 */ 94 VMD_FEAT_USE_BIOS_INFO = (1 << 6), 95 96 /* 97 * Some Intel VMD devices are affected by interrupt ordering errata, 98 * including MTL016 (0x7d0b) and ARL004 (0xad0b): 99 * the VMD may signal its MSI before the posted writes that carry the 100 * child device's DMA data have landed in memory. The demuxed handler 101 * then runs against a not-yet-coherent completion queue and misses the 102 * completion entirely, so the I/O is only recovered when the block 103 * layer timeout fires and polls the queue ("timeout, completion 104 * polled"). Intel's documented workaround is to issue a dummy read 105 * to the MSI initiator (the child device) before handling the 106 * interrupt: the read completion cannot pass the device's earlier 107 * posted writes, so it pulls them into memory per PCIe ordering 108 * rules. A read that terminates at the VMD itself does not order 109 * against the child's writes and is not sufficient (measured). 110 */ 111 VMD_FEAT_INTERRUPT_QUIRK = (1 << 7), 112 }; 113 114 #define VMD_BIOS_PM_QUIRK_LTR 0x1003 /* 3145728 ns */ 115 116 #define VMD_FEATS_CLIENT (VMD_FEAT_HAS_MEMBAR_SHADOW_VSCAP | \ 117 VMD_FEAT_HAS_BUS_RESTRICTIONS | \ 118 VMD_FEAT_OFFSET_FIRST_VECTOR | \ 119 VMD_FEAT_BIOS_PM_QUIRK) 120 121 static DEFINE_IDA(vmd_instance_ida); 122 123 /* 124 * Lock for manipulating VMD IRQ lists. 125 */ 126 static DEFINE_RAW_SPINLOCK(list_lock); 127 128 /** 129 * struct vmd_irq - private data to map driver IRQ to the VMD shared vector 130 * @node: list item for parent traversal. 131 * @irq: back pointer to parent. 132 * @enabled: true if driver enabled IRQ 133 * @virq: the virtual IRQ value provided to the requesting driver. 134 * @flush_addr: config space address of the initiating device, read before 135 * demuxing to flush its posted writes; NULL if the 136 * VMD is not affected. 137 * 138 * Every MSI/MSI-X IRQ requested for a device in a VMD domain will be mapped to 139 * a VMD IRQ using this structure. 140 */ 141 struct vmd_irq { 142 struct list_head node; 143 struct vmd_irq_list *irq; 144 bool enabled; 145 unsigned int virq; 146 void __iomem *flush_addr; 147 }; 148 149 struct vmd_dev; 150 151 static void __iomem *vmd_cfg_addr(struct vmd_dev *vmd, struct pci_bus *bus, 152 unsigned int devfn, int reg, int len); 153 154 /** 155 * struct vmd_irq_list - list of driver requested IRQs mapping to a VMD vector 156 * @irq_list: the list of irq's the VMD one demuxes to. 157 * @srcu: SRCU struct for local synchronization. 158 * @count: number of child IRQs assigned to this vector; used to track 159 * sharing. 160 * @virq: The underlying VMD Linux interrupt number 161 * @vmd: back pointer to the owning VMD device; serializes the MTL016 162 * flush read against other config space access. 163 */ 164 struct vmd_irq_list { 165 struct list_head irq_list; 166 struct srcu_struct srcu; 167 unsigned int count; 168 unsigned int virq; 169 struct vmd_dev *vmd; 170 }; 171 172 struct vmd_dev { 173 struct pci_dev *dev; 174 175 raw_spinlock_t cfg_lock; 176 void __iomem *cfgbar; 177 178 int msix_count; 179 struct vmd_irq_list *irqs; 180 181 struct pci_sysdata sysdata; 182 struct resource resources[3]; 183 struct irq_domain *irq_domain; 184 struct pci_bus *bus; 185 u8 busn_start; 186 u8 first_vec; 187 char *name; 188 int instance; 189 unsigned long features; 190 }; 191 192 static inline struct vmd_dev *vmd_from_bus(struct pci_bus *bus) 193 { 194 return container_of(bus->sysdata, struct vmd_dev, sysdata); 195 } 196 197 static inline unsigned int index_from_irqs(struct vmd_dev *vmd, 198 struct vmd_irq_list *irqs) 199 { 200 return irqs - vmd->irqs; 201 } 202 203 /* 204 * Drivers managing a device in a VMD domain allocate their own IRQs as before, 205 * but the MSI entry for the hardware it's driving will be programmed with a 206 * destination ID for the VMD MSI-X table. The VMD muxes interrupts in its 207 * domain into one of its own, and the VMD driver de-muxes these for the 208 * handlers sharing that VMD IRQ. The vmd irq_domain provides the operations 209 * and irq_chip to set this up. 210 */ 211 static void vmd_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) 212 { 213 struct vmd_irq *vmdirq = data->chip_data; 214 struct vmd_irq_list *irq = vmdirq->irq; 215 struct vmd_dev *vmd = irq_data_get_irq_handler_data(data); 216 217 memset(msg, 0, sizeof(*msg)); 218 msg->address_hi = X86_MSI_BASE_ADDRESS_HIGH; 219 msg->arch_addr_lo.base_address = X86_MSI_BASE_ADDRESS_LOW; 220 msg->arch_addr_lo.destid_0_7 = index_from_irqs(vmd, irq); 221 } 222 223 static void vmd_irq_enable(struct irq_data *data) 224 { 225 struct vmd_irq *vmdirq = data->chip_data; 226 227 scoped_guard(raw_spinlock_irqsave, &list_lock) { 228 WARN_ON(vmdirq->enabled); 229 list_add_tail_rcu(&vmdirq->node, &vmdirq->irq->irq_list); 230 vmdirq->enabled = true; 231 } 232 } 233 234 static void vmd_pci_msi_enable(struct irq_data *data) 235 { 236 vmd_irq_enable(data->parent_data); 237 data->chip->irq_unmask(data); 238 } 239 240 static unsigned int vmd_pci_msi_startup(struct irq_data *data) 241 { 242 vmd_pci_msi_enable(data); 243 return 0; 244 } 245 246 static void vmd_irq_disable(struct irq_data *data) 247 { 248 struct vmd_irq *vmdirq = data->chip_data; 249 250 scoped_guard(raw_spinlock_irqsave, &list_lock) { 251 if (vmdirq->enabled) { 252 list_del_rcu(&vmdirq->node); 253 vmdirq->enabled = false; 254 } 255 } 256 } 257 258 static void vmd_pci_msi_disable(struct irq_data *data) 259 { 260 data->chip->irq_mask(data); 261 vmd_irq_disable(data->parent_data); 262 } 263 264 static void vmd_pci_msi_shutdown(struct irq_data *data) 265 { 266 vmd_pci_msi_disable(data); 267 } 268 269 static struct irq_chip vmd_msi_controller = { 270 .name = "VMD-MSI", 271 .irq_compose_msi_msg = vmd_compose_msi_msg, 272 }; 273 274 /* 275 * XXX: We can be even smarter selecting the best IRQ once we solve the 276 * affinity problem. 277 */ 278 static struct vmd_irq_list *vmd_next_irq(struct vmd_dev *vmd, struct msi_desc *desc) 279 { 280 int i, best; 281 282 if (vmd->msix_count == 1 + vmd->first_vec) 283 return &vmd->irqs[vmd->first_vec]; 284 285 /* 286 * White list for fast-interrupt handlers. All others will share the 287 * "slow" interrupt vector. 288 */ 289 switch (msi_desc_to_pci_dev(desc)->class) { 290 case PCI_CLASS_STORAGE_EXPRESS: 291 break; 292 default: 293 return &vmd->irqs[vmd->first_vec]; 294 } 295 296 scoped_guard(raw_spinlock_irq, &list_lock) { 297 best = vmd->first_vec + 1; 298 for (i = best; i < vmd->msix_count; i++) 299 if (vmd->irqs[i].count < vmd->irqs[best].count) 300 best = i; 301 vmd->irqs[best].count++; 302 } 303 304 return &vmd->irqs[best]; 305 } 306 307 static void vmd_msi_free(struct irq_domain *domain, unsigned int virq, 308 unsigned int nr_irqs); 309 310 static int vmd_msi_alloc(struct irq_domain *domain, unsigned int virq, 311 unsigned int nr_irqs, void *arg) 312 { 313 struct msi_desc *desc = ((msi_alloc_info_t *)arg)->desc; 314 struct vmd_dev *vmd = domain->host_data; 315 struct vmd_irq *vmdirq; 316 317 for (int i = 0; i < nr_irqs; ++i) { 318 vmdirq = kzalloc_obj(*vmdirq); 319 if (!vmdirq) { 320 vmd_msi_free(domain, virq, i); 321 return -ENOMEM; 322 } 323 324 INIT_LIST_HEAD(&vmdirq->node); 325 vmdirq->irq = vmd_next_irq(vmd, desc); 326 vmdirq->virq = virq + i; 327 if (vmd->features & VMD_FEAT_INTERRUPT_QUIRK) { 328 struct pci_dev *pdev = msi_desc_to_pci_dev(desc); 329 330 vmdirq->flush_addr = vmd_cfg_addr(vmd, pdev->bus, 331 pdev->devfn, 332 PCI_VENDOR_ID, 2); 333 } 334 335 irq_domain_set_info(domain, virq + i, vmdirq->irq->virq, 336 &vmd_msi_controller, vmdirq, 337 handle_untracked_irq, vmd, NULL); 338 } 339 340 return 0; 341 } 342 343 static void vmd_msi_free(struct irq_domain *domain, unsigned int virq, 344 unsigned int nr_irqs) 345 { 346 struct irq_data *irq_data; 347 struct vmd_irq *vmdirq; 348 349 for (int i = 0; i < nr_irqs; ++i) { 350 irq_data = irq_domain_get_irq_data(domain, virq + i); 351 vmdirq = irq_data->chip_data; 352 353 synchronize_srcu(&vmdirq->irq->srcu); 354 355 /* XXX: Potential optimization to rebalance */ 356 scoped_guard(raw_spinlock_irq, &list_lock) 357 vmdirq->irq->count--; 358 359 kfree(vmdirq); 360 } 361 } 362 363 static const struct irq_domain_ops vmd_msi_domain_ops = { 364 .alloc = vmd_msi_alloc, 365 .free = vmd_msi_free, 366 }; 367 368 static bool vmd_init_dev_msi_info(struct device *dev, struct irq_domain *domain, 369 struct irq_domain *real_parent, 370 struct msi_domain_info *info) 371 { 372 if (!msi_lib_init_dev_msi_info(dev, domain, real_parent, info)) 373 return false; 374 375 info->chip->irq_startup = vmd_pci_msi_startup; 376 info->chip->irq_shutdown = vmd_pci_msi_shutdown; 377 info->chip->irq_enable = vmd_pci_msi_enable; 378 info->chip->irq_disable = vmd_pci_msi_disable; 379 return true; 380 } 381 382 #define VMD_MSI_FLAGS_SUPPORTED (MSI_GENERIC_FLAGS_MASK | MSI_FLAG_PCI_MSIX) 383 #define VMD_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_NO_AFFINITY) 384 385 static const struct msi_parent_ops vmd_msi_parent_ops = { 386 .supported_flags = VMD_MSI_FLAGS_SUPPORTED, 387 .required_flags = VMD_MSI_FLAGS_REQUIRED, 388 .bus_select_token = DOMAIN_BUS_VMD_MSI, 389 .bus_select_mask = MATCH_PCI_MSI, 390 .prefix = "VMD-", 391 .init_dev_msi_info = vmd_init_dev_msi_info, 392 }; 393 394 static int vmd_create_irq_domain(struct vmd_dev *vmd) 395 { 396 struct irq_domain_info info = { 397 .size = vmd->msix_count, 398 .ops = &vmd_msi_domain_ops, 399 .host_data = vmd, 400 }; 401 402 info.fwnode = irq_domain_alloc_named_id_fwnode("VMD-MSI", 403 vmd->sysdata.domain); 404 if (!info.fwnode) 405 return -ENODEV; 406 407 vmd->irq_domain = msi_create_parent_irq_domain(&info, 408 &vmd_msi_parent_ops); 409 if (!vmd->irq_domain) { 410 irq_domain_free_fwnode(info.fwnode); 411 return -ENODEV; 412 } 413 414 return 0; 415 } 416 417 static void vmd_set_msi_remapping(struct vmd_dev *vmd, bool enable) 418 { 419 u16 reg; 420 421 if (!!(vmd->features & VMD_FEAT_USE_BIOS_INFO)) 422 return; 423 424 pci_read_config_word(vmd->dev, PCI_REG_VMCONFIG, ®); 425 reg = enable ? (reg & ~VMCONFIG_MSI_REMAP) : 426 (reg | VMCONFIG_MSI_REMAP); 427 pci_write_config_word(vmd->dev, PCI_REG_VMCONFIG, reg); 428 } 429 430 static void vmd_remove_irq_domain(struct vmd_dev *vmd) 431 { 432 /* 433 * Some production BIOS won't enable remapping between soft reboots. 434 * Ensure remapping is restored before unloading the driver. 435 */ 436 if (!vmd->msix_count) 437 vmd_set_msi_remapping(vmd, true); 438 439 if (vmd->irq_domain) { 440 struct fwnode_handle *fn = vmd->irq_domain->fwnode; 441 442 irq_domain_remove(vmd->irq_domain); 443 irq_domain_free_fwnode(fn); 444 } 445 } 446 447 static unsigned int vmd_bus_to_ecam(struct vmd_dev *vmd, unsigned int busnr) 448 { 449 if (!!(vmd->features & VMD_FEAT_USE_BIOS_INFO)) 450 return busnr; 451 452 return busnr - vmd->busn_start; 453 } 454 455 static void __iomem *vmd_cfg_addr(struct vmd_dev *vmd, struct pci_bus *bus, 456 unsigned int devfn, int reg, int len) 457 { 458 unsigned int busnr_ecam; 459 u32 offset; 460 461 busnr_ecam = vmd_bus_to_ecam(vmd, bus->number); 462 offset = PCIE_ECAM_OFFSET(busnr_ecam, devfn, reg); 463 464 if (offset + len >= resource_size(&vmd->dev->resource[VMD_CFGBAR])) 465 return NULL; 466 467 return vmd->cfgbar + offset; 468 } 469 470 /* 471 * CPU may deadlock if config space is not serialized on some versions of this 472 * hardware, so all config space access is done under a spinlock. 473 */ 474 static int vmd_pci_read(struct pci_bus *bus, unsigned int devfn, int reg, 475 int len, u32 *value) 476 { 477 struct vmd_dev *vmd = vmd_from_bus(bus); 478 void __iomem *addr = vmd_cfg_addr(vmd, bus, devfn, reg, len); 479 480 if (!addr) 481 return -EFAULT; 482 483 guard(raw_spinlock_irqsave)(&vmd->cfg_lock); 484 switch (len) { 485 case 1: 486 *value = readb(addr); 487 return 0; 488 case 2: 489 *value = readw(addr); 490 return 0; 491 case 4: 492 *value = readl(addr); 493 return 0; 494 default: 495 return -EINVAL; 496 } 497 } 498 499 /* 500 * VMD h/w converts non-posted config writes to posted memory writes. The 501 * read-back in this function forces the completion so it returns only after 502 * the config space was written, as expected. 503 */ 504 static int vmd_pci_write(struct pci_bus *bus, unsigned int devfn, int reg, 505 int len, u32 value) 506 { 507 struct vmd_dev *vmd = vmd_from_bus(bus); 508 void __iomem *addr = vmd_cfg_addr(vmd, bus, devfn, reg, len); 509 510 if (!addr) 511 return -EFAULT; 512 513 guard(raw_spinlock_irqsave)(&vmd->cfg_lock); 514 switch (len) { 515 case 1: 516 writeb(value, addr); 517 readb(addr); 518 return 0; 519 case 2: 520 writew(value, addr); 521 readw(addr); 522 return 0; 523 case 4: 524 writel(value, addr); 525 readl(addr); 526 return 0; 527 default: 528 return -EINVAL; 529 } 530 } 531 532 static struct pci_ops vmd_ops = { 533 .read = vmd_pci_read, 534 .write = vmd_pci_write, 535 }; 536 537 #ifdef CONFIG_ACPI 538 static struct acpi_device *vmd_acpi_find_companion(struct pci_dev *pci_dev) 539 { 540 struct pci_host_bridge *bridge; 541 u32 busnr, addr; 542 543 if (pci_dev->bus->ops != &vmd_ops) 544 return NULL; 545 546 bridge = pci_find_host_bridge(pci_dev->bus); 547 busnr = pci_dev->bus->number - bridge->bus->number; 548 /* 549 * The address computation below is only applicable to relative bus 550 * numbers below 32. 551 */ 552 if (busnr > 31) 553 return NULL; 554 555 addr = (busnr << 24) | ((u32)pci_dev->devfn << 16) | 0x8000FFFFU; 556 557 dev_dbg(&pci_dev->dev, "Looking for ACPI companion (address 0x%x)\n", 558 addr); 559 560 return acpi_find_child_device(ACPI_COMPANION(bridge->dev.parent), addr, 561 false); 562 } 563 564 static bool hook_installed; 565 566 static void vmd_acpi_begin(void) 567 { 568 if (pci_acpi_set_companion_lookup_hook(vmd_acpi_find_companion)) 569 return; 570 571 hook_installed = true; 572 } 573 574 static void vmd_acpi_end(void) 575 { 576 if (!hook_installed) 577 return; 578 579 pci_acpi_clear_companion_lookup_hook(); 580 hook_installed = false; 581 } 582 #else 583 static inline void vmd_acpi_begin(void) { } 584 static inline void vmd_acpi_end(void) { } 585 #endif /* CONFIG_ACPI */ 586 587 static resource_size_t vmd_cfgbar_ecam_space(struct vmd_dev *vmd) 588 { 589 resource_size_t cfgbar_buses; 590 unsigned int ecam_start; 591 592 cfgbar_buses = resource_size(&vmd->dev->resource[VMD_CFGBAR]) >> 20; 593 ecam_start = vmd_bus_to_ecam(vmd, vmd->resources[0].start); 594 if (ecam_start >= cfgbar_buses) 595 return 0; 596 597 return cfgbar_buses - ecam_start; 598 } 599 static void vmd_domain_reset(struct vmd_dev *vmd) 600 { 601 u16 bus, max_buses = resource_size(&vmd->resources[0]); 602 u8 dev, functions, fn, hdr_type; 603 unsigned int ecam_bus; 604 char __iomem *base; 605 606 max_buses = min_t(u16, max_buses, vmd_cfgbar_ecam_space(vmd)); 607 for (bus = 0; bus < max_buses; bus++) { 608 ecam_bus = vmd_bus_to_ecam(vmd, vmd->resources[0].start + bus); 609 for (dev = 0; dev < 32; dev++) { 610 base = vmd->cfgbar + PCIE_ECAM_OFFSET(ecam_bus, 611 PCI_DEVFN(dev, 0), 0); 612 613 hdr_type = readb(base + PCI_HEADER_TYPE); 614 615 functions = (hdr_type & PCI_HEADER_TYPE_MFD) ? 8 : 1; 616 for (fn = 0; fn < functions; fn++) { 617 base = vmd->cfgbar + PCIE_ECAM_OFFSET(ecam_bus, 618 PCI_DEVFN(dev, fn), 0); 619 620 hdr_type = readb(base + PCI_HEADER_TYPE) & 621 PCI_HEADER_TYPE_MASK; 622 623 if (hdr_type != PCI_HEADER_TYPE_BRIDGE || 624 (readw(base + PCI_CLASS_DEVICE) != 625 PCI_CLASS_BRIDGE_PCI)) 626 continue; 627 628 /* 629 * Temporarily disable the I/O range before updating 630 * PCI_IO_BASE. 631 */ 632 writel(0x0000ffff, base + PCI_IO_BASE_UPPER16); 633 /* Update lower 16 bits of I/O base/limit */ 634 writew(0x00f0, base + PCI_IO_BASE); 635 /* Update upper 16 bits of I/O base/limit */ 636 writel(0, base + PCI_IO_BASE_UPPER16); 637 638 /* MMIO Base/Limit */ 639 writel(0x0000fff0, base + PCI_MEMORY_BASE); 640 641 /* Prefetchable MMIO Base/Limit */ 642 writel(0, base + PCI_PREF_LIMIT_UPPER32); 643 writel(0x0000fff0, base + PCI_PREF_MEMORY_BASE); 644 writel(0xffffffff, base + PCI_PREF_BASE_UPPER32); 645 } 646 } 647 } 648 } 649 650 static void vmd_attach_resources(struct vmd_dev *vmd) 651 { 652 vmd->dev->resource[VMD_MEMBAR1].child = &vmd->resources[1]; 653 vmd->dev->resource[VMD_MEMBAR2].child = &vmd->resources[2]; 654 } 655 656 static void vmd_detach_resources(struct vmd_dev *vmd) 657 { 658 vmd->dev->resource[VMD_MEMBAR1].child = NULL; 659 vmd->dev->resource[VMD_MEMBAR2].child = NULL; 660 } 661 662 static int vmd_get_phys_offsets(struct vmd_dev *vmd, bool native_hint, 663 resource_size_t *offset1, 664 resource_size_t *offset2) 665 { 666 struct pci_dev *dev = vmd->dev; 667 u64 phys1, phys2; 668 669 if (native_hint) { 670 u32 vmlock; 671 int ret; 672 673 ret = pci_read_config_dword(dev, PCI_REG_VMLOCK, &vmlock); 674 if (ret || PCI_POSSIBLE_ERROR(vmlock)) 675 return -ENODEV; 676 677 if (MB2_SHADOW_EN(vmlock)) { 678 void __iomem *membar2; 679 680 membar2 = pci_iomap(dev, VMD_MEMBAR2, 0); 681 if (!membar2) 682 return -ENOMEM; 683 phys1 = readq(membar2 + MB2_SHADOW_OFFSET); 684 phys2 = readq(membar2 + MB2_SHADOW_OFFSET + 8); 685 pci_iounmap(dev, membar2); 686 } else 687 return 0; 688 } else { 689 /* Hypervisor-Emulated Vendor-Specific Capability */ 690 int pos = pci_find_capability(dev, PCI_CAP_ID_VNDR); 691 u32 reg, regu; 692 693 pci_read_config_dword(dev, pos + 4, ®); 694 695 /* "SHDW" */ 696 if (pos && reg == 0x53484457) { 697 pci_read_config_dword(dev, pos + 8, ®); 698 pci_read_config_dword(dev, pos + 12, ®u); 699 phys1 = (u64) regu << 32 | reg; 700 701 pci_read_config_dword(dev, pos + 16, ®); 702 pci_read_config_dword(dev, pos + 20, ®u); 703 phys2 = (u64) regu << 32 | reg; 704 } else 705 return 0; 706 } 707 708 *offset1 = dev->resource[VMD_MEMBAR1].start - 709 (phys1 & PCI_BASE_ADDRESS_MEM_MASK); 710 *offset2 = dev->resource[VMD_MEMBAR2].start - 711 (phys2 & PCI_BASE_ADDRESS_MEM_MASK); 712 713 return 0; 714 } 715 716 static int vmd_get_bus_number_start(struct vmd_dev *vmd) 717 { 718 struct pci_dev *dev = vmd->dev; 719 u16 reg; 720 721 pci_read_config_word(dev, PCI_REG_VMCAP, ®); 722 if (BUS_RESTRICT_CAP(reg)) { 723 pci_read_config_word(dev, PCI_REG_VMCONFIG, ®); 724 if (PCI_POSSIBLE_ERROR(reg)) 725 return -ENODEV; 726 727 switch (BUS_RESTRICT_CFG(reg)) { 728 case 0: 729 vmd->busn_start = 0; 730 break; 731 case 1: 732 vmd->busn_start = 128; 733 break; 734 case 3: 735 case 2: 736 vmd->busn_start = 224; 737 break; 738 default: 739 pci_err(dev, "Unknown Bus Offset Setting (%d)\n", 740 BUS_RESTRICT_CFG(reg)); 741 return -ENODEV; 742 } 743 } 744 745 return 0; 746 } 747 748 static int vmd_get_bus_info_from_bar4(struct vmd_dev *vmd, 749 resource_size_t *offset1, 750 resource_size_t *offset2) 751 { 752 u64 phys1, phys2, bar4_2840; 753 void __iomem *bar4; 754 u32 base_id; 755 u8 base_bus; 756 757 bar4 = pci_ioremap_bar(vmd->dev, 4); 758 if (!bar4) 759 return -ENOMEM; 760 761 /* Read shadow registers for MEMBAR1 and MEMBAR2 physical addresses */ 762 phys1 = readq(bar4 + SHADOW_MEMBAR1_28C1); 763 phys2 = readq(bar4 + SHADOW_MEMBAR2_28C1); 764 765 /* 766 * Read and set bus start number from Base ID register. 24-bit Base ID 767 * register is part of 64-bit shadowed reqid hide range register and 768 * holds segment, bus, device and function. 769 */ 770 bar4_2840 = readq(bar4 + BASE_ID_REG_28C1); 771 base_id = bar4_2840 & 0xFFFFFF; 772 base_bus = base_id >> 8; 773 vmd->busn_start = base_bus; 774 775 /* Calculate offsets like vmd_get_phys_offsets() does */ 776 if (phys1) 777 *offset1 = vmd->dev->resource[VMD_MEMBAR1].start - 778 (phys1 & PCI_BASE_ADDRESS_MEM_MASK); 779 if (phys2) 780 *offset2 = vmd->dev->resource[VMD_MEMBAR2].start - 781 (phys2 & PCI_BASE_ADDRESS_MEM_MASK); 782 783 pci_iounmap(vmd->dev, bar4); 784 785 return 0; 786 } 787 788 static irqreturn_t vmd_irq(int irq, void *data) 789 { 790 struct vmd_irq_list *irqs = data; 791 struct vmd_irq *vmdirq; 792 int idx; 793 794 idx = srcu_read_lock(&irqs->srcu); 795 list_for_each_entry_rcu(vmdirq, &irqs->irq_list, node) { 796 /* 797 * MTL016: the MSI may have outrun the initiating device's 798 * posted writes (e.g. its NVMe completion entry). A read 799 * that completes at the initiator flushes them, so the 800 * demuxed handler observes a coherent completion queue. 801 * The value is discarded; only the ordering matters. 802 */ 803 if (vmdirq->flush_addr) { 804 guard(raw_spinlock)(&irqs->vmd->cfg_lock); 805 readw(vmdirq->flush_addr); 806 } 807 generic_handle_irq(vmdirq->virq); 808 } 809 srcu_read_unlock(&irqs->srcu, idx); 810 811 return IRQ_HANDLED; 812 } 813 814 static int vmd_alloc_irqs(struct vmd_dev *vmd) 815 { 816 struct pci_dev *dev = vmd->dev; 817 int i, err; 818 819 vmd->msix_count = pci_msix_vec_count(dev); 820 if (vmd->msix_count < 0) 821 return -ENODEV; 822 823 vmd->msix_count = pci_alloc_irq_vectors(dev, vmd->first_vec + 1, 824 vmd->msix_count, PCI_IRQ_MSIX); 825 if (vmd->msix_count < 0) 826 return vmd->msix_count; 827 828 vmd->irqs = devm_kzalloc_objs(&dev->dev, *vmd->irqs, vmd->msix_count); 829 if (!vmd->irqs) 830 return -ENOMEM; 831 832 for (i = 0; i < vmd->msix_count; i++) { 833 err = init_srcu_struct(&vmd->irqs[i].srcu); 834 if (err) 835 return err; 836 837 INIT_LIST_HEAD(&vmd->irqs[i].irq_list); 838 vmd->irqs[i].vmd = vmd; 839 vmd->irqs[i].virq = pci_irq_vector(dev, i); 840 err = devm_request_irq(&dev->dev, vmd->irqs[i].virq, 841 vmd_irq, IRQF_NO_THREAD, 842 vmd->name, &vmd->irqs[i]); 843 if (err) 844 return err; 845 } 846 847 return 0; 848 } 849 850 static int vmd_prepare_offsets_and_bus(struct vmd_dev *vmd, 851 unsigned long features, 852 resource_size_t *membar2_offset, 853 resource_size_t *offset1, 854 resource_size_t *offset2) 855 { 856 int ret; 857 858 /* 859 * Shadow registers may exist in certain VMD device IDs which allow 860 * guests to correctly assign host physical addresses to the root ports 861 * and child devices. These registers will either return the host value 862 * or 0, depending on an enable bit in the VMD device. 863 * 864 * For certain VMD devices (i.e. 0x28C1), BIOS places device info 865 * in BAR4 shadow registers to determine the base bus number and memory 866 * offsets. 867 */ 868 if (features & VMD_FEAT_USE_BIOS_INFO) { 869 *membar2_offset = MEMBAR2_OFFSET_28C1; 870 ret = vmd_get_bus_info_from_bar4(vmd, offset1, offset2); 871 if (ret) 872 return ret; 873 } else if (features & VMD_FEAT_HAS_MEMBAR_SHADOW) { 874 *membar2_offset = MB2_SHADOW_OFFSET + MB2_SHADOW_SIZE; 875 ret = vmd_get_phys_offsets(vmd, true, offset1, offset2); 876 if (ret) 877 return ret; 878 } else if (features & VMD_FEAT_HAS_MEMBAR_SHADOW_VSCAP) { 879 ret = vmd_get_phys_offsets(vmd, false, offset1, offset2); 880 if (ret) 881 return ret; 882 } 883 884 /* 885 * Certain VMD devices may have a root port configuration option which 886 * limits the bus range to between 0-127, 128-255, or 224-255. 887 */ 888 if (features & VMD_FEAT_HAS_BUS_RESTRICTIONS) { 889 ret = vmd_get_bus_number_start(vmd); 890 if (ret) 891 return ret; 892 } 893 return 0; 894 } 895 896 /* 897 * Since VMD is an aperture to regular PCIe root ports, only allow it to 898 * control features that the OS is allowed to control on the physical PCI bus. 899 */ 900 static void vmd_copy_host_bridge_flags(struct pci_host_bridge *root_bridge, 901 struct pci_host_bridge *vmd_bridge) 902 { 903 vmd_bridge->native_pcie_hotplug = root_bridge->native_pcie_hotplug; 904 vmd_bridge->native_shpc_hotplug = root_bridge->native_shpc_hotplug; 905 vmd_bridge->native_aer = root_bridge->native_aer; 906 vmd_bridge->native_pme = root_bridge->native_pme; 907 vmd_bridge->native_ltr = root_bridge->native_ltr; 908 vmd_bridge->native_dpc = root_bridge->native_dpc; 909 } 910 911 /* 912 * Enable ASPM and LTR settings on devices that aren't configured by BIOS. 913 */ 914 static int vmd_pm_enable_quirk(struct pci_dev *pdev, void *userdata) 915 { 916 unsigned long features = *(unsigned long *)userdata; 917 u16 ltr = VMD_BIOS_PM_QUIRK_LTR; 918 u32 ltr_reg; 919 int pos; 920 921 if (!(features & VMD_FEAT_BIOS_PM_QUIRK)) 922 return 0; 923 924 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_LTR); 925 if (!pos) 926 goto out_state_change; 927 928 /* 929 * Skip if the max snoop LTR is non-zero, indicating BIOS has set it 930 * so the LTR quirk is not needed. 931 */ 932 pci_read_config_dword(pdev, pos + PCI_LTR_MAX_SNOOP_LAT, <r_reg); 933 if (!!(ltr_reg & (PCI_LTR_VALUE_MASK | PCI_LTR_SCALE_MASK))) 934 goto out_state_change; 935 936 /* 937 * Set the default values to the maximum required by the platform to 938 * allow the deepest power management savings. Write as a DWORD where 939 * the lower word is the max snoop latency and the upper word is the 940 * max non-snoop latency. 941 */ 942 ltr_reg = (ltr << 16) | ltr; 943 pci_write_config_dword(pdev, pos + PCI_LTR_MAX_SNOOP_LAT, ltr_reg); 944 pci_info(pdev, "VMD: Default LTR value set by driver\n"); 945 946 out_state_change: 947 /* 948 * Ensure devices are in D0 before enabling PCI-PM L1 PM Substates, per 949 * PCIe r6.0, sec 5.5.4. 950 */ 951 pci_set_power_state_locked(pdev, PCI_D0); 952 pci_enable_link_state_locked(pdev, PCIE_LINK_STATE_ALL); 953 return 0; 954 } 955 956 static int vmd_enable_domain(struct vmd_dev *vmd, unsigned long features) 957 { 958 struct pci_sysdata *sd = &vmd->sysdata; 959 struct resource *res; 960 u32 upper_bits; 961 unsigned long flags; 962 LIST_HEAD(resources); 963 resource_size_t offset[2] = {0}; 964 resource_size_t membar2_offset = 0x2000; 965 resource_size_t busn_end; 966 struct pci_bus *child; 967 struct pci_dev *dev; 968 bool vmd_in_guest; 969 int ret; 970 971 ret = vmd_prepare_offsets_and_bus(vmd, features, &membar2_offset, 972 &offset[0], &offset[1]); 973 if (ret) 974 return ret; 975 976 /* Do not let resource[0] end go out of bounds */ 977 res = &vmd->dev->resource[VMD_CFGBAR]; 978 busn_end = vmd->busn_start + (resource_size(res) >> 20) - 1; 979 busn_end = min_t(resource_size_t, busn_end, 0xff); 980 vmd->resources[0] = (struct resource) { 981 .name = "VMD CFGBAR", 982 .start = vmd->busn_start, 983 .end = busn_end, 984 .flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED, 985 }; 986 987 /* 988 * If the window is below 4GB, clear IORESOURCE_MEM_64 so we can 989 * put 32-bit resources in the window. 990 * 991 * There's no hardware reason why a 64-bit window *couldn't* 992 * contain a 32-bit resource, but pbus_size_mem() computes the 993 * bridge window size assuming a 64-bit window will contain no 994 * 32-bit resources. __pci_assign_resource() enforces that 995 * artificial restriction to make sure everything will fit. 996 * 997 * The only way we could use a 64-bit non-prefetchable MEMBAR is 998 * if its address is <4GB so that we can convert it to a 32-bit 999 * resource. To be visible to the host OS, all VMD endpoints must 1000 * be initially configured by platform BIOS, which includes setting 1001 * up these resources. We can assume the device is configured 1002 * according to the platform needs. 1003 */ 1004 res = &vmd->dev->resource[VMD_MEMBAR1]; 1005 upper_bits = upper_32_bits(res->end); 1006 flags = res->flags & ~IORESOURCE_SIZEALIGN; 1007 if (!upper_bits) 1008 flags &= ~IORESOURCE_MEM_64; 1009 vmd->resources[1] = (struct resource) { 1010 .name = "VMD MEMBAR1", 1011 .start = res->start, 1012 .end = res->end, 1013 .flags = flags, 1014 .parent = res, 1015 }; 1016 1017 res = &vmd->dev->resource[VMD_MEMBAR2]; 1018 upper_bits = upper_32_bits(res->end); 1019 flags = res->flags & ~IORESOURCE_SIZEALIGN; 1020 if (!upper_bits) 1021 flags &= ~IORESOURCE_MEM_64; 1022 vmd->resources[2] = (struct resource) { 1023 .name = "VMD MEMBAR2", 1024 .start = res->start + membar2_offset, 1025 .end = res->end, 1026 .flags = flags, 1027 .parent = res, 1028 }; 1029 1030 /* Non-zero offset means guest/direct assign view. */ 1031 vmd_in_guest = offset[0] || offset[1]; 1032 1033 /* 1034 * Currently MSI remapping must be enabled in guest passthrough mode 1035 * due to some missing interrupt remapping plumbing. This is probably 1036 * acceptable because the guest is usually CPU-limited and MSI 1037 * remapping doesn't become a performance bottleneck. 1038 */ 1039 if (!(features & VMD_FEAT_CAN_BYPASS_MSI_REMAP) || vmd_in_guest) { 1040 ret = vmd_alloc_irqs(vmd); 1041 if (ret) 1042 return ret; 1043 1044 vmd_set_msi_remapping(vmd, true); 1045 1046 ret = vmd_create_irq_domain(vmd); 1047 if (ret) 1048 return ret; 1049 } else { 1050 vmd_set_msi_remapping(vmd, false); 1051 } 1052 1053 pci_add_resource(&resources, &vmd->resources[0]); 1054 pci_add_resource_offset(&resources, &vmd->resources[1], offset[0]); 1055 pci_add_resource_offset(&resources, &vmd->resources[2], offset[1]); 1056 1057 sd->vmd_dev = vmd->dev; 1058 1059 /* 1060 * Emulated domains start at 0x10000 to not clash with ACPI _SEG 1061 * domains. Per ACPI r6.0, sec 6.5.6, _SEG returns an integer, of 1062 * which the lower 16 bits are the PCI Segment Group (domain) number. 1063 * Other bits are currently reserved. 1064 */ 1065 sd->domain = pci_bus_find_emul_domain_nr(0, 0x10000, INT_MAX); 1066 if (sd->domain < 0) 1067 return sd->domain; 1068 1069 sd->node = pcibus_to_node(vmd->dev->bus); 1070 1071 vmd->bus = pci_create_root_bus(&vmd->dev->dev, vmd->busn_start, 1072 &vmd_ops, sd, &resources); 1073 if (!vmd->bus) { 1074 pci_bus_release_emul_domain_nr(sd->domain); 1075 pci_free_resource_list(&resources); 1076 vmd_remove_irq_domain(vmd); 1077 return -ENODEV; 1078 } 1079 1080 /* 1081 * Don't copy _OSC control flags from root bridge if running in a VM, as 1082 * they don't reflect the physical root bridge capabilities. 1083 */ 1084 if (!vmd_in_guest) 1085 vmd_copy_host_bridge_flags(pci_find_host_bridge(vmd->dev->bus), 1086 to_pci_host_bridge(vmd->bus->bridge)); 1087 1088 vmd_attach_resources(vmd); 1089 if (vmd->irq_domain) 1090 dev_set_msi_domain(&vmd->bus->dev, vmd->irq_domain); 1091 else 1092 dev_set_msi_domain(&vmd->bus->dev, 1093 dev_get_msi_domain(&vmd->dev->dev)); 1094 1095 WARN(sysfs_create_link(&vmd->dev->dev.kobj, &vmd->bus->dev.kobj, 1096 "domain"), "Can't create symlink to domain\n"); 1097 1098 vmd_acpi_begin(); 1099 1100 pci_scan_child_bus(vmd->bus); 1101 vmd_domain_reset(vmd); 1102 1103 /* When Intel VMD is enabled, the OS does not discover the Root Ports 1104 * owned by Intel VMD within the MMCFG space. pci_reset_bus() applies 1105 * a reset to the parent of the PCI device supplied as argument. This 1106 * is why we pass a child device, so the reset can be triggered at 1107 * the Intel bridge level and propagated to all the children in the 1108 * hierarchy. 1109 */ 1110 list_for_each_entry(child, &vmd->bus->children, node) { 1111 if (!list_empty(&child->devices)) { 1112 dev = list_first_entry(&child->devices, 1113 struct pci_dev, bus_list); 1114 ret = pci_reset_bus(dev); 1115 if (ret) 1116 pci_warn(dev, "can't reset device: %d\n", ret); 1117 1118 break; 1119 } 1120 } 1121 1122 pci_assign_unassigned_bus_resources(vmd->bus); 1123 1124 pci_walk_bus(vmd->bus, vmd_pm_enable_quirk, &features); 1125 1126 /* 1127 * VMD root buses are virtual and don't return true on pci_is_pcie() 1128 * and will fail pcie_bus_configure_settings() early. It can instead be 1129 * run on each of the real root ports. 1130 */ 1131 list_for_each_entry(child, &vmd->bus->children, node) 1132 pcie_bus_configure_settings(child); 1133 1134 pci_bus_add_devices(vmd->bus); 1135 1136 vmd_acpi_end(); 1137 return 0; 1138 } 1139 1140 static int vmd_probe(struct pci_dev *dev, const struct pci_device_id *id) 1141 { 1142 unsigned long features = (unsigned long) id->driver_data; 1143 struct vmd_dev *vmd; 1144 int err; 1145 1146 if (xen_domain()) { 1147 /* 1148 * Xen doesn't have knowledge about devices in the VMD bus 1149 * because the config space of devices behind the VMD bridge is 1150 * not known to Xen, and hence Xen cannot discover or configure 1151 * them in any way. 1152 * 1153 * Bypass of MSI remapping won't work in that case as direct 1154 * write by Linux to the MSI entries won't result in functional 1155 * interrupts, as Xen is the entity that manages the host 1156 * interrupt controller and must configure interrupts. However 1157 * multiplexing of interrupts by the VMD bridge will work under 1158 * Xen, so force the usage of that mode which must always be 1159 * supported by VMD bridges. 1160 */ 1161 features &= ~VMD_FEAT_CAN_BYPASS_MSI_REMAP; 1162 } 1163 1164 if (resource_size(&dev->resource[VMD_CFGBAR]) < (1 << 20)) 1165 return -ENOMEM; 1166 1167 vmd = devm_kzalloc_obj(&dev->dev, *vmd); 1168 if (!vmd) 1169 return -ENOMEM; 1170 1171 vmd->dev = dev; 1172 vmd->sysdata.domain = PCI_DOMAIN_NR_NOT_SET; 1173 vmd->features = features; 1174 vmd->instance = ida_alloc(&vmd_instance_ida, GFP_KERNEL); 1175 if (vmd->instance < 0) 1176 return vmd->instance; 1177 1178 vmd->name = devm_kasprintf(&dev->dev, GFP_KERNEL, "vmd%d", 1179 vmd->instance); 1180 if (!vmd->name) { 1181 err = -ENOMEM; 1182 goto out_release_instance; 1183 } 1184 1185 err = pcim_enable_device(dev); 1186 if (err < 0) 1187 goto out_release_instance; 1188 1189 vmd->cfgbar = pcim_iomap(dev, VMD_CFGBAR, 0); 1190 if (!vmd->cfgbar) { 1191 err = -ENOMEM; 1192 goto out_release_instance; 1193 } 1194 1195 pci_set_master(dev); 1196 if (dma_set_mask_and_coherent(&dev->dev, DMA_BIT_MASK(64)) && 1197 dma_set_mask_and_coherent(&dev->dev, DMA_BIT_MASK(32))) { 1198 err = -ENODEV; 1199 goto out_release_instance; 1200 } 1201 1202 if (features & VMD_FEAT_OFFSET_FIRST_VECTOR) 1203 vmd->first_vec = 1; 1204 1205 raw_spin_lock_init(&vmd->cfg_lock); 1206 pci_set_drvdata(dev, vmd); 1207 err = vmd_enable_domain(vmd, features); 1208 if (err) 1209 goto out_release_instance; 1210 1211 dev_info(&vmd->dev->dev, "Bound to PCI domain %04x\n", 1212 vmd->sysdata.domain); 1213 return 0; 1214 1215 out_release_instance: 1216 ida_free(&vmd_instance_ida, vmd->instance); 1217 return err; 1218 } 1219 1220 static void vmd_cleanup_srcu(struct vmd_dev *vmd) 1221 { 1222 int i; 1223 1224 for (i = 0; i < vmd->msix_count; i++) 1225 cleanup_srcu_struct(&vmd->irqs[i].srcu); 1226 } 1227 1228 static void vmd_remove(struct pci_dev *dev) 1229 { 1230 struct vmd_dev *vmd = pci_get_drvdata(dev); 1231 1232 pci_stop_root_bus(vmd->bus); 1233 sysfs_remove_link(&vmd->dev->dev.kobj, "domain"); 1234 pci_remove_root_bus(vmd->bus); 1235 vmd_cleanup_srcu(vmd); 1236 vmd_detach_resources(vmd); 1237 vmd_remove_irq_domain(vmd); 1238 ida_free(&vmd_instance_ida, vmd->instance); 1239 pci_bus_release_emul_domain_nr(vmd->sysdata.domain); 1240 } 1241 1242 static void vmd_shutdown(struct pci_dev *dev) 1243 { 1244 struct vmd_dev *vmd = pci_get_drvdata(dev); 1245 1246 vmd_remove_irq_domain(vmd); 1247 } 1248 1249 #ifdef CONFIG_PM_SLEEP 1250 static int vmd_suspend(struct device *dev) 1251 { 1252 struct pci_dev *pdev = to_pci_dev(dev); 1253 struct vmd_dev *vmd = pci_get_drvdata(pdev); 1254 int i; 1255 1256 for (i = 0; i < vmd->msix_count; i++) 1257 devm_free_irq(dev, vmd->irqs[i].virq, &vmd->irqs[i]); 1258 1259 return 0; 1260 } 1261 1262 static int vmd_resume(struct device *dev) 1263 { 1264 struct pci_dev *pdev = to_pci_dev(dev); 1265 struct vmd_dev *vmd = pci_get_drvdata(pdev); 1266 int err, i; 1267 1268 vmd_set_msi_remapping(vmd, !!vmd->irq_domain); 1269 1270 for (i = 0; i < vmd->msix_count; i++) { 1271 err = devm_request_irq(dev, vmd->irqs[i].virq, 1272 vmd_irq, IRQF_NO_THREAD, 1273 vmd->name, &vmd->irqs[i]); 1274 if (err) 1275 return err; 1276 } 1277 1278 return 0; 1279 } 1280 #endif 1281 static SIMPLE_DEV_PM_OPS(vmd_dev_pm_ops, vmd_suspend, vmd_resume); 1282 1283 static const struct pci_device_id vmd_ids[] = { 1284 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_VMD_201D), 1285 .driver_data = VMD_FEAT_HAS_MEMBAR_SHADOW_VSCAP,}, 1286 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_VMD_28C0), 1287 .driver_data = VMD_FEAT_HAS_MEMBAR_SHADOW | 1288 VMD_FEAT_HAS_BUS_RESTRICTIONS | 1289 VMD_FEAT_CAN_BYPASS_MSI_REMAP,}, 1290 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_VMD_28C1), 1291 .driver_data = VMD_FEAT_HAS_MEMBAR_SHADOW | 1292 VMD_FEAT_CAN_BYPASS_MSI_REMAP | 1293 VMD_FEAT_USE_BIOS_INFO,}, 1294 {PCI_VDEVICE(INTEL, 0x467f), 1295 .driver_data = VMD_FEATS_CLIENT,}, 1296 {PCI_VDEVICE(INTEL, 0x4c3d), 1297 .driver_data = VMD_FEATS_CLIENT,}, 1298 {PCI_VDEVICE(INTEL, 0xa77f), 1299 .driver_data = VMD_FEATS_CLIENT,}, 1300 {PCI_VDEVICE(INTEL, 0x7d0b), 1301 .driver_data = VMD_FEATS_CLIENT | VMD_FEAT_INTERRUPT_QUIRK,}, 1302 {PCI_VDEVICE(INTEL, 0xad0b), 1303 .driver_data = VMD_FEATS_CLIENT | VMD_FEAT_INTERRUPT_QUIRK,}, 1304 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_VMD_9A0B), 1305 .driver_data = VMD_FEATS_CLIENT,}, 1306 {PCI_VDEVICE(INTEL, 0xb60b), 1307 .driver_data = VMD_FEATS_CLIENT,}, 1308 {PCI_VDEVICE(INTEL, 0xb06f), 1309 .driver_data = VMD_FEATS_CLIENT,}, 1310 {PCI_VDEVICE(INTEL, 0xb07f), 1311 .driver_data = VMD_FEATS_CLIENT,}, 1312 {PCI_VDEVICE(INTEL, 0xd70b), 1313 .driver_data = VMD_FEATS_CLIENT,}, 1314 {PCI_VDEVICE(INTEL, 0xd73b), 1315 .driver_data = VMD_FEATS_CLIENT,}, 1316 {0,} 1317 }; 1318 MODULE_DEVICE_TABLE(pci, vmd_ids); 1319 1320 static struct pci_driver vmd_drv = { 1321 .name = "vmd", 1322 .id_table = vmd_ids, 1323 .probe = vmd_probe, 1324 .remove = vmd_remove, 1325 .shutdown = vmd_shutdown, 1326 .driver = { 1327 .pm = &vmd_dev_pm_ops, 1328 }, 1329 }; 1330 module_pci_driver(vmd_drv); 1331 1332 MODULE_AUTHOR("Intel Corporation"); 1333 MODULE_DESCRIPTION("Volume Management Device driver"); 1334 MODULE_LICENSE("GPL v2"); 1335 MODULE_VERSION("0.6"); 1336