1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Volume Management Device driver 4 * Copyright (c) 2015, Intel Corporation. 5 */ 6 7 #include <linux/device.h> 8 #include <linux/interrupt.h> 9 #include <linux/irq.h> 10 #include <linux/irqchip/irq-msi-lib.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/msi.h> 14 #include <linux/pci.h> 15 #include <linux/pci-acpi.h> 16 #include <linux/pci-ecam.h> 17 #include <linux/srcu.h> 18 #include <linux/rculist.h> 19 #include <linux/rcupdate.h> 20 21 #include <xen/xen.h> 22 23 #include <asm/irqdomain.h> 24 25 #define VMD_CFGBAR 0 26 #define VMD_MEMBAR1 2 27 #define VMD_MEMBAR2 4 28 29 #define PCI_REG_VMCAP 0x40 30 #define BUS_RESTRICT_CAP(vmcap) (vmcap & 0x1) 31 #define PCI_REG_VMCONFIG 0x44 32 #define BUS_RESTRICT_CFG(vmcfg) ((vmcfg >> 8) & 0x3) 33 #define VMCONFIG_MSI_REMAP 0x2 34 #define PCI_REG_VMLOCK 0x70 35 #define MB2_SHADOW_EN(vmlock) (vmlock & 0x2) 36 37 #define MB2_SHADOW_OFFSET 0x2000 38 #define MB2_SHADOW_SIZE 16 39 40 /* DMR BAR4 register offsets */ 41 #define SHADOW_MEMBAR1_28C1 0x2818 /* MEMBAR1 physical address */ 42 #define SHADOW_MEMBAR2_28C1 0x2820 /* MEMBAR2 physical address */ 43 #define BASE_ID_REG_28C1 0x2840 44 #define MEMBAR2_OFFSET_28C1 0x30d0 45 46 enum vmd_features { 47 /* 48 * Device may contain registers which hint the physical location of the 49 * membars, in order to allow proper address translation during 50 * resource assignment to enable guest virtualization 51 */ 52 VMD_FEAT_HAS_MEMBAR_SHADOW = (1 << 0), 53 54 /* 55 * Device may provide root port configuration information which limits 56 * bus numbering 57 */ 58 VMD_FEAT_HAS_BUS_RESTRICTIONS = (1 << 1), 59 60 /* 61 * Device contains physical location shadow registers in 62 * vendor-specific capability space 63 */ 64 VMD_FEAT_HAS_MEMBAR_SHADOW_VSCAP = (1 << 2), 65 66 /* 67 * Device may use MSI-X vector 0 for software triggering and will not 68 * be used for MSI remapping 69 */ 70 VMD_FEAT_OFFSET_FIRST_VECTOR = (1 << 3), 71 72 /* 73 * Device can bypass remapping MSI-X transactions into its MSI-X table, 74 * avoiding the requirement of a VMD MSI domain for child device 75 * interrupt handling. 76 */ 77 VMD_FEAT_CAN_BYPASS_MSI_REMAP = (1 << 4), 78 79 /* 80 * Enable ASPM on the PCIE root ports and set the default LTR of the 81 * storage devices on platforms where these values are not configured by 82 * BIOS. This is needed for laptops, which require these settings for 83 * proper power management of the SoC. 84 */ 85 VMD_FEAT_BIOS_PM_QUIRK = (1 << 5), 86 87 /* 88 * Newer VMD with device ID 0x28C1 has unique settings compared to its 89 * predecessor where BIOS enumerates the entire VMD device tree and 90 * stores respective configurations including bus start range and 91 * shadow registers in VMD MMIO space in VMD BAR4/BAR5, otherwise 92 * referred to as MEMBAR2 or MSI-X BAR. 93 */ 94 VMD_FEAT_USE_BIOS_INFO = (1 << 6), 95 }; 96 97 #define VMD_BIOS_PM_QUIRK_LTR 0x1003 /* 3145728 ns */ 98 99 #define VMD_FEATS_CLIENT (VMD_FEAT_HAS_MEMBAR_SHADOW_VSCAP | \ 100 VMD_FEAT_HAS_BUS_RESTRICTIONS | \ 101 VMD_FEAT_OFFSET_FIRST_VECTOR | \ 102 VMD_FEAT_BIOS_PM_QUIRK) 103 104 static DEFINE_IDA(vmd_instance_ida); 105 106 /* 107 * Lock for manipulating VMD IRQ lists. 108 */ 109 static DEFINE_RAW_SPINLOCK(list_lock); 110 111 /** 112 * struct vmd_irq - private data to map driver IRQ to the VMD shared vector 113 * @node: list item for parent traversal. 114 * @irq: back pointer to parent. 115 * @enabled: true if driver enabled IRQ 116 * @virq: the virtual IRQ value provided to the requesting driver. 117 * 118 * Every MSI/MSI-X IRQ requested for a device in a VMD domain will be mapped to 119 * a VMD IRQ using this structure. 120 */ 121 struct vmd_irq { 122 struct list_head node; 123 struct vmd_irq_list *irq; 124 bool enabled; 125 unsigned int virq; 126 }; 127 128 /** 129 * struct vmd_irq_list - list of driver requested IRQs mapping to a VMD vector 130 * @irq_list: the list of irq's the VMD one demuxes to. 131 * @srcu: SRCU struct for local synchronization. 132 * @count: number of child IRQs assigned to this vector; used to track 133 * sharing. 134 * @virq: The underlying VMD Linux interrupt number 135 */ 136 struct vmd_irq_list { 137 struct list_head irq_list; 138 struct srcu_struct srcu; 139 unsigned int count; 140 unsigned int virq; 141 }; 142 143 struct vmd_dev { 144 struct pci_dev *dev; 145 146 raw_spinlock_t cfg_lock; 147 void __iomem *cfgbar; 148 149 int msix_count; 150 struct vmd_irq_list *irqs; 151 152 struct pci_sysdata sysdata; 153 struct resource resources[3]; 154 struct irq_domain *irq_domain; 155 struct pci_bus *bus; 156 u8 busn_start; 157 u8 first_vec; 158 char *name; 159 int instance; 160 unsigned long features; 161 }; 162 163 static inline struct vmd_dev *vmd_from_bus(struct pci_bus *bus) 164 { 165 return container_of(bus->sysdata, struct vmd_dev, sysdata); 166 } 167 168 static inline unsigned int index_from_irqs(struct vmd_dev *vmd, 169 struct vmd_irq_list *irqs) 170 { 171 return irqs - vmd->irqs; 172 } 173 174 /* 175 * Drivers managing a device in a VMD domain allocate their own IRQs as before, 176 * but the MSI entry for the hardware it's driving will be programmed with a 177 * destination ID for the VMD MSI-X table. The VMD muxes interrupts in its 178 * domain into one of its own, and the VMD driver de-muxes these for the 179 * handlers sharing that VMD IRQ. The vmd irq_domain provides the operations 180 * and irq_chip to set this up. 181 */ 182 static void vmd_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) 183 { 184 struct vmd_irq *vmdirq = data->chip_data; 185 struct vmd_irq_list *irq = vmdirq->irq; 186 struct vmd_dev *vmd = irq_data_get_irq_handler_data(data); 187 188 memset(msg, 0, sizeof(*msg)); 189 msg->address_hi = X86_MSI_BASE_ADDRESS_HIGH; 190 msg->arch_addr_lo.base_address = X86_MSI_BASE_ADDRESS_LOW; 191 msg->arch_addr_lo.destid_0_7 = index_from_irqs(vmd, irq); 192 } 193 194 static void vmd_irq_enable(struct irq_data *data) 195 { 196 struct vmd_irq *vmdirq = data->chip_data; 197 198 scoped_guard(raw_spinlock_irqsave, &list_lock) { 199 WARN_ON(vmdirq->enabled); 200 list_add_tail_rcu(&vmdirq->node, &vmdirq->irq->irq_list); 201 vmdirq->enabled = true; 202 } 203 } 204 205 static void vmd_pci_msi_enable(struct irq_data *data) 206 { 207 vmd_irq_enable(data->parent_data); 208 data->chip->irq_unmask(data); 209 } 210 211 static unsigned int vmd_pci_msi_startup(struct irq_data *data) 212 { 213 vmd_pci_msi_enable(data); 214 return 0; 215 } 216 217 static void vmd_irq_disable(struct irq_data *data) 218 { 219 struct vmd_irq *vmdirq = data->chip_data; 220 221 scoped_guard(raw_spinlock_irqsave, &list_lock) { 222 if (vmdirq->enabled) { 223 list_del_rcu(&vmdirq->node); 224 vmdirq->enabled = false; 225 } 226 } 227 } 228 229 static void vmd_pci_msi_disable(struct irq_data *data) 230 { 231 data->chip->irq_mask(data); 232 vmd_irq_disable(data->parent_data); 233 } 234 235 static void vmd_pci_msi_shutdown(struct irq_data *data) 236 { 237 vmd_pci_msi_disable(data); 238 } 239 240 static struct irq_chip vmd_msi_controller = { 241 .name = "VMD-MSI", 242 .irq_compose_msi_msg = vmd_compose_msi_msg, 243 }; 244 245 /* 246 * XXX: We can be even smarter selecting the best IRQ once we solve the 247 * affinity problem. 248 */ 249 static struct vmd_irq_list *vmd_next_irq(struct vmd_dev *vmd, struct msi_desc *desc) 250 { 251 int i, best; 252 253 if (vmd->msix_count == 1 + vmd->first_vec) 254 return &vmd->irqs[vmd->first_vec]; 255 256 /* 257 * White list for fast-interrupt handlers. All others will share the 258 * "slow" interrupt vector. 259 */ 260 switch (msi_desc_to_pci_dev(desc)->class) { 261 case PCI_CLASS_STORAGE_EXPRESS: 262 break; 263 default: 264 return &vmd->irqs[vmd->first_vec]; 265 } 266 267 scoped_guard(raw_spinlock_irq, &list_lock) { 268 best = vmd->first_vec + 1; 269 for (i = best; i < vmd->msix_count; i++) 270 if (vmd->irqs[i].count < vmd->irqs[best].count) 271 best = i; 272 vmd->irqs[best].count++; 273 } 274 275 return &vmd->irqs[best]; 276 } 277 278 static void vmd_msi_free(struct irq_domain *domain, unsigned int virq, 279 unsigned int nr_irqs); 280 281 static int vmd_msi_alloc(struct irq_domain *domain, unsigned int virq, 282 unsigned int nr_irqs, void *arg) 283 { 284 struct msi_desc *desc = ((msi_alloc_info_t *)arg)->desc; 285 struct vmd_dev *vmd = domain->host_data; 286 struct vmd_irq *vmdirq; 287 288 for (int i = 0; i < nr_irqs; ++i) { 289 vmdirq = kzalloc_obj(*vmdirq); 290 if (!vmdirq) { 291 vmd_msi_free(domain, virq, i); 292 return -ENOMEM; 293 } 294 295 INIT_LIST_HEAD(&vmdirq->node); 296 vmdirq->irq = vmd_next_irq(vmd, desc); 297 vmdirq->virq = virq + i; 298 299 irq_domain_set_info(domain, virq + i, vmdirq->irq->virq, 300 &vmd_msi_controller, vmdirq, 301 handle_untracked_irq, vmd, NULL); 302 } 303 304 return 0; 305 } 306 307 static void vmd_msi_free(struct irq_domain *domain, unsigned int virq, 308 unsigned int nr_irqs) 309 { 310 struct irq_data *irq_data; 311 struct vmd_irq *vmdirq; 312 313 for (int i = 0; i < nr_irqs; ++i) { 314 irq_data = irq_domain_get_irq_data(domain, virq + i); 315 vmdirq = irq_data->chip_data; 316 317 synchronize_srcu(&vmdirq->irq->srcu); 318 319 /* XXX: Potential optimization to rebalance */ 320 scoped_guard(raw_spinlock_irq, &list_lock) 321 vmdirq->irq->count--; 322 323 kfree(vmdirq); 324 } 325 } 326 327 static const struct irq_domain_ops vmd_msi_domain_ops = { 328 .alloc = vmd_msi_alloc, 329 .free = vmd_msi_free, 330 }; 331 332 static bool vmd_init_dev_msi_info(struct device *dev, struct irq_domain *domain, 333 struct irq_domain *real_parent, 334 struct msi_domain_info *info) 335 { 336 if (!msi_lib_init_dev_msi_info(dev, domain, real_parent, info)) 337 return false; 338 339 info->chip->irq_startup = vmd_pci_msi_startup; 340 info->chip->irq_shutdown = vmd_pci_msi_shutdown; 341 info->chip->irq_enable = vmd_pci_msi_enable; 342 info->chip->irq_disable = vmd_pci_msi_disable; 343 return true; 344 } 345 346 #define VMD_MSI_FLAGS_SUPPORTED (MSI_GENERIC_FLAGS_MASK | MSI_FLAG_PCI_MSIX) 347 #define VMD_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_NO_AFFINITY) 348 349 static const struct msi_parent_ops vmd_msi_parent_ops = { 350 .supported_flags = VMD_MSI_FLAGS_SUPPORTED, 351 .required_flags = VMD_MSI_FLAGS_REQUIRED, 352 .bus_select_token = DOMAIN_BUS_VMD_MSI, 353 .bus_select_mask = MATCH_PCI_MSI, 354 .prefix = "VMD-", 355 .init_dev_msi_info = vmd_init_dev_msi_info, 356 }; 357 358 static int vmd_create_irq_domain(struct vmd_dev *vmd) 359 { 360 struct irq_domain_info info = { 361 .size = vmd->msix_count, 362 .ops = &vmd_msi_domain_ops, 363 .host_data = vmd, 364 }; 365 366 info.fwnode = irq_domain_alloc_named_id_fwnode("VMD-MSI", 367 vmd->sysdata.domain); 368 if (!info.fwnode) 369 return -ENODEV; 370 371 vmd->irq_domain = msi_create_parent_irq_domain(&info, 372 &vmd_msi_parent_ops); 373 if (!vmd->irq_domain) { 374 irq_domain_free_fwnode(info.fwnode); 375 return -ENODEV; 376 } 377 378 return 0; 379 } 380 381 static void vmd_set_msi_remapping(struct vmd_dev *vmd, bool enable) 382 { 383 u16 reg; 384 385 if (!!(vmd->features & VMD_FEAT_USE_BIOS_INFO)) 386 return; 387 388 pci_read_config_word(vmd->dev, PCI_REG_VMCONFIG, ®); 389 reg = enable ? (reg & ~VMCONFIG_MSI_REMAP) : 390 (reg | VMCONFIG_MSI_REMAP); 391 pci_write_config_word(vmd->dev, PCI_REG_VMCONFIG, reg); 392 } 393 394 static void vmd_remove_irq_domain(struct vmd_dev *vmd) 395 { 396 /* 397 * Some production BIOS won't enable remapping between soft reboots. 398 * Ensure remapping is restored before unloading the driver. 399 */ 400 if (!vmd->msix_count) 401 vmd_set_msi_remapping(vmd, true); 402 403 if (vmd->irq_domain) { 404 struct fwnode_handle *fn = vmd->irq_domain->fwnode; 405 406 irq_domain_remove(vmd->irq_domain); 407 irq_domain_free_fwnode(fn); 408 } 409 } 410 411 static unsigned int vmd_bus_to_ecam(struct vmd_dev *vmd, unsigned int busnr) 412 { 413 if (!!(vmd->features & VMD_FEAT_USE_BIOS_INFO)) 414 return busnr; 415 416 return busnr - vmd->busn_start; 417 } 418 419 static void __iomem *vmd_cfg_addr(struct vmd_dev *vmd, struct pci_bus *bus, 420 unsigned int devfn, int reg, int len) 421 { 422 unsigned int busnr_ecam; 423 u32 offset; 424 425 busnr_ecam = vmd_bus_to_ecam(vmd, bus->number); 426 offset = PCIE_ECAM_OFFSET(busnr_ecam, devfn, reg); 427 428 if (offset + len >= resource_size(&vmd->dev->resource[VMD_CFGBAR])) 429 return NULL; 430 431 return vmd->cfgbar + offset; 432 } 433 434 /* 435 * CPU may deadlock if config space is not serialized on some versions of this 436 * hardware, so all config space access is done under a spinlock. 437 */ 438 static int vmd_pci_read(struct pci_bus *bus, unsigned int devfn, int reg, 439 int len, u32 *value) 440 { 441 struct vmd_dev *vmd = vmd_from_bus(bus); 442 void __iomem *addr = vmd_cfg_addr(vmd, bus, devfn, reg, len); 443 444 if (!addr) 445 return -EFAULT; 446 447 guard(raw_spinlock_irqsave)(&vmd->cfg_lock); 448 switch (len) { 449 case 1: 450 *value = readb(addr); 451 return 0; 452 case 2: 453 *value = readw(addr); 454 return 0; 455 case 4: 456 *value = readl(addr); 457 return 0; 458 default: 459 return -EINVAL; 460 } 461 } 462 463 /* 464 * VMD h/w converts non-posted config writes to posted memory writes. The 465 * read-back in this function forces the completion so it returns only after 466 * the config space was written, as expected. 467 */ 468 static int vmd_pci_write(struct pci_bus *bus, unsigned int devfn, int reg, 469 int len, u32 value) 470 { 471 struct vmd_dev *vmd = vmd_from_bus(bus); 472 void __iomem *addr = vmd_cfg_addr(vmd, bus, devfn, reg, len); 473 474 if (!addr) 475 return -EFAULT; 476 477 guard(raw_spinlock_irqsave)(&vmd->cfg_lock); 478 switch (len) { 479 case 1: 480 writeb(value, addr); 481 readb(addr); 482 return 0; 483 case 2: 484 writew(value, addr); 485 readw(addr); 486 return 0; 487 case 4: 488 writel(value, addr); 489 readl(addr); 490 return 0; 491 default: 492 return -EINVAL; 493 } 494 } 495 496 static struct pci_ops vmd_ops = { 497 .read = vmd_pci_read, 498 .write = vmd_pci_write, 499 }; 500 501 #ifdef CONFIG_ACPI 502 static struct acpi_device *vmd_acpi_find_companion(struct pci_dev *pci_dev) 503 { 504 struct pci_host_bridge *bridge; 505 u32 busnr, addr; 506 507 if (pci_dev->bus->ops != &vmd_ops) 508 return NULL; 509 510 bridge = pci_find_host_bridge(pci_dev->bus); 511 busnr = pci_dev->bus->number - bridge->bus->number; 512 /* 513 * The address computation below is only applicable to relative bus 514 * numbers below 32. 515 */ 516 if (busnr > 31) 517 return NULL; 518 519 addr = (busnr << 24) | ((u32)pci_dev->devfn << 16) | 0x8000FFFFU; 520 521 dev_dbg(&pci_dev->dev, "Looking for ACPI companion (address 0x%x)\n", 522 addr); 523 524 return acpi_find_child_device(ACPI_COMPANION(bridge->dev.parent), addr, 525 false); 526 } 527 528 static bool hook_installed; 529 530 static void vmd_acpi_begin(void) 531 { 532 if (pci_acpi_set_companion_lookup_hook(vmd_acpi_find_companion)) 533 return; 534 535 hook_installed = true; 536 } 537 538 static void vmd_acpi_end(void) 539 { 540 if (!hook_installed) 541 return; 542 543 pci_acpi_clear_companion_lookup_hook(); 544 hook_installed = false; 545 } 546 #else 547 static inline void vmd_acpi_begin(void) { } 548 static inline void vmd_acpi_end(void) { } 549 #endif /* CONFIG_ACPI */ 550 551 static resource_size_t vmd_cfgbar_ecam_space(struct vmd_dev *vmd) 552 { 553 resource_size_t cfgbar_buses; 554 unsigned int ecam_start; 555 556 cfgbar_buses = resource_size(&vmd->dev->resource[VMD_CFGBAR]) >> 20; 557 ecam_start = vmd_bus_to_ecam(vmd, vmd->resources[0].start); 558 if (ecam_start >= cfgbar_buses) 559 return 0; 560 561 return cfgbar_buses - ecam_start; 562 } 563 static void vmd_domain_reset(struct vmd_dev *vmd) 564 { 565 u16 bus, max_buses = resource_size(&vmd->resources[0]); 566 u8 dev, functions, fn, hdr_type; 567 unsigned int ecam_bus; 568 char __iomem *base; 569 570 max_buses = min_t(u16, max_buses, vmd_cfgbar_ecam_space(vmd)); 571 for (bus = 0; bus < max_buses; bus++) { 572 ecam_bus = vmd_bus_to_ecam(vmd, vmd->resources[0].start + bus); 573 for (dev = 0; dev < 32; dev++) { 574 base = vmd->cfgbar + PCIE_ECAM_OFFSET(ecam_bus, 575 PCI_DEVFN(dev, 0), 0); 576 577 hdr_type = readb(base + PCI_HEADER_TYPE); 578 579 functions = (hdr_type & PCI_HEADER_TYPE_MFD) ? 8 : 1; 580 for (fn = 0; fn < functions; fn++) { 581 base = vmd->cfgbar + PCIE_ECAM_OFFSET(ecam_bus, 582 PCI_DEVFN(dev, fn), 0); 583 584 hdr_type = readb(base + PCI_HEADER_TYPE) & 585 PCI_HEADER_TYPE_MASK; 586 587 if (hdr_type != PCI_HEADER_TYPE_BRIDGE || 588 (readw(base + PCI_CLASS_DEVICE) != 589 PCI_CLASS_BRIDGE_PCI)) 590 continue; 591 592 /* 593 * Temporarily disable the I/O range before updating 594 * PCI_IO_BASE. 595 */ 596 writel(0x0000ffff, base + PCI_IO_BASE_UPPER16); 597 /* Update lower 16 bits of I/O base/limit */ 598 writew(0x00f0, base + PCI_IO_BASE); 599 /* Update upper 16 bits of I/O base/limit */ 600 writel(0, base + PCI_IO_BASE_UPPER16); 601 602 /* MMIO Base/Limit */ 603 writel(0x0000fff0, base + PCI_MEMORY_BASE); 604 605 /* Prefetchable MMIO Base/Limit */ 606 writel(0, base + PCI_PREF_LIMIT_UPPER32); 607 writel(0x0000fff0, base + PCI_PREF_MEMORY_BASE); 608 writel(0xffffffff, base + PCI_PREF_BASE_UPPER32); 609 } 610 } 611 } 612 } 613 614 static void vmd_attach_resources(struct vmd_dev *vmd) 615 { 616 vmd->dev->resource[VMD_MEMBAR1].child = &vmd->resources[1]; 617 vmd->dev->resource[VMD_MEMBAR2].child = &vmd->resources[2]; 618 } 619 620 static void vmd_detach_resources(struct vmd_dev *vmd) 621 { 622 vmd->dev->resource[VMD_MEMBAR1].child = NULL; 623 vmd->dev->resource[VMD_MEMBAR2].child = NULL; 624 } 625 626 static int vmd_get_phys_offsets(struct vmd_dev *vmd, bool native_hint, 627 resource_size_t *offset1, 628 resource_size_t *offset2) 629 { 630 struct pci_dev *dev = vmd->dev; 631 u64 phys1, phys2; 632 633 if (native_hint) { 634 u32 vmlock; 635 int ret; 636 637 ret = pci_read_config_dword(dev, PCI_REG_VMLOCK, &vmlock); 638 if (ret || PCI_POSSIBLE_ERROR(vmlock)) 639 return -ENODEV; 640 641 if (MB2_SHADOW_EN(vmlock)) { 642 void __iomem *membar2; 643 644 membar2 = pci_iomap(dev, VMD_MEMBAR2, 0); 645 if (!membar2) 646 return -ENOMEM; 647 phys1 = readq(membar2 + MB2_SHADOW_OFFSET); 648 phys2 = readq(membar2 + MB2_SHADOW_OFFSET + 8); 649 pci_iounmap(dev, membar2); 650 } else 651 return 0; 652 } else { 653 /* Hypervisor-Emulated Vendor-Specific Capability */ 654 int pos = pci_find_capability(dev, PCI_CAP_ID_VNDR); 655 u32 reg, regu; 656 657 pci_read_config_dword(dev, pos + 4, ®); 658 659 /* "SHDW" */ 660 if (pos && reg == 0x53484457) { 661 pci_read_config_dword(dev, pos + 8, ®); 662 pci_read_config_dword(dev, pos + 12, ®u); 663 phys1 = (u64) regu << 32 | reg; 664 665 pci_read_config_dword(dev, pos + 16, ®); 666 pci_read_config_dword(dev, pos + 20, ®u); 667 phys2 = (u64) regu << 32 | reg; 668 } else 669 return 0; 670 } 671 672 *offset1 = dev->resource[VMD_MEMBAR1].start - 673 (phys1 & PCI_BASE_ADDRESS_MEM_MASK); 674 *offset2 = dev->resource[VMD_MEMBAR2].start - 675 (phys2 & PCI_BASE_ADDRESS_MEM_MASK); 676 677 return 0; 678 } 679 680 static int vmd_get_bus_number_start(struct vmd_dev *vmd) 681 { 682 struct pci_dev *dev = vmd->dev; 683 u16 reg; 684 685 pci_read_config_word(dev, PCI_REG_VMCAP, ®); 686 if (BUS_RESTRICT_CAP(reg)) { 687 pci_read_config_word(dev, PCI_REG_VMCONFIG, ®); 688 if (PCI_POSSIBLE_ERROR(reg)) 689 return -ENODEV; 690 691 switch (BUS_RESTRICT_CFG(reg)) { 692 case 0: 693 vmd->busn_start = 0; 694 break; 695 case 1: 696 vmd->busn_start = 128; 697 break; 698 case 3: 699 case 2: 700 vmd->busn_start = 224; 701 break; 702 default: 703 pci_err(dev, "Unknown Bus Offset Setting (%d)\n", 704 BUS_RESTRICT_CFG(reg)); 705 return -ENODEV; 706 } 707 } 708 709 return 0; 710 } 711 712 static int vmd_get_bus_info_from_bar4(struct vmd_dev *vmd, 713 resource_size_t *offset1, 714 resource_size_t *offset2) 715 { 716 u64 phys1, phys2, bar4_2840; 717 void __iomem *bar4; 718 u32 base_id; 719 u8 base_bus; 720 721 bar4 = pci_ioremap_bar(vmd->dev, 4); 722 if (!bar4) 723 return -ENOMEM; 724 725 /* Read shadow registers for MEMBAR1 and MEMBAR2 physical addresses */ 726 phys1 = readq(bar4 + SHADOW_MEMBAR1_28C1); 727 phys2 = readq(bar4 + SHADOW_MEMBAR2_28C1); 728 729 /* 730 * Read and set bus start number from Base ID register. 24-bit Base ID 731 * register is part of 64-bit shadowed reqid hide range register and 732 * holds segment, bus, device and function. 733 */ 734 bar4_2840 = readq(bar4 + BASE_ID_REG_28C1); 735 base_id = bar4_2840 & 0xFFFFFF; 736 base_bus = base_id >> 8; 737 vmd->busn_start = base_bus; 738 739 /* Calculate offsets like vmd_get_phys_offsets() does */ 740 if (phys1) 741 *offset1 = vmd->dev->resource[VMD_MEMBAR1].start - 742 (phys1 & PCI_BASE_ADDRESS_MEM_MASK); 743 if (phys2) 744 *offset2 = vmd->dev->resource[VMD_MEMBAR2].start - 745 (phys2 & PCI_BASE_ADDRESS_MEM_MASK); 746 747 pci_iounmap(vmd->dev, bar4); 748 749 return 0; 750 } 751 752 static irqreturn_t vmd_irq(int irq, void *data) 753 { 754 struct vmd_irq_list *irqs = data; 755 struct vmd_irq *vmdirq; 756 int idx; 757 758 idx = srcu_read_lock(&irqs->srcu); 759 list_for_each_entry_rcu(vmdirq, &irqs->irq_list, node) 760 generic_handle_irq(vmdirq->virq); 761 srcu_read_unlock(&irqs->srcu, idx); 762 763 return IRQ_HANDLED; 764 } 765 766 static int vmd_alloc_irqs(struct vmd_dev *vmd) 767 { 768 struct pci_dev *dev = vmd->dev; 769 int i, err; 770 771 vmd->msix_count = pci_msix_vec_count(dev); 772 if (vmd->msix_count < 0) 773 return -ENODEV; 774 775 vmd->msix_count = pci_alloc_irq_vectors(dev, vmd->first_vec + 1, 776 vmd->msix_count, PCI_IRQ_MSIX); 777 if (vmd->msix_count < 0) 778 return vmd->msix_count; 779 780 vmd->irqs = devm_kcalloc(&dev->dev, vmd->msix_count, sizeof(*vmd->irqs), 781 GFP_KERNEL); 782 if (!vmd->irqs) 783 return -ENOMEM; 784 785 for (i = 0; i < vmd->msix_count; i++) { 786 err = init_srcu_struct(&vmd->irqs[i].srcu); 787 if (err) 788 return err; 789 790 INIT_LIST_HEAD(&vmd->irqs[i].irq_list); 791 vmd->irqs[i].virq = pci_irq_vector(dev, i); 792 err = devm_request_irq(&dev->dev, vmd->irqs[i].virq, 793 vmd_irq, IRQF_NO_THREAD, 794 vmd->name, &vmd->irqs[i]); 795 if (err) 796 return err; 797 } 798 799 return 0; 800 } 801 802 static int vmd_prepare_offsets_and_bus(struct vmd_dev *vmd, 803 unsigned long features, 804 resource_size_t *membar2_offset, 805 resource_size_t *offset1, 806 resource_size_t *offset2) 807 { 808 int ret; 809 810 /* 811 * Shadow registers may exist in certain VMD device IDs which allow 812 * guests to correctly assign host physical addresses to the root ports 813 * and child devices. These registers will either return the host value 814 * or 0, depending on an enable bit in the VMD device. 815 * 816 * For certain VMD devices (i.e. 0x28C1), BIOS places device info 817 * in BAR4 shadow registers to determine the base bus number and memory 818 * offsets. 819 */ 820 if (features & VMD_FEAT_USE_BIOS_INFO) { 821 *membar2_offset = MEMBAR2_OFFSET_28C1; 822 ret = vmd_get_bus_info_from_bar4(vmd, offset1, offset2); 823 if (ret) 824 return ret; 825 } else if (features & VMD_FEAT_HAS_MEMBAR_SHADOW) { 826 *membar2_offset = MB2_SHADOW_OFFSET + MB2_SHADOW_SIZE; 827 ret = vmd_get_phys_offsets(vmd, true, offset1, offset2); 828 if (ret) 829 return ret; 830 } else if (features & VMD_FEAT_HAS_MEMBAR_SHADOW_VSCAP) { 831 ret = vmd_get_phys_offsets(vmd, false, offset1, offset2); 832 if (ret) 833 return ret; 834 } 835 836 /* 837 * Certain VMD devices may have a root port configuration option which 838 * limits the bus range to between 0-127, 128-255, or 224-255. 839 */ 840 if (features & VMD_FEAT_HAS_BUS_RESTRICTIONS) { 841 ret = vmd_get_bus_number_start(vmd); 842 if (ret) 843 return ret; 844 } 845 return 0; 846 } 847 848 /* 849 * Since VMD is an aperture to regular PCIe root ports, only allow it to 850 * control features that the OS is allowed to control on the physical PCI bus. 851 */ 852 static void vmd_copy_host_bridge_flags(struct pci_host_bridge *root_bridge, 853 struct pci_host_bridge *vmd_bridge) 854 { 855 vmd_bridge->native_pcie_hotplug = root_bridge->native_pcie_hotplug; 856 vmd_bridge->native_shpc_hotplug = root_bridge->native_shpc_hotplug; 857 vmd_bridge->native_aer = root_bridge->native_aer; 858 vmd_bridge->native_pme = root_bridge->native_pme; 859 vmd_bridge->native_ltr = root_bridge->native_ltr; 860 vmd_bridge->native_dpc = root_bridge->native_dpc; 861 } 862 863 /* 864 * Enable ASPM and LTR settings on devices that aren't configured by BIOS. 865 */ 866 static int vmd_pm_enable_quirk(struct pci_dev *pdev, void *userdata) 867 { 868 unsigned long features = *(unsigned long *)userdata; 869 u16 ltr = VMD_BIOS_PM_QUIRK_LTR; 870 u32 ltr_reg; 871 int pos; 872 873 if (!(features & VMD_FEAT_BIOS_PM_QUIRK)) 874 return 0; 875 876 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_LTR); 877 if (!pos) 878 goto out_state_change; 879 880 /* 881 * Skip if the max snoop LTR is non-zero, indicating BIOS has set it 882 * so the LTR quirk is not needed. 883 */ 884 pci_read_config_dword(pdev, pos + PCI_LTR_MAX_SNOOP_LAT, <r_reg); 885 if (!!(ltr_reg & (PCI_LTR_VALUE_MASK | PCI_LTR_SCALE_MASK))) 886 goto out_state_change; 887 888 /* 889 * Set the default values to the maximum required by the platform to 890 * allow the deepest power management savings. Write as a DWORD where 891 * the lower word is the max snoop latency and the upper word is the 892 * max non-snoop latency. 893 */ 894 ltr_reg = (ltr << 16) | ltr; 895 pci_write_config_dword(pdev, pos + PCI_LTR_MAX_SNOOP_LAT, ltr_reg); 896 pci_info(pdev, "VMD: Default LTR value set by driver\n"); 897 898 out_state_change: 899 /* 900 * Ensure devices are in D0 before enabling PCI-PM L1 PM Substates, per 901 * PCIe r6.0, sec 5.5.4. 902 */ 903 pci_set_power_state_locked(pdev, PCI_D0); 904 pci_enable_link_state_locked(pdev, PCIE_LINK_STATE_ALL); 905 return 0; 906 } 907 908 static int vmd_enable_domain(struct vmd_dev *vmd, unsigned long features) 909 { 910 struct pci_sysdata *sd = &vmd->sysdata; 911 struct resource *res; 912 u32 upper_bits; 913 unsigned long flags; 914 LIST_HEAD(resources); 915 resource_size_t offset[2] = {0}; 916 resource_size_t membar2_offset = 0x2000; 917 resource_size_t busn_end; 918 struct pci_bus *child; 919 struct pci_dev *dev; 920 bool vmd_in_guest; 921 int ret; 922 923 ret = vmd_prepare_offsets_and_bus(vmd, features, &membar2_offset, 924 &offset[0], &offset[1]); 925 if (ret) 926 return ret; 927 928 /* Do not let resource[0] end go out of bounds */ 929 res = &vmd->dev->resource[VMD_CFGBAR]; 930 busn_end = vmd->busn_start + (resource_size(res) >> 20) - 1; 931 busn_end = min_t(resource_size_t, busn_end, 0xff); 932 vmd->resources[0] = (struct resource) { 933 .name = "VMD CFGBAR", 934 .start = vmd->busn_start, 935 .end = busn_end, 936 .flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED, 937 }; 938 939 /* 940 * If the window is below 4GB, clear IORESOURCE_MEM_64 so we can 941 * put 32-bit resources in the window. 942 * 943 * There's no hardware reason why a 64-bit window *couldn't* 944 * contain a 32-bit resource, but pbus_size_mem() computes the 945 * bridge window size assuming a 64-bit window will contain no 946 * 32-bit resources. __pci_assign_resource() enforces that 947 * artificial restriction to make sure everything will fit. 948 * 949 * The only way we could use a 64-bit non-prefetchable MEMBAR is 950 * if its address is <4GB so that we can convert it to a 32-bit 951 * resource. To be visible to the host OS, all VMD endpoints must 952 * be initially configured by platform BIOS, which includes setting 953 * up these resources. We can assume the device is configured 954 * according to the platform needs. 955 */ 956 res = &vmd->dev->resource[VMD_MEMBAR1]; 957 upper_bits = upper_32_bits(res->end); 958 flags = res->flags & ~IORESOURCE_SIZEALIGN; 959 if (!upper_bits) 960 flags &= ~IORESOURCE_MEM_64; 961 vmd->resources[1] = (struct resource) { 962 .name = "VMD MEMBAR1", 963 .start = res->start, 964 .end = res->end, 965 .flags = flags, 966 .parent = res, 967 }; 968 969 res = &vmd->dev->resource[VMD_MEMBAR2]; 970 upper_bits = upper_32_bits(res->end); 971 flags = res->flags & ~IORESOURCE_SIZEALIGN; 972 if (!upper_bits) 973 flags &= ~IORESOURCE_MEM_64; 974 vmd->resources[2] = (struct resource) { 975 .name = "VMD MEMBAR2", 976 .start = res->start + membar2_offset, 977 .end = res->end, 978 .flags = flags, 979 .parent = res, 980 }; 981 982 /* Non-zero offset means guest/direct assign view. */ 983 vmd_in_guest = offset[0] || offset[1]; 984 985 /* 986 * Currently MSI remapping must be enabled in guest passthrough mode 987 * due to some missing interrupt remapping plumbing. This is probably 988 * acceptable because the guest is usually CPU-limited and MSI 989 * remapping doesn't become a performance bottleneck. 990 */ 991 if (!(features & VMD_FEAT_CAN_BYPASS_MSI_REMAP) || vmd_in_guest) { 992 ret = vmd_alloc_irqs(vmd); 993 if (ret) 994 return ret; 995 996 vmd_set_msi_remapping(vmd, true); 997 998 ret = vmd_create_irq_domain(vmd); 999 if (ret) 1000 return ret; 1001 } else { 1002 vmd_set_msi_remapping(vmd, false); 1003 } 1004 1005 pci_add_resource(&resources, &vmd->resources[0]); 1006 pci_add_resource_offset(&resources, &vmd->resources[1], offset[0]); 1007 pci_add_resource_offset(&resources, &vmd->resources[2], offset[1]); 1008 1009 sd->vmd_dev = vmd->dev; 1010 1011 /* 1012 * Emulated domains start at 0x10000 to not clash with ACPI _SEG 1013 * domains. Per ACPI r6.0, sec 6.5.6, _SEG returns an integer, of 1014 * which the lower 16 bits are the PCI Segment Group (domain) number. 1015 * Other bits are currently reserved. 1016 */ 1017 sd->domain = pci_bus_find_emul_domain_nr(0, 0x10000, INT_MAX); 1018 if (sd->domain < 0) 1019 return sd->domain; 1020 1021 sd->node = pcibus_to_node(vmd->dev->bus); 1022 1023 vmd->bus = pci_create_root_bus(&vmd->dev->dev, vmd->busn_start, 1024 &vmd_ops, sd, &resources); 1025 if (!vmd->bus) { 1026 pci_bus_release_emul_domain_nr(sd->domain); 1027 pci_free_resource_list(&resources); 1028 vmd_remove_irq_domain(vmd); 1029 return -ENODEV; 1030 } 1031 1032 /* 1033 * Don't copy _OSC control flags from root bridge if running in a VM, as 1034 * they don't reflect the physical root bridge capabilities. 1035 */ 1036 if (!vmd_in_guest) 1037 vmd_copy_host_bridge_flags(pci_find_host_bridge(vmd->dev->bus), 1038 to_pci_host_bridge(vmd->bus->bridge)); 1039 1040 vmd_attach_resources(vmd); 1041 if (vmd->irq_domain) 1042 dev_set_msi_domain(&vmd->bus->dev, vmd->irq_domain); 1043 else 1044 dev_set_msi_domain(&vmd->bus->dev, 1045 dev_get_msi_domain(&vmd->dev->dev)); 1046 1047 WARN(sysfs_create_link(&vmd->dev->dev.kobj, &vmd->bus->dev.kobj, 1048 "domain"), "Can't create symlink to domain\n"); 1049 1050 vmd_acpi_begin(); 1051 1052 pci_scan_child_bus(vmd->bus); 1053 vmd_domain_reset(vmd); 1054 1055 /* When Intel VMD is enabled, the OS does not discover the Root Ports 1056 * owned by Intel VMD within the MMCFG space. pci_reset_bus() applies 1057 * a reset to the parent of the PCI device supplied as argument. This 1058 * is why we pass a child device, so the reset can be triggered at 1059 * the Intel bridge level and propagated to all the children in the 1060 * hierarchy. 1061 */ 1062 list_for_each_entry(child, &vmd->bus->children, node) { 1063 if (!list_empty(&child->devices)) { 1064 dev = list_first_entry(&child->devices, 1065 struct pci_dev, bus_list); 1066 ret = pci_reset_bus(dev); 1067 if (ret) 1068 pci_warn(dev, "can't reset device: %d\n", ret); 1069 1070 break; 1071 } 1072 } 1073 1074 pci_assign_unassigned_bus_resources(vmd->bus); 1075 1076 pci_walk_bus(vmd->bus, vmd_pm_enable_quirk, &features); 1077 1078 /* 1079 * VMD root buses are virtual and don't return true on pci_is_pcie() 1080 * and will fail pcie_bus_configure_settings() early. It can instead be 1081 * run on each of the real root ports. 1082 */ 1083 list_for_each_entry(child, &vmd->bus->children, node) 1084 pcie_bus_configure_settings(child); 1085 1086 pci_bus_add_devices(vmd->bus); 1087 1088 vmd_acpi_end(); 1089 return 0; 1090 } 1091 1092 static int vmd_probe(struct pci_dev *dev, const struct pci_device_id *id) 1093 { 1094 unsigned long features = (unsigned long) id->driver_data; 1095 struct vmd_dev *vmd; 1096 int err; 1097 1098 if (xen_domain()) { 1099 /* 1100 * Xen doesn't have knowledge about devices in the VMD bus 1101 * because the config space of devices behind the VMD bridge is 1102 * not known to Xen, and hence Xen cannot discover or configure 1103 * them in any way. 1104 * 1105 * Bypass of MSI remapping won't work in that case as direct 1106 * write by Linux to the MSI entries won't result in functional 1107 * interrupts, as Xen is the entity that manages the host 1108 * interrupt controller and must configure interrupts. However 1109 * multiplexing of interrupts by the VMD bridge will work under 1110 * Xen, so force the usage of that mode which must always be 1111 * supported by VMD bridges. 1112 */ 1113 features &= ~VMD_FEAT_CAN_BYPASS_MSI_REMAP; 1114 } 1115 1116 if (resource_size(&dev->resource[VMD_CFGBAR]) < (1 << 20)) 1117 return -ENOMEM; 1118 1119 vmd = devm_kzalloc(&dev->dev, sizeof(*vmd), GFP_KERNEL); 1120 if (!vmd) 1121 return -ENOMEM; 1122 1123 vmd->dev = dev; 1124 vmd->sysdata.domain = PCI_DOMAIN_NR_NOT_SET; 1125 vmd->features = features; 1126 vmd->instance = ida_alloc(&vmd_instance_ida, GFP_KERNEL); 1127 if (vmd->instance < 0) 1128 return vmd->instance; 1129 1130 vmd->name = devm_kasprintf(&dev->dev, GFP_KERNEL, "vmd%d", 1131 vmd->instance); 1132 if (!vmd->name) { 1133 err = -ENOMEM; 1134 goto out_release_instance; 1135 } 1136 1137 err = pcim_enable_device(dev); 1138 if (err < 0) 1139 goto out_release_instance; 1140 1141 vmd->cfgbar = pcim_iomap(dev, VMD_CFGBAR, 0); 1142 if (!vmd->cfgbar) { 1143 err = -ENOMEM; 1144 goto out_release_instance; 1145 } 1146 1147 pci_set_master(dev); 1148 if (dma_set_mask_and_coherent(&dev->dev, DMA_BIT_MASK(64)) && 1149 dma_set_mask_and_coherent(&dev->dev, DMA_BIT_MASK(32))) { 1150 err = -ENODEV; 1151 goto out_release_instance; 1152 } 1153 1154 if (features & VMD_FEAT_OFFSET_FIRST_VECTOR) 1155 vmd->first_vec = 1; 1156 1157 raw_spin_lock_init(&vmd->cfg_lock); 1158 pci_set_drvdata(dev, vmd); 1159 err = vmd_enable_domain(vmd, features); 1160 if (err) 1161 goto out_release_instance; 1162 1163 dev_info(&vmd->dev->dev, "Bound to PCI domain %04x\n", 1164 vmd->sysdata.domain); 1165 return 0; 1166 1167 out_release_instance: 1168 ida_free(&vmd_instance_ida, vmd->instance); 1169 return err; 1170 } 1171 1172 static void vmd_cleanup_srcu(struct vmd_dev *vmd) 1173 { 1174 int i; 1175 1176 for (i = 0; i < vmd->msix_count; i++) 1177 cleanup_srcu_struct(&vmd->irqs[i].srcu); 1178 } 1179 1180 static void vmd_remove(struct pci_dev *dev) 1181 { 1182 struct vmd_dev *vmd = pci_get_drvdata(dev); 1183 1184 pci_stop_root_bus(vmd->bus); 1185 sysfs_remove_link(&vmd->dev->dev.kobj, "domain"); 1186 pci_remove_root_bus(vmd->bus); 1187 vmd_cleanup_srcu(vmd); 1188 vmd_detach_resources(vmd); 1189 vmd_remove_irq_domain(vmd); 1190 ida_free(&vmd_instance_ida, vmd->instance); 1191 pci_bus_release_emul_domain_nr(vmd->sysdata.domain); 1192 } 1193 1194 static void vmd_shutdown(struct pci_dev *dev) 1195 { 1196 struct vmd_dev *vmd = pci_get_drvdata(dev); 1197 1198 vmd_remove_irq_domain(vmd); 1199 } 1200 1201 #ifdef CONFIG_PM_SLEEP 1202 static int vmd_suspend(struct device *dev) 1203 { 1204 struct pci_dev *pdev = to_pci_dev(dev); 1205 struct vmd_dev *vmd = pci_get_drvdata(pdev); 1206 int i; 1207 1208 for (i = 0; i < vmd->msix_count; i++) 1209 devm_free_irq(dev, vmd->irqs[i].virq, &vmd->irqs[i]); 1210 1211 return 0; 1212 } 1213 1214 static int vmd_resume(struct device *dev) 1215 { 1216 struct pci_dev *pdev = to_pci_dev(dev); 1217 struct vmd_dev *vmd = pci_get_drvdata(pdev); 1218 int err, i; 1219 1220 vmd_set_msi_remapping(vmd, !!vmd->irq_domain); 1221 1222 for (i = 0; i < vmd->msix_count; i++) { 1223 err = devm_request_irq(dev, vmd->irqs[i].virq, 1224 vmd_irq, IRQF_NO_THREAD, 1225 vmd->name, &vmd->irqs[i]); 1226 if (err) 1227 return err; 1228 } 1229 1230 return 0; 1231 } 1232 #endif 1233 static SIMPLE_DEV_PM_OPS(vmd_dev_pm_ops, vmd_suspend, vmd_resume); 1234 1235 static const struct pci_device_id vmd_ids[] = { 1236 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_VMD_201D), 1237 .driver_data = VMD_FEAT_HAS_MEMBAR_SHADOW_VSCAP,}, 1238 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_VMD_28C0), 1239 .driver_data = VMD_FEAT_HAS_MEMBAR_SHADOW | 1240 VMD_FEAT_HAS_BUS_RESTRICTIONS | 1241 VMD_FEAT_CAN_BYPASS_MSI_REMAP,}, 1242 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_VMD_28C1), 1243 .driver_data = VMD_FEAT_HAS_MEMBAR_SHADOW | 1244 VMD_FEAT_CAN_BYPASS_MSI_REMAP | 1245 VMD_FEAT_USE_BIOS_INFO,}, 1246 {PCI_VDEVICE(INTEL, 0x467f), 1247 .driver_data = VMD_FEATS_CLIENT,}, 1248 {PCI_VDEVICE(INTEL, 0x4c3d), 1249 .driver_data = VMD_FEATS_CLIENT,}, 1250 {PCI_VDEVICE(INTEL, 0xa77f), 1251 .driver_data = VMD_FEATS_CLIENT,}, 1252 {PCI_VDEVICE(INTEL, 0x7d0b), 1253 .driver_data = VMD_FEATS_CLIENT,}, 1254 {PCI_VDEVICE(INTEL, 0xad0b), 1255 .driver_data = VMD_FEATS_CLIENT,}, 1256 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_VMD_9A0B), 1257 .driver_data = VMD_FEATS_CLIENT,}, 1258 {PCI_VDEVICE(INTEL, 0xb60b), 1259 .driver_data = VMD_FEATS_CLIENT,}, 1260 {PCI_VDEVICE(INTEL, 0xb06f), 1261 .driver_data = VMD_FEATS_CLIENT,}, 1262 {PCI_VDEVICE(INTEL, 0xb07f), 1263 .driver_data = VMD_FEATS_CLIENT,}, 1264 {PCI_VDEVICE(INTEL, 0xd70b), 1265 .driver_data = VMD_FEATS_CLIENT,}, 1266 {PCI_VDEVICE(INTEL, 0xd73b), 1267 .driver_data = VMD_FEATS_CLIENT,}, 1268 {0,} 1269 }; 1270 MODULE_DEVICE_TABLE(pci, vmd_ids); 1271 1272 static struct pci_driver vmd_drv = { 1273 .name = "vmd", 1274 .id_table = vmd_ids, 1275 .probe = vmd_probe, 1276 .remove = vmd_remove, 1277 .shutdown = vmd_shutdown, 1278 .driver = { 1279 .pm = &vmd_dev_pm_ops, 1280 }, 1281 }; 1282 module_pci_driver(vmd_drv); 1283 1284 MODULE_AUTHOR("Intel Corporation"); 1285 MODULE_DESCRIPTION("Volume Management Device driver"); 1286 MODULE_LICENSE("GPL v2"); 1287 MODULE_VERSION("0.6"); 1288