xref: /linux/drivers/pci/controller/plda/pcie-starfive.c (revision ca220141fa8ebae09765a242076b2b77338106b0) 
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * PCIe host controller driver for StarFive JH7110 Soc.
4  *
5  * Copyright (C) 2023 StarFive Technology Co., Ltd.
6  */
7 
8 #include <linux/bitfield.h>
9 #include <linux/clk.h>
10 #include <linux/delay.h>
11 #include <linux/gpio/consumer.h>
12 #include <linux/interrupt.h>
13 #include <linux/kernel.h>
14 #include <linux/mfd/syscon.h>
15 #include <linux/module.h>
16 #include <linux/of_address.h>
17 #include <linux/of_irq.h>
18 #include <linux/of_pci.h>
19 #include <linux/pci.h>
20 #include <linux/phy/phy.h>
21 #include <linux/platform_device.h>
22 #include <linux/pm_runtime.h>
23 #include <linux/regmap.h>
24 #include <linux/reset.h>
25 #include "../../pci.h"
26 
27 #include "pcie-plda.h"
28 
29 #define PCIE_FUNC_NUM			4
30 
31 /* system control */
32 #define STG_SYSCON_PCIE0_BASE			0x48
33 #define STG_SYSCON_PCIE1_BASE			0x1f8
34 
35 #define STG_SYSCON_AR_OFFSET			0x78
36 #define STG_SYSCON_AXI4_SLVL_AR_MASK		GENMASK(22, 8)
37 #define STG_SYSCON_AXI4_SLVL_PHY_AR(x)		FIELD_PREP(GENMASK(20, 17), x)
38 #define STG_SYSCON_AW_OFFSET			0x7c
39 #define STG_SYSCON_AXI4_SLVL_AW_MASK		GENMASK(14, 0)
40 #define STG_SYSCON_AXI4_SLVL_PHY_AW(x)		FIELD_PREP(GENMASK(12, 9), x)
41 #define STG_SYSCON_CLKREQ			BIT(22)
42 #define STG_SYSCON_CKREF_SRC_MASK		GENMASK(19, 18)
43 #define STG_SYSCON_RP_NEP_OFFSET		0xe8
44 #define STG_SYSCON_K_RP_NEP			BIT(8)
45 #define STG_SYSCON_LNKSTA_OFFSET		0x170
46 #define DATA_LINK_ACTIVE			BIT(5)
47 
48 /* Parameters for the waiting for link up routine */
49 #define LINK_WAIT_MAX_RETRIES	10
50 #define LINK_WAIT_USLEEP_MIN	90000
51 #define LINK_WAIT_USLEEP_MAX	100000
52 
53 struct starfive_jh7110_pcie {
54 	struct plda_pcie_rp plda;
55 	struct reset_control *resets;
56 	struct clk_bulk_data *clks;
57 	struct regmap *reg_syscon;
58 	struct regulator *vpcie3v3;
59 	struct gpio_desc *reset_gpio;
60 	struct phy *phy;
61 
62 	unsigned int stg_pcie_base;
63 	int num_clks;
64 };
65 
66 /*
67  * JH7110 PCIe port BAR0/1 can be configured as 64-bit prefetchable memory
68  * space. PCIe read and write requests targeting BAR0/1 are routed to so called
69  * 'Bridge Configuration space' in PLDA IP datasheet, which contains the bridge
70  * internal registers, such as interrupt, DMA and ATU registers...
71  * JH7110 can access the Bridge Configuration space by local bus, and don`t
72  * want the bridge internal registers accessed by the DMA from EP devices.
73  * Thus, they are unimplemented and should be hidden here.
74  */
75 static bool starfive_pcie_hide_rc_bar(struct pci_bus *bus, unsigned int devfn,
76 				      int offset)
77 {
78 	if (pci_is_root_bus(bus) && !devfn &&
79 	    (offset == PCI_BASE_ADDRESS_0 || offset == PCI_BASE_ADDRESS_1))
80 		return true;
81 
82 	return false;
83 }
84 
85 static int starfive_pcie_config_write(struct pci_bus *bus, unsigned int devfn,
86 				      int where, int size, u32 value)
87 {
88 	if (starfive_pcie_hide_rc_bar(bus, devfn, where))
89 		return PCIBIOS_SUCCESSFUL;
90 
91 	return pci_generic_config_write(bus, devfn, where, size, value);
92 }
93 
94 static int starfive_pcie_config_read(struct pci_bus *bus, unsigned int devfn,
95 				     int where, int size, u32 *value)
96 {
97 	if (starfive_pcie_hide_rc_bar(bus, devfn, where)) {
98 		*value = 0;
99 		return PCIBIOS_SUCCESSFUL;
100 	}
101 
102 	return pci_generic_config_read(bus, devfn, where, size, value);
103 }
104 
105 static int starfive_pcie_parse_dt(struct starfive_jh7110_pcie *pcie,
106 				  struct device *dev)
107 {
108 	int domain_nr;
109 
110 	pcie->num_clks = devm_clk_bulk_get_all(dev, &pcie->clks);
111 	if (pcie->num_clks < 0)
112 		return dev_err_probe(dev, pcie->num_clks,
113 				     "failed to get pcie clocks\n");
114 
115 	pcie->resets = devm_reset_control_array_get_exclusive(dev);
116 	if (IS_ERR(pcie->resets))
117 		return dev_err_probe(dev, PTR_ERR(pcie->resets),
118 				     "failed to get pcie resets");
119 
120 	pcie->reg_syscon =
121 		syscon_regmap_lookup_by_phandle(dev->of_node,
122 						"starfive,stg-syscon");
123 
124 	if (IS_ERR(pcie->reg_syscon))
125 		return dev_err_probe(dev, PTR_ERR(pcie->reg_syscon),
126 				     "failed to parse starfive,stg-syscon\n");
127 
128 	pcie->phy = devm_phy_optional_get(dev, NULL);
129 	if (IS_ERR(pcie->phy))
130 		return dev_err_probe(dev, PTR_ERR(pcie->phy),
131 				     "failed to get pcie phy\n");
132 
133 	/*
134 	 * The PCIe domain numbers are set to be static in JH7110 DTS.
135 	 * As the STG system controller defines different bases in PCIe RP0 &
136 	 * RP1, we use them to identify which controller is doing the hardware
137 	 * initialization.
138 	 */
139 	domain_nr = of_get_pci_domain_nr(dev->of_node);
140 
141 	if (domain_nr < 0 || domain_nr > 1)
142 		return dev_err_probe(dev, -ENODEV,
143 				     "failed to get valid pcie domain\n");
144 
145 	if (domain_nr == 0)
146 		pcie->stg_pcie_base = STG_SYSCON_PCIE0_BASE;
147 	else
148 		pcie->stg_pcie_base = STG_SYSCON_PCIE1_BASE;
149 
150 	pcie->reset_gpio = devm_gpiod_get_optional(dev, "perst",
151 						   GPIOD_OUT_HIGH);
152 	if (IS_ERR(pcie->reset_gpio))
153 		return dev_err_probe(dev, PTR_ERR(pcie->reset_gpio),
154 				     "failed to get perst-gpio\n");
155 
156 	pcie->vpcie3v3 = devm_regulator_get_optional(dev, "vpcie3v3");
157 	if (IS_ERR(pcie->vpcie3v3)) {
158 		if (PTR_ERR(pcie->vpcie3v3) != -ENODEV)
159 			return dev_err_probe(dev, PTR_ERR(pcie->vpcie3v3),
160 					     "failed to get vpcie3v3 regulator\n");
161 		pcie->vpcie3v3 = NULL;
162 	}
163 
164 	return 0;
165 }
166 
167 static struct pci_ops starfive_pcie_ops = {
168 	.map_bus	= plda_pcie_map_bus,
169 	.read           = starfive_pcie_config_read,
170 	.write          = starfive_pcie_config_write,
171 };
172 
173 static int starfive_pcie_clk_rst_init(struct starfive_jh7110_pcie *pcie)
174 {
175 	struct device *dev = pcie->plda.dev;
176 	int ret;
177 
178 	ret = clk_bulk_prepare_enable(pcie->num_clks, pcie->clks);
179 	if (ret)
180 		return dev_err_probe(dev, ret, "failed to enable clocks\n");
181 
182 	ret = reset_control_deassert(pcie->resets);
183 	if (ret) {
184 		clk_bulk_disable_unprepare(pcie->num_clks, pcie->clks);
185 		dev_err_probe(dev, ret, "failed to deassert resets\n");
186 	}
187 
188 	return ret;
189 }
190 
191 static void starfive_pcie_clk_rst_deinit(struct starfive_jh7110_pcie *pcie)
192 {
193 	reset_control_assert(pcie->resets);
194 	clk_bulk_disable_unprepare(pcie->num_clks, pcie->clks);
195 }
196 
197 static bool starfive_pcie_link_up(struct plda_pcie_rp *plda)
198 {
199 	struct starfive_jh7110_pcie *pcie =
200 		container_of(plda, struct starfive_jh7110_pcie, plda);
201 	int ret;
202 	u32 stg_reg_val;
203 
204 	ret = regmap_read(pcie->reg_syscon,
205 			  pcie->stg_pcie_base + STG_SYSCON_LNKSTA_OFFSET,
206 			  &stg_reg_val);
207 	if (ret) {
208 		dev_err(pcie->plda.dev, "failed to read link status\n");
209 		return false;
210 	}
211 
212 	return !!(stg_reg_val & DATA_LINK_ACTIVE);
213 }
214 
215 static int starfive_pcie_host_wait_for_link(struct starfive_jh7110_pcie *pcie)
216 {
217 	int retries;
218 
219 	/* Check if the link is up or not */
220 	for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
221 		if (starfive_pcie_link_up(&pcie->plda)) {
222 			dev_info(pcie->plda.dev, "port link up\n");
223 			return 0;
224 		}
225 		usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);
226 	}
227 
228 	return -ETIMEDOUT;
229 }
230 
231 static int starfive_pcie_enable_phy(struct device *dev,
232 				    struct starfive_jh7110_pcie *pcie)
233 {
234 	int ret;
235 
236 	if (!pcie->phy)
237 		return 0;
238 
239 	ret = phy_init(pcie->phy);
240 	if (ret)
241 		return dev_err_probe(dev, ret,
242 				     "failed to initialize pcie phy\n");
243 
244 	ret = phy_set_mode(pcie->phy, PHY_MODE_PCIE);
245 	if (ret) {
246 		dev_err_probe(dev, ret, "failed to set pcie mode\n");
247 		goto err_phy_on;
248 	}
249 
250 	ret = phy_power_on(pcie->phy);
251 	if (ret) {
252 		dev_err_probe(dev, ret, "failed to power on pcie phy\n");
253 		goto err_phy_on;
254 	}
255 
256 	return 0;
257 
258 err_phy_on:
259 	phy_exit(pcie->phy);
260 	return ret;
261 }
262 
263 static void starfive_pcie_disable_phy(struct starfive_jh7110_pcie *pcie)
264 {
265 	phy_power_off(pcie->phy);
266 	phy_exit(pcie->phy);
267 }
268 
269 static void starfive_pcie_host_deinit(struct plda_pcie_rp *plda)
270 {
271 	struct starfive_jh7110_pcie *pcie =
272 		container_of(plda, struct starfive_jh7110_pcie, plda);
273 
274 	starfive_pcie_clk_rst_deinit(pcie);
275 	if (pcie->vpcie3v3)
276 		regulator_disable(pcie->vpcie3v3);
277 	starfive_pcie_disable_phy(pcie);
278 }
279 
280 static int starfive_pcie_host_init(struct plda_pcie_rp *plda)
281 {
282 	struct starfive_jh7110_pcie *pcie =
283 		container_of(plda, struct starfive_jh7110_pcie, plda);
284 	struct device *dev = plda->dev;
285 	int ret;
286 	int i;
287 
288 	ret = starfive_pcie_enable_phy(dev, pcie);
289 	if (ret)
290 		return ret;
291 
292 	regmap_update_bits(pcie->reg_syscon,
293 			   pcie->stg_pcie_base + STG_SYSCON_RP_NEP_OFFSET,
294 			   STG_SYSCON_K_RP_NEP, STG_SYSCON_K_RP_NEP);
295 
296 	regmap_update_bits(pcie->reg_syscon,
297 			   pcie->stg_pcie_base + STG_SYSCON_AW_OFFSET,
298 			   STG_SYSCON_CKREF_SRC_MASK,
299 			   FIELD_PREP(STG_SYSCON_CKREF_SRC_MASK, 2));
300 
301 	regmap_update_bits(pcie->reg_syscon,
302 			   pcie->stg_pcie_base + STG_SYSCON_AW_OFFSET,
303 			   STG_SYSCON_CLKREQ, STG_SYSCON_CLKREQ);
304 
305 	ret = starfive_pcie_clk_rst_init(pcie);
306 	if (ret)
307 		return ret;
308 
309 	if (pcie->vpcie3v3) {
310 		ret = regulator_enable(pcie->vpcie3v3);
311 		if (ret)
312 			dev_err_probe(dev, ret, "failed to enable vpcie3v3 regulator\n");
313 	}
314 
315 	if (pcie->reset_gpio)
316 		gpiod_set_value_cansleep(pcie->reset_gpio, 1);
317 
318 	/* Disable physical functions except #0 */
319 	for (i = 1; i < PCIE_FUNC_NUM; i++) {
320 		regmap_update_bits(pcie->reg_syscon,
321 				   pcie->stg_pcie_base + STG_SYSCON_AR_OFFSET,
322 				   STG_SYSCON_AXI4_SLVL_AR_MASK,
323 				   STG_SYSCON_AXI4_SLVL_PHY_AR(i));
324 
325 		regmap_update_bits(pcie->reg_syscon,
326 				   pcie->stg_pcie_base + STG_SYSCON_AW_OFFSET,
327 				   STG_SYSCON_AXI4_SLVL_AW_MASK,
328 				   STG_SYSCON_AXI4_SLVL_PHY_AW(i));
329 
330 		plda_pcie_disable_func(plda);
331 	}
332 
333 	regmap_update_bits(pcie->reg_syscon,
334 			   pcie->stg_pcie_base + STG_SYSCON_AR_OFFSET,
335 			   STG_SYSCON_AXI4_SLVL_AR_MASK, 0);
336 	regmap_update_bits(pcie->reg_syscon,
337 			   pcie->stg_pcie_base + STG_SYSCON_AW_OFFSET,
338 			   STG_SYSCON_AXI4_SLVL_AW_MASK, 0);
339 
340 	plda_pcie_enable_root_port(plda);
341 	plda_pcie_write_rc_bar(plda, 0);
342 
343 	/* PCIe PCI Standard Configuration Identification Settings. */
344 	plda_pcie_set_standard_class(plda);
345 
346 	/*
347 	 * The LTR message receiving is enabled by the register "PCIe Message
348 	 * Reception" as default, but the forward id & addr are uninitialized.
349 	 * If we do not disable LTR message forwarding here, or set a legal
350 	 * forwarding address, the kernel will get stuck.
351 	 * To workaround, disable the LTR message forwarding here before using
352 	 * this feature.
353 	 */
354 	plda_pcie_disable_ltr(plda);
355 
356 	/*
357 	 * Enable the prefetchable memory window 64-bit addressing in JH7110.
358 	 * The 64-bits prefetchable address translation configurations in ATU
359 	 * can be work after enable the register setting below.
360 	 */
361 	plda_pcie_set_pref_win_64bit(plda);
362 
363 	/*
364 	 * Ensure that PERST has been asserted for at least 100 ms,
365 	 * the sleep value is T_PVPERL from PCIe CEM spec r2.0 (Table 2-4)
366 	 */
367 	msleep(100);
368 	if (pcie->reset_gpio)
369 		gpiod_set_value_cansleep(pcie->reset_gpio, 0);
370 
371 	/*
372 	 * With a Downstream Port (<=5GT/s), software must wait a minimum
373 	 * of 100ms following exit from a conventional reset before
374 	 * sending a configuration request to the device.
375 	 */
376 	msleep(PCIE_RESET_CONFIG_WAIT_MS);
377 
378 	if (starfive_pcie_host_wait_for_link(pcie))
379 		dev_info(dev, "port link down\n");
380 
381 	return 0;
382 }
383 
384 static const struct plda_pcie_host_ops sf_host_ops = {
385 	.host_init = starfive_pcie_host_init,
386 	.host_deinit = starfive_pcie_host_deinit,
387 };
388 
389 static const struct plda_event stf_pcie_event = {
390 	.intx_event = EVENT_PM_MSI_INT_INTX,
391 	.msi_event  = EVENT_PM_MSI_INT_MSI
392 };
393 
394 static int starfive_pcie_probe(struct platform_device *pdev)
395 {
396 	struct starfive_jh7110_pcie *pcie;
397 	struct device *dev = &pdev->dev;
398 	struct plda_pcie_rp *plda;
399 	int ret;
400 
401 	pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
402 	if (!pcie)
403 		return -ENOMEM;
404 
405 	plda = &pcie->plda;
406 	plda->dev = dev;
407 
408 	ret = starfive_pcie_parse_dt(pcie, dev);
409 	if (ret)
410 		return ret;
411 
412 	pm_runtime_enable(&pdev->dev);
413 	pm_runtime_get_sync(&pdev->dev);
414 
415 	plda->host_ops = &sf_host_ops;
416 	plda->num_events = PLDA_MAX_EVENT_NUM;
417 	/* mask doorbell event */
418 	plda->events_bitmap = GENMASK(PLDA_INT_EVENT_NUM - 1, 0)
419 			     & ~BIT(PLDA_AXI_DOORBELL)
420 			     & ~BIT(PLDA_PCIE_DOORBELL);
421 	plda->events_bitmap <<= PLDA_NUM_DMA_EVENTS;
422 	ret = plda_pcie_host_init(&pcie->plda, &starfive_pcie_ops,
423 				  &stf_pcie_event);
424 	if (ret) {
425 		pm_runtime_put_sync(&pdev->dev);
426 		pm_runtime_disable(&pdev->dev);
427 		return ret;
428 	}
429 
430 	platform_set_drvdata(pdev, pcie);
431 
432 	return 0;
433 }
434 
435 static void starfive_pcie_remove(struct platform_device *pdev)
436 {
437 	struct starfive_jh7110_pcie *pcie = platform_get_drvdata(pdev);
438 
439 	pm_runtime_put(&pdev->dev);
440 	pm_runtime_disable(&pdev->dev);
441 	plda_pcie_host_deinit(&pcie->plda);
442 	platform_set_drvdata(pdev, NULL);
443 }
444 
445 static int starfive_pcie_suspend_noirq(struct device *dev)
446 {
447 	struct starfive_jh7110_pcie *pcie = dev_get_drvdata(dev);
448 
449 	clk_bulk_disable_unprepare(pcie->num_clks, pcie->clks);
450 	starfive_pcie_disable_phy(pcie);
451 
452 	return 0;
453 }
454 
455 static int starfive_pcie_resume_noirq(struct device *dev)
456 {
457 	struct starfive_jh7110_pcie *pcie = dev_get_drvdata(dev);
458 	int ret;
459 
460 	ret = starfive_pcie_enable_phy(dev, pcie);
461 	if (ret)
462 		return ret;
463 
464 	ret = clk_bulk_prepare_enable(pcie->num_clks, pcie->clks);
465 	if (ret) {
466 		dev_err(dev, "failed to enable clocks\n");
467 		starfive_pcie_disable_phy(pcie);
468 		return ret;
469 	}
470 
471 	return 0;
472 }
473 
474 static const struct dev_pm_ops starfive_pcie_pm_ops = {
475 	NOIRQ_SYSTEM_SLEEP_PM_OPS(starfive_pcie_suspend_noirq,
476 				  starfive_pcie_resume_noirq)
477 };
478 
479 static const struct of_device_id starfive_pcie_of_match[] = {
480 	{ .compatible = "starfive,jh7110-pcie", },
481 	{ /* sentinel */ }
482 };
483 MODULE_DEVICE_TABLE(of, starfive_pcie_of_match);
484 
485 static struct platform_driver starfive_pcie_driver = {
486 	.driver = {
487 		.name = "pcie-starfive",
488 		.of_match_table = of_match_ptr(starfive_pcie_of_match),
489 		.pm = pm_sleep_ptr(&starfive_pcie_pm_ops),
490 	},
491 	.probe = starfive_pcie_probe,
492 	.remove = starfive_pcie_remove,
493 };
494 module_platform_driver(starfive_pcie_driver);
495 
496 MODULE_DESCRIPTION("StarFive JH7110 PCIe host driver");
497 MODULE_LICENSE("GPL v2");
498