xref: /linux/drivers/pci/controller/plda/pcie-starfive.c (revision 3a2c4d55e32ad65efebdb6de44eef3bfa08bb49d) 
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * PCIe host controller driver for StarFive JH7110 Soc.
4  *
5  * Copyright (C) 2023 StarFive Technology Co., Ltd.
6  */
7 
8 #include <linux/bitfield.h>
9 #include <linux/clk.h>
10 #include <linux/delay.h>
11 #include <linux/gpio/consumer.h>
12 #include <linux/interrupt.h>
13 #include <linux/kernel.h>
14 #include <linux/mfd/syscon.h>
15 #include <linux/module.h>
16 #include <linux/of_address.h>
17 #include <linux/of_irq.h>
18 #include <linux/of_pci.h>
19 #include <linux/pci.h>
20 #include <linux/phy/phy.h>
21 #include <linux/platform_device.h>
22 #include <linux/pm_runtime.h>
23 #include <linux/regmap.h>
24 #include <linux/reset.h>
25 #include "../../pci.h"
26 
27 #include "pcie-plda.h"
28 
29 #define PCIE_FUNC_NUM			4
30 
31 /* system control */
32 #define STG_SYSCON_PCIE0_BASE			0x48
33 #define STG_SYSCON_PCIE1_BASE			0x1f8
34 
35 #define STG_SYSCON_AR_OFFSET			0x78
36 #define STG_SYSCON_AXI4_SLVL_AR_MASK		GENMASK(22, 8)
37 #define STG_SYSCON_AXI4_SLVL_PHY_AR(x)		FIELD_PREP(GENMASK(20, 17), x)
38 #define STG_SYSCON_AW_OFFSET			0x7c
39 #define STG_SYSCON_AXI4_SLVL_AW_MASK		GENMASK(14, 0)
40 #define STG_SYSCON_AXI4_SLVL_PHY_AW(x)		FIELD_PREP(GENMASK(12, 9), x)
41 #define STG_SYSCON_CLKREQ			BIT(22)
42 #define STG_SYSCON_CKREF_SRC_MASK		GENMASK(19, 18)
43 #define STG_SYSCON_RP_NEP_OFFSET		0xe8
44 #define STG_SYSCON_K_RP_NEP			BIT(8)
45 #define STG_SYSCON_LNKSTA_OFFSET		0x170
46 #define DATA_LINK_ACTIVE			BIT(5)
47 
48 struct starfive_jh7110_pcie {
49 	struct plda_pcie_rp plda;
50 	struct reset_control *resets;
51 	struct clk_bulk_data *clks;
52 	struct regmap *reg_syscon;
53 	struct regulator *vpcie3v3;
54 	struct gpio_desc *reset_gpio;
55 	struct phy *phy;
56 
57 	unsigned int stg_pcie_base;
58 	int num_clks;
59 };
60 
61 /*
62  * JH7110 PCIe port BAR0/1 can be configured as 64-bit prefetchable memory
63  * space. PCIe read and write requests targeting BAR0/1 are routed to so called
64  * 'Bridge Configuration space' in PLDA IP datasheet, which contains the bridge
65  * internal registers, such as interrupt, DMA and ATU registers...
66  * JH7110 can access the Bridge Configuration space by local bus, and don`t
67  * want the bridge internal registers accessed by the DMA from EP devices.
68  * Thus, they are unimplemented and should be hidden here.
69  */
70 static bool starfive_pcie_hide_rc_bar(struct pci_bus *bus, unsigned int devfn,
71 				      int offset)
72 {
73 	if (pci_is_root_bus(bus) && !devfn &&
74 	    (offset == PCI_BASE_ADDRESS_0 || offset == PCI_BASE_ADDRESS_1))
75 		return true;
76 
77 	return false;
78 }
79 
80 static int starfive_pcie_config_write(struct pci_bus *bus, unsigned int devfn,
81 				      int where, int size, u32 value)
82 {
83 	if (starfive_pcie_hide_rc_bar(bus, devfn, where))
84 		return PCIBIOS_SUCCESSFUL;
85 
86 	return pci_generic_config_write(bus, devfn, where, size, value);
87 }
88 
89 static int starfive_pcie_config_read(struct pci_bus *bus, unsigned int devfn,
90 				     int where, int size, u32 *value)
91 {
92 	if (starfive_pcie_hide_rc_bar(bus, devfn, where)) {
93 		*value = 0;
94 		return PCIBIOS_SUCCESSFUL;
95 	}
96 
97 	return pci_generic_config_read(bus, devfn, where, size, value);
98 }
99 
100 static int starfive_pcie_parse_dt(struct starfive_jh7110_pcie *pcie,
101 				  struct device *dev)
102 {
103 	int domain_nr;
104 
105 	pcie->num_clks = devm_clk_bulk_get_all(dev, &pcie->clks);
106 	if (pcie->num_clks < 0)
107 		return dev_err_probe(dev, pcie->num_clks,
108 				     "failed to get pcie clocks\n");
109 
110 	pcie->resets = devm_reset_control_array_get_exclusive(dev);
111 	if (IS_ERR(pcie->resets))
112 		return dev_err_probe(dev, PTR_ERR(pcie->resets),
113 				     "failed to get pcie resets");
114 
115 	pcie->reg_syscon =
116 		syscon_regmap_lookup_by_phandle(dev->of_node,
117 						"starfive,stg-syscon");
118 
119 	if (IS_ERR(pcie->reg_syscon))
120 		return dev_err_probe(dev, PTR_ERR(pcie->reg_syscon),
121 				     "failed to parse starfive,stg-syscon\n");
122 
123 	pcie->phy = devm_phy_optional_get(dev, NULL);
124 	if (IS_ERR(pcie->phy))
125 		return dev_err_probe(dev, PTR_ERR(pcie->phy),
126 				     "failed to get pcie phy\n");
127 
128 	/*
129 	 * The PCIe domain numbers are set to be static in JH7110 DTS.
130 	 * As the STG system controller defines different bases in PCIe RP0 &
131 	 * RP1, we use them to identify which controller is doing the hardware
132 	 * initialization.
133 	 */
134 	domain_nr = of_get_pci_domain_nr(dev->of_node);
135 
136 	if (domain_nr < 0 || domain_nr > 1)
137 		return dev_err_probe(dev, -ENODEV,
138 				     "failed to get valid pcie domain\n");
139 
140 	if (domain_nr == 0)
141 		pcie->stg_pcie_base = STG_SYSCON_PCIE0_BASE;
142 	else
143 		pcie->stg_pcie_base = STG_SYSCON_PCIE1_BASE;
144 
145 	pcie->reset_gpio = devm_gpiod_get_optional(dev, "perst",
146 						   GPIOD_OUT_HIGH);
147 	if (IS_ERR(pcie->reset_gpio))
148 		return dev_err_probe(dev, PTR_ERR(pcie->reset_gpio),
149 				     "failed to get perst-gpio\n");
150 
151 	pcie->vpcie3v3 = devm_regulator_get_optional(dev, "vpcie3v3");
152 	if (IS_ERR(pcie->vpcie3v3)) {
153 		if (PTR_ERR(pcie->vpcie3v3) != -ENODEV)
154 			return dev_err_probe(dev, PTR_ERR(pcie->vpcie3v3),
155 					     "failed to get vpcie3v3 regulator\n");
156 		pcie->vpcie3v3 = NULL;
157 	}
158 
159 	return 0;
160 }
161 
162 static struct pci_ops starfive_pcie_ops = {
163 	.map_bus	= plda_pcie_map_bus,
164 	.read           = starfive_pcie_config_read,
165 	.write          = starfive_pcie_config_write,
166 };
167 
168 static int starfive_pcie_clk_rst_init(struct starfive_jh7110_pcie *pcie)
169 {
170 	struct device *dev = pcie->plda.dev;
171 	int ret;
172 
173 	ret = clk_bulk_prepare_enable(pcie->num_clks, pcie->clks);
174 	if (ret)
175 		return dev_err_probe(dev, ret, "failed to enable clocks\n");
176 
177 	ret = reset_control_deassert(pcie->resets);
178 	if (ret) {
179 		clk_bulk_disable_unprepare(pcie->num_clks, pcie->clks);
180 		dev_err_probe(dev, ret, "failed to deassert resets\n");
181 	}
182 
183 	return ret;
184 }
185 
186 static void starfive_pcie_clk_rst_deinit(struct starfive_jh7110_pcie *pcie)
187 {
188 	reset_control_assert(pcie->resets);
189 	clk_bulk_disable_unprepare(pcie->num_clks, pcie->clks);
190 }
191 
192 static bool starfive_pcie_link_up(struct plda_pcie_rp *plda)
193 {
194 	struct starfive_jh7110_pcie *pcie =
195 		container_of(plda, struct starfive_jh7110_pcie, plda);
196 	int ret;
197 	u32 stg_reg_val;
198 
199 	ret = regmap_read(pcie->reg_syscon,
200 			  pcie->stg_pcie_base + STG_SYSCON_LNKSTA_OFFSET,
201 			  &stg_reg_val);
202 	if (ret) {
203 		dev_err(pcie->plda.dev, "failed to read link status\n");
204 		return false;
205 	}
206 
207 	return !!(stg_reg_val & DATA_LINK_ACTIVE);
208 }
209 
210 static int starfive_pcie_host_wait_for_link(struct starfive_jh7110_pcie *pcie)
211 {
212 	int retries;
213 
214 	/* Check if the link is up or not */
215 	for (retries = 0; retries < PCIE_LINK_WAIT_MAX_RETRIES; retries++) {
216 		if (starfive_pcie_link_up(&pcie->plda)) {
217 			dev_info(pcie->plda.dev, "port link up\n");
218 			return 0;
219 		}
220 		msleep(PCIE_LINK_WAIT_SLEEP_MS);
221 	}
222 
223 	return -ETIMEDOUT;
224 }
225 
226 static int starfive_pcie_enable_phy(struct device *dev,
227 				    struct starfive_jh7110_pcie *pcie)
228 {
229 	int ret;
230 
231 	if (!pcie->phy)
232 		return 0;
233 
234 	ret = phy_init(pcie->phy);
235 	if (ret)
236 		return dev_err_probe(dev, ret,
237 				     "failed to initialize pcie phy\n");
238 
239 	ret = phy_set_mode(pcie->phy, PHY_MODE_PCIE);
240 	if (ret) {
241 		dev_err_probe(dev, ret, "failed to set pcie mode\n");
242 		goto err_phy_on;
243 	}
244 
245 	ret = phy_power_on(pcie->phy);
246 	if (ret) {
247 		dev_err_probe(dev, ret, "failed to power on pcie phy\n");
248 		goto err_phy_on;
249 	}
250 
251 	return 0;
252 
253 err_phy_on:
254 	phy_exit(pcie->phy);
255 	return ret;
256 }
257 
258 static void starfive_pcie_disable_phy(struct starfive_jh7110_pcie *pcie)
259 {
260 	phy_power_off(pcie->phy);
261 	phy_exit(pcie->phy);
262 }
263 
264 static void starfive_pcie_host_deinit(struct plda_pcie_rp *plda)
265 {
266 	struct starfive_jh7110_pcie *pcie =
267 		container_of(plda, struct starfive_jh7110_pcie, plda);
268 
269 	starfive_pcie_clk_rst_deinit(pcie);
270 	if (pcie->vpcie3v3)
271 		regulator_disable(pcie->vpcie3v3);
272 	starfive_pcie_disable_phy(pcie);
273 }
274 
275 static int starfive_pcie_host_init(struct plda_pcie_rp *plda)
276 {
277 	struct starfive_jh7110_pcie *pcie =
278 		container_of(plda, struct starfive_jh7110_pcie, plda);
279 	struct device *dev = plda->dev;
280 	int ret;
281 	int i;
282 
283 	ret = starfive_pcie_enable_phy(dev, pcie);
284 	if (ret)
285 		return ret;
286 
287 	regmap_update_bits(pcie->reg_syscon,
288 			   pcie->stg_pcie_base + STG_SYSCON_RP_NEP_OFFSET,
289 			   STG_SYSCON_K_RP_NEP, STG_SYSCON_K_RP_NEP);
290 
291 	regmap_update_bits(pcie->reg_syscon,
292 			   pcie->stg_pcie_base + STG_SYSCON_AW_OFFSET,
293 			   STG_SYSCON_CKREF_SRC_MASK,
294 			   FIELD_PREP(STG_SYSCON_CKREF_SRC_MASK, 2));
295 
296 	regmap_update_bits(pcie->reg_syscon,
297 			   pcie->stg_pcie_base + STG_SYSCON_AW_OFFSET,
298 			   STG_SYSCON_CLKREQ, STG_SYSCON_CLKREQ);
299 
300 	ret = starfive_pcie_clk_rst_init(pcie);
301 	if (ret)
302 		goto err_disable_phy;
303 
304 	if (pcie->vpcie3v3) {
305 		ret = regulator_enable(pcie->vpcie3v3);
306 		if (ret) {
307 			dev_err_probe(dev, ret, "failed to enable vpcie3v3 regulator\n");
308 			goto err_clk_rst;
309 		}
310 	}
311 
312 	if (pcie->reset_gpio)
313 		gpiod_set_value_cansleep(pcie->reset_gpio, 1);
314 
315 	/* Disable physical functions except #0 */
316 	for (i = 1; i < PCIE_FUNC_NUM; i++) {
317 		regmap_update_bits(pcie->reg_syscon,
318 				   pcie->stg_pcie_base + STG_SYSCON_AR_OFFSET,
319 				   STG_SYSCON_AXI4_SLVL_AR_MASK,
320 				   STG_SYSCON_AXI4_SLVL_PHY_AR(i));
321 
322 		regmap_update_bits(pcie->reg_syscon,
323 				   pcie->stg_pcie_base + STG_SYSCON_AW_OFFSET,
324 				   STG_SYSCON_AXI4_SLVL_AW_MASK,
325 				   STG_SYSCON_AXI4_SLVL_PHY_AW(i));
326 
327 		plda_pcie_disable_func(plda);
328 	}
329 
330 	regmap_update_bits(pcie->reg_syscon,
331 			   pcie->stg_pcie_base + STG_SYSCON_AR_OFFSET,
332 			   STG_SYSCON_AXI4_SLVL_AR_MASK, 0);
333 	regmap_update_bits(pcie->reg_syscon,
334 			   pcie->stg_pcie_base + STG_SYSCON_AW_OFFSET,
335 			   STG_SYSCON_AXI4_SLVL_AW_MASK, 0);
336 
337 	plda_pcie_enable_root_port(plda);
338 	plda_pcie_write_rc_bar(plda, 0);
339 
340 	/* PCIe PCI Standard Configuration Identification Settings. */
341 	plda_pcie_set_standard_class(plda);
342 
343 	/*
344 	 * The LTR message receiving is enabled by the register "PCIe Message
345 	 * Reception" as default, but the forward id & addr are uninitialized.
346 	 * If we do not disable LTR message forwarding here, or set a legal
347 	 * forwarding address, the kernel will get stuck.
348 	 * To workaround, disable the LTR message forwarding here before using
349 	 * this feature.
350 	 */
351 	plda_pcie_disable_ltr(plda);
352 
353 	/*
354 	 * Enable the prefetchable memory window 64-bit addressing in JH7110.
355 	 * The 64-bits prefetchable address translation configurations in ATU
356 	 * can be work after enable the register setting below.
357 	 */
358 	plda_pcie_set_pref_win_64bit(plda);
359 
360 	/*
361 	 * Ensure that PERST has been asserted for at least 100 ms,
362 	 * the sleep value is T_PVPERL from PCIe CEM spec r2.0 (Table 2-4)
363 	 */
364 	msleep(100);
365 	if (pcie->reset_gpio)
366 		gpiod_set_value_cansleep(pcie->reset_gpio, 0);
367 
368 	/*
369 	 * With a Downstream Port (<=5GT/s), software must wait a minimum
370 	 * of 100ms following exit from a conventional reset before
371 	 * sending a configuration request to the device.
372 	 */
373 	msleep(PCIE_RESET_CONFIG_WAIT_MS);
374 
375 	if (starfive_pcie_host_wait_for_link(pcie))
376 		dev_info(dev, "port link down\n");
377 
378 	return 0;
379 
380 err_clk_rst:
381 	starfive_pcie_clk_rst_deinit(pcie);
382 err_disable_phy:
383 	starfive_pcie_disable_phy(pcie);
384 
385 	return ret;
386 }
387 
388 static const struct plda_pcie_host_ops sf_host_ops = {
389 	.host_init = starfive_pcie_host_init,
390 	.host_deinit = starfive_pcie_host_deinit,
391 };
392 
393 static const struct plda_event stf_pcie_event = {
394 	.intx_event = EVENT_PM_MSI_INT_INTX,
395 	.msi_event  = EVENT_PM_MSI_INT_MSI
396 };
397 
398 static int starfive_pcie_probe(struct platform_device *pdev)
399 {
400 	struct starfive_jh7110_pcie *pcie;
401 	struct device *dev = &pdev->dev;
402 	struct plda_pcie_rp *plda;
403 	int ret;
404 
405 	pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
406 	if (!pcie)
407 		return -ENOMEM;
408 
409 	plda = &pcie->plda;
410 	plda->dev = dev;
411 
412 	ret = starfive_pcie_parse_dt(pcie, dev);
413 	if (ret)
414 		return ret;
415 
416 	pm_runtime_enable(&pdev->dev);
417 	ret = pm_runtime_resume_and_get(&pdev->dev);
418 	if (ret < 0) {
419 		pm_runtime_disable(&pdev->dev);
420 		return dev_err_probe(dev, ret, "failed to resume device\n");
421 	}
422 
423 	plda->host_ops = &sf_host_ops;
424 	plda->num_events = PLDA_MAX_EVENT_NUM;
425 	/* mask doorbell event */
426 	plda->events_bitmap = GENMASK(PLDA_INT_EVENT_NUM - 1, 0)
427 			     & ~BIT(PLDA_AXI_DOORBELL)
428 			     & ~BIT(PLDA_PCIE_DOORBELL);
429 	plda->events_bitmap <<= PLDA_NUM_DMA_EVENTS;
430 	ret = plda_pcie_host_init(&pcie->plda, &starfive_pcie_ops,
431 				  &stf_pcie_event);
432 	if (ret) {
433 		pm_runtime_put_sync(&pdev->dev);
434 		pm_runtime_disable(&pdev->dev);
435 		return ret;
436 	}
437 
438 	platform_set_drvdata(pdev, pcie);
439 
440 	return 0;
441 }
442 
443 static void starfive_pcie_remove(struct platform_device *pdev)
444 {
445 	struct starfive_jh7110_pcie *pcie = platform_get_drvdata(pdev);
446 
447 	plda_pcie_host_deinit(&pcie->plda);
448 	pm_runtime_put_sync(&pdev->dev);
449 	pm_runtime_disable(&pdev->dev);
450 	platform_set_drvdata(pdev, NULL);
451 }
452 
453 static int starfive_pcie_suspend_noirq(struct device *dev)
454 {
455 	struct starfive_jh7110_pcie *pcie = dev_get_drvdata(dev);
456 
457 	clk_bulk_disable_unprepare(pcie->num_clks, pcie->clks);
458 	starfive_pcie_disable_phy(pcie);
459 
460 	return 0;
461 }
462 
463 static int starfive_pcie_resume_noirq(struct device *dev)
464 {
465 	struct starfive_jh7110_pcie *pcie = dev_get_drvdata(dev);
466 	int ret;
467 
468 	ret = starfive_pcie_enable_phy(dev, pcie);
469 	if (ret)
470 		return ret;
471 
472 	ret = clk_bulk_prepare_enable(pcie->num_clks, pcie->clks);
473 	if (ret) {
474 		dev_err(dev, "failed to enable clocks\n");
475 		starfive_pcie_disable_phy(pcie);
476 		return ret;
477 	}
478 
479 	return 0;
480 }
481 
482 static const struct dev_pm_ops starfive_pcie_pm_ops = {
483 	NOIRQ_SYSTEM_SLEEP_PM_OPS(starfive_pcie_suspend_noirq,
484 				  starfive_pcie_resume_noirq)
485 };
486 
487 static const struct of_device_id starfive_pcie_of_match[] = {
488 	{ .compatible = "starfive,jh7110-pcie", },
489 	{ /* sentinel */ }
490 };
491 MODULE_DEVICE_TABLE(of, starfive_pcie_of_match);
492 
493 static struct platform_driver starfive_pcie_driver = {
494 	.driver = {
495 		.name = "pcie-starfive",
496 		.of_match_table = of_match_ptr(starfive_pcie_of_match),
497 		.pm = pm_sleep_ptr(&starfive_pcie_pm_ops),
498 	},
499 	.probe = starfive_pcie_probe,
500 	.remove = starfive_pcie_remove,
501 };
502 module_platform_driver(starfive_pcie_driver);
503 
504 MODULE_DESCRIPTION("StarFive JH7110 PCIe host driver");
505 MODULE_LICENSE("GPL v2");
506