1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * PLDA PCIe host controller driver 4 */ 5 6 #ifndef _PCIE_PLDA_H 7 #define _PCIE_PLDA_H 8 9 /* Number of MSI IRQs */ 10 #define PLDA_MAX_NUM_MSI_IRQS 32 11 12 /* PCIe Bridge Phy Regs */ 13 #define GEN_SETTINGS 0x80 14 #define RP_ENABLE 1 15 #define PCIE_PCI_IDS_DW1 0x9c 16 #define IDS_CLASS_CODE_SHIFT 16 17 #define REVISION_ID_MASK GENMASK(7, 0) 18 #define CLASS_CODE_ID_MASK GENMASK(31, 8) 19 #define PCIE_PCI_IRQ_DW0 0xa8 20 #define MSIX_CAP_MASK BIT(31) 21 #define NUM_MSI_MSGS_MASK GENMASK(6, 4) 22 #define NUM_MSI_MSGS_SHIFT 4 23 #define PCI_MISC 0xb4 24 #define PHY_FUNCTION_DIS BIT(15) 25 #define PCIE_WINROM 0xfc 26 #define PREF_MEM_WIN_64_SUPPORT BIT(3) 27 28 #define IMASK_LOCAL 0x180 29 #define DMA_END_ENGINE_0_MASK 0x00000000u 30 #define DMA_END_ENGINE_0_SHIFT 0 31 #define DMA_END_ENGINE_1_MASK 0x00000000u 32 #define DMA_END_ENGINE_1_SHIFT 1 33 #define DMA_ERROR_ENGINE_0_MASK 0x00000100u 34 #define DMA_ERROR_ENGINE_0_SHIFT 8 35 #define DMA_ERROR_ENGINE_1_MASK 0x00000200u 36 #define DMA_ERROR_ENGINE_1_SHIFT 9 37 #define A_ATR_EVT_POST_ERR_MASK 0x00010000u 38 #define A_ATR_EVT_POST_ERR_SHIFT 16 39 #define A_ATR_EVT_FETCH_ERR_MASK 0x00020000u 40 #define A_ATR_EVT_FETCH_ERR_SHIFT 17 41 #define A_ATR_EVT_DISCARD_ERR_MASK 0x00040000u 42 #define A_ATR_EVT_DISCARD_ERR_SHIFT 18 43 #define A_ATR_EVT_DOORBELL_MASK 0x00000000u 44 #define A_ATR_EVT_DOORBELL_SHIFT 19 45 #define P_ATR_EVT_POST_ERR_MASK 0x00100000u 46 #define P_ATR_EVT_POST_ERR_SHIFT 20 47 #define P_ATR_EVT_FETCH_ERR_MASK 0x00200000u 48 #define P_ATR_EVT_FETCH_ERR_SHIFT 21 49 #define P_ATR_EVT_DISCARD_ERR_MASK 0x00400000u 50 #define P_ATR_EVT_DISCARD_ERR_SHIFT 22 51 #define P_ATR_EVT_DOORBELL_MASK 0x00000000u 52 #define P_ATR_EVT_DOORBELL_SHIFT 23 53 #define PM_MSI_INT_INTA_MASK 0x01000000u 54 #define PM_MSI_INT_INTA_SHIFT 24 55 #define PM_MSI_INT_INTB_MASK 0x02000000u 56 #define PM_MSI_INT_INTB_SHIFT 25 57 #define PM_MSI_INT_INTC_MASK 0x04000000u 58 #define PM_MSI_INT_INTC_SHIFT 26 59 #define PM_MSI_INT_INTD_MASK 0x08000000u 60 #define PM_MSI_INT_INTD_SHIFT 27 61 #define PM_MSI_INT_INTX_MASK 0x0f000000u 62 #define PM_MSI_INT_INTX_SHIFT 24 63 #define PM_MSI_INT_MSI_MASK 0x10000000u 64 #define PM_MSI_INT_MSI_SHIFT 28 65 #define PM_MSI_INT_AER_EVT_MASK 0x20000000u 66 #define PM_MSI_INT_AER_EVT_SHIFT 29 67 #define PM_MSI_INT_EVENTS_MASK 0x40000000u 68 #define PM_MSI_INT_EVENTS_SHIFT 30 69 #define PM_MSI_INT_SYS_ERR_MASK 0x80000000u 70 #define PM_MSI_INT_SYS_ERR_SHIFT 31 71 #define SYS_AND_MSI_MASK GENMASK(31, 28) 72 #define NUM_LOCAL_EVENTS 15 73 #define ISTATUS_LOCAL 0x184 74 #define IMASK_HOST 0x188 75 #define ISTATUS_HOST 0x18c 76 #define IMSI_ADDR 0x190 77 #define ISTATUS_MSI 0x194 78 #define PMSG_SUPPORT_RX 0x3f0 79 #define PMSG_LTR_SUPPORT BIT(2) 80 81 /* PCIe Master table init defines */ 82 #define ATR0_PCIE_WIN0_SRCADDR_PARAM 0x600u 83 #define ATR0_PCIE_ATR_SIZE 0x25 84 #define ATR0_PCIE_ATR_SIZE_SHIFT 1 85 #define ATR0_PCIE_WIN0_SRC_ADDR 0x604u 86 #define ATR0_PCIE_WIN0_TRSL_ADDR_LSB 0x608u 87 #define ATR0_PCIE_WIN0_TRSL_ADDR_UDW 0x60cu 88 #define ATR0_PCIE_WIN0_TRSL_PARAM 0x610u 89 90 /* PCIe AXI slave table init defines */ 91 #define ATR0_AXI4_SLV0_SRCADDR_PARAM 0x800u 92 #define ATR_SIZE_SHIFT 1 93 #define ATR_IMPL_ENABLE 1 94 #define ATR0_AXI4_SLV0_SRC_ADDR 0x804u 95 #define ATR0_AXI4_SLV0_TRSL_ADDR_LSB 0x808u 96 #define ATR0_AXI4_SLV0_TRSL_ADDR_UDW 0x80cu 97 #define ATR0_AXI4_SLV0_TRSL_PARAM 0x810u 98 #define PCIE_TX_RX_INTERFACE 0x00000000u 99 #define PCIE_CONFIG_INTERFACE 0x00000001u 100 101 #define CONFIG_SPACE_ADDR_OFFSET 0x1000u 102 103 #define ATR_ENTRY_SIZE 32 104 105 enum plda_int_event { 106 PLDA_AXI_POST_ERR, 107 PLDA_AXI_FETCH_ERR, 108 PLDA_AXI_DISCARD_ERR, 109 PLDA_AXI_DOORBELL, 110 PLDA_PCIE_POST_ERR, 111 PLDA_PCIE_FETCH_ERR, 112 PLDA_PCIE_DISCARD_ERR, 113 PLDA_PCIE_DOORBELL, 114 PLDA_INTX, 115 PLDA_MSI, 116 PLDA_AER_EVENT, 117 PLDA_MISC_EVENTS, 118 PLDA_SYS_ERR, 119 PLDA_INT_EVENT_NUM 120 }; 121 122 #define PLDA_NUM_DMA_EVENTS 16 123 124 #define EVENT_PM_MSI_INT_INTX (PLDA_NUM_DMA_EVENTS + PLDA_INTX) 125 #define EVENT_PM_MSI_INT_MSI (PLDA_NUM_DMA_EVENTS + PLDA_MSI) 126 #define PLDA_MAX_EVENT_NUM (PLDA_NUM_DMA_EVENTS + PLDA_INT_EVENT_NUM) 127 128 /* 129 * PLDA interrupt register 130 * 131 * 31 27 23 15 7 0 132 * +--+--+--+-+------+-+-+-+-+-+-+-+-+-----------+-----------+ 133 * |12|11|10|9| intx |7|6|5|4|3|2|1|0| DMA error | DMA end | 134 * +--+--+--+-+------+-+-+-+-+-+-+-+-+-----------+-----------+ 135 * event bit 136 * 0-7 (0-7) DMA interrupt end : reserved for vendor implement 137 * 8-15 (8-15) DMA error : reserved for vendor implement 138 * 16 (16) AXI post error (PLDA_AXI_POST_ERR) 139 * 17 (17) AXI fetch error (PLDA_AXI_FETCH_ERR) 140 * 18 (18) AXI discard error (PLDA_AXI_DISCARD_ERR) 141 * 19 (19) AXI doorbell (PLDA_PCIE_DOORBELL) 142 * 20 (20) PCIe post error (PLDA_PCIE_POST_ERR) 143 * 21 (21) PCIe fetch error (PLDA_PCIE_FETCH_ERR) 144 * 22 (22) PCIe discard error (PLDA_PCIE_DISCARD_ERR) 145 * 23 (23) PCIe doorbell (PLDA_PCIE_DOORBELL) 146 * 24 (27-24) INTx interruts (PLDA_INTX) 147 * 25 (28): MSI interrupt (PLDA_MSI) 148 * 26 (29): AER event (PLDA_AER_EVENT) 149 * 27 (30): PM/LTR/Hotplug (PLDA_MISC_EVENTS) 150 * 28 (31): System error (PLDA_SYS_ERR) 151 */ 152 153 struct plda_pcie_rp; 154 155 struct plda_event_ops { 156 u32 (*get_events)(struct plda_pcie_rp *pcie); 157 }; 158 159 struct plda_pcie_host_ops { 160 int (*host_init)(struct plda_pcie_rp *pcie); 161 void (*host_deinit)(struct plda_pcie_rp *pcie); 162 }; 163 164 struct plda_msi { 165 struct mutex lock; /* Protect used bitmap */ 166 struct irq_domain *msi_domain; 167 struct irq_domain *dev_domain; 168 u32 num_vectors; 169 u64 vector_phy; 170 DECLARE_BITMAP(used, PLDA_MAX_NUM_MSI_IRQS); 171 }; 172 173 struct plda_pcie_rp { 174 struct device *dev; 175 struct pci_host_bridge *bridge; 176 struct irq_domain *intx_domain; 177 struct irq_domain *event_domain; 178 raw_spinlock_t lock; 179 struct plda_msi msi; 180 const struct plda_event_ops *event_ops; 181 const struct irq_chip *event_irq_chip; 182 const struct plda_pcie_host_ops *host_ops; 183 void __iomem *bridge_addr; 184 void __iomem *config_base; 185 unsigned long events_bitmap; 186 int irq; 187 int msi_irq; 188 int intx_irq; 189 int num_events; 190 }; 191 192 struct plda_event { 193 int (*request_event_irq)(struct plda_pcie_rp *pcie, 194 int event_irq, int event); 195 int intx_event; 196 int msi_event; 197 }; 198 199 void __iomem *plda_pcie_map_bus(struct pci_bus *bus, unsigned int devfn, 200 int where); 201 int plda_init_interrupts(struct platform_device *pdev, 202 struct plda_pcie_rp *port, 203 const struct plda_event *event); 204 void plda_pcie_setup_window(void __iomem *bridge_base_addr, u32 index, 205 phys_addr_t axi_addr, phys_addr_t pci_addr, 206 size_t size); 207 int plda_pcie_setup_iomems(struct pci_host_bridge *bridge, 208 struct plda_pcie_rp *port); 209 int plda_pcie_host_init(struct plda_pcie_rp *port, struct pci_ops *ops, 210 const struct plda_event *plda_event); 211 void plda_pcie_host_deinit(struct plda_pcie_rp *pcie); 212 213 static inline void plda_set_default_msi(struct plda_msi *msi) 214 { 215 msi->vector_phy = IMSI_ADDR; 216 msi->num_vectors = PLDA_MAX_NUM_MSI_IRQS; 217 } 218 219 static inline void plda_pcie_enable_root_port(struct plda_pcie_rp *plda) 220 { 221 u32 value; 222 223 value = readl_relaxed(plda->bridge_addr + GEN_SETTINGS); 224 value |= RP_ENABLE; 225 writel_relaxed(value, plda->bridge_addr + GEN_SETTINGS); 226 } 227 228 static inline void plda_pcie_set_standard_class(struct plda_pcie_rp *plda) 229 { 230 u32 value; 231 232 /* set class code and reserve revision id */ 233 value = readl_relaxed(plda->bridge_addr + PCIE_PCI_IDS_DW1); 234 value &= REVISION_ID_MASK; 235 value |= (PCI_CLASS_BRIDGE_PCI << IDS_CLASS_CODE_SHIFT); 236 writel_relaxed(value, plda->bridge_addr + PCIE_PCI_IDS_DW1); 237 } 238 239 static inline void plda_pcie_set_pref_win_64bit(struct plda_pcie_rp *plda) 240 { 241 u32 value; 242 243 value = readl_relaxed(plda->bridge_addr + PCIE_WINROM); 244 value |= PREF_MEM_WIN_64_SUPPORT; 245 writel_relaxed(value, plda->bridge_addr + PCIE_WINROM); 246 } 247 248 static inline void plda_pcie_disable_ltr(struct plda_pcie_rp *plda) 249 { 250 u32 value; 251 252 value = readl_relaxed(plda->bridge_addr + PMSG_SUPPORT_RX); 253 value &= ~PMSG_LTR_SUPPORT; 254 writel_relaxed(value, plda->bridge_addr + PMSG_SUPPORT_RX); 255 } 256 257 static inline void plda_pcie_disable_func(struct plda_pcie_rp *plda) 258 { 259 u32 value; 260 261 value = readl_relaxed(plda->bridge_addr + PCI_MISC); 262 value |= PHY_FUNCTION_DIS; 263 writel_relaxed(value, plda->bridge_addr + PCI_MISC); 264 } 265 266 static inline void plda_pcie_write_rc_bar(struct plda_pcie_rp *plda, u64 val) 267 { 268 void __iomem *addr = plda->bridge_addr + CONFIG_SPACE_ADDR_OFFSET; 269 270 writel_relaxed(lower_32_bits(val), addr + PCI_BASE_ADDRESS_0); 271 writel_relaxed(upper_32_bits(val), addr + PCI_BASE_ADDRESS_1); 272 } 273 #endif /* _PCIE_PLDA_H */ 274