1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Microchip AXI PCIe Bridge host controller driver 4 * 5 * Copyright (c) 2018 - 2020 Microchip Corporation. All rights reserved. 6 * 7 * Author: Daire McNamara <daire.mcnamara@microchip.com> 8 */ 9 10 #include <linux/bitfield.h> 11 #include <linux/clk.h> 12 #include <linux/irqchip/chained_irq.h> 13 #include <linux/irqdomain.h> 14 #include <linux/module.h> 15 #include <linux/msi.h> 16 #include <linux/of_address.h> 17 #include <linux/of_pci.h> 18 #include <linux/pci-ecam.h> 19 #include <linux/platform_device.h> 20 21 #include "../../pci.h" 22 #include "pcie-plda.h" 23 24 /* PCIe Bridge Phy and Controller Phy offsets */ 25 #define MC_PCIE1_BRIDGE_ADDR 0x00008000u 26 #define MC_PCIE1_CTRL_ADDR 0x0000a000u 27 28 /* PCIe Controller Phy Regs */ 29 #define SEC_ERROR_EVENT_CNT 0x20 30 #define DED_ERROR_EVENT_CNT 0x24 31 #define SEC_ERROR_INT 0x28 32 #define SEC_ERROR_INT_TX_RAM_SEC_ERR_INT GENMASK(3, 0) 33 #define SEC_ERROR_INT_RX_RAM_SEC_ERR_INT GENMASK(7, 4) 34 #define SEC_ERROR_INT_PCIE2AXI_RAM_SEC_ERR_INT GENMASK(11, 8) 35 #define SEC_ERROR_INT_AXI2PCIE_RAM_SEC_ERR_INT GENMASK(15, 12) 36 #define SEC_ERROR_INT_ALL_RAM_SEC_ERR_INT GENMASK(15, 0) 37 #define NUM_SEC_ERROR_INTS (4) 38 #define SEC_ERROR_INT_MASK 0x2c 39 #define DED_ERROR_INT 0x30 40 #define DED_ERROR_INT_TX_RAM_DED_ERR_INT GENMASK(3, 0) 41 #define DED_ERROR_INT_RX_RAM_DED_ERR_INT GENMASK(7, 4) 42 #define DED_ERROR_INT_PCIE2AXI_RAM_DED_ERR_INT GENMASK(11, 8) 43 #define DED_ERROR_INT_AXI2PCIE_RAM_DED_ERR_INT GENMASK(15, 12) 44 #define DED_ERROR_INT_ALL_RAM_DED_ERR_INT GENMASK(15, 0) 45 #define NUM_DED_ERROR_INTS (4) 46 #define DED_ERROR_INT_MASK 0x34 47 #define ECC_CONTROL 0x38 48 #define ECC_CONTROL_TX_RAM_INJ_ERROR_0 BIT(0) 49 #define ECC_CONTROL_TX_RAM_INJ_ERROR_1 BIT(1) 50 #define ECC_CONTROL_TX_RAM_INJ_ERROR_2 BIT(2) 51 #define ECC_CONTROL_TX_RAM_INJ_ERROR_3 BIT(3) 52 #define ECC_CONTROL_RX_RAM_INJ_ERROR_0 BIT(4) 53 #define ECC_CONTROL_RX_RAM_INJ_ERROR_1 BIT(5) 54 #define ECC_CONTROL_RX_RAM_INJ_ERROR_2 BIT(6) 55 #define ECC_CONTROL_RX_RAM_INJ_ERROR_3 BIT(7) 56 #define ECC_CONTROL_PCIE2AXI_RAM_INJ_ERROR_0 BIT(8) 57 #define ECC_CONTROL_PCIE2AXI_RAM_INJ_ERROR_1 BIT(9) 58 #define ECC_CONTROL_PCIE2AXI_RAM_INJ_ERROR_2 BIT(10) 59 #define ECC_CONTROL_PCIE2AXI_RAM_INJ_ERROR_3 BIT(11) 60 #define ECC_CONTROL_AXI2PCIE_RAM_INJ_ERROR_0 BIT(12) 61 #define ECC_CONTROL_AXI2PCIE_RAM_INJ_ERROR_1 BIT(13) 62 #define ECC_CONTROL_AXI2PCIE_RAM_INJ_ERROR_2 BIT(14) 63 #define ECC_CONTROL_AXI2PCIE_RAM_INJ_ERROR_3 BIT(15) 64 #define ECC_CONTROL_TX_RAM_ECC_BYPASS BIT(24) 65 #define ECC_CONTROL_RX_RAM_ECC_BYPASS BIT(25) 66 #define ECC_CONTROL_PCIE2AXI_RAM_ECC_BYPASS BIT(26) 67 #define ECC_CONTROL_AXI2PCIE_RAM_ECC_BYPASS BIT(27) 68 #define PCIE_EVENT_INT 0x14c 69 #define PCIE_EVENT_INT_L2_EXIT_INT BIT(0) 70 #define PCIE_EVENT_INT_HOTRST_EXIT_INT BIT(1) 71 #define PCIE_EVENT_INT_DLUP_EXIT_INT BIT(2) 72 #define PCIE_EVENT_INT_MASK GENMASK(2, 0) 73 #define PCIE_EVENT_INT_L2_EXIT_INT_MASK BIT(16) 74 #define PCIE_EVENT_INT_HOTRST_EXIT_INT_MASK BIT(17) 75 #define PCIE_EVENT_INT_DLUP_EXIT_INT_MASK BIT(18) 76 #define PCIE_EVENT_INT_ENB_MASK GENMASK(18, 16) 77 #define PCIE_EVENT_INT_ENB_SHIFT 16 78 #define NUM_PCIE_EVENTS (3) 79 80 /* PCIe Config space MSI capability structure */ 81 #define MC_MSI_CAP_CTRL_OFFSET 0xe0u 82 83 /* Events */ 84 #define EVENT_PCIE_L2_EXIT 0 85 #define EVENT_PCIE_HOTRST_EXIT 1 86 #define EVENT_PCIE_DLUP_EXIT 2 87 #define EVENT_SEC_TX_RAM_SEC_ERR 3 88 #define EVENT_SEC_RX_RAM_SEC_ERR 4 89 #define EVENT_SEC_PCIE2AXI_RAM_SEC_ERR 5 90 #define EVENT_SEC_AXI2PCIE_RAM_SEC_ERR 6 91 #define EVENT_DED_TX_RAM_DED_ERR 7 92 #define EVENT_DED_RX_RAM_DED_ERR 8 93 #define EVENT_DED_PCIE2AXI_RAM_DED_ERR 9 94 #define EVENT_DED_AXI2PCIE_RAM_DED_ERR 10 95 #define EVENT_LOCAL_DMA_END_ENGINE_0 11 96 #define EVENT_LOCAL_DMA_END_ENGINE_1 12 97 #define EVENT_LOCAL_DMA_ERROR_ENGINE_0 13 98 #define EVENT_LOCAL_DMA_ERROR_ENGINE_1 14 99 #define NUM_MC_EVENTS 15 100 #define EVENT_LOCAL_A_ATR_EVT_POST_ERR (NUM_MC_EVENTS + PLDA_AXI_POST_ERR) 101 #define EVENT_LOCAL_A_ATR_EVT_FETCH_ERR (NUM_MC_EVENTS + PLDA_AXI_FETCH_ERR) 102 #define EVENT_LOCAL_A_ATR_EVT_DISCARD_ERR (NUM_MC_EVENTS + PLDA_AXI_DISCARD_ERR) 103 #define EVENT_LOCAL_A_ATR_EVT_DOORBELL (NUM_MC_EVENTS + PLDA_AXI_DOORBELL) 104 #define EVENT_LOCAL_P_ATR_EVT_POST_ERR (NUM_MC_EVENTS + PLDA_PCIE_POST_ERR) 105 #define EVENT_LOCAL_P_ATR_EVT_FETCH_ERR (NUM_MC_EVENTS + PLDA_PCIE_FETCH_ERR) 106 #define EVENT_LOCAL_P_ATR_EVT_DISCARD_ERR (NUM_MC_EVENTS + PLDA_PCIE_DISCARD_ERR) 107 #define EVENT_LOCAL_P_ATR_EVT_DOORBELL (NUM_MC_EVENTS + PLDA_PCIE_DOORBELL) 108 #define EVENT_LOCAL_PM_MSI_INT_INTX (NUM_MC_EVENTS + PLDA_INTX) 109 #define EVENT_LOCAL_PM_MSI_INT_MSI (NUM_MC_EVENTS + PLDA_MSI) 110 #define EVENT_LOCAL_PM_MSI_INT_AER_EVT (NUM_MC_EVENTS + PLDA_AER_EVENT) 111 #define EVENT_LOCAL_PM_MSI_INT_EVENTS (NUM_MC_EVENTS + PLDA_MISC_EVENTS) 112 #define EVENT_LOCAL_PM_MSI_INT_SYS_ERR (NUM_MC_EVENTS + PLDA_SYS_ERR) 113 #define NUM_EVENTS (NUM_MC_EVENTS + PLDA_INT_EVENT_NUM) 114 115 #define PCIE_EVENT_CAUSE(x, s) \ 116 [EVENT_PCIE_ ## x] = { __stringify(x), s } 117 118 #define SEC_ERROR_CAUSE(x, s) \ 119 [EVENT_SEC_ ## x] = { __stringify(x), s } 120 121 #define DED_ERROR_CAUSE(x, s) \ 122 [EVENT_DED_ ## x] = { __stringify(x), s } 123 124 #define LOCAL_EVENT_CAUSE(x, s) \ 125 [EVENT_LOCAL_ ## x] = { __stringify(x), s } 126 127 #define PCIE_EVENT(x) \ 128 .offset = PCIE_EVENT_INT, \ 129 .mask_offset = PCIE_EVENT_INT, \ 130 .mask_high = 1, \ 131 .mask = PCIE_EVENT_INT_ ## x ## _INT, \ 132 .enb_mask = PCIE_EVENT_INT_ENB_MASK 133 134 #define SEC_EVENT(x) \ 135 .offset = SEC_ERROR_INT, \ 136 .mask_offset = SEC_ERROR_INT_MASK, \ 137 .mask = SEC_ERROR_INT_ ## x ## _INT, \ 138 .mask_high = 1, \ 139 .enb_mask = 0 140 141 #define DED_EVENT(x) \ 142 .offset = DED_ERROR_INT, \ 143 .mask_offset = DED_ERROR_INT_MASK, \ 144 .mask_high = 1, \ 145 .mask = DED_ERROR_INT_ ## x ## _INT, \ 146 .enb_mask = 0 147 148 #define LOCAL_EVENT(x) \ 149 .offset = ISTATUS_LOCAL, \ 150 .mask_offset = IMASK_LOCAL, \ 151 .mask_high = 0, \ 152 .mask = x ## _MASK, \ 153 .enb_mask = 0 154 155 #define PCIE_EVENT_TO_EVENT_MAP(x) \ 156 { PCIE_EVENT_INT_ ## x ## _INT, EVENT_PCIE_ ## x } 157 158 #define SEC_ERROR_TO_EVENT_MAP(x) \ 159 { SEC_ERROR_INT_ ## x ## _INT, EVENT_SEC_ ## x } 160 161 #define DED_ERROR_TO_EVENT_MAP(x) \ 162 { DED_ERROR_INT_ ## x ## _INT, EVENT_DED_ ## x } 163 164 #define LOCAL_STATUS_TO_EVENT_MAP(x) \ 165 { x ## _MASK, EVENT_LOCAL_ ## x } 166 167 struct event_map { 168 u32 reg_mask; 169 u32 event_bit; 170 }; 171 172 173 struct mc_pcie { 174 struct plda_pcie_rp plda; 175 void __iomem *bridge_base_addr; 176 void __iomem *ctrl_base_addr; 177 }; 178 179 struct cause { 180 const char *sym; 181 const char *str; 182 }; 183 184 static const struct cause event_cause[NUM_EVENTS] = { 185 PCIE_EVENT_CAUSE(L2_EXIT, "L2 exit event"), 186 PCIE_EVENT_CAUSE(HOTRST_EXIT, "Hot reset exit event"), 187 PCIE_EVENT_CAUSE(DLUP_EXIT, "DLUP exit event"), 188 SEC_ERROR_CAUSE(TX_RAM_SEC_ERR, "sec error in tx buffer"), 189 SEC_ERROR_CAUSE(RX_RAM_SEC_ERR, "sec error in rx buffer"), 190 SEC_ERROR_CAUSE(PCIE2AXI_RAM_SEC_ERR, "sec error in pcie2axi buffer"), 191 SEC_ERROR_CAUSE(AXI2PCIE_RAM_SEC_ERR, "sec error in axi2pcie buffer"), 192 DED_ERROR_CAUSE(TX_RAM_DED_ERR, "ded error in tx buffer"), 193 DED_ERROR_CAUSE(RX_RAM_DED_ERR, "ded error in rx buffer"), 194 DED_ERROR_CAUSE(PCIE2AXI_RAM_DED_ERR, "ded error in pcie2axi buffer"), 195 DED_ERROR_CAUSE(AXI2PCIE_RAM_DED_ERR, "ded error in axi2pcie buffer"), 196 LOCAL_EVENT_CAUSE(DMA_ERROR_ENGINE_0, "dma engine 0 error"), 197 LOCAL_EVENT_CAUSE(DMA_ERROR_ENGINE_1, "dma engine 1 error"), 198 LOCAL_EVENT_CAUSE(A_ATR_EVT_POST_ERR, "axi write request error"), 199 LOCAL_EVENT_CAUSE(A_ATR_EVT_FETCH_ERR, "axi read request error"), 200 LOCAL_EVENT_CAUSE(A_ATR_EVT_DISCARD_ERR, "axi read timeout"), 201 LOCAL_EVENT_CAUSE(P_ATR_EVT_POST_ERR, "pcie write request error"), 202 LOCAL_EVENT_CAUSE(P_ATR_EVT_FETCH_ERR, "pcie read request error"), 203 LOCAL_EVENT_CAUSE(P_ATR_EVT_DISCARD_ERR, "pcie read timeout"), 204 LOCAL_EVENT_CAUSE(PM_MSI_INT_AER_EVT, "aer event"), 205 LOCAL_EVENT_CAUSE(PM_MSI_INT_EVENTS, "pm/ltr/hotplug event"), 206 LOCAL_EVENT_CAUSE(PM_MSI_INT_SYS_ERR, "system error"), 207 }; 208 209 static struct event_map pcie_event_to_event[] = { 210 PCIE_EVENT_TO_EVENT_MAP(L2_EXIT), 211 PCIE_EVENT_TO_EVENT_MAP(HOTRST_EXIT), 212 PCIE_EVENT_TO_EVENT_MAP(DLUP_EXIT), 213 }; 214 215 static struct event_map sec_error_to_event[] = { 216 SEC_ERROR_TO_EVENT_MAP(TX_RAM_SEC_ERR), 217 SEC_ERROR_TO_EVENT_MAP(RX_RAM_SEC_ERR), 218 SEC_ERROR_TO_EVENT_MAP(PCIE2AXI_RAM_SEC_ERR), 219 SEC_ERROR_TO_EVENT_MAP(AXI2PCIE_RAM_SEC_ERR), 220 }; 221 222 static struct event_map ded_error_to_event[] = { 223 DED_ERROR_TO_EVENT_MAP(TX_RAM_DED_ERR), 224 DED_ERROR_TO_EVENT_MAP(RX_RAM_DED_ERR), 225 DED_ERROR_TO_EVENT_MAP(PCIE2AXI_RAM_DED_ERR), 226 DED_ERROR_TO_EVENT_MAP(AXI2PCIE_RAM_DED_ERR), 227 }; 228 229 static struct event_map local_status_to_event[] = { 230 LOCAL_STATUS_TO_EVENT_MAP(DMA_END_ENGINE_0), 231 LOCAL_STATUS_TO_EVENT_MAP(DMA_END_ENGINE_1), 232 LOCAL_STATUS_TO_EVENT_MAP(DMA_ERROR_ENGINE_0), 233 LOCAL_STATUS_TO_EVENT_MAP(DMA_ERROR_ENGINE_1), 234 LOCAL_STATUS_TO_EVENT_MAP(A_ATR_EVT_POST_ERR), 235 LOCAL_STATUS_TO_EVENT_MAP(A_ATR_EVT_FETCH_ERR), 236 LOCAL_STATUS_TO_EVENT_MAP(A_ATR_EVT_DISCARD_ERR), 237 LOCAL_STATUS_TO_EVENT_MAP(A_ATR_EVT_DOORBELL), 238 LOCAL_STATUS_TO_EVENT_MAP(P_ATR_EVT_POST_ERR), 239 LOCAL_STATUS_TO_EVENT_MAP(P_ATR_EVT_FETCH_ERR), 240 LOCAL_STATUS_TO_EVENT_MAP(P_ATR_EVT_DISCARD_ERR), 241 LOCAL_STATUS_TO_EVENT_MAP(P_ATR_EVT_DOORBELL), 242 LOCAL_STATUS_TO_EVENT_MAP(PM_MSI_INT_INTX), 243 LOCAL_STATUS_TO_EVENT_MAP(PM_MSI_INT_MSI), 244 LOCAL_STATUS_TO_EVENT_MAP(PM_MSI_INT_AER_EVT), 245 LOCAL_STATUS_TO_EVENT_MAP(PM_MSI_INT_EVENTS), 246 LOCAL_STATUS_TO_EVENT_MAP(PM_MSI_INT_SYS_ERR), 247 }; 248 249 static struct { 250 u32 offset; 251 u32 mask; 252 u32 shift; 253 u32 enb_mask; 254 u32 mask_high; 255 u32 mask_offset; 256 } event_descs[] = { 257 { PCIE_EVENT(L2_EXIT) }, 258 { PCIE_EVENT(HOTRST_EXIT) }, 259 { PCIE_EVENT(DLUP_EXIT) }, 260 { SEC_EVENT(TX_RAM_SEC_ERR) }, 261 { SEC_EVENT(RX_RAM_SEC_ERR) }, 262 { SEC_EVENT(PCIE2AXI_RAM_SEC_ERR) }, 263 { SEC_EVENT(AXI2PCIE_RAM_SEC_ERR) }, 264 { DED_EVENT(TX_RAM_DED_ERR) }, 265 { DED_EVENT(RX_RAM_DED_ERR) }, 266 { DED_EVENT(PCIE2AXI_RAM_DED_ERR) }, 267 { DED_EVENT(AXI2PCIE_RAM_DED_ERR) }, 268 { LOCAL_EVENT(DMA_END_ENGINE_0) }, 269 { LOCAL_EVENT(DMA_END_ENGINE_1) }, 270 { LOCAL_EVENT(DMA_ERROR_ENGINE_0) }, 271 { LOCAL_EVENT(DMA_ERROR_ENGINE_1) }, 272 { LOCAL_EVENT(A_ATR_EVT_POST_ERR) }, 273 { LOCAL_EVENT(A_ATR_EVT_FETCH_ERR) }, 274 { LOCAL_EVENT(A_ATR_EVT_DISCARD_ERR) }, 275 { LOCAL_EVENT(A_ATR_EVT_DOORBELL) }, 276 { LOCAL_EVENT(P_ATR_EVT_POST_ERR) }, 277 { LOCAL_EVENT(P_ATR_EVT_FETCH_ERR) }, 278 { LOCAL_EVENT(P_ATR_EVT_DISCARD_ERR) }, 279 { LOCAL_EVENT(P_ATR_EVT_DOORBELL) }, 280 { LOCAL_EVENT(PM_MSI_INT_INTX) }, 281 { LOCAL_EVENT(PM_MSI_INT_MSI) }, 282 { LOCAL_EVENT(PM_MSI_INT_AER_EVT) }, 283 { LOCAL_EVENT(PM_MSI_INT_EVENTS) }, 284 { LOCAL_EVENT(PM_MSI_INT_SYS_ERR) }, 285 }; 286 287 static char poss_clks[][5] = { "fic0", "fic1", "fic2", "fic3" }; 288 289 static struct mc_pcie *port; 290 291 static void mc_pcie_enable_msi(struct mc_pcie *port, void __iomem *ecam) 292 { 293 struct plda_msi *msi = &port->plda.msi; 294 u16 reg; 295 u8 queue_size; 296 297 /* Fixup MSI enable flag */ 298 reg = readw_relaxed(ecam + MC_MSI_CAP_CTRL_OFFSET + PCI_MSI_FLAGS); 299 reg |= PCI_MSI_FLAGS_ENABLE; 300 writew_relaxed(reg, ecam + MC_MSI_CAP_CTRL_OFFSET + PCI_MSI_FLAGS); 301 302 /* Fixup PCI MSI queue flags */ 303 queue_size = FIELD_GET(PCI_MSI_FLAGS_QMASK, reg); 304 reg |= FIELD_PREP(PCI_MSI_FLAGS_QSIZE, queue_size); 305 writew_relaxed(reg, ecam + MC_MSI_CAP_CTRL_OFFSET + PCI_MSI_FLAGS); 306 307 /* Fixup MSI addr fields */ 308 writel_relaxed(lower_32_bits(msi->vector_phy), 309 ecam + MC_MSI_CAP_CTRL_OFFSET + PCI_MSI_ADDRESS_LO); 310 writel_relaxed(upper_32_bits(msi->vector_phy), 311 ecam + MC_MSI_CAP_CTRL_OFFSET + PCI_MSI_ADDRESS_HI); 312 } 313 314 static inline u32 reg_to_event(u32 reg, struct event_map field) 315 { 316 return (reg & field.reg_mask) ? BIT(field.event_bit) : 0; 317 } 318 319 static u32 pcie_events(struct mc_pcie *port) 320 { 321 u32 reg = readl_relaxed(port->ctrl_base_addr + PCIE_EVENT_INT); 322 u32 val = 0; 323 int i; 324 325 for (i = 0; i < ARRAY_SIZE(pcie_event_to_event); i++) 326 val |= reg_to_event(reg, pcie_event_to_event[i]); 327 328 return val; 329 } 330 331 static u32 sec_errors(struct mc_pcie *port) 332 { 333 u32 reg = readl_relaxed(port->ctrl_base_addr + SEC_ERROR_INT); 334 u32 val = 0; 335 int i; 336 337 for (i = 0; i < ARRAY_SIZE(sec_error_to_event); i++) 338 val |= reg_to_event(reg, sec_error_to_event[i]); 339 340 return val; 341 } 342 343 static u32 ded_errors(struct mc_pcie *port) 344 { 345 u32 reg = readl_relaxed(port->ctrl_base_addr + DED_ERROR_INT); 346 u32 val = 0; 347 int i; 348 349 for (i = 0; i < ARRAY_SIZE(ded_error_to_event); i++) 350 val |= reg_to_event(reg, ded_error_to_event[i]); 351 352 return val; 353 } 354 355 static u32 local_events(struct mc_pcie *port) 356 { 357 u32 reg = readl_relaxed(port->bridge_base_addr + ISTATUS_LOCAL); 358 u32 val = 0; 359 int i; 360 361 for (i = 0; i < ARRAY_SIZE(local_status_to_event); i++) 362 val |= reg_to_event(reg, local_status_to_event[i]); 363 364 return val; 365 } 366 367 static u32 mc_get_events(struct plda_pcie_rp *port) 368 { 369 struct mc_pcie *mc_port = container_of(port, struct mc_pcie, plda); 370 u32 events = 0; 371 372 events |= pcie_events(mc_port); 373 events |= sec_errors(mc_port); 374 events |= ded_errors(mc_port); 375 events |= local_events(mc_port); 376 377 return events; 378 } 379 380 static irqreturn_t mc_event_handler(int irq, void *dev_id) 381 { 382 struct plda_pcie_rp *port = dev_id; 383 struct device *dev = port->dev; 384 struct irq_data *data; 385 386 data = irq_domain_get_irq_data(port->event_domain, irq); 387 388 if (event_cause[data->hwirq].str) 389 dev_err_ratelimited(dev, "%s\n", event_cause[data->hwirq].str); 390 else 391 dev_err_ratelimited(dev, "bad event IRQ %ld\n", data->hwirq); 392 393 return IRQ_HANDLED; 394 } 395 396 static void mc_ack_event_irq(struct irq_data *data) 397 { 398 struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); 399 struct mc_pcie *mc_port = container_of(port, struct mc_pcie, plda); 400 u32 event = data->hwirq; 401 void __iomem *addr; 402 u32 mask; 403 404 if (event_descs[event].offset == ISTATUS_LOCAL) 405 addr = mc_port->bridge_base_addr; 406 else 407 addr = mc_port->ctrl_base_addr; 408 409 addr += event_descs[event].offset; 410 mask = event_descs[event].mask; 411 mask |= event_descs[event].enb_mask; 412 413 writel_relaxed(mask, addr); 414 } 415 416 static void mc_mask_event_irq(struct irq_data *data) 417 { 418 struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); 419 struct mc_pcie *mc_port = container_of(port, struct mc_pcie, plda); 420 u32 event = data->hwirq; 421 void __iomem *addr; 422 u32 mask; 423 u32 val; 424 425 if (event_descs[event].offset == ISTATUS_LOCAL) 426 addr = mc_port->bridge_base_addr; 427 else 428 addr = mc_port->ctrl_base_addr; 429 430 addr += event_descs[event].mask_offset; 431 mask = event_descs[event].mask; 432 if (event_descs[event].enb_mask) { 433 mask <<= PCIE_EVENT_INT_ENB_SHIFT; 434 mask &= PCIE_EVENT_INT_ENB_MASK; 435 } 436 437 if (!event_descs[event].mask_high) 438 mask = ~mask; 439 440 raw_spin_lock(&port->lock); 441 val = readl_relaxed(addr); 442 if (event_descs[event].mask_high) 443 val |= mask; 444 else 445 val &= mask; 446 447 writel_relaxed(val, addr); 448 raw_spin_unlock(&port->lock); 449 } 450 451 static void mc_unmask_event_irq(struct irq_data *data) 452 { 453 struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); 454 struct mc_pcie *mc_port = container_of(port, struct mc_pcie, plda); 455 u32 event = data->hwirq; 456 void __iomem *addr; 457 u32 mask; 458 u32 val; 459 460 if (event_descs[event].offset == ISTATUS_LOCAL) 461 addr = mc_port->bridge_base_addr; 462 else 463 addr = mc_port->ctrl_base_addr; 464 465 addr += event_descs[event].mask_offset; 466 mask = event_descs[event].mask; 467 468 if (event_descs[event].enb_mask) 469 mask <<= PCIE_EVENT_INT_ENB_SHIFT; 470 471 if (event_descs[event].mask_high) 472 mask = ~mask; 473 474 if (event_descs[event].enb_mask) 475 mask &= PCIE_EVENT_INT_ENB_MASK; 476 477 raw_spin_lock(&port->lock); 478 val = readl_relaxed(addr); 479 if (event_descs[event].mask_high) 480 val &= mask; 481 else 482 val |= mask; 483 writel_relaxed(val, addr); 484 raw_spin_unlock(&port->lock); 485 } 486 487 static struct irq_chip mc_event_irq_chip = { 488 .name = "Microchip PCIe EVENT", 489 .irq_ack = mc_ack_event_irq, 490 .irq_mask = mc_mask_event_irq, 491 .irq_unmask = mc_unmask_event_irq, 492 }; 493 494 static inline void mc_pcie_deinit_clk(void *data) 495 { 496 struct clk *clk = data; 497 498 clk_disable_unprepare(clk); 499 } 500 501 static inline struct clk *mc_pcie_init_clk(struct device *dev, const char *id) 502 { 503 struct clk *clk; 504 int ret; 505 506 clk = devm_clk_get_optional(dev, id); 507 if (IS_ERR(clk)) 508 return clk; 509 if (!clk) 510 return clk; 511 512 ret = clk_prepare_enable(clk); 513 if (ret) 514 return ERR_PTR(ret); 515 516 devm_add_action_or_reset(dev, mc_pcie_deinit_clk, clk); 517 518 return clk; 519 } 520 521 static int mc_pcie_init_clks(struct device *dev) 522 { 523 int i; 524 struct clk *fic; 525 526 /* 527 * PCIe may be clocked via Fabric Interface using between 1 and 4 528 * clocks. Scan DT for clocks and enable them if present 529 */ 530 for (i = 0; i < ARRAY_SIZE(poss_clks); i++) { 531 fic = mc_pcie_init_clk(dev, poss_clks[i]); 532 if (IS_ERR(fic)) 533 return PTR_ERR(fic); 534 } 535 536 return 0; 537 } 538 539 static int mc_request_event_irq(struct plda_pcie_rp *plda, int event_irq, 540 int event) 541 { 542 return devm_request_irq(plda->dev, event_irq, mc_event_handler, 543 0, event_cause[event].sym, plda); 544 } 545 546 static const struct plda_event_ops mc_event_ops = { 547 .get_events = mc_get_events, 548 }; 549 550 static const struct plda_event mc_event = { 551 .request_event_irq = mc_request_event_irq, 552 .intx_event = EVENT_LOCAL_PM_MSI_INT_INTX, 553 .msi_event = EVENT_LOCAL_PM_MSI_INT_MSI, 554 }; 555 556 static inline void mc_clear_secs(struct mc_pcie *port) 557 { 558 writel_relaxed(SEC_ERROR_INT_ALL_RAM_SEC_ERR_INT, 559 port->ctrl_base_addr + SEC_ERROR_INT); 560 writel_relaxed(0, port->ctrl_base_addr + SEC_ERROR_EVENT_CNT); 561 } 562 563 static inline void mc_clear_deds(struct mc_pcie *port) 564 { 565 writel_relaxed(DED_ERROR_INT_ALL_RAM_DED_ERR_INT, 566 port->ctrl_base_addr + DED_ERROR_INT); 567 writel_relaxed(0, port->ctrl_base_addr + DED_ERROR_EVENT_CNT); 568 } 569 570 static void mc_disable_interrupts(struct mc_pcie *port) 571 { 572 u32 val; 573 574 /* Ensure ECC bypass is enabled */ 575 val = ECC_CONTROL_TX_RAM_ECC_BYPASS | 576 ECC_CONTROL_RX_RAM_ECC_BYPASS | 577 ECC_CONTROL_PCIE2AXI_RAM_ECC_BYPASS | 578 ECC_CONTROL_AXI2PCIE_RAM_ECC_BYPASS; 579 writel_relaxed(val, port->ctrl_base_addr + ECC_CONTROL); 580 581 /* Disable SEC errors and clear any outstanding */ 582 writel_relaxed(SEC_ERROR_INT_ALL_RAM_SEC_ERR_INT, 583 port->ctrl_base_addr + SEC_ERROR_INT_MASK); 584 mc_clear_secs(port); 585 586 /* Disable DED errors and clear any outstanding */ 587 writel_relaxed(DED_ERROR_INT_ALL_RAM_DED_ERR_INT, 588 port->ctrl_base_addr + DED_ERROR_INT_MASK); 589 mc_clear_deds(port); 590 591 /* Disable local interrupts and clear any outstanding */ 592 writel_relaxed(0, port->bridge_base_addr + IMASK_LOCAL); 593 writel_relaxed(GENMASK(31, 0), port->bridge_base_addr + ISTATUS_LOCAL); 594 writel_relaxed(GENMASK(31, 0), port->bridge_base_addr + ISTATUS_MSI); 595 596 /* Disable PCIe events and clear any outstanding */ 597 val = PCIE_EVENT_INT_L2_EXIT_INT | 598 PCIE_EVENT_INT_HOTRST_EXIT_INT | 599 PCIE_EVENT_INT_DLUP_EXIT_INT | 600 PCIE_EVENT_INT_L2_EXIT_INT_MASK | 601 PCIE_EVENT_INT_HOTRST_EXIT_INT_MASK | 602 PCIE_EVENT_INT_DLUP_EXIT_INT_MASK; 603 writel_relaxed(val, port->ctrl_base_addr + PCIE_EVENT_INT); 604 605 /* Disable host interrupts and clear any outstanding */ 606 writel_relaxed(0, port->bridge_base_addr + IMASK_HOST); 607 writel_relaxed(GENMASK(31, 0), port->bridge_base_addr + ISTATUS_HOST); 608 } 609 610 static int mc_platform_init(struct pci_config_window *cfg) 611 { 612 struct device *dev = cfg->parent; 613 struct platform_device *pdev = to_platform_device(dev); 614 struct pci_host_bridge *bridge = platform_get_drvdata(pdev); 615 int ret; 616 617 /* Configure address translation table 0 for PCIe config space */ 618 plda_pcie_setup_window(port->bridge_base_addr, 0, cfg->res.start, 619 cfg->res.start, 620 resource_size(&cfg->res)); 621 622 /* Need some fixups in config space */ 623 mc_pcie_enable_msi(port, cfg->win); 624 625 /* Configure non-config space outbound ranges */ 626 ret = plda_pcie_setup_iomems(bridge, &port->plda); 627 if (ret) 628 return ret; 629 630 port->plda.event_ops = &mc_event_ops; 631 port->plda.event_irq_chip = &mc_event_irq_chip; 632 port->plda.events_bitmap = GENMASK(NUM_EVENTS - 1, 0); 633 634 /* Address translation is up; safe to enable interrupts */ 635 ret = plda_init_interrupts(pdev, &port->plda, &mc_event); 636 if (ret) 637 return ret; 638 639 return 0; 640 } 641 642 static int mc_host_probe(struct platform_device *pdev) 643 { 644 struct device *dev = &pdev->dev; 645 void __iomem *apb_base_addr; 646 struct plda_pcie_rp *plda; 647 int ret; 648 u32 val; 649 650 port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL); 651 if (!port) 652 return -ENOMEM; 653 654 plda = &port->plda; 655 plda->dev = dev; 656 657 port->bridge_base_addr = devm_platform_ioremap_resource_byname(pdev, 658 "bridge"); 659 port->ctrl_base_addr = devm_platform_ioremap_resource_byname(pdev, 660 "ctrl"); 661 if (!IS_ERR(port->bridge_base_addr) && !IS_ERR(port->ctrl_base_addr)) 662 goto addrs_set; 663 664 /* 665 * The original, incorrect, binding that lumped the control and 666 * bridge addresses together still needs to be handled by the driver. 667 */ 668 apb_base_addr = devm_platform_ioremap_resource_byname(pdev, "apb"); 669 if (IS_ERR(apb_base_addr)) 670 return dev_err_probe(dev, PTR_ERR(apb_base_addr), 671 "both legacy apb register and ctrl/bridge regions missing"); 672 673 port->bridge_base_addr = apb_base_addr + MC_PCIE1_BRIDGE_ADDR; 674 port->ctrl_base_addr = apb_base_addr + MC_PCIE1_CTRL_ADDR; 675 676 addrs_set: 677 mc_disable_interrupts(port); 678 679 plda->bridge_addr = port->bridge_base_addr; 680 plda->num_events = NUM_EVENTS; 681 682 /* Allow enabling MSI by disabling MSI-X */ 683 val = readl(port->bridge_base_addr + PCIE_PCI_IRQ_DW0); 684 val &= ~MSIX_CAP_MASK; 685 writel(val, port->bridge_base_addr + PCIE_PCI_IRQ_DW0); 686 687 /* Pick num vectors from bitfile programmed onto FPGA fabric */ 688 val = readl(port->bridge_base_addr + PCIE_PCI_IRQ_DW0); 689 val &= NUM_MSI_MSGS_MASK; 690 val >>= NUM_MSI_MSGS_SHIFT; 691 692 plda->msi.num_vectors = 1 << val; 693 694 /* Pick vector address from design */ 695 plda->msi.vector_phy = readl_relaxed(port->bridge_base_addr + IMSI_ADDR); 696 697 ret = mc_pcie_init_clks(dev); 698 if (ret) { 699 dev_err(dev, "failed to get clock resources, error %d\n", ret); 700 return -ENODEV; 701 } 702 703 return pci_host_common_probe(pdev); 704 } 705 706 static const struct pci_ecam_ops mc_ecam_ops = { 707 .init = mc_platform_init, 708 .pci_ops = { 709 .map_bus = pci_ecam_map_bus, 710 .read = pci_generic_config_read, 711 .write = pci_generic_config_write, 712 } 713 }; 714 715 static const struct of_device_id mc_pcie_of_match[] = { 716 { 717 .compatible = "microchip,pcie-host-1.0", 718 .data = &mc_ecam_ops, 719 }, 720 {}, 721 }; 722 723 MODULE_DEVICE_TABLE(of, mc_pcie_of_match); 724 725 static struct platform_driver mc_pcie_driver = { 726 .probe = mc_host_probe, 727 .driver = { 728 .name = "microchip-pcie", 729 .of_match_table = mc_pcie_of_match, 730 .suppress_bind_attrs = true, 731 }, 732 }; 733 734 builtin_platform_driver(mc_pcie_driver); 735 MODULE_LICENSE("GPL"); 736 MODULE_DESCRIPTION("Microchip PCIe host controller driver"); 737 MODULE_AUTHOR("Daire McNamara <daire.mcnamara@microchip.com>"); 738