1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * PCIe host controller driver for Tegra264 SoC 4 * 5 * Copyright (c) 2022-2026, NVIDIA CORPORATION. All rights reserved. 6 */ 7 8 #include <linux/delay.h> 9 #include <linux/init.h> 10 #include <linux/interconnect.h> 11 #include <linux/iopoll.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/of_address.h> 15 #include <linux/of_device.h> 16 #include <linux/of.h> 17 #include <linux/of_pci.h> 18 #include <linux/of_platform.h> 19 #include <linux/pci-ecam.h> 20 #include <linux/pci.h> 21 #include <linux/platform_device.h> 22 #include <linux/pm_runtime.h> 23 24 #include <soc/tegra/bpmp.h> 25 #include <soc/tegra/bpmp-abi.h> 26 #include <soc/tegra/fuse.h> 27 28 #include "../pci.h" 29 30 /* XAL registers */ 31 #define XAL_RC_ECAM_BASE_HI 0x00 32 #define XAL_RC_ECAM_BASE_LO 0x04 33 #define XAL_RC_ECAM_BUSMASK 0x08 34 #define XAL_RC_IO_BASE_HI 0x0c 35 #define XAL_RC_IO_BASE_LO 0x10 36 #define XAL_RC_IO_LIMIT_HI 0x14 37 #define XAL_RC_IO_LIMIT_LO 0x18 38 #define XAL_RC_MEM_32BIT_BASE_HI 0x1c 39 #define XAL_RC_MEM_32BIT_BASE_LO 0x20 40 #define XAL_RC_MEM_32BIT_LIMIT_HI 0x24 41 #define XAL_RC_MEM_32BIT_LIMIT_LO 0x28 42 #define XAL_RC_MEM_64BIT_BASE_HI 0x2c 43 #define XAL_RC_MEM_64BIT_BASE_LO 0x30 44 #define XAL_RC_MEM_64BIT_LIMIT_HI 0x34 45 #define XAL_RC_MEM_64BIT_LIMIT_LO 0x38 46 #define XAL_RC_BAR_CNTL_STANDARD 0x40 47 #define XAL_RC_BAR_CNTL_STANDARD_IOBAR_EN BIT(0) 48 #define XAL_RC_BAR_CNTL_STANDARD_32B_BAR_EN BIT(1) 49 #define XAL_RC_BAR_CNTL_STANDARD_64B_BAR_EN BIT(2) 50 51 /* XTL registers */ 52 #define XTL_RC_PCIE_CFG_LINK_CAPS 0x56 53 #define XTL_RC_PCIE_CFG_LINK_STATUS 0x5a 54 55 #define XTL_RC_MGMT_PERST_CONTROL 0x218 56 #define XTL_RC_MGMT_PERST_CONTROL_PERST_O_N BIT(0) 57 58 #define XTL_RC_MGMT_CLOCK_CONTROL 0x47c 59 #define XTL_RC_MGMT_CLOCK_CONTROL_PEX_CLKREQ_I_N_PIN_USE_CONV_TO_PRSNT BIT(9) 60 61 struct tegra264_pcie { 62 struct device *dev; 63 64 /* I/O memory */ 65 void __iomem *xal; 66 void __iomem *xtl; 67 void __iomem *ecam; 68 69 /* bridge configuration */ 70 struct pci_config_window *cfg; 71 struct pci_host_bridge *bridge; 72 73 /* BPMP and bandwidth management */ 74 struct icc_path *icc_path; 75 struct tegra_bpmp *bpmp; 76 u32 ctl_id; 77 78 bool supports_hotplug; 79 bool link_up; 80 }; 81 82 static void tegra264_pcie_power_off(struct tegra264_pcie *pcie) 83 { 84 struct tegra_bpmp_message msg = {}; 85 struct mrq_pcie_request req = {}; 86 int err; 87 88 req.cmd = CMD_PCIE_RP_CONTROLLER_OFF; 89 req.rp_ctrlr_off.rp_controller = pcie->ctl_id; 90 91 msg.mrq = MRQ_PCIE; 92 msg.tx.data = &req; 93 msg.tx.size = sizeof(req); 94 95 err = tegra_bpmp_transfer(pcie->bpmp, &msg); 96 if (err) 97 dev_err(pcie->dev, "failed to turn off PCIe #%u: %pe\n", 98 pcie->ctl_id, ERR_PTR(err)); 99 100 if (msg.rx.ret) 101 dev_err(pcie->dev, "failed to turn off PCIe #%u: %d\n", 102 pcie->ctl_id, msg.rx.ret); 103 } 104 105 static void tegra264_pcie_icc_set(struct tegra264_pcie *pcie) 106 { 107 u32 value, speed, width; 108 int err; 109 110 /* 111 * If the link is up, read the negotiated speed and width fields from 112 * the link status register. Otherwise, read the corresponding values 113 * from the link capabilities register to ensure the link works after 114 * hotplug. 115 * 116 * Ideally we'll want to update this dynamically, either on hotplug 117 * or bandwidth change notifications. Neither of those are currently 118 * possible, so this is as good as it gets for now. 119 */ 120 if (pcie->link_up) { 121 value = readw(pcie->ecam + XTL_RC_PCIE_CFG_LINK_STATUS); 122 speed = FIELD_GET(PCI_EXP_LNKSTA_CLS, value); 123 width = FIELD_GET(PCI_EXP_LNKSTA_NLW, value); 124 } else { 125 value = readw(pcie->ecam + XTL_RC_PCIE_CFG_LINK_CAPS); 126 speed = FIELD_GET(PCI_EXP_LNKCAP_SLS, value); 127 width = FIELD_GET(PCI_EXP_LNKCAP_MLW, value); 128 } 129 130 value = Mbps_to_icc(width * PCIE_SPEED2MBS_ENC(pcie_link_speed[speed])); 131 132 /* 133 * We don't want to error out here because a boot-critical device 134 * could be connected to this root port. Failure to set the bandwidth 135 * request may have an adverse impact on performance, but it is not 136 * generally fatal, so we opt to continue regardless so that users 137 * get a chance to fix things. 138 */ 139 err = icc_set_bw(pcie->icc_path, value, value); 140 if (err < 0) 141 dev_err(pcie->dev, 142 "failed to request bandwidth (%u kBps): %pe\n", 143 value, ERR_PTR(err)); 144 } 145 146 /* 147 * The various memory regions used by the controller (I/O, memory, ECAM) are 148 * set up during early boot and have hardware-level protections in place. If 149 * the DT ranges don't match what's been setup, the controller won't be able 150 * to write the address endpoints properly, so make sure to validate that DT 151 * and firmware programming agree on these ranges. 152 */ 153 static bool tegra264_pcie_valid_ranges(struct platform_device *pdev) 154 { 155 struct tegra264_pcie *pcie = platform_get_drvdata(pdev); 156 struct device_node *np = pcie->dev->of_node; 157 struct of_pci_range_parser parser; 158 phys_addr_t phys, limit, hi, lo; 159 struct of_pci_range range; 160 struct resource *res; 161 bool status = true; 162 u32 value; 163 int err; 164 165 err = of_pci_range_parser_init(&parser, np); 166 if (err < 0) 167 return false; 168 169 for_each_of_pci_range(&parser, &range) { 170 unsigned int addr_hi, addr_lo, limit_hi, limit_lo, enable; 171 unsigned long type = range.flags & IORESOURCE_TYPE_BITS; 172 phys_addr_t start, end, mask; 173 const char *region = NULL; 174 175 end = range.cpu_addr + range.size - 1; 176 start = range.cpu_addr; 177 178 switch (type) { 179 case IORESOURCE_IO: 180 addr_hi = XAL_RC_IO_BASE_HI; 181 addr_lo = XAL_RC_IO_BASE_LO; 182 limit_hi = XAL_RC_IO_LIMIT_HI; 183 limit_lo = XAL_RC_IO_LIMIT_LO; 184 enable = XAL_RC_BAR_CNTL_STANDARD_IOBAR_EN; 185 mask = SZ_64K - 1; 186 region = "I/O"; 187 break; 188 189 case IORESOURCE_MEM: 190 if (range.flags & IORESOURCE_PREFETCH) { 191 addr_hi = XAL_RC_MEM_64BIT_BASE_HI; 192 addr_lo = XAL_RC_MEM_64BIT_BASE_LO; 193 limit_hi = XAL_RC_MEM_64BIT_LIMIT_HI; 194 limit_lo = XAL_RC_MEM_64BIT_LIMIT_LO; 195 enable = XAL_RC_BAR_CNTL_STANDARD_64B_BAR_EN; 196 region = "prefetchable memory"; 197 } else { 198 addr_hi = XAL_RC_MEM_32BIT_BASE_HI; 199 addr_lo = XAL_RC_MEM_32BIT_BASE_LO; 200 limit_hi = XAL_RC_MEM_32BIT_LIMIT_HI; 201 limit_lo = XAL_RC_MEM_32BIT_LIMIT_LO; 202 enable = XAL_RC_BAR_CNTL_STANDARD_32B_BAR_EN; 203 region = "memory"; 204 } 205 206 mask = SZ_1M - 1; 207 break; 208 } 209 210 /* not interested in anything that's not I/O or memory */ 211 if (!region) 212 continue; 213 214 /* don't check regions that haven't been enabled */ 215 value = readl(pcie->xal + XAL_RC_BAR_CNTL_STANDARD); 216 if ((value & enable) == 0) 217 continue; 218 219 hi = readl(pcie->xal + addr_hi); 220 lo = readl(pcie->xal + addr_lo); 221 phys = ((hi << 16) << 16) | lo; 222 223 hi = readl(pcie->xal + limit_hi); 224 lo = readl(pcie->xal + limit_lo); 225 limit = ((hi << 16) << 16) | lo | mask; 226 227 if (phys != start || limit != end) { 228 dev_err(pcie->dev, 229 "%s region mismatch: %pap-%pap -> %pap-%pap\n", 230 region, &phys, &limit, &start, &end); 231 status = false; 232 } 233 } 234 235 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ecam"); 236 if (!res) 237 return false; 238 239 hi = readl(pcie->xal + XAL_RC_ECAM_BASE_HI); 240 lo = readl(pcie->xal + XAL_RC_ECAM_BASE_LO); 241 phys = ((hi << 16) << 16) | lo; 242 243 value = readl(pcie->xal + XAL_RC_ECAM_BUSMASK); 244 limit = phys + ((value + 1) << 20) - 1; 245 246 if (phys != res->start || limit != res->end) { 247 dev_err(pcie->dev, 248 "ECAM region mismatch: %pap-%pap -> %pap-%pap\n", 249 &phys, &limit, &res->start, &res->end); 250 status = false; 251 } 252 253 return status; 254 } 255 256 static bool tegra264_pcie_supports_hotplug(struct tegra264_pcie *pcie) 257 { 258 u32 value = readl(pcie->xtl + XTL_RC_MGMT_CLOCK_CONTROL); 259 260 return (value & XTL_RC_MGMT_CLOCK_CONTROL_PEX_CLKREQ_I_N_PIN_USE_CONV_TO_PRSNT) != 0; 261 } 262 263 static bool tegra264_pcie_link_up(struct tegra264_pcie *pcie, 264 enum pci_bus_speed *speed) 265 { 266 u16 value = readw(pcie->ecam + XTL_RC_PCIE_CFG_LINK_STATUS); 267 268 if (value & PCI_EXP_LNKSTA_DLLLA) { 269 if (speed) 270 *speed = pcie_link_speed[FIELD_GET(PCI_EXP_LNKSTA_CLS, 271 value)]; 272 273 return true; 274 } 275 276 return false; 277 } 278 279 static void tegra264_pcie_init(struct tegra264_pcie *pcie) 280 { 281 enum pci_bus_speed speed; 282 unsigned int i; 283 u32 value; 284 285 /* bring the endpoint out of reset */ 286 value = readl(pcie->xtl + XTL_RC_MGMT_PERST_CONTROL); 287 value |= XTL_RC_MGMT_PERST_CONTROL_PERST_O_N; 288 writel(value, pcie->xtl + XTL_RC_MGMT_PERST_CONTROL); 289 290 for (i = 0; i < PCIE_LINK_WAIT_MAX_RETRIES; i++) { 291 if (tegra264_pcie_link_up(pcie, NULL)) 292 break; 293 294 msleep(PCIE_LINK_WAIT_SLEEP_MS); 295 } 296 297 pcie->supports_hotplug = tegra264_pcie_supports_hotplug(pcie); 298 pcie->link_up = tegra264_pcie_link_up(pcie, &speed); 299 300 if (pcie->link_up) { 301 msleep(PCIE_RESET_CONFIG_WAIT_MS); 302 dev_info(pcie->dev, "PCIe #%u link is up (speed: %s)\n", 303 pcie->ctl_id, pci_speed_string(speed)); 304 tegra264_pcie_icc_set(pcie); 305 } else { 306 dev_info(pcie->dev, "PCIe #%u link is down\n", pcie->ctl_id); 307 308 /* 309 * Make sure to reset the bandwidth requirements if the link 310 * is down but hotplug-capable. 311 */ 312 if (pcie->supports_hotplug) 313 tegra264_pcie_icc_set(pcie); 314 } 315 } 316 317 static int tegra264_pcie_probe(struct platform_device *pdev) 318 { 319 struct device *dev = &pdev->dev; 320 struct pci_host_bridge *bridge; 321 struct tegra264_pcie *pcie; 322 struct resource_entry *bus; 323 struct resource *res; 324 int err; 325 326 bridge = devm_pci_alloc_host_bridge(dev, sizeof(struct tegra264_pcie)); 327 if (!bridge) 328 return dev_err_probe(dev, -ENOMEM, 329 "failed to allocate host bridge\n"); 330 331 pcie = pci_host_bridge_priv(bridge); 332 platform_set_drvdata(pdev, pcie); 333 pcie->bridge = bridge; 334 pcie->dev = dev; 335 336 pcie->xal = devm_platform_ioremap_resource_byname(pdev, "xal"); 337 if (IS_ERR(pcie->xal)) 338 return dev_err_probe(dev, PTR_ERR(pcie->xal), 339 "failed to map XAL memory\n"); 340 341 pcie->xtl = devm_platform_ioremap_resource_byname(pdev, "xtl-pri"); 342 if (IS_ERR(pcie->xtl)) 343 return dev_err_probe(dev, PTR_ERR(pcie->xtl), 344 "failed to map XTL-PRI memory\n"); 345 346 bus = resource_list_first_type(&bridge->windows, IORESOURCE_BUS); 347 if (!bus) 348 return dev_err_probe(dev, -ENODEV, 349 "failed to get bus resources\n"); 350 351 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ecam"); 352 if (!res) 353 return dev_err_probe(dev, -ENXIO, 354 "failed to get ECAM resource\n"); 355 356 pcie->icc_path = devm_of_icc_get(dev, "write"); 357 if (IS_ERR(pcie->icc_path)) 358 return dev_err_probe(dev, PTR_ERR(pcie->icc_path), 359 "failed to get ICC\n"); 360 361 pcie->bpmp = tegra_bpmp_get_with_id(dev, &pcie->ctl_id); 362 if (IS_ERR(pcie->bpmp)) 363 return dev_err_probe(dev, PTR_ERR(pcie->bpmp), 364 "failed to get BPMP\n"); 365 366 err = devm_pm_runtime_set_active_enabled(dev); 367 if (err < 0) { 368 dev_err_probe(dev, err, "failed to enable runtime PM\n"); 369 goto err_put_bpmp; 370 } 371 372 err = pm_runtime_resume_and_get(dev); 373 if (err < 0) { 374 dev_err_probe(dev, err, "failed to power on device\n"); 375 goto err_put_bpmp; 376 } 377 378 /* sanity check that programmed ranges match what's in DT */ 379 if (!tegra264_pcie_valid_ranges(pdev)) { 380 err = -EINVAL; 381 goto err_put_pm; 382 } 383 384 pcie->cfg = pci_ecam_create(dev, res, bus->res, &pci_generic_ecam_ops); 385 if (IS_ERR(pcie->cfg)) { 386 err = dev_err_probe(dev, PTR_ERR(pcie->cfg), 387 "failed to create ECAM\n"); 388 goto err_put_pm; 389 } 390 391 bridge->ops = (struct pci_ops *)&pci_generic_ecam_ops.pci_ops; 392 bridge->sysdata = pcie->cfg; 393 pcie->ecam = pcie->cfg->win; 394 395 tegra264_pcie_init(pcie); 396 397 /* 398 * Fail if the link isn't up and doesn't support hotplug, no device 399 * will ever be able to be added on this bus. 400 */ 401 if (!pcie->link_up && !pcie->supports_hotplug) { 402 err = dev_err_probe(pcie->dev, -ENODEV, 403 "PCIe #%u link is down and not hotplug-capable, turning off\n", 404 pcie->ctl_id); 405 tegra264_pcie_power_off(pcie); 406 goto err_free_ecam; 407 } 408 409 err = pci_host_probe(bridge); 410 if (err < 0) { 411 dev_err_probe(dev, err, "failed to register Host Bridge\n"); 412 goto err_free_ecam; 413 } 414 415 return 0; 416 417 err_free_ecam: 418 pci_ecam_free(pcie->cfg); 419 err_put_pm: 420 pm_runtime_put_sync(dev); 421 err_put_bpmp: 422 tegra_bpmp_put(pcie->bpmp); 423 424 return err; 425 } 426 427 static void tegra264_pcie_remove(struct platform_device *pdev) 428 { 429 struct tegra264_pcie *pcie = platform_get_drvdata(pdev); 430 431 /* 432 * If we undo tegra264_pcie_init() then link goes down and need 433 * controller reset to bring up the link again. Remove intention is 434 * to clean up the root bridge and re-enumerate during bind. 435 */ 436 pci_lock_rescan_remove(); 437 pci_stop_root_bus(pcie->bridge->bus); 438 pci_remove_root_bus(pcie->bridge->bus); 439 pci_unlock_rescan_remove(); 440 441 pm_runtime_put_sync(&pdev->dev); 442 tegra_bpmp_put(pcie->bpmp); 443 pci_ecam_free(pcie->cfg); 444 } 445 446 static const struct of_device_id tegra264_pcie_of_match[] = { 447 { 448 .compatible = "nvidia,tegra264-pcie", 449 }, 450 { /* sentinel */ } 451 }; 452 MODULE_DEVICE_TABLE(of, tegra264_pcie_of_match); 453 454 static struct platform_driver tegra264_pcie_driver = { 455 .probe = tegra264_pcie_probe, 456 .remove = tegra264_pcie_remove, 457 .driver = { 458 .name = "tegra264-pcie", 459 .of_match_table = tegra264_pcie_of_match, 460 }, 461 }; 462 module_platform_driver(tegra264_pcie_driver); 463 464 MODULE_AUTHOR("Manikanta Maddireddy <mmaddireddy@nvidia.com>"); 465 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 466 MODULE_DESCRIPTION("NVIDIA Tegra264 PCIe host controller driver"); 467 MODULE_LICENSE("GPL"); 468