1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * PCIe driver for Renesas RZ/G3S SoCs 4 * 5 * Copyright (C) 2025 Renesas Electronics Corp. 6 * 7 * Based on: 8 * drivers/pci/controller/pcie-rcar-host.c 9 * Copyright (C) 2009 - 2011 Paul Mundt 10 */ 11 12 #include <linux/bitfield.h> 13 #include <linux/bitmap.h> 14 #include <linux/bitops.h> 15 #include <linux/cleanup.h> 16 #include <linux/clk.h> 17 #include <linux/delay.h> 18 #include <linux/iopoll.h> 19 #include <linux/interrupt.h> 20 #include <linux/irq.h> 21 #include <linux/irqchip/chained_irq.h> 22 #include <linux/irqchip/irq-msi-lib.h> 23 #include <linux/irqdomain.h> 24 #include <linux/kernel.h> 25 #include <linux/mfd/syscon.h> 26 #include <linux/mutex.h> 27 #include <linux/msi.h> 28 #include <linux/of_irq.h> 29 #include <linux/pci.h> 30 #include <linux/platform_device.h> 31 #include <linux/pm_runtime.h> 32 #include <linux/regmap.h> 33 #include <linux/reset.h> 34 #include <linux/sizes.h> 35 #include <linux/slab.h> 36 #include <linux/units.h> 37 38 #include "../pci.h" 39 40 /* AXI registers */ 41 #define RZG3S_PCI_REQDATA(id) (0x80 + (id) * 0x4) 42 #define RZG3S_PCI_REQRCVDAT 0x8c 43 44 #define RZG3S_PCI_REQADR1 0x90 45 #define RZG3S_PCI_REQADR1_BUS GENMASK(31, 24) 46 #define RZG3S_PCI_REQADR1_DEV GENMASK(23, 19) 47 #define RZG3S_PCI_REQADR1_FUNC GENMASK(18, 16) 48 #define RZG3S_PCI_REQADR1_REG GENMASK(11, 0) 49 50 #define RZG3S_PCI_REQBE 0x98 51 #define RZG3S_PCI_REQBE_BYTE_EN GENMASK(3, 0) 52 53 #define RZG3S_PCI_REQISS 0x9c 54 #define RZG3S_PCI_REQISS_MOR_STATUS GENMASK(18, 16) 55 #define RZG3S_PCI_REQISS_TR_TYPE GENMASK(11, 8) 56 #define RZG3S_PCI_REQISS_TR_TP0_RD FIELD_PREP(RZG3S_PCI_REQISS_TR_TYPE, 0x4) 57 #define RZG3S_PCI_REQISS_TR_TP0_WR FIELD_PREP(RZG3S_PCI_REQISS_TR_TYPE, 0x5) 58 #define RZG3S_PCI_REQISS_TR_TP1_RD FIELD_PREP(RZG3S_PCI_REQISS_TR_TYPE, 0x6) 59 #define RZG3S_PCI_REQISS_TR_TP1_WR FIELD_PREP(RZG3S_PCI_REQISS_TR_TYPE, 0x7) 60 #define RZG3S_PCI_REQISS_REQ_ISSUE BIT(0) 61 62 #define RZG3S_PCI_MSIRCVWADRL 0x100 63 #define RZG3S_PCI_MSIRCVWADRL_MASK GENMASK(31, 3) 64 #define RZG3S_PCI_MSIRCVWADRL_MSG_DATA_ENA BIT(1) 65 #define RZG3S_PCI_MSIRCVWADRL_ENA BIT(0) 66 67 #define RZG3S_PCI_MSIRCVWADRU 0x104 68 69 #define RZG3S_PCI_MSIRCVWMSKL 0x108 70 #define RZG3S_PCI_MSIRCVWMSKL_MASK GENMASK(31, 2) 71 72 #define RZG3S_PCI_PINTRCVIE 0x110 73 #define RZG3S_PCI_PINTRCVIE_INTX(i) BIT(i) 74 #define RZG3S_PCI_PINTRCVIE_MSI BIT(4) 75 76 #define RZG3S_PCI_PINTRCVIS 0x114 77 #define RZG3S_PCI_PINTRCVIS_INTX(i) BIT(i) 78 #define RZG3S_PCI_PINTRCVIS_MSI BIT(4) 79 80 #define RZG3S_PCI_MSGRCVIE 0x120 81 #define RZG3S_PCI_MSGRCVIE_MSG_RCV BIT(24) 82 83 #define RZG3S_PCI_MSGRCVIS 0x124 84 #define RZG3S_PCI_MSGRCVIS_MRI BIT(24) 85 86 #define RZG3S_PCI_PEIE0 0x200 87 88 #define RZG3S_PCI_PEIS0 0x204 89 #define RZG3S_PCI_PEIS0_RX_DLLP_PM_ENTER BIT(12) 90 #define RZG3S_PCI_PEIS0_DL_UPDOWN BIT(9) 91 92 #define RZG3S_PCI_PEIE1 0x208 93 #define RZG3S_PCI_PEIS1 0x20c 94 #define RZG3S_PCI_AMEIS 0x214 95 #define RZG3S_PCI_ASEIS1 0x224 96 97 #define RZG3S_PCI_PCSTAT1 0x408 98 #define RZG3S_PCI_PCSTAT1_LTSSM_STATE GENMASK(14, 10) 99 #define RZG3S_PCI_PCSTAT1_DL_DOWN_STS BIT(0) 100 101 #define RZG3S_PCI_PCCTRL2 0x410 102 #define RZG3S_PCI_PCCTRL2_LS_CHG GENMASK(9, 8) 103 #define RZG3S_PCI_PCCTRL2_LS_CHG_REQ BIT(0) 104 105 #define RZG3S_PCI_PCSTAT2 0x414 106 #define RZG3S_PCI_PCSTAT2_LS_CHG_DONE BIT(28) 107 #define RZG3S_PCI_PCSTAT2_SDRIRE GENMASK(7, 1) 108 109 #define RZG3S_PCI_PERM 0x300 110 #define RZG3S_PCI_PERM_CFG_HWINIT_EN BIT(2) 111 #define RZG3S_PCI_PERM_PIPE_PHY_REG_EN BIT(1) 112 113 #define RZG3S_PCI_MSIRE(id) (0x600 + (id) * 0x10) 114 #define RZG3S_PCI_MSIRE_ENA BIT(0) 115 116 #define RZG3S_PCI_MSIRM(id) (0x608 + (id) * 0x10) 117 #define RZG3S_PCI_MSIRS(id) (0x60c + (id) * 0x10) 118 119 #define RZG3S_PCI_AWBASEL(id) (0x1000 + (id) * 0x20) 120 #define RZG3S_PCI_AWBASEL_WIN_ENA BIT(0) 121 122 #define RZG3S_PCI_AWBASEU(id) (0x1004 + (id) * 0x20) 123 #define RZG3S_PCI_AWMASKL(id) (0x1008 + (id) * 0x20) 124 #define RZG3S_PCI_AWMASKU(id) (0x100c + (id) * 0x20) 125 #define RZG3S_PCI_ADESTL(id) (0x1010 + (id) * 0x20) 126 #define RZG3S_PCI_ADESTU(id) (0x1014 + (id) * 0x20) 127 128 #define RZG3S_PCI_PWBASEL(id) (0x1100 + (id) * 0x20) 129 #define RZG3S_PCI_PWBASEL_ENA BIT(0) 130 131 #define RZG3S_PCI_PWBASEU(id) (0x1104 + (id) * 0x20) 132 #define RZG3S_PCI_PDESTL(id) (0x1110 + (id) * 0x20) 133 #define RZG3S_PCI_PDESTU(id) (0x1114 + (id) * 0x20) 134 #define RZG3S_PCI_PWMASKL(id) (0x1108 + (id) * 0x20) 135 #define RZG3S_PCI_PWMASKU(id) (0x110c + (id) * 0x20) 136 137 /* PHY control registers */ 138 #define RZG3S_PCI_PHY_XCFGD(id) (0x2000 + (id) * 0x10) 139 #define RZG3S_PCI_PHY_XCFGD_NUM 39 140 141 #define RZG3S_PCI_PHY_XCFGA_CMN(id) (0x2400 + (id) * 0x10) 142 #define RZG3S_PCI_PHY_XCFGA_CMN_NUM 16 143 144 #define RZG3S_PCI_PHY_XCFGA_RX(id) (0x2500 + (id) * 0x10) 145 #define RZG3S_PCI_PHY_XCFGA_RX_NUM 13 146 147 #define RZG3S_PCI_PHY_XCFGA_TX 0x25d0 148 149 #define RZG3S_PCI_PHY_XCFG_CTRL 0x2a20 150 #define RZG3S_PCI_PHY_XCFG_CTRL_PHYREG_SEL BIT(0) 151 152 /* PCIe registers */ 153 #define RZG3S_PCI_CFG_BASE 0x6000 154 #define RZG3S_PCI_CFG_BARMSK00L 0xa0 155 #define RZG3S_PCI_CFG_BARMSK00U 0xa4 156 157 #define RZG3S_PCI_CFG_PCIEC 0x60 158 159 /* System controller registers */ 160 #define RZG3S_SYS_PCIE_RST_RSM_B 0xd74 161 #define RZG3S_SYS_PCIE_RST_RSM_B_MASK BIT(0) 162 163 /* Maximum number of windows */ 164 #define RZG3S_MAX_WINDOWS 8 165 166 /* Number of MSI interrupts per register */ 167 #define RZG3S_PCI_MSI_INT_PER_REG 32 168 /* The number of MSI interrupts */ 169 #define RZG3S_PCI_MSI_INT_NR RZG3S_PCI_MSI_INT_PER_REG 170 171 /* Timeouts experimentally determined */ 172 #define RZG3S_REQ_ISSUE_TIMEOUT_US 2500 173 174 /** 175 * struct rzg3s_pcie_msi - RZ/G3S PCIe MSI data structure 176 * @domain: IRQ domain 177 * @map: bitmap with the allocated MSIs 178 * @dma_addr: address of the allocated MSI window 179 * @window_base: base address of the MSI window 180 * @pages: allocated pages for MSI window mapping 181 * @map_lock: lock for bitmap with the allocated MSIs 182 * @irq: MSI interrupt 183 */ 184 struct rzg3s_pcie_msi { 185 struct irq_domain *domain; 186 DECLARE_BITMAP(map, RZG3S_PCI_MSI_INT_NR); 187 dma_addr_t dma_addr; 188 dma_addr_t window_base; 189 unsigned long pages; 190 struct mutex map_lock; 191 int irq; 192 }; 193 194 struct rzg3s_pcie_host; 195 196 /** 197 * struct rzg3s_pcie_soc_data - SoC specific data 198 * @init_phy: PHY initialization function 199 * @power_resets: array with the resets that need to be de-asserted after 200 * power-on 201 * @cfg_resets: array with the resets that need to be de-asserted after 202 * configuration 203 * @num_power_resets: number of power resets 204 * @num_cfg_resets: number of configuration resets 205 */ 206 struct rzg3s_pcie_soc_data { 207 int (*init_phy)(struct rzg3s_pcie_host *host); 208 const char * const *power_resets; 209 const char * const *cfg_resets; 210 u8 num_power_resets; 211 u8 num_cfg_resets; 212 }; 213 214 /** 215 * struct rzg3s_pcie_port - RZ/G3S PCIe Root Port data structure 216 * @refclk: PCIe reference clock 217 * @vendor_id: Vendor ID 218 * @device_id: Device ID 219 */ 220 struct rzg3s_pcie_port { 221 struct clk *refclk; 222 u32 vendor_id; 223 u32 device_id; 224 }; 225 226 /** 227 * struct rzg3s_pcie_host - RZ/G3S PCIe data structure 228 * @axi: base address for AXI registers 229 * @pcie: base address for PCIe registers 230 * @dev: struct device 231 * @power_resets: reset control signals that should be set after power up 232 * @cfg_resets: reset control signals that should be set after configuration 233 * @sysc: SYSC regmap 234 * @intx_domain: INTx IRQ domain 235 * @data: SoC specific data 236 * @msi: MSI data structure 237 * @port: PCIe Root Port 238 * @hw_lock: lock for access to the HW resources 239 * @intx_irqs: INTx interrupts 240 * @max_link_speed: maximum supported link speed 241 */ 242 struct rzg3s_pcie_host { 243 void __iomem *axi; 244 void __iomem *pcie; 245 struct device *dev; 246 struct reset_control_bulk_data *power_resets; 247 struct reset_control_bulk_data *cfg_resets; 248 struct regmap *sysc; 249 struct irq_domain *intx_domain; 250 const struct rzg3s_pcie_soc_data *data; 251 struct rzg3s_pcie_msi msi; 252 struct rzg3s_pcie_port port; 253 raw_spinlock_t hw_lock; 254 int intx_irqs[PCI_NUM_INTX]; 255 int max_link_speed; 256 }; 257 258 #define rzg3s_msi_to_host(_msi) container_of(_msi, struct rzg3s_pcie_host, msi) 259 260 static void rzg3s_pcie_update_bits(void __iomem *base, u32 offset, u32 mask, 261 u32 val) 262 { 263 u32 tmp; 264 265 tmp = readl_relaxed(base + offset); 266 tmp &= ~mask; 267 tmp |= val & mask; 268 writel_relaxed(tmp, base + offset); 269 } 270 271 static int rzg3s_pcie_child_issue_request(struct rzg3s_pcie_host *host) 272 { 273 u32 val; 274 int ret; 275 276 rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_REQISS, 277 RZG3S_PCI_REQISS_REQ_ISSUE, 278 RZG3S_PCI_REQISS_REQ_ISSUE); 279 ret = readl_poll_timeout_atomic(host->axi + RZG3S_PCI_REQISS, val, 280 !(val & RZG3S_PCI_REQISS_REQ_ISSUE), 281 5, RZG3S_REQ_ISSUE_TIMEOUT_US); 282 283 if (val & RZG3S_PCI_REQISS_MOR_STATUS) 284 return -EIO; 285 286 return ret; 287 } 288 289 static void rzg3s_pcie_child_prepare_bus(struct pci_bus *bus, 290 unsigned int devfn, int where) 291 { 292 struct rzg3s_pcie_host *host = bus->sysdata; 293 unsigned int dev, func, reg; 294 295 dev = PCI_SLOT(devfn); 296 func = PCI_FUNC(devfn); 297 reg = where & ~0x3; 298 299 /* Set the destination */ 300 writel_relaxed(FIELD_PREP(RZG3S_PCI_REQADR1_BUS, bus->number) | 301 FIELD_PREP(RZG3S_PCI_REQADR1_DEV, dev) | 302 FIELD_PREP(RZG3S_PCI_REQADR1_FUNC, func) | 303 FIELD_PREP(RZG3S_PCI_REQADR1_REG, reg), 304 host->axi + RZG3S_PCI_REQADR1); 305 306 /* Set byte enable */ 307 writel_relaxed(RZG3S_PCI_REQBE_BYTE_EN, host->axi + RZG3S_PCI_REQBE); 308 } 309 310 static int rzg3s_pcie_child_read_conf(struct rzg3s_pcie_host *host, 311 struct pci_bus *bus, unsigned int devfn, 312 int where, u32 *data) 313 { 314 bool type0 = pci_is_root_bus(bus->parent) ? true : false; 315 int ret; 316 317 rzg3s_pcie_child_prepare_bus(bus, devfn, where); 318 319 /* Set the type of request */ 320 writel_relaxed(type0 ? RZG3S_PCI_REQISS_TR_TP0_RD : 321 RZG3S_PCI_REQISS_TR_TP1_RD, 322 host->axi + RZG3S_PCI_REQISS); 323 324 /* Issue the request and wait to finish */ 325 ret = rzg3s_pcie_child_issue_request(host); 326 if (ret) 327 return PCIBIOS_SET_FAILED; 328 329 /* Read the data */ 330 *data = readl_relaxed(host->axi + RZG3S_PCI_REQRCVDAT); 331 332 return PCIBIOS_SUCCESSFUL; 333 } 334 335 /* Serialization is provided by 'pci_lock' in drivers/pci/access.c */ 336 static int rzg3s_pcie_child_read(struct pci_bus *bus, unsigned int devfn, 337 int where, int size, u32 *val) 338 { 339 struct rzg3s_pcie_host *host = bus->sysdata; 340 int ret; 341 342 ret = rzg3s_pcie_child_read_conf(host, bus, devfn, where, val); 343 if (ret != PCIBIOS_SUCCESSFUL) 344 return ret; 345 346 if (size <= 2) 347 *val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1); 348 349 return PCIBIOS_SUCCESSFUL; 350 } 351 352 static int rzg3s_pcie_child_write_conf(struct rzg3s_pcie_host *host, 353 struct pci_bus *bus, unsigned int devfn, 354 int where, u32 data) 355 { 356 bool type0 = pci_is_root_bus(bus->parent) ? true : false; 357 int ret; 358 359 rzg3s_pcie_child_prepare_bus(bus, devfn, where); 360 361 /* Set the write data */ 362 writel_relaxed(0, host->axi + RZG3S_PCI_REQDATA(0)); 363 writel_relaxed(0, host->axi + RZG3S_PCI_REQDATA(1)); 364 writel_relaxed(data, host->axi + RZG3S_PCI_REQDATA(2)); 365 366 /* Set the type of request */ 367 writel_relaxed(type0 ? RZG3S_PCI_REQISS_TR_TP0_WR : 368 RZG3S_PCI_REQISS_TR_TP1_WR, 369 host->axi + RZG3S_PCI_REQISS); 370 371 /* Issue the request and wait to finish */ 372 ret = rzg3s_pcie_child_issue_request(host); 373 if (ret) 374 return PCIBIOS_SET_FAILED; 375 376 return PCIBIOS_SUCCESSFUL; 377 } 378 379 /* Serialization is provided by 'pci_lock' in drivers/pci/access.c */ 380 static int rzg3s_pcie_child_write(struct pci_bus *bus, unsigned int devfn, 381 int where, int size, u32 val) 382 { 383 struct rzg3s_pcie_host *host = bus->sysdata; 384 u32 data, shift; 385 int ret; 386 387 if (size == 4) 388 return rzg3s_pcie_child_write_conf(host, bus, devfn, where, val); 389 390 /* 391 * Controller does 32 bit accesses. To do byte accesses software need 392 * to do read/modify/write. This may have potential side effects. For 393 * example, software may perform a 16-bit write. If the hardware only 394 * supports 32-bit accesses, we must do a 32-bit read, merge in the 16 395 * bits we intend to write, followed by a 32-bit write. If the 16 bits 396 * we *don't* intend to write happen to have any RW1C 397 * (write-one-to-clear) bits set, we just inadvertently cleared 398 * something we shouldn't have. 399 */ 400 if (!bus->unsafe_warn) { 401 dev_warn(&bus->dev, "%d-byte config write to %04x:%02x:%02x.%d offset %#x may corrupt adjacent RW1C bits\n", 402 size, pci_domain_nr(bus), bus->number, 403 PCI_SLOT(devfn), PCI_FUNC(devfn), where); 404 bus->unsafe_warn = 1; 405 } 406 407 ret = rzg3s_pcie_child_read_conf(host, bus, devfn, where, &data); 408 if (ret != PCIBIOS_SUCCESSFUL) 409 return ret; 410 411 if (size == 1) { 412 shift = BITS_PER_BYTE * (where & 3); 413 data &= ~(0xff << shift); 414 data |= ((val & 0xff) << shift); 415 } else if (size == 2) { 416 shift = BITS_PER_BYTE * (where & 2); 417 data &= ~(0xffff << shift); 418 data |= ((val & 0xffff) << shift); 419 } else { 420 data = val; 421 } 422 423 return rzg3s_pcie_child_write_conf(host, bus, devfn, where, data); 424 } 425 426 static struct pci_ops rzg3s_pcie_child_ops = { 427 .read = rzg3s_pcie_child_read, 428 .write = rzg3s_pcie_child_write, 429 }; 430 431 static void __iomem *rzg3s_pcie_root_map_bus(struct pci_bus *bus, 432 unsigned int devfn, int where) 433 { 434 struct rzg3s_pcie_host *host = bus->sysdata; 435 436 if (devfn) 437 return NULL; 438 439 return host->pcie + where; 440 } 441 442 /* Serialized by 'pci_lock' */ 443 static int rzg3s_pcie_root_write(struct pci_bus *bus, unsigned int devfn, 444 int where, int size, u32 val) 445 { 446 struct rzg3s_pcie_host *host = bus->sysdata; 447 int ret; 448 449 /* Enable access control to the CFGU */ 450 writel_relaxed(RZG3S_PCI_PERM_CFG_HWINIT_EN, 451 host->axi + RZG3S_PCI_PERM); 452 453 ret = pci_generic_config_write(bus, devfn, where, size, val); 454 455 /* Disable access control to the CFGU */ 456 writel_relaxed(0, host->axi + RZG3S_PCI_PERM); 457 458 return ret; 459 } 460 461 static struct pci_ops rzg3s_pcie_root_ops = { 462 .read = pci_generic_config_read, 463 .write = rzg3s_pcie_root_write, 464 .map_bus = rzg3s_pcie_root_map_bus, 465 }; 466 467 static void rzg3s_pcie_intx_irq_handler(struct irq_desc *desc) 468 { 469 struct rzg3s_pcie_host *host = irq_desc_get_handler_data(desc); 470 struct irq_chip *chip = irq_desc_get_chip(desc); 471 unsigned int irq = irq_desc_get_irq(desc); 472 u32 intx = irq - host->intx_irqs[0]; 473 474 chained_irq_enter(chip, desc); 475 generic_handle_domain_irq(host->intx_domain, intx); 476 chained_irq_exit(chip, desc); 477 } 478 479 static irqreturn_t rzg3s_pcie_msi_irq(int irq, void *data) 480 { 481 u8 regs = RZG3S_PCI_MSI_INT_NR / RZG3S_PCI_MSI_INT_PER_REG; 482 DECLARE_BITMAP(bitmap, RZG3S_PCI_MSI_INT_NR) = {0}; 483 struct rzg3s_pcie_host *host = data; 484 struct rzg3s_pcie_msi *msi = &host->msi; 485 unsigned long bit; 486 u32 status; 487 488 status = readl_relaxed(host->axi + RZG3S_PCI_PINTRCVIS); 489 if (!(status & RZG3S_PCI_PINTRCVIS_MSI)) 490 return IRQ_NONE; 491 492 /* Clear the MSI */ 493 rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_PINTRCVIS, 494 RZG3S_PCI_PINTRCVIS_MSI, 495 RZG3S_PCI_PINTRCVIS_MSI); 496 rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_MSGRCVIS, 497 RZG3S_PCI_MSGRCVIS_MRI, RZG3S_PCI_MSGRCVIS_MRI); 498 499 for (u8 reg_id = 0; reg_id < regs; reg_id++) { 500 status = readl_relaxed(host->axi + RZG3S_PCI_MSIRS(reg_id)); 501 bitmap_write(bitmap, status, reg_id * RZG3S_PCI_MSI_INT_PER_REG, 502 RZG3S_PCI_MSI_INT_PER_REG); 503 } 504 505 for_each_set_bit(bit, bitmap, RZG3S_PCI_MSI_INT_NR) { 506 int ret; 507 508 ret = generic_handle_domain_irq(msi->domain, bit); 509 if (ret) { 510 u8 reg_bit = bit % RZG3S_PCI_MSI_INT_PER_REG; 511 u8 reg_id = bit / RZG3S_PCI_MSI_INT_PER_REG; 512 513 /* Unknown MSI, just clear it */ 514 writel_relaxed(BIT(reg_bit), 515 host->axi + RZG3S_PCI_MSIRS(reg_id)); 516 } 517 } 518 519 return IRQ_HANDLED; 520 } 521 522 static void rzg3s_pcie_msi_irq_ack(struct irq_data *d) 523 { 524 struct rzg3s_pcie_msi *msi = irq_data_get_irq_chip_data(d); 525 struct rzg3s_pcie_host *host = rzg3s_msi_to_host(msi); 526 u8 reg_bit = d->hwirq % RZG3S_PCI_MSI_INT_PER_REG; 527 u8 reg_id = d->hwirq / RZG3S_PCI_MSI_INT_PER_REG; 528 529 guard(raw_spinlock_irqsave)(&host->hw_lock); 530 531 writel_relaxed(BIT(reg_bit), host->axi + RZG3S_PCI_MSIRS(reg_id)); 532 } 533 534 static void rzg3s_pcie_msi_irq_mask(struct irq_data *d) 535 { 536 struct rzg3s_pcie_msi *msi = irq_data_get_irq_chip_data(d); 537 struct rzg3s_pcie_host *host = rzg3s_msi_to_host(msi); 538 u8 reg_bit = d->hwirq % RZG3S_PCI_MSI_INT_PER_REG; 539 u8 reg_id = d->hwirq / RZG3S_PCI_MSI_INT_PER_REG; 540 541 guard(raw_spinlock_irqsave)(&host->hw_lock); 542 543 rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_MSIRM(reg_id), BIT(reg_bit), 544 BIT(reg_bit)); 545 } 546 547 static void rzg3s_pcie_msi_irq_unmask(struct irq_data *d) 548 { 549 struct rzg3s_pcie_msi *msi = irq_data_get_irq_chip_data(d); 550 struct rzg3s_pcie_host *host = rzg3s_msi_to_host(msi); 551 u8 reg_bit = d->hwirq % RZG3S_PCI_MSI_INT_PER_REG; 552 u8 reg_id = d->hwirq / RZG3S_PCI_MSI_INT_PER_REG; 553 554 guard(raw_spinlock_irqsave)(&host->hw_lock); 555 556 rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_MSIRM(reg_id), BIT(reg_bit), 557 0); 558 } 559 560 static void rzg3s_pcie_irq_compose_msi_msg(struct irq_data *data, 561 struct msi_msg *msg) 562 { 563 struct rzg3s_pcie_msi *msi = irq_data_get_irq_chip_data(data); 564 struct rzg3s_pcie_host *host = rzg3s_msi_to_host(msi); 565 u32 lo, hi; 566 567 /* 568 * Enable and msg data enable bits are part of the address lo. Drop 569 * them along with the unused bit. 570 */ 571 lo = readl_relaxed(host->axi + RZG3S_PCI_MSIRCVWADRL) & 572 RZG3S_PCI_MSIRCVWADRL_MASK; 573 hi = readl_relaxed(host->axi + RZG3S_PCI_MSIRCVWADRU); 574 575 msg->address_lo = lo; 576 msg->address_hi = hi; 577 msg->data = data->hwirq; 578 } 579 580 static struct irq_chip rzg3s_pcie_msi_bottom_chip = { 581 .name = "rzg3s-pcie-msi", 582 .irq_ack = rzg3s_pcie_msi_irq_ack, 583 .irq_mask = rzg3s_pcie_msi_irq_mask, 584 .irq_unmask = rzg3s_pcie_msi_irq_unmask, 585 .irq_compose_msi_msg = rzg3s_pcie_irq_compose_msi_msg, 586 }; 587 588 static int rzg3s_pcie_msi_domain_alloc(struct irq_domain *domain, 589 unsigned int virq, unsigned int nr_irqs, 590 void *args) 591 { 592 struct rzg3s_pcie_msi *msi = domain->host_data; 593 int hwirq; 594 595 scoped_guard(mutex, &msi->map_lock) { 596 hwirq = bitmap_find_free_region(msi->map, RZG3S_PCI_MSI_INT_NR, 597 order_base_2(nr_irqs)); 598 } 599 600 if (hwirq < 0) 601 return -ENOSPC; 602 603 for (unsigned int i = 0; i < nr_irqs; i++) { 604 irq_domain_set_info(domain, virq + i, hwirq + i, 605 &rzg3s_pcie_msi_bottom_chip, 606 domain->host_data, handle_edge_irq, NULL, 607 NULL); 608 } 609 610 return 0; 611 } 612 613 static void rzg3s_pcie_msi_domain_free(struct irq_domain *domain, 614 unsigned int virq, unsigned int nr_irqs) 615 { 616 struct irq_data *d = irq_domain_get_irq_data(domain, virq); 617 struct rzg3s_pcie_msi *msi = domain->host_data; 618 619 guard(mutex)(&msi->map_lock); 620 621 bitmap_release_region(msi->map, d->hwirq, order_base_2(nr_irqs)); 622 } 623 624 static const struct irq_domain_ops rzg3s_pcie_msi_domain_ops = { 625 .alloc = rzg3s_pcie_msi_domain_alloc, 626 .free = rzg3s_pcie_msi_domain_free, 627 }; 628 629 #define RZG3S_PCIE_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS | \ 630 MSI_FLAG_USE_DEF_CHIP_OPS | \ 631 MSI_FLAG_NO_AFFINITY | \ 632 MSI_FLAG_PCI_MSI_MASK_PARENT) 633 634 #define RZG3S_PCIE_MSI_FLAGS_SUPPORTED (MSI_FLAG_MULTI_PCI_MSI | \ 635 MSI_GENERIC_FLAGS_MASK) 636 637 static const struct msi_parent_ops rzg3s_pcie_msi_parent_ops = { 638 .required_flags = RZG3S_PCIE_MSI_FLAGS_REQUIRED, 639 .supported_flags = RZG3S_PCIE_MSI_FLAGS_SUPPORTED, 640 .bus_select_token = DOMAIN_BUS_PCI_MSI, 641 .chip_flags = MSI_CHIP_FLAG_SET_ACK, 642 .prefix = "RZG3S-", 643 .init_dev_msi_info = msi_lib_init_dev_msi_info, 644 }; 645 646 static int rzg3s_pcie_msi_allocate_domains(struct rzg3s_pcie_msi *msi) 647 { 648 struct rzg3s_pcie_host *host = rzg3s_msi_to_host(msi); 649 struct device *dev = host->dev; 650 struct irq_domain_info info = { 651 .fwnode = dev_fwnode(dev), 652 .ops = &rzg3s_pcie_msi_domain_ops, 653 .size = RZG3S_PCI_MSI_INT_NR, 654 .host_data = msi, 655 }; 656 657 msi->domain = msi_create_parent_irq_domain(&info, 658 &rzg3s_pcie_msi_parent_ops); 659 if (!msi->domain) 660 return dev_err_probe(dev, -ENOMEM, 661 "failed to create IRQ domain\n"); 662 663 return 0; 664 } 665 666 static int rzg3s_pcie_msi_hw_setup(struct rzg3s_pcie_host *host) 667 { 668 u8 regs = RZG3S_PCI_MSI_INT_NR / RZG3S_PCI_MSI_INT_PER_REG; 669 struct rzg3s_pcie_msi *msi = &host->msi; 670 671 /* 672 * Set MSI window size. HW will set the window to 673 * RZG3S_PCI_MSI_INT_NR * 4 bytes. 674 */ 675 writel_relaxed(FIELD_PREP(RZG3S_PCI_MSIRCVWMSKL_MASK, 676 RZG3S_PCI_MSI_INT_NR - 1), 677 host->axi + RZG3S_PCI_MSIRCVWMSKL); 678 679 /* Set MSI window address and enable MSI window */ 680 writel_relaxed(upper_32_bits(msi->window_base), 681 host->axi + RZG3S_PCI_MSIRCVWADRU); 682 writel_relaxed(lower_32_bits(msi->window_base) | 683 RZG3S_PCI_MSIRCVWADRL_ENA | 684 RZG3S_PCI_MSIRCVWADRL_MSG_DATA_ENA, 685 host->axi + RZG3S_PCI_MSIRCVWADRL); 686 687 /* Set MSI receive enable */ 688 for (u8 reg_id = 0; reg_id < regs; reg_id++) { 689 writel_relaxed(RZG3S_PCI_MSIRE_ENA, 690 host->axi + RZG3S_PCI_MSIRE(reg_id)); 691 } 692 693 /* Enable message receive interrupts */ 694 writel_relaxed(RZG3S_PCI_MSGRCVIE_MSG_RCV, 695 host->axi + RZG3S_PCI_MSGRCVIE); 696 697 /* Enable MSI */ 698 rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_PINTRCVIE, 699 RZG3S_PCI_PINTRCVIE_MSI, 700 RZG3S_PCI_PINTRCVIE_MSI); 701 702 return 0; 703 } 704 705 static int rzg3s_pcie_msi_setup(struct rzg3s_pcie_host *host) 706 { 707 size_t size = RZG3S_PCI_MSI_INT_NR * sizeof(u32); 708 struct rzg3s_pcie_msi *msi = &host->msi; 709 struct device *dev = host->dev; 710 int id, ret; 711 712 msi->pages = __get_free_pages(GFP_KERNEL | GFP_DMA, 0); 713 if (!msi->pages) 714 return -ENOMEM; 715 716 msi->dma_addr = dma_map_single(dev, (void *)msi->pages, size * 2, 717 DMA_BIDIRECTIONAL); 718 if (dma_mapping_error(dev, msi->dma_addr)) { 719 ret = -ENOMEM; 720 goto free_pages; 721 } 722 723 /* 724 * According to the RZ/G3S HW manual (Rev.1.10, section 34.4.5.2 Setting 725 * the MSI Window) the MSI window needs to fall within one of the 726 * enabled AXI windows. Find an enabled AXI window to setup the MSI 727 * window. 728 */ 729 for (id = 0; id < RZG3S_MAX_WINDOWS; id++) { 730 u64 base, basel, baseu; 731 u64 mask, maskl, masku; 732 733 basel = readl_relaxed(host->axi + RZG3S_PCI_AWBASEL(id)); 734 /* Skip checking this AXI window if it's not enabled */ 735 if (!(basel & RZG3S_PCI_AWBASEL_WIN_ENA)) 736 continue; 737 738 baseu = readl_relaxed(host->axi + RZG3S_PCI_AWBASEU(id)); 739 base = baseu << 32 | basel; 740 741 maskl = readl_relaxed(host->axi + RZG3S_PCI_AWMASKL(id)); 742 masku = readl_relaxed(host->axi + RZG3S_PCI_AWMASKU(id)); 743 mask = masku << 32 | maskl; 744 745 if (msi->dma_addr < base || msi->dma_addr > base + mask) 746 continue; 747 748 break; 749 } 750 751 if (id == RZG3S_MAX_WINDOWS) { 752 ret = -EINVAL; 753 goto dma_unmap; 754 } 755 756 /* The MSI base address must be aligned to the MSI size */ 757 msi->window_base = ALIGN(msi->dma_addr, size); 758 if (msi->window_base < msi->dma_addr) { 759 ret = -EINVAL; 760 goto dma_unmap; 761 } 762 763 rzg3s_pcie_msi_hw_setup(host); 764 765 return 0; 766 767 dma_unmap: 768 dma_unmap_single(dev, msi->dma_addr, size * 2, DMA_BIDIRECTIONAL); 769 free_pages: 770 free_pages(msi->pages, 0); 771 return ret; 772 } 773 774 static void rzg3s_pcie_msi_hw_teardown(struct rzg3s_pcie_host *host) 775 { 776 u8 regs = RZG3S_PCI_MSI_INT_NR / RZG3S_PCI_MSI_INT_PER_REG; 777 778 /* Disable MSI */ 779 rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_PINTRCVIE, 780 RZG3S_PCI_PINTRCVIE_MSI, 0); 781 782 /* Disable message receive interrupts */ 783 rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_MSGRCVIE, 784 RZG3S_PCI_MSGRCVIE_MSG_RCV, 0); 785 786 /* Disable MSI receive enable */ 787 for (u8 reg_id = 0; reg_id < regs; reg_id++) 788 writel_relaxed(0, host->axi + RZG3S_PCI_MSIRE(reg_id)); 789 790 /* Disable MSI window */ 791 writel_relaxed(0, host->axi + RZG3S_PCI_MSIRCVWADRL); 792 } 793 794 static void rzg3s_pcie_teardown_msi(struct rzg3s_pcie_host *host) 795 { 796 size_t size = RZG3S_PCI_MSI_INT_NR * sizeof(u32); 797 struct rzg3s_pcie_msi *msi = &host->msi; 798 799 rzg3s_pcie_msi_hw_teardown(host); 800 801 free_irq(msi->irq, host); 802 irq_domain_remove(msi->domain); 803 804 /* Free unused memory */ 805 dma_unmap_single(host->dev, msi->dma_addr, size * 2, DMA_BIDIRECTIONAL); 806 free_pages(msi->pages, 0); 807 } 808 809 static int rzg3s_pcie_init_msi(struct rzg3s_pcie_host *host) 810 { 811 struct platform_device *pdev = to_platform_device(host->dev); 812 struct rzg3s_pcie_msi *msi = &host->msi; 813 struct device *dev = host->dev; 814 const char *devname; 815 int ret; 816 817 ret = devm_mutex_init(dev, &msi->map_lock); 818 if (ret) 819 return ret; 820 821 msi->irq = platform_get_irq_byname(pdev, "msi"); 822 if (msi->irq < 0) 823 return dev_err_probe(dev, msi->irq, "Failed to get MSI IRQ!\n"); 824 825 devname = devm_kasprintf(dev, GFP_KERNEL, "%s-msi", dev_name(dev)); 826 if (!devname) 827 return -ENOMEM; 828 829 ret = rzg3s_pcie_msi_allocate_domains(msi); 830 if (ret) 831 return ret; 832 833 /* 834 * Don't use devm_request_irq() as the driver uses non-devm helpers 835 * to control clocks. Mixing them may lead to subtle bugs. 836 */ 837 ret = request_irq(msi->irq, rzg3s_pcie_msi_irq, 0, devname, host); 838 if (ret) { 839 dev_err_probe(dev, ret, "Failed to request IRQ: %d\n", ret); 840 goto free_domains; 841 } 842 843 ret = rzg3s_pcie_msi_setup(host); 844 if (ret) { 845 dev_err_probe(dev, ret, "Failed to setup MSI!\n"); 846 goto free_irq; 847 } 848 849 return 0; 850 851 free_irq: 852 free_irq(msi->irq, host); 853 free_domains: 854 irq_domain_remove(msi->domain); 855 return ret; 856 } 857 858 static void rzg3s_pcie_intx_irq_ack(struct irq_data *d) 859 { 860 struct rzg3s_pcie_host *host = irq_data_get_irq_chip_data(d); 861 862 guard(raw_spinlock_irqsave)(&host->hw_lock); 863 864 rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_PINTRCVIS, 865 RZG3S_PCI_PINTRCVIS_INTX(d->hwirq), 866 RZG3S_PCI_PINTRCVIS_INTX(d->hwirq)); 867 } 868 869 static void rzg3s_pcie_intx_irq_mask(struct irq_data *d) 870 { 871 struct rzg3s_pcie_host *host = irq_data_get_irq_chip_data(d); 872 873 guard(raw_spinlock_irqsave)(&host->hw_lock); 874 875 rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_PINTRCVIE, 876 RZG3S_PCI_PINTRCVIE_INTX(d->hwirq), 0); 877 } 878 879 static void rzg3s_pcie_intx_irq_unmask(struct irq_data *d) 880 { 881 struct rzg3s_pcie_host *host = irq_data_get_irq_chip_data(d); 882 883 guard(raw_spinlock_irqsave)(&host->hw_lock); 884 885 rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_PINTRCVIE, 886 RZG3S_PCI_PINTRCVIE_INTX(d->hwirq), 887 RZG3S_PCI_PINTRCVIE_INTX(d->hwirq)); 888 } 889 890 static struct irq_chip rzg3s_pcie_intx_irq_chip = { 891 .name = "PCIe INTx", 892 .irq_ack = rzg3s_pcie_intx_irq_ack, 893 .irq_mask = rzg3s_pcie_intx_irq_mask, 894 .irq_unmask = rzg3s_pcie_intx_irq_unmask, 895 }; 896 897 static int rzg3s_pcie_intx_map(struct irq_domain *domain, unsigned int irq, 898 irq_hw_number_t hwirq) 899 { 900 irq_set_chip_and_handler(irq, &rzg3s_pcie_intx_irq_chip, 901 handle_level_irq); 902 irq_set_chip_data(irq, domain->host_data); 903 904 return 0; 905 } 906 907 static const struct irq_domain_ops rzg3s_pcie_intx_domain_ops = { 908 .map = rzg3s_pcie_intx_map, 909 .xlate = irq_domain_xlate_onetwocell, 910 }; 911 912 static int rzg3s_pcie_init_irqdomain(struct rzg3s_pcie_host *host) 913 { 914 struct device *dev = host->dev; 915 struct platform_device *pdev = to_platform_device(dev); 916 917 for (int i = 0; i < PCI_NUM_INTX; i++) { 918 char irq_name[5] = {0}; 919 int irq; 920 921 scnprintf(irq_name, ARRAY_SIZE(irq_name), "int%c", 'a' + i); 922 923 irq = platform_get_irq_byname(pdev, irq_name); 924 if (irq < 0) 925 return dev_err_probe(dev, -EINVAL, 926 "Failed to parse and map INT%c IRQ\n", 927 'A' + i); 928 929 host->intx_irqs[i] = irq; 930 irq_set_chained_handler_and_data(irq, 931 rzg3s_pcie_intx_irq_handler, 932 host); 933 } 934 935 host->intx_domain = irq_domain_create_linear(dev_fwnode(dev), 936 PCI_NUM_INTX, 937 &rzg3s_pcie_intx_domain_ops, 938 host); 939 if (!host->intx_domain) 940 return dev_err_probe(dev, -EINVAL, 941 "Failed to add irq domain for INTx IRQs\n"); 942 irq_domain_update_bus_token(host->intx_domain, DOMAIN_BUS_WIRED); 943 944 if (IS_ENABLED(CONFIG_PCI_MSI)) { 945 int ret = rzg3s_pcie_init_msi(host); 946 947 if (ret) { 948 irq_domain_remove(host->intx_domain); 949 return ret; 950 } 951 } 952 953 return 0; 954 } 955 956 static void rzg3s_pcie_teardown_irqdomain(struct rzg3s_pcie_host *host) 957 { 958 if (IS_ENABLED(CONFIG_PCI_MSI)) 959 rzg3s_pcie_teardown_msi(host); 960 961 irq_domain_remove(host->intx_domain); 962 } 963 964 static int rzg3s_pcie_set_max_link_speed(struct rzg3s_pcie_host *host) 965 { 966 u32 remote_supported_link_speeds, max_supported_link_speeds; 967 u32 cs2, tmp, pcie_cap = RZG3S_PCI_CFG_PCIEC; 968 u32 cur_link_speed, link_speed; 969 u8 ltssm_state_l0 = 0xc; 970 int ret; 971 u16 ls; 972 973 /* 974 * According to the RZ/G3S HW manual (Rev.1.10, section 34.6.3 Caution 975 * when Changing the Speed Spontaneously) link speed change can be done 976 * only when the LTSSM is in L0. 977 */ 978 ret = readl_poll_timeout(host->axi + RZG3S_PCI_PCSTAT1, tmp, 979 FIELD_GET(RZG3S_PCI_PCSTAT1_LTSSM_STATE, tmp) == ltssm_state_l0, 980 PCIE_LINK_WAIT_SLEEP_MS * MILLI, 981 PCIE_LINK_WAIT_SLEEP_MS * MILLI * 982 PCIE_LINK_WAIT_MAX_RETRIES); 983 if (ret) 984 return ret; 985 986 ls = readw_relaxed(host->pcie + pcie_cap + PCI_EXP_LNKSTA); 987 cs2 = readl_relaxed(host->axi + RZG3S_PCI_PCSTAT2); 988 989 switch (pcie_link_speed[host->max_link_speed]) { 990 case PCIE_SPEED_5_0GT: 991 max_supported_link_speeds = GENMASK(PCI_EXP_LNKSTA_CLS_5_0GB - 1, 0); 992 link_speed = PCI_EXP_LNKCTL2_TLS_5_0GT; 993 break; 994 default: 995 /* Should not happen */ 996 return -EINVAL; 997 } 998 999 cur_link_speed = FIELD_GET(PCI_EXP_LNKSTA_CLS, ls); 1000 remote_supported_link_speeds = FIELD_GET(RZG3S_PCI_PCSTAT2_SDRIRE, cs2); 1001 /* Drop reserved bits */ 1002 remote_supported_link_speeds &= max_supported_link_speeds; 1003 1004 /* 1005 * Return if max link speed is already set or the connected device 1006 * doesn't support it. 1007 */ 1008 if (cur_link_speed == host->max_link_speed || 1009 remote_supported_link_speeds != max_supported_link_speeds) 1010 return 0; 1011 1012 /* Set target Link speed */ 1013 rzg3s_pcie_update_bits(host->pcie, pcie_cap + PCI_EXP_LNKCTL2, 1014 PCI_EXP_LNKCTL2_TLS, 1015 FIELD_PREP(PCI_EXP_LNKCTL2_TLS, link_speed)); 1016 1017 /* Request link speed change */ 1018 rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_PCCTRL2, 1019 RZG3S_PCI_PCCTRL2_LS_CHG_REQ | 1020 RZG3S_PCI_PCCTRL2_LS_CHG, 1021 RZG3S_PCI_PCCTRL2_LS_CHG_REQ | 1022 FIELD_PREP(RZG3S_PCI_PCCTRL2_LS_CHG, 1023 link_speed - 1)); 1024 1025 ret = readl_poll_timeout(host->axi + RZG3S_PCI_PCSTAT2, cs2, 1026 (cs2 & RZG3S_PCI_PCSTAT2_LS_CHG_DONE), 1027 PCIE_LINK_WAIT_SLEEP_MS * MILLI, 1028 PCIE_LINK_WAIT_SLEEP_MS * MILLI * 1029 PCIE_LINK_WAIT_MAX_RETRIES); 1030 1031 /* 1032 * According to the RZ/G3S HW manual (Rev.1.10, section 34.6.3 Caution 1033 * when Changing the Speed Spontaneously) the PCI_PCCTRL2_LS_CHG_REQ 1034 * should be de-asserted after checking for PCI_PCSTAT2_LS_CHG_DONE. 1035 */ 1036 rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_PCCTRL2, 1037 RZG3S_PCI_PCCTRL2_LS_CHG_REQ, 0); 1038 1039 return ret; 1040 } 1041 1042 static int rzg3s_pcie_config_init(struct rzg3s_pcie_host *host) 1043 { 1044 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(host); 1045 struct resource_entry *ft; 1046 struct resource *bus; 1047 u8 subordinate_bus; 1048 u8 secondary_bus; 1049 u8 primary_bus; 1050 1051 ft = resource_list_first_type(&bridge->windows, IORESOURCE_BUS); 1052 if (!ft) 1053 return -ENODEV; 1054 1055 bus = ft->res; 1056 primary_bus = bus->start; 1057 secondary_bus = bus->start + 1; 1058 subordinate_bus = bus->end; 1059 1060 /* Enable access control to the CFGU */ 1061 writel_relaxed(RZG3S_PCI_PERM_CFG_HWINIT_EN, 1062 host->axi + RZG3S_PCI_PERM); 1063 1064 /* HW manual recommends to write 0xffffffff on initialization */ 1065 writel_relaxed(0xffffffff, host->pcie + RZG3S_PCI_CFG_BARMSK00L); 1066 writel_relaxed(0xffffffff, host->pcie + RZG3S_PCI_CFG_BARMSK00U); 1067 1068 /* Update bus info */ 1069 writeb_relaxed(primary_bus, host->pcie + PCI_PRIMARY_BUS); 1070 writeb_relaxed(secondary_bus, host->pcie + PCI_SECONDARY_BUS); 1071 writeb_relaxed(subordinate_bus, host->pcie + PCI_SUBORDINATE_BUS); 1072 1073 /* Disable access control to the CFGU */ 1074 writel_relaxed(0, host->axi + RZG3S_PCI_PERM); 1075 1076 return 0; 1077 } 1078 1079 static void rzg3s_pcie_irq_init(struct rzg3s_pcie_host *host) 1080 { 1081 /* 1082 * According to the HW manual of the RZ/G3S (Rev.1.10, sections 1083 * corresponding to all registers written with ~0U), the hardware 1084 * ignores value written to unused bits. Writing ~0U to these registers 1085 * should be safe. 1086 */ 1087 1088 /* Clear the link state and PM transitions */ 1089 writel_relaxed(RZG3S_PCI_PEIS0_DL_UPDOWN | 1090 RZG3S_PCI_PEIS0_RX_DLLP_PM_ENTER, 1091 host->axi + RZG3S_PCI_PEIS0); 1092 1093 /* Disable all interrupts */ 1094 writel_relaxed(0, host->axi + RZG3S_PCI_PEIE0); 1095 1096 /* Clear all parity and ecc error interrupts */ 1097 writel_relaxed(~0U, host->axi + RZG3S_PCI_PEIS1); 1098 1099 /* Disable all parity and ecc error interrupts */ 1100 writel_relaxed(0, host->axi + RZG3S_PCI_PEIE1); 1101 1102 /* Clear all AXI master error interrupts */ 1103 writel_relaxed(~0U, host->axi + RZG3S_PCI_AMEIS); 1104 1105 /* Clear all AXI slave error interrupts */ 1106 writel_relaxed(~0U, host->axi + RZG3S_PCI_ASEIS1); 1107 1108 /* Clear all message receive interrupts */ 1109 writel_relaxed(~0U, host->axi + RZG3S_PCI_MSGRCVIS); 1110 } 1111 1112 static int rzg3s_pcie_power_resets_deassert(struct rzg3s_pcie_host *host) 1113 { 1114 const struct rzg3s_pcie_soc_data *data = host->data; 1115 1116 /* 1117 * According to the RZ/G3S HW manual (Rev.1.10, section 1118 * 34.5.1.2 De-asserting the Reset) the PCIe IP needs to wait 5ms from 1119 * power on to the de-assertion of reset. 1120 */ 1121 fsleep(5000); 1122 return reset_control_bulk_deassert(data->num_power_resets, 1123 host->power_resets); 1124 } 1125 1126 static int rzg3s_pcie_resets_prepare_and_get(struct rzg3s_pcie_host *host) 1127 { 1128 const struct rzg3s_pcie_soc_data *data = host->data; 1129 unsigned int i; 1130 int ret; 1131 1132 host->power_resets = devm_kmalloc_array(host->dev, 1133 data->num_power_resets, 1134 sizeof(*host->power_resets), 1135 GFP_KERNEL); 1136 if (!host->power_resets) 1137 return -ENOMEM; 1138 1139 for (i = 0; i < data->num_power_resets; i++) 1140 host->power_resets[i].id = data->power_resets[i]; 1141 1142 host->cfg_resets = devm_kmalloc_array(host->dev, 1143 data->num_cfg_resets, 1144 sizeof(*host->cfg_resets), 1145 GFP_KERNEL); 1146 if (!host->cfg_resets) 1147 return -ENOMEM; 1148 1149 for (i = 0; i < data->num_cfg_resets; i++) 1150 host->cfg_resets[i].id = data->cfg_resets[i]; 1151 1152 ret = devm_reset_control_bulk_get_exclusive(host->dev, 1153 data->num_power_resets, 1154 host->power_resets); 1155 if (ret) 1156 return ret; 1157 1158 return devm_reset_control_bulk_get_exclusive(host->dev, 1159 data->num_cfg_resets, 1160 host->cfg_resets); 1161 } 1162 1163 static int rzg3s_pcie_host_parse_port(struct rzg3s_pcie_host *host) 1164 { 1165 struct device_node *of_port = of_get_next_child(host->dev->of_node, NULL); 1166 struct rzg3s_pcie_port *port = &host->port; 1167 int ret; 1168 1169 ret = of_property_read_u32(of_port, "vendor-id", &port->vendor_id); 1170 if (ret) 1171 return ret; 1172 1173 ret = of_property_read_u32(of_port, "device-id", &port->device_id); 1174 if (ret) 1175 return ret; 1176 1177 port->refclk = of_clk_get_by_name(of_port, "ref"); 1178 if (IS_ERR(port->refclk)) 1179 return PTR_ERR(port->refclk); 1180 1181 return 0; 1182 } 1183 1184 static int rzg3s_pcie_host_init_port(struct rzg3s_pcie_host *host) 1185 { 1186 struct rzg3s_pcie_port *port = &host->port; 1187 struct device *dev = host->dev; 1188 int ret; 1189 1190 /* Enable access control to the CFGU */ 1191 writel_relaxed(RZG3S_PCI_PERM_CFG_HWINIT_EN, 1192 host->axi + RZG3S_PCI_PERM); 1193 1194 /* Update vendor ID and device ID */ 1195 writew_relaxed(port->vendor_id, host->pcie + PCI_VENDOR_ID); 1196 writew_relaxed(port->device_id, host->pcie + PCI_DEVICE_ID); 1197 1198 /* Disable access control to the CFGU */ 1199 writel_relaxed(0, host->axi + RZG3S_PCI_PERM); 1200 1201 ret = clk_prepare_enable(port->refclk); 1202 if (ret) 1203 return dev_err_probe(dev, ret, "Failed to enable refclk!\n"); 1204 1205 /* Set the PHY, if any */ 1206 if (host->data->init_phy) { 1207 ret = host->data->init_phy(host); 1208 if (ret) { 1209 dev_err_probe(dev, ret, "Failed to set the PHY!\n"); 1210 goto refclk_disable; 1211 } 1212 } 1213 1214 return 0; 1215 1216 refclk_disable: 1217 clk_disable_unprepare(port->refclk); 1218 return ret; 1219 } 1220 1221 static int rzg3s_pcie_host_init(struct rzg3s_pcie_host *host) 1222 { 1223 u32 val; 1224 int ret; 1225 1226 /* Initialize the PCIe related registers */ 1227 ret = rzg3s_pcie_config_init(host); 1228 if (ret) 1229 return ret; 1230 1231 ret = rzg3s_pcie_host_init_port(host); 1232 if (ret) 1233 return ret; 1234 1235 /* Initialize the interrupts */ 1236 rzg3s_pcie_irq_init(host); 1237 1238 ret = reset_control_bulk_deassert(host->data->num_cfg_resets, 1239 host->cfg_resets); 1240 if (ret) 1241 goto disable_port_refclk; 1242 1243 /* Wait for link up */ 1244 ret = readl_poll_timeout(host->axi + RZG3S_PCI_PCSTAT1, val, 1245 !(val & RZG3S_PCI_PCSTAT1_DL_DOWN_STS), 1246 PCIE_LINK_WAIT_SLEEP_MS * MILLI, 1247 PCIE_LINK_WAIT_SLEEP_MS * MILLI * 1248 PCIE_LINK_WAIT_MAX_RETRIES); 1249 if (ret) 1250 goto cfg_resets_deassert; 1251 1252 val = readl_relaxed(host->axi + RZG3S_PCI_PCSTAT2); 1253 dev_info(host->dev, "PCIe link status [0x%x]\n", val); 1254 1255 return 0; 1256 1257 cfg_resets_deassert: 1258 reset_control_bulk_assert(host->data->num_cfg_resets, 1259 host->cfg_resets); 1260 disable_port_refclk: 1261 clk_disable_unprepare(host->port.refclk); 1262 return ret; 1263 } 1264 1265 static void rzg3s_pcie_set_inbound_window(struct rzg3s_pcie_host *host, 1266 u64 cpu_addr, u64 pci_addr, u64 size, 1267 int id) 1268 { 1269 /* Set CPU window base address */ 1270 writel_relaxed(upper_32_bits(cpu_addr), 1271 host->axi + RZG3S_PCI_ADESTU(id)); 1272 writel_relaxed(lower_32_bits(cpu_addr), 1273 host->axi + RZG3S_PCI_ADESTL(id)); 1274 1275 /* Set window size */ 1276 writel_relaxed(upper_32_bits(size), host->axi + RZG3S_PCI_AWMASKU(id)); 1277 writel_relaxed(lower_32_bits(size), host->axi + RZG3S_PCI_AWMASKL(id)); 1278 1279 /* Set PCIe window base address and enable the window */ 1280 writel_relaxed(upper_32_bits(pci_addr), 1281 host->axi + RZG3S_PCI_AWBASEU(id)); 1282 writel_relaxed(lower_32_bits(pci_addr) | RZG3S_PCI_AWBASEL_WIN_ENA, 1283 host->axi + RZG3S_PCI_AWBASEL(id)); 1284 } 1285 1286 static int rzg3s_pcie_set_inbound_windows(struct rzg3s_pcie_host *host, 1287 struct resource_entry *entry, 1288 int *index) 1289 { 1290 u64 pci_addr = entry->res->start - entry->offset; 1291 u64 cpu_addr = entry->res->start; 1292 u64 cpu_end = entry->res->end; 1293 u64 size_id = 0; 1294 int id = *index; 1295 u64 size; 1296 1297 while (cpu_addr < cpu_end) { 1298 if (id >= RZG3S_MAX_WINDOWS) 1299 return dev_err_probe(host->dev, -ENOSPC, 1300 "Failed to map inbound window for resource (%s)\n", 1301 entry->res->name); 1302 1303 size = resource_size(entry->res) - size_id; 1304 1305 /* 1306 * According to the RZ/G3S HW manual (Rev.1.10, 1307 * section 34.3.1.71 AXI Window Mask (Lower) Registers) the min 1308 * size is 4K. 1309 */ 1310 size = max(size, SZ_4K); 1311 1312 /* 1313 * According the RZ/G3S HW manual (Rev.1.10, sections: 1314 * - 34.3.1.69 AXI Window Base (Lower) Registers 1315 * - 34.3.1.71 AXI Window Mask (Lower) Registers 1316 * - 34.3.1.73 AXI Destination (Lower) Registers) 1317 * the CPU addr, PCIe addr, size should be 4K aligned and be a 1318 * power of 2. 1319 */ 1320 size = ALIGN(size, SZ_4K); 1321 size = roundup_pow_of_two(size); 1322 1323 cpu_addr = ALIGN(cpu_addr, SZ_4K); 1324 pci_addr = ALIGN(pci_addr, SZ_4K); 1325 1326 /* 1327 * According to the RZ/G3S HW manual (Rev.1.10, section 1328 * 34.3.1.71 AXI Window Mask (Lower) Registers) HW expects first 1329 * 12 LSB bits to be 0xfff. Subtract 1 from size for this. 1330 */ 1331 rzg3s_pcie_set_inbound_window(host, cpu_addr, pci_addr, 1332 size - 1, id); 1333 1334 pci_addr += size; 1335 cpu_addr += size; 1336 size_id = size; 1337 id++; 1338 } 1339 *index = id; 1340 1341 return 0; 1342 } 1343 1344 static int rzg3s_pcie_parse_map_dma_ranges(struct rzg3s_pcie_host *host) 1345 { 1346 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(host); 1347 struct resource_entry *entry; 1348 int i = 0, ret; 1349 1350 resource_list_for_each_entry(entry, &bridge->dma_ranges) { 1351 ret = rzg3s_pcie_set_inbound_windows(host, entry, &i); 1352 if (ret) 1353 return ret; 1354 } 1355 1356 return 0; 1357 } 1358 1359 static void rzg3s_pcie_set_outbound_window(struct rzg3s_pcie_host *host, 1360 struct resource_entry *win, int id) 1361 { 1362 struct resource *res = win->res; 1363 resource_size_t size = resource_size(res); 1364 resource_size_t res_start; 1365 1366 if (res->flags & IORESOURCE_IO) 1367 res_start = pci_pio_to_address(res->start) - win->offset; 1368 else 1369 res_start = res->start - win->offset; 1370 1371 /* 1372 * According to the RZ/G3S HW manual (Rev.1.10, section 34.3.1.75 PCIe 1373 * Window Base (Lower) Registers) the window base address need to be 4K 1374 * aligned. 1375 */ 1376 res_start = ALIGN(res_start, SZ_4K); 1377 1378 size = ALIGN(size, SZ_4K); 1379 size = roundup_pow_of_two(size) - 1; 1380 1381 /* Set PCIe destination */ 1382 writel_relaxed(upper_32_bits(res_start), 1383 host->axi + RZG3S_PCI_PDESTU(id)); 1384 writel_relaxed(lower_32_bits(res_start), 1385 host->axi + RZG3S_PCI_PDESTL(id)); 1386 1387 /* Set PCIe window mask */ 1388 writel_relaxed(upper_32_bits(size), host->axi + RZG3S_PCI_PWMASKU(id)); 1389 writel_relaxed(lower_32_bits(size), host->axi + RZG3S_PCI_PWMASKL(id)); 1390 1391 /* Set PCIe window base and enable the window */ 1392 writel_relaxed(upper_32_bits(res_start), 1393 host->axi + RZG3S_PCI_PWBASEU(id)); 1394 writel_relaxed(lower_32_bits(res_start) | RZG3S_PCI_PWBASEL_ENA, 1395 host->axi + RZG3S_PCI_PWBASEL(id)); 1396 } 1397 1398 static int rzg3s_pcie_parse_map_ranges(struct rzg3s_pcie_host *host) 1399 { 1400 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(host); 1401 struct resource_entry *win; 1402 int i = 0; 1403 1404 resource_list_for_each_entry(win, &bridge->windows) { 1405 struct resource *res = win->res; 1406 1407 if (i >= RZG3S_MAX_WINDOWS) 1408 return dev_err_probe(host->dev, -ENOSPC, 1409 "Failed to map outbound window for resource (%s)\n", 1410 res->name); 1411 1412 if (!res->flags) 1413 continue; 1414 1415 switch (resource_type(res)) { 1416 case IORESOURCE_IO: 1417 case IORESOURCE_MEM: 1418 rzg3s_pcie_set_outbound_window(host, win, i); 1419 i++; 1420 break; 1421 } 1422 } 1423 1424 return 0; 1425 } 1426 1427 static int rzg3s_soc_pcie_init_phy(struct rzg3s_pcie_host *host) 1428 { 1429 static const u32 xcfgd_settings[RZG3S_PCI_PHY_XCFGD_NUM] = { 1430 [8] = 0xe0006801, 0x007f7e30, 0x183e0000, 0x978ff500, 1431 0xec000000, 0x009f1400, 0x0000d009, 1432 [17] = 0x78000000, 1433 [19] = 0x00880000, 0x000005c0, 0x07000000, 0x00780920, 1434 0xc9400ce2, 0x90000c0c, 0x000c1414, 0x00005034, 1435 0x00006000, 0x00000001, 1436 }; 1437 static const u32 xcfga_cmn_settings[RZG3S_PCI_PHY_XCFGA_CMN_NUM] = { 1438 0x00000d10, 0x08310100, 0x00c21404, 0x013c0010, 0x01874440, 1439 0x1a216082, 0x00103440, 0x00000080, 0x00000010, 0x0c1000c1, 1440 0x1000c100, 0x0222000c, 0x00640019, 0x00a00028, 0x01d11228, 1441 0x0201001d, 1442 }; 1443 static const u32 xcfga_rx_settings[RZG3S_PCI_PHY_XCFGA_RX_NUM] = { 1444 0x07d55000, 0x030e3f00, 0x00000288, 0x102c5880, 0x0000000b, 1445 0x04141441, 0x00641641, 0x00d63d63, 0x00641641, 0x01970377, 1446 0x00190287, 0x00190028, 0x00000028, 1447 }; 1448 unsigned int i; 1449 1450 /* 1451 * Enable access permission for physical layer control and status 1452 * registers. 1453 */ 1454 writel_relaxed(RZG3S_PCI_PERM_PIPE_PHY_REG_EN, 1455 host->axi + RZG3S_PCI_PERM); 1456 1457 for (i = 0; i < RZG3S_PCI_PHY_XCFGD_NUM; i++) { 1458 writel_relaxed(xcfgd_settings[i], 1459 host->axi + RZG3S_PCI_PHY_XCFGD(i)); 1460 } 1461 1462 for (i = 0; i < RZG3S_PCI_PHY_XCFGA_CMN_NUM; i++) { 1463 writel_relaxed(xcfga_cmn_settings[i], 1464 host->axi + RZG3S_PCI_PHY_XCFGA_CMN(i)); 1465 } 1466 1467 for (i = 0; i < RZG3S_PCI_PHY_XCFGA_RX_NUM; i++) { 1468 writel_relaxed(xcfga_rx_settings[i], 1469 host->axi + RZG3S_PCI_PHY_XCFGA_RX(i)); 1470 } 1471 1472 writel_relaxed(0x107, host->axi + RZG3S_PCI_PHY_XCFGA_TX); 1473 1474 /* Select PHY settings values */ 1475 writel_relaxed(RZG3S_PCI_PHY_XCFG_CTRL_PHYREG_SEL, 1476 host->axi + RZG3S_PCI_PHY_XCFG_CTRL); 1477 1478 /* 1479 * Disable access permission for physical layer control and status 1480 * registers. 1481 */ 1482 writel_relaxed(0, host->axi + RZG3S_PCI_PERM); 1483 1484 return 0; 1485 } 1486 1487 static int 1488 rzg3s_pcie_host_setup(struct rzg3s_pcie_host *host, 1489 int (*init_irqdomain)(struct rzg3s_pcie_host *host), 1490 void (*teardown_irqdomain)(struct rzg3s_pcie_host *host)) 1491 { 1492 struct device *dev = host->dev; 1493 int ret; 1494 1495 /* Set inbound windows */ 1496 ret = rzg3s_pcie_parse_map_dma_ranges(host); 1497 if (ret) 1498 return dev_err_probe(dev, ret, 1499 "Failed to set inbound windows!\n"); 1500 1501 /* Set outbound windows */ 1502 ret = rzg3s_pcie_parse_map_ranges(host); 1503 if (ret) 1504 return dev_err_probe(dev, ret, 1505 "Failed to set outbound windows!\n"); 1506 1507 ret = init_irqdomain(host); 1508 if (ret) 1509 return dev_err_probe(dev, ret, "Failed to init IRQ domain\n"); 1510 1511 ret = rzg3s_pcie_host_init(host); 1512 if (ret) { 1513 dev_err_probe(dev, ret, "Failed to initialize the HW!\n"); 1514 goto teardown_irqdomain; 1515 } 1516 1517 ret = rzg3s_pcie_set_max_link_speed(host); 1518 if (ret) 1519 dev_info(dev, "Failed to set max link speed\n"); 1520 1521 msleep(PCIE_RESET_CONFIG_WAIT_MS); 1522 1523 return 0; 1524 1525 teardown_irqdomain: 1526 teardown_irqdomain(host); 1527 1528 return ret; 1529 } 1530 1531 static int rzg3s_pcie_probe(struct platform_device *pdev) 1532 { 1533 struct pci_host_bridge *bridge; 1534 struct device *dev = &pdev->dev; 1535 struct device_node *np = dev->of_node; 1536 struct device_node *sysc_np __free(device_node) = 1537 of_parse_phandle(np, "renesas,sysc", 0); 1538 struct rzg3s_pcie_host *host; 1539 int ret; 1540 1541 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*host)); 1542 if (!bridge) 1543 return -ENOMEM; 1544 1545 host = pci_host_bridge_priv(bridge); 1546 host->dev = dev; 1547 host->data = device_get_match_data(dev); 1548 platform_set_drvdata(pdev, host); 1549 1550 host->axi = devm_platform_ioremap_resource(pdev, 0); 1551 if (IS_ERR(host->axi)) 1552 return PTR_ERR(host->axi); 1553 host->pcie = host->axi + RZG3S_PCI_CFG_BASE; 1554 1555 host->max_link_speed = of_pci_get_max_link_speed(np); 1556 if (host->max_link_speed < 0) 1557 host->max_link_speed = 2; 1558 1559 ret = rzg3s_pcie_host_parse_port(host); 1560 if (ret) 1561 return ret; 1562 1563 host->sysc = syscon_node_to_regmap(sysc_np); 1564 if (IS_ERR(host->sysc)) { 1565 ret = PTR_ERR(host->sysc); 1566 goto port_refclk_put; 1567 } 1568 1569 ret = regmap_update_bits(host->sysc, RZG3S_SYS_PCIE_RST_RSM_B, 1570 RZG3S_SYS_PCIE_RST_RSM_B_MASK, 1571 FIELD_PREP(RZG3S_SYS_PCIE_RST_RSM_B_MASK, 1)); 1572 if (ret) 1573 goto port_refclk_put; 1574 1575 ret = rzg3s_pcie_resets_prepare_and_get(host); 1576 if (ret) 1577 goto sysc_signal_restore; 1578 1579 ret = rzg3s_pcie_power_resets_deassert(host); 1580 if (ret) 1581 goto sysc_signal_restore; 1582 1583 pm_runtime_enable(dev); 1584 1585 /* 1586 * Controller clocks are part of a clock power domain. Enable them 1587 * through runtime PM. 1588 */ 1589 ret = pm_runtime_resume_and_get(dev); 1590 if (ret) 1591 goto rpm_disable; 1592 1593 raw_spin_lock_init(&host->hw_lock); 1594 1595 ret = rzg3s_pcie_host_setup(host, rzg3s_pcie_init_irqdomain, 1596 rzg3s_pcie_teardown_irqdomain); 1597 if (ret) 1598 goto rpm_put; 1599 1600 bridge->sysdata = host; 1601 bridge->ops = &rzg3s_pcie_root_ops; 1602 bridge->child_ops = &rzg3s_pcie_child_ops; 1603 ret = pci_host_probe(bridge); 1604 if (ret) 1605 goto host_probe_teardown; 1606 1607 return 0; 1608 1609 host_probe_teardown: 1610 rzg3s_pcie_teardown_irqdomain(host); 1611 reset_control_bulk_deassert(host->data->num_cfg_resets, 1612 host->cfg_resets); 1613 rpm_put: 1614 pm_runtime_put_sync(dev); 1615 rpm_disable: 1616 pm_runtime_disable(dev); 1617 reset_control_bulk_assert(host->data->num_power_resets, 1618 host->power_resets); 1619 sysc_signal_restore: 1620 /* 1621 * SYSC RST_RSM_B signal need to be asserted before turning off the 1622 * power to the PHY. 1623 */ 1624 regmap_update_bits(host->sysc, RZG3S_SYS_PCIE_RST_RSM_B, 1625 RZG3S_SYS_PCIE_RST_RSM_B_MASK, 1626 FIELD_PREP(RZG3S_SYS_PCIE_RST_RSM_B_MASK, 0)); 1627 port_refclk_put: 1628 clk_put(host->port.refclk); 1629 1630 return ret; 1631 } 1632 1633 static int rzg3s_pcie_suspend_noirq(struct device *dev) 1634 { 1635 struct rzg3s_pcie_host *host = dev_get_drvdata(dev); 1636 const struct rzg3s_pcie_soc_data *data = host->data; 1637 struct rzg3s_pcie_port *port = &host->port; 1638 struct regmap *sysc = host->sysc; 1639 int ret; 1640 1641 ret = pm_runtime_put_sync(dev); 1642 if (ret) 1643 return ret; 1644 1645 clk_disable_unprepare(port->refclk); 1646 1647 ret = reset_control_bulk_assert(data->num_power_resets, 1648 host->power_resets); 1649 if (ret) 1650 goto refclk_restore; 1651 1652 ret = reset_control_bulk_assert(data->num_cfg_resets, 1653 host->cfg_resets); 1654 if (ret) 1655 goto power_resets_restore; 1656 1657 ret = regmap_update_bits(sysc, RZG3S_SYS_PCIE_RST_RSM_B, 1658 RZG3S_SYS_PCIE_RST_RSM_B_MASK, 1659 FIELD_PREP(RZG3S_SYS_PCIE_RST_RSM_B_MASK, 0)); 1660 if (ret) 1661 goto cfg_resets_restore; 1662 1663 return 0; 1664 1665 /* Restore the previous state if any error happens */ 1666 cfg_resets_restore: 1667 reset_control_bulk_deassert(data->num_cfg_resets, 1668 host->cfg_resets); 1669 power_resets_restore: 1670 reset_control_bulk_deassert(data->num_power_resets, 1671 host->power_resets); 1672 refclk_restore: 1673 clk_prepare_enable(port->refclk); 1674 pm_runtime_resume_and_get(dev); 1675 return ret; 1676 } 1677 1678 static int rzg3s_pcie_resume_noirq(struct device *dev) 1679 { 1680 struct rzg3s_pcie_host *host = dev_get_drvdata(dev); 1681 const struct rzg3s_pcie_soc_data *data = host->data; 1682 struct regmap *sysc = host->sysc; 1683 int ret; 1684 1685 ret = regmap_update_bits(sysc, RZG3S_SYS_PCIE_RST_RSM_B, 1686 RZG3S_SYS_PCIE_RST_RSM_B_MASK, 1687 FIELD_PREP(RZG3S_SYS_PCIE_RST_RSM_B_MASK, 1)); 1688 if (ret) 1689 return ret; 1690 1691 ret = rzg3s_pcie_power_resets_deassert(host); 1692 if (ret) 1693 goto assert_rst_rsm_b; 1694 1695 ret = pm_runtime_resume_and_get(dev); 1696 if (ret) 1697 goto assert_power_resets; 1698 1699 ret = rzg3s_pcie_host_setup(host, rzg3s_pcie_msi_hw_setup, 1700 rzg3s_pcie_msi_hw_teardown); 1701 if (ret) 1702 goto rpm_put; 1703 1704 return 0; 1705 1706 /* 1707 * If any error happens there is no way to recover the IP. Put it in the 1708 * lowest possible power state. 1709 */ 1710 rpm_put: 1711 pm_runtime_put_sync(dev); 1712 assert_power_resets: 1713 reset_control_bulk_assert(data->num_power_resets, 1714 host->power_resets); 1715 assert_rst_rsm_b: 1716 regmap_update_bits(sysc, RZG3S_SYS_PCIE_RST_RSM_B, 1717 RZG3S_SYS_PCIE_RST_RSM_B_MASK, 1718 FIELD_PREP(RZG3S_SYS_PCIE_RST_RSM_B_MASK, 0)); 1719 return ret; 1720 } 1721 1722 static const struct dev_pm_ops rzg3s_pcie_pm_ops = { 1723 NOIRQ_SYSTEM_SLEEP_PM_OPS(rzg3s_pcie_suspend_noirq, 1724 rzg3s_pcie_resume_noirq) 1725 }; 1726 1727 static const char * const rzg3s_soc_power_resets[] = { 1728 "aresetn", "rst_cfg_b", "rst_load_b", 1729 }; 1730 1731 static const char * const rzg3s_soc_cfg_resets[] = { 1732 "rst_b", "rst_ps_b", "rst_gp_b", "rst_rsm_b", 1733 }; 1734 1735 static const struct rzg3s_pcie_soc_data rzg3s_soc_data = { 1736 .power_resets = rzg3s_soc_power_resets, 1737 .num_power_resets = ARRAY_SIZE(rzg3s_soc_power_resets), 1738 .cfg_resets = rzg3s_soc_cfg_resets, 1739 .num_cfg_resets = ARRAY_SIZE(rzg3s_soc_cfg_resets), 1740 .init_phy = rzg3s_soc_pcie_init_phy, 1741 }; 1742 1743 static const struct of_device_id rzg3s_pcie_of_match[] = { 1744 { 1745 .compatible = "renesas,r9a08g045-pcie", 1746 .data = &rzg3s_soc_data, 1747 }, 1748 {} 1749 }; 1750 1751 static struct platform_driver rzg3s_pcie_driver = { 1752 .driver = { 1753 .name = "rzg3s-pcie-host", 1754 .of_match_table = rzg3s_pcie_of_match, 1755 .pm = pm_ptr(&rzg3s_pcie_pm_ops), 1756 .suppress_bind_attrs = true, 1757 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 1758 }, 1759 .probe = rzg3s_pcie_probe, 1760 }; 1761 builtin_platform_driver(rzg3s_pcie_driver); 1762