1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Rockchip AXI PCIe host controller driver 4 * 5 * Copyright (c) 2016 Rockchip, Inc. 6 * 7 * Author: Shawn Lin <shawn.lin@rock-chips.com> 8 * Wenrui Li <wenrui.li@rock-chips.com> 9 * 10 * Bits taken from Synopsys DesignWare Host controller driver and 11 * ARM PCI Host generic driver. 12 */ 13 14 #include <linux/bitrev.h> 15 #include <linux/clk.h> 16 #include <linux/delay.h> 17 #include <linux/gpio/consumer.h> 18 #include <linux/init.h> 19 #include <linux/interrupt.h> 20 #include <linux/iopoll.h> 21 #include <linux/irq.h> 22 #include <linux/irqchip/chained_irq.h> 23 #include <linux/irqdomain.h> 24 #include <linux/kernel.h> 25 #include <linux/mfd/syscon.h> 26 #include <linux/module.h> 27 #include <linux/of_address.h> 28 #include <linux/of_device.h> 29 #include <linux/of_pci.h> 30 #include <linux/of_platform.h> 31 #include <linux/of_irq.h> 32 #include <linux/pci.h> 33 #include <linux/pci_ids.h> 34 #include <linux/phy/phy.h> 35 #include <linux/platform_device.h> 36 #include <linux/reset.h> 37 #include <linux/regmap.h> 38 39 #include "../pci.h" 40 #include "pcie-rockchip.h" 41 42 static void rockchip_pcie_enable_bw_int(struct rockchip_pcie *rockchip) 43 { 44 u32 status; 45 46 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS); 47 status |= (PCI_EXP_LNKCTL_LBMIE | PCI_EXP_LNKCTL_LABIE); 48 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS); 49 } 50 51 static void rockchip_pcie_clr_bw_int(struct rockchip_pcie *rockchip) 52 { 53 u32 status; 54 55 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS); 56 status |= (PCI_EXP_LNKSTA_LBMS | PCI_EXP_LNKSTA_LABS) << 16; 57 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS); 58 } 59 60 static void rockchip_pcie_update_txcredit_mui(struct rockchip_pcie *rockchip) 61 { 62 u32 val; 63 64 /* Update Tx credit maximum update interval */ 65 val = rockchip_pcie_read(rockchip, PCIE_CORE_TXCREDIT_CFG1); 66 val &= ~PCIE_CORE_TXCREDIT_CFG1_MUI_MASK; 67 val |= PCIE_CORE_TXCREDIT_CFG1_MUI_ENCODE(24000); /* ns */ 68 rockchip_pcie_write(rockchip, val, PCIE_CORE_TXCREDIT_CFG1); 69 } 70 71 static int rockchip_pcie_valid_device(struct rockchip_pcie *rockchip, 72 struct pci_bus *bus, int dev) 73 { 74 /* access only one slot on each root port */ 75 if (bus->number == rockchip->root_bus_nr && dev > 0) 76 return 0; 77 78 /* 79 * do not read more than one device on the bus directly attached 80 * to RC's downstream side. 81 */ 82 if (bus->primary == rockchip->root_bus_nr && dev > 0) 83 return 0; 84 85 return 1; 86 } 87 88 static u8 rockchip_pcie_lane_map(struct rockchip_pcie *rockchip) 89 { 90 u32 val; 91 u8 map; 92 93 if (rockchip->legacy_phy) 94 return GENMASK(MAX_LANE_NUM - 1, 0); 95 96 val = rockchip_pcie_read(rockchip, PCIE_CORE_LANE_MAP); 97 map = val & PCIE_CORE_LANE_MAP_MASK; 98 99 /* The link may be using a reverse-indexed mapping. */ 100 if (val & PCIE_CORE_LANE_MAP_REVERSE) 101 map = bitrev8(map) >> 4; 102 103 return map; 104 } 105 106 static int rockchip_pcie_rd_own_conf(struct rockchip_pcie *rockchip, 107 int where, int size, u32 *val) 108 { 109 void __iomem *addr; 110 111 addr = rockchip->apb_base + PCIE_RC_CONFIG_NORMAL_BASE + where; 112 113 if (!IS_ALIGNED((uintptr_t)addr, size)) { 114 *val = 0; 115 return PCIBIOS_BAD_REGISTER_NUMBER; 116 } 117 118 if (size == 4) { 119 *val = readl(addr); 120 } else if (size == 2) { 121 *val = readw(addr); 122 } else if (size == 1) { 123 *val = readb(addr); 124 } else { 125 *val = 0; 126 return PCIBIOS_BAD_REGISTER_NUMBER; 127 } 128 return PCIBIOS_SUCCESSFUL; 129 } 130 131 static int rockchip_pcie_wr_own_conf(struct rockchip_pcie *rockchip, 132 int where, int size, u32 val) 133 { 134 u32 mask, tmp, offset; 135 void __iomem *addr; 136 137 offset = where & ~0x3; 138 addr = rockchip->apb_base + PCIE_RC_CONFIG_NORMAL_BASE + offset; 139 140 if (size == 4) { 141 writel(val, addr); 142 return PCIBIOS_SUCCESSFUL; 143 } 144 145 mask = ~(((1 << (size * 8)) - 1) << ((where & 0x3) * 8)); 146 147 /* 148 * N.B. This read/modify/write isn't safe in general because it can 149 * corrupt RW1C bits in adjacent registers. But the hardware 150 * doesn't support smaller writes. 151 */ 152 tmp = readl(addr) & mask; 153 tmp |= val << ((where & 0x3) * 8); 154 writel(tmp, addr); 155 156 return PCIBIOS_SUCCESSFUL; 157 } 158 159 static int rockchip_pcie_rd_other_conf(struct rockchip_pcie *rockchip, 160 struct pci_bus *bus, u32 devfn, 161 int where, int size, u32 *val) 162 { 163 u32 busdev; 164 165 busdev = PCIE_ECAM_ADDR(bus->number, PCI_SLOT(devfn), 166 PCI_FUNC(devfn), where); 167 168 if (!IS_ALIGNED(busdev, size)) { 169 *val = 0; 170 return PCIBIOS_BAD_REGISTER_NUMBER; 171 } 172 173 if (bus->parent->number == rockchip->root_bus_nr) 174 rockchip_pcie_cfg_configuration_accesses(rockchip, 175 AXI_WRAPPER_TYPE0_CFG); 176 else 177 rockchip_pcie_cfg_configuration_accesses(rockchip, 178 AXI_WRAPPER_TYPE1_CFG); 179 180 if (size == 4) { 181 *val = readl(rockchip->reg_base + busdev); 182 } else if (size == 2) { 183 *val = readw(rockchip->reg_base + busdev); 184 } else if (size == 1) { 185 *val = readb(rockchip->reg_base + busdev); 186 } else { 187 *val = 0; 188 return PCIBIOS_BAD_REGISTER_NUMBER; 189 } 190 return PCIBIOS_SUCCESSFUL; 191 } 192 193 static int rockchip_pcie_wr_other_conf(struct rockchip_pcie *rockchip, 194 struct pci_bus *bus, u32 devfn, 195 int where, int size, u32 val) 196 { 197 u32 busdev; 198 199 busdev = PCIE_ECAM_ADDR(bus->number, PCI_SLOT(devfn), 200 PCI_FUNC(devfn), where); 201 if (!IS_ALIGNED(busdev, size)) 202 return PCIBIOS_BAD_REGISTER_NUMBER; 203 204 if (bus->parent->number == rockchip->root_bus_nr) 205 rockchip_pcie_cfg_configuration_accesses(rockchip, 206 AXI_WRAPPER_TYPE0_CFG); 207 else 208 rockchip_pcie_cfg_configuration_accesses(rockchip, 209 AXI_WRAPPER_TYPE1_CFG); 210 211 if (size == 4) 212 writel(val, rockchip->reg_base + busdev); 213 else if (size == 2) 214 writew(val, rockchip->reg_base + busdev); 215 else if (size == 1) 216 writeb(val, rockchip->reg_base + busdev); 217 else 218 return PCIBIOS_BAD_REGISTER_NUMBER; 219 220 return PCIBIOS_SUCCESSFUL; 221 } 222 223 static int rockchip_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, 224 int size, u32 *val) 225 { 226 struct rockchip_pcie *rockchip = bus->sysdata; 227 228 if (!rockchip_pcie_valid_device(rockchip, bus, PCI_SLOT(devfn))) { 229 *val = 0xffffffff; 230 return PCIBIOS_DEVICE_NOT_FOUND; 231 } 232 233 if (bus->number == rockchip->root_bus_nr) 234 return rockchip_pcie_rd_own_conf(rockchip, where, size, val); 235 236 return rockchip_pcie_rd_other_conf(rockchip, bus, devfn, where, size, 237 val); 238 } 239 240 static int rockchip_pcie_wr_conf(struct pci_bus *bus, u32 devfn, 241 int where, int size, u32 val) 242 { 243 struct rockchip_pcie *rockchip = bus->sysdata; 244 245 if (!rockchip_pcie_valid_device(rockchip, bus, PCI_SLOT(devfn))) 246 return PCIBIOS_DEVICE_NOT_FOUND; 247 248 if (bus->number == rockchip->root_bus_nr) 249 return rockchip_pcie_wr_own_conf(rockchip, where, size, val); 250 251 return rockchip_pcie_wr_other_conf(rockchip, bus, devfn, where, size, 252 val); 253 } 254 255 static struct pci_ops rockchip_pcie_ops = { 256 .read = rockchip_pcie_rd_conf, 257 .write = rockchip_pcie_wr_conf, 258 }; 259 260 static void rockchip_pcie_set_power_limit(struct rockchip_pcie *rockchip) 261 { 262 int curr; 263 u32 status, scale, power; 264 265 if (IS_ERR(rockchip->vpcie3v3)) 266 return; 267 268 /* 269 * Set RC's captured slot power limit and scale if 270 * vpcie3v3 available. The default values are both zero 271 * which means the software should set these two according 272 * to the actual power supply. 273 */ 274 curr = regulator_get_current_limit(rockchip->vpcie3v3); 275 if (curr <= 0) 276 return; 277 278 scale = 3; /* 0.001x */ 279 curr = curr / 1000; /* convert to mA */ 280 power = (curr * 3300) / 1000; /* milliwatt */ 281 while (power > PCIE_RC_CONFIG_DCR_CSPL_LIMIT) { 282 if (!scale) { 283 dev_warn(rockchip->dev, "invalid power supply\n"); 284 return; 285 } 286 scale--; 287 power = power / 10; 288 } 289 290 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_DCR); 291 status |= (power << PCIE_RC_CONFIG_DCR_CSPL_SHIFT) | 292 (scale << PCIE_RC_CONFIG_DCR_CPLS_SHIFT); 293 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_DCR); 294 } 295 296 /** 297 * rockchip_pcie_host_init_port - Initialize hardware 298 * @rockchip: PCIe port information 299 */ 300 static int rockchip_pcie_host_init_port(struct rockchip_pcie *rockchip) 301 { 302 struct device *dev = rockchip->dev; 303 int err, i = MAX_LANE_NUM; 304 u32 status; 305 306 gpiod_set_value_cansleep(rockchip->ep_gpio, 0); 307 308 err = rockchip_pcie_init_port(rockchip); 309 if (err) 310 return err; 311 312 /* Fix the transmitted FTS count desired to exit from L0s. */ 313 status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL_PLC1); 314 status = (status & ~PCIE_CORE_CTRL_PLC1_FTS_MASK) | 315 (PCIE_CORE_CTRL_PLC1_FTS_CNT << PCIE_CORE_CTRL_PLC1_FTS_SHIFT); 316 rockchip_pcie_write(rockchip, status, PCIE_CORE_CTRL_PLC1); 317 318 rockchip_pcie_set_power_limit(rockchip); 319 320 /* Set RC's clock architecture as common clock */ 321 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS); 322 status |= PCI_EXP_LNKSTA_SLC << 16; 323 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS); 324 325 /* Set RC's RCB to 128 */ 326 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS); 327 status |= PCI_EXP_LNKCTL_RCB; 328 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS); 329 330 /* Enable Gen1 training */ 331 rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE, 332 PCIE_CLIENT_CONFIG); 333 334 gpiod_set_value_cansleep(rockchip->ep_gpio, 1); 335 336 /* 500ms timeout value should be enough for Gen1/2 training */ 337 err = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_BASIC_STATUS1, 338 status, PCIE_LINK_UP(status), 20, 339 500 * USEC_PER_MSEC); 340 if (err) { 341 dev_err(dev, "PCIe link training gen1 timeout!\n"); 342 goto err_power_off_phy; 343 } 344 345 if (rockchip->link_gen == 2) { 346 /* 347 * Enable retrain for gen2. This should be configured only after 348 * gen1 finished. 349 */ 350 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS); 351 status |= PCI_EXP_LNKCTL_RL; 352 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS); 353 354 err = readl_poll_timeout(rockchip->apb_base + PCIE_CORE_CTRL, 355 status, PCIE_LINK_IS_GEN2(status), 20, 356 500 * USEC_PER_MSEC); 357 if (err) 358 dev_dbg(dev, "PCIe link training gen2 timeout, fall back to gen1!\n"); 359 } 360 361 /* Check the final link width from negotiated lane counter from MGMT */ 362 status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL); 363 status = 0x1 << ((status & PCIE_CORE_PL_CONF_LANE_MASK) >> 364 PCIE_CORE_PL_CONF_LANE_SHIFT); 365 dev_dbg(dev, "current link width is x%d\n", status); 366 367 /* Power off unused lane(s) */ 368 rockchip->lanes_map = rockchip_pcie_lane_map(rockchip); 369 for (i = 0; i < MAX_LANE_NUM; i++) { 370 if (!(rockchip->lanes_map & BIT(i))) { 371 dev_dbg(dev, "idling lane %d\n", i); 372 phy_power_off(rockchip->phys[i]); 373 } 374 } 375 376 rockchip_pcie_write(rockchip, ROCKCHIP_VENDOR_ID, 377 PCIE_CORE_CONFIG_VENDOR); 378 rockchip_pcie_write(rockchip, 379 PCI_CLASS_BRIDGE_PCI << PCIE_RC_CONFIG_SCC_SHIFT, 380 PCIE_RC_CONFIG_RID_CCR); 381 382 /* Clear THP cap's next cap pointer to remove L1 substate cap */ 383 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_THP_CAP); 384 status &= ~PCIE_RC_CONFIG_THP_CAP_NEXT_MASK; 385 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_THP_CAP); 386 387 /* Clear L0s from RC's link cap */ 388 if (of_property_read_bool(dev->of_node, "aspm-no-l0s")) { 389 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LINK_CAP); 390 status &= ~PCIE_RC_CONFIG_LINK_CAP_L0S; 391 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LINK_CAP); 392 } 393 394 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_DCSR); 395 status &= ~PCIE_RC_CONFIG_DCSR_MPS_MASK; 396 status |= PCIE_RC_CONFIG_DCSR_MPS_256; 397 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_DCSR); 398 399 return 0; 400 err_power_off_phy: 401 while (i--) 402 phy_power_off(rockchip->phys[i]); 403 i = MAX_LANE_NUM; 404 while (i--) 405 phy_exit(rockchip->phys[i]); 406 return err; 407 } 408 409 static irqreturn_t rockchip_pcie_subsys_irq_handler(int irq, void *arg) 410 { 411 struct rockchip_pcie *rockchip = arg; 412 struct device *dev = rockchip->dev; 413 u32 reg; 414 u32 sub_reg; 415 416 reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS); 417 if (reg & PCIE_CLIENT_INT_LOCAL) { 418 dev_dbg(dev, "local interrupt received\n"); 419 sub_reg = rockchip_pcie_read(rockchip, PCIE_CORE_INT_STATUS); 420 if (sub_reg & PCIE_CORE_INT_PRFPE) 421 dev_dbg(dev, "parity error detected while reading from the PNP receive FIFO RAM\n"); 422 423 if (sub_reg & PCIE_CORE_INT_CRFPE) 424 dev_dbg(dev, "parity error detected while reading from the Completion Receive FIFO RAM\n"); 425 426 if (sub_reg & PCIE_CORE_INT_RRPE) 427 dev_dbg(dev, "parity error detected while reading from replay buffer RAM\n"); 428 429 if (sub_reg & PCIE_CORE_INT_PRFO) 430 dev_dbg(dev, "overflow occurred in the PNP receive FIFO\n"); 431 432 if (sub_reg & PCIE_CORE_INT_CRFO) 433 dev_dbg(dev, "overflow occurred in the completion receive FIFO\n"); 434 435 if (sub_reg & PCIE_CORE_INT_RT) 436 dev_dbg(dev, "replay timer timed out\n"); 437 438 if (sub_reg & PCIE_CORE_INT_RTR) 439 dev_dbg(dev, "replay timer rolled over after 4 transmissions of the same TLP\n"); 440 441 if (sub_reg & PCIE_CORE_INT_PE) 442 dev_dbg(dev, "phy error detected on receive side\n"); 443 444 if (sub_reg & PCIE_CORE_INT_MTR) 445 dev_dbg(dev, "malformed TLP received from the link\n"); 446 447 if (sub_reg & PCIE_CORE_INT_UCR) 448 dev_dbg(dev, "malformed TLP received from the link\n"); 449 450 if (sub_reg & PCIE_CORE_INT_FCE) 451 dev_dbg(dev, "an error was observed in the flow control advertisements from the other side\n"); 452 453 if (sub_reg & PCIE_CORE_INT_CT) 454 dev_dbg(dev, "a request timed out waiting for completion\n"); 455 456 if (sub_reg & PCIE_CORE_INT_UTC) 457 dev_dbg(dev, "unmapped TC error\n"); 458 459 if (sub_reg & PCIE_CORE_INT_MMVC) 460 dev_dbg(dev, "MSI mask register changes\n"); 461 462 rockchip_pcie_write(rockchip, sub_reg, PCIE_CORE_INT_STATUS); 463 } else if (reg & PCIE_CLIENT_INT_PHY) { 464 dev_dbg(dev, "phy link changes\n"); 465 rockchip_pcie_update_txcredit_mui(rockchip); 466 rockchip_pcie_clr_bw_int(rockchip); 467 } 468 469 rockchip_pcie_write(rockchip, reg & PCIE_CLIENT_INT_LOCAL, 470 PCIE_CLIENT_INT_STATUS); 471 472 return IRQ_HANDLED; 473 } 474 475 static irqreturn_t rockchip_pcie_client_irq_handler(int irq, void *arg) 476 { 477 struct rockchip_pcie *rockchip = arg; 478 struct device *dev = rockchip->dev; 479 u32 reg; 480 481 reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS); 482 if (reg & PCIE_CLIENT_INT_LEGACY_DONE) 483 dev_dbg(dev, "legacy done interrupt received\n"); 484 485 if (reg & PCIE_CLIENT_INT_MSG) 486 dev_dbg(dev, "message done interrupt received\n"); 487 488 if (reg & PCIE_CLIENT_INT_HOT_RST) 489 dev_dbg(dev, "hot reset interrupt received\n"); 490 491 if (reg & PCIE_CLIENT_INT_DPA) 492 dev_dbg(dev, "dpa interrupt received\n"); 493 494 if (reg & PCIE_CLIENT_INT_FATAL_ERR) 495 dev_dbg(dev, "fatal error interrupt received\n"); 496 497 if (reg & PCIE_CLIENT_INT_NFATAL_ERR) 498 dev_dbg(dev, "no fatal error interrupt received\n"); 499 500 if (reg & PCIE_CLIENT_INT_CORR_ERR) 501 dev_dbg(dev, "correctable error interrupt received\n"); 502 503 if (reg & PCIE_CLIENT_INT_PHY) 504 dev_dbg(dev, "phy interrupt received\n"); 505 506 rockchip_pcie_write(rockchip, reg & (PCIE_CLIENT_INT_LEGACY_DONE | 507 PCIE_CLIENT_INT_MSG | PCIE_CLIENT_INT_HOT_RST | 508 PCIE_CLIENT_INT_DPA | PCIE_CLIENT_INT_FATAL_ERR | 509 PCIE_CLIENT_INT_NFATAL_ERR | 510 PCIE_CLIENT_INT_CORR_ERR | 511 PCIE_CLIENT_INT_PHY), 512 PCIE_CLIENT_INT_STATUS); 513 514 return IRQ_HANDLED; 515 } 516 517 static void rockchip_pcie_legacy_int_handler(struct irq_desc *desc) 518 { 519 struct irq_chip *chip = irq_desc_get_chip(desc); 520 struct rockchip_pcie *rockchip = irq_desc_get_handler_data(desc); 521 struct device *dev = rockchip->dev; 522 u32 reg; 523 u32 hwirq; 524 u32 virq; 525 526 chained_irq_enter(chip, desc); 527 528 reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS); 529 reg = (reg & PCIE_CLIENT_INTR_MASK) >> PCIE_CLIENT_INTR_SHIFT; 530 531 while (reg) { 532 hwirq = ffs(reg) - 1; 533 reg &= ~BIT(hwirq); 534 535 virq = irq_find_mapping(rockchip->irq_domain, hwirq); 536 if (virq) 537 generic_handle_irq(virq); 538 else 539 dev_err(dev, "unexpected IRQ, INT%d\n", hwirq); 540 } 541 542 chained_irq_exit(chip, desc); 543 } 544 545 static int rockchip_pcie_setup_irq(struct rockchip_pcie *rockchip) 546 { 547 int irq, err; 548 struct device *dev = rockchip->dev; 549 struct platform_device *pdev = to_platform_device(dev); 550 551 irq = platform_get_irq_byname(pdev, "sys"); 552 if (irq < 0) { 553 dev_err(dev, "missing sys IRQ resource\n"); 554 return irq; 555 } 556 557 err = devm_request_irq(dev, irq, rockchip_pcie_subsys_irq_handler, 558 IRQF_SHARED, "pcie-sys", rockchip); 559 if (err) { 560 dev_err(dev, "failed to request PCIe subsystem IRQ\n"); 561 return err; 562 } 563 564 irq = platform_get_irq_byname(pdev, "legacy"); 565 if (irq < 0) { 566 dev_err(dev, "missing legacy IRQ resource\n"); 567 return irq; 568 } 569 570 irq_set_chained_handler_and_data(irq, 571 rockchip_pcie_legacy_int_handler, 572 rockchip); 573 574 irq = platform_get_irq_byname(pdev, "client"); 575 if (irq < 0) { 576 dev_err(dev, "missing client IRQ resource\n"); 577 return irq; 578 } 579 580 err = devm_request_irq(dev, irq, rockchip_pcie_client_irq_handler, 581 IRQF_SHARED, "pcie-client", rockchip); 582 if (err) { 583 dev_err(dev, "failed to request PCIe client IRQ\n"); 584 return err; 585 } 586 587 return 0; 588 } 589 590 /** 591 * rockchip_pcie_parse_host_dt - Parse Device Tree 592 * @rockchip: PCIe port information 593 * 594 * Return: '0' on success and error value on failure 595 */ 596 static int rockchip_pcie_parse_host_dt(struct rockchip_pcie *rockchip) 597 { 598 struct device *dev = rockchip->dev; 599 int err; 600 601 err = rockchip_pcie_parse_dt(rockchip); 602 if (err) 603 return err; 604 605 err = rockchip_pcie_setup_irq(rockchip); 606 if (err) 607 return err; 608 609 rockchip->vpcie12v = devm_regulator_get_optional(dev, "vpcie12v"); 610 if (IS_ERR(rockchip->vpcie12v)) { 611 if (PTR_ERR(rockchip->vpcie12v) != -ENODEV) 612 return PTR_ERR(rockchip->vpcie12v); 613 dev_info(dev, "no vpcie12v regulator found\n"); 614 } 615 616 rockchip->vpcie3v3 = devm_regulator_get_optional(dev, "vpcie3v3"); 617 if (IS_ERR(rockchip->vpcie3v3)) { 618 if (PTR_ERR(rockchip->vpcie3v3) != -ENODEV) 619 return PTR_ERR(rockchip->vpcie3v3); 620 dev_info(dev, "no vpcie3v3 regulator found\n"); 621 } 622 623 rockchip->vpcie1v8 = devm_regulator_get(dev, "vpcie1v8"); 624 if (IS_ERR(rockchip->vpcie1v8)) 625 return PTR_ERR(rockchip->vpcie1v8); 626 627 rockchip->vpcie0v9 = devm_regulator_get(dev, "vpcie0v9"); 628 if (IS_ERR(rockchip->vpcie0v9)) 629 return PTR_ERR(rockchip->vpcie0v9); 630 631 return 0; 632 } 633 634 static int rockchip_pcie_set_vpcie(struct rockchip_pcie *rockchip) 635 { 636 struct device *dev = rockchip->dev; 637 int err; 638 639 if (!IS_ERR(rockchip->vpcie12v)) { 640 err = regulator_enable(rockchip->vpcie12v); 641 if (err) { 642 dev_err(dev, "fail to enable vpcie12v regulator\n"); 643 goto err_out; 644 } 645 } 646 647 if (!IS_ERR(rockchip->vpcie3v3)) { 648 err = regulator_enable(rockchip->vpcie3v3); 649 if (err) { 650 dev_err(dev, "fail to enable vpcie3v3 regulator\n"); 651 goto err_disable_12v; 652 } 653 } 654 655 err = regulator_enable(rockchip->vpcie1v8); 656 if (err) { 657 dev_err(dev, "fail to enable vpcie1v8 regulator\n"); 658 goto err_disable_3v3; 659 } 660 661 err = regulator_enable(rockchip->vpcie0v9); 662 if (err) { 663 dev_err(dev, "fail to enable vpcie0v9 regulator\n"); 664 goto err_disable_1v8; 665 } 666 667 return 0; 668 669 err_disable_1v8: 670 regulator_disable(rockchip->vpcie1v8); 671 err_disable_3v3: 672 if (!IS_ERR(rockchip->vpcie3v3)) 673 regulator_disable(rockchip->vpcie3v3); 674 err_disable_12v: 675 if (!IS_ERR(rockchip->vpcie12v)) 676 regulator_disable(rockchip->vpcie12v); 677 err_out: 678 return err; 679 } 680 681 static void rockchip_pcie_enable_interrupts(struct rockchip_pcie *rockchip) 682 { 683 rockchip_pcie_write(rockchip, (PCIE_CLIENT_INT_CLI << 16) & 684 (~PCIE_CLIENT_INT_CLI), PCIE_CLIENT_INT_MASK); 685 rockchip_pcie_write(rockchip, (u32)(~PCIE_CORE_INT), 686 PCIE_CORE_INT_MASK); 687 688 rockchip_pcie_enable_bw_int(rockchip); 689 } 690 691 static int rockchip_pcie_intx_map(struct irq_domain *domain, unsigned int irq, 692 irq_hw_number_t hwirq) 693 { 694 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq); 695 irq_set_chip_data(irq, domain->host_data); 696 697 return 0; 698 } 699 700 static const struct irq_domain_ops intx_domain_ops = { 701 .map = rockchip_pcie_intx_map, 702 }; 703 704 static int rockchip_pcie_init_irq_domain(struct rockchip_pcie *rockchip) 705 { 706 struct device *dev = rockchip->dev; 707 struct device_node *intc = of_get_next_child(dev->of_node, NULL); 708 709 if (!intc) { 710 dev_err(dev, "missing child interrupt-controller node\n"); 711 return -EINVAL; 712 } 713 714 rockchip->irq_domain = irq_domain_add_linear(intc, PCI_NUM_INTX, 715 &intx_domain_ops, rockchip); 716 of_node_put(intc); 717 if (!rockchip->irq_domain) { 718 dev_err(dev, "failed to get a INTx IRQ domain\n"); 719 return -EINVAL; 720 } 721 722 return 0; 723 } 724 725 static int rockchip_pcie_prog_ob_atu(struct rockchip_pcie *rockchip, 726 int region_no, int type, u8 num_pass_bits, 727 u32 lower_addr, u32 upper_addr) 728 { 729 u32 ob_addr_0; 730 u32 ob_addr_1; 731 u32 ob_desc_0; 732 u32 aw_offset; 733 734 if (region_no >= MAX_AXI_WRAPPER_REGION_NUM) 735 return -EINVAL; 736 if (num_pass_bits + 1 < 8) 737 return -EINVAL; 738 if (num_pass_bits > 63) 739 return -EINVAL; 740 if (region_no == 0) { 741 if (AXI_REGION_0_SIZE < (2ULL << num_pass_bits)) 742 return -EINVAL; 743 } 744 if (region_no != 0) { 745 if (AXI_REGION_SIZE < (2ULL << num_pass_bits)) 746 return -EINVAL; 747 } 748 749 aw_offset = (region_no << OB_REG_SIZE_SHIFT); 750 751 ob_addr_0 = num_pass_bits & PCIE_CORE_OB_REGION_ADDR0_NUM_BITS; 752 ob_addr_0 |= lower_addr & PCIE_CORE_OB_REGION_ADDR0_LO_ADDR; 753 ob_addr_1 = upper_addr; 754 ob_desc_0 = (1 << 23 | type); 755 756 rockchip_pcie_write(rockchip, ob_addr_0, 757 PCIE_CORE_OB_REGION_ADDR0 + aw_offset); 758 rockchip_pcie_write(rockchip, ob_addr_1, 759 PCIE_CORE_OB_REGION_ADDR1 + aw_offset); 760 rockchip_pcie_write(rockchip, ob_desc_0, 761 PCIE_CORE_OB_REGION_DESC0 + aw_offset); 762 rockchip_pcie_write(rockchip, 0, 763 PCIE_CORE_OB_REGION_DESC1 + aw_offset); 764 765 return 0; 766 } 767 768 static int rockchip_pcie_prog_ib_atu(struct rockchip_pcie *rockchip, 769 int region_no, u8 num_pass_bits, 770 u32 lower_addr, u32 upper_addr) 771 { 772 u32 ib_addr_0; 773 u32 ib_addr_1; 774 u32 aw_offset; 775 776 if (region_no > MAX_AXI_IB_ROOTPORT_REGION_NUM) 777 return -EINVAL; 778 if (num_pass_bits + 1 < MIN_AXI_ADDR_BITS_PASSED) 779 return -EINVAL; 780 if (num_pass_bits > 63) 781 return -EINVAL; 782 783 aw_offset = (region_no << IB_ROOT_PORT_REG_SIZE_SHIFT); 784 785 ib_addr_0 = num_pass_bits & PCIE_CORE_IB_REGION_ADDR0_NUM_BITS; 786 ib_addr_0 |= (lower_addr << 8) & PCIE_CORE_IB_REGION_ADDR0_LO_ADDR; 787 ib_addr_1 = upper_addr; 788 789 rockchip_pcie_write(rockchip, ib_addr_0, PCIE_RP_IB_ADDR0 + aw_offset); 790 rockchip_pcie_write(rockchip, ib_addr_1, PCIE_RP_IB_ADDR1 + aw_offset); 791 792 return 0; 793 } 794 795 static int rockchip_pcie_cfg_atu(struct rockchip_pcie *rockchip) 796 { 797 struct device *dev = rockchip->dev; 798 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(rockchip); 799 struct resource_entry *entry; 800 u64 pci_addr, size; 801 int offset; 802 int err; 803 int reg_no; 804 805 rockchip_pcie_cfg_configuration_accesses(rockchip, 806 AXI_WRAPPER_TYPE0_CFG); 807 entry = resource_list_first_type(&bridge->windows, IORESOURCE_MEM); 808 if (!entry) 809 return -ENODEV; 810 811 size = resource_size(entry->res); 812 pci_addr = entry->res->start - entry->offset; 813 rockchip->msg_bus_addr = pci_addr; 814 815 for (reg_no = 0; reg_no < (size >> 20); reg_no++) { 816 err = rockchip_pcie_prog_ob_atu(rockchip, reg_no + 1, 817 AXI_WRAPPER_MEM_WRITE, 818 20 - 1, 819 pci_addr + (reg_no << 20), 820 0); 821 if (err) { 822 dev_err(dev, "program RC mem outbound ATU failed\n"); 823 return err; 824 } 825 } 826 827 err = rockchip_pcie_prog_ib_atu(rockchip, 2, 32 - 1, 0x0, 0); 828 if (err) { 829 dev_err(dev, "program RC mem inbound ATU failed\n"); 830 return err; 831 } 832 833 entry = resource_list_first_type(&bridge->windows, IORESOURCE_IO); 834 if (!entry) 835 return -ENODEV; 836 837 size = resource_size(entry->res); 838 pci_addr = entry->res->start - entry->offset; 839 840 offset = size >> 20; 841 for (reg_no = 0; reg_no < (size >> 20); reg_no++) { 842 err = rockchip_pcie_prog_ob_atu(rockchip, 843 reg_no + 1 + offset, 844 AXI_WRAPPER_IO_WRITE, 845 20 - 1, 846 pci_addr + (reg_no << 20), 847 0); 848 if (err) { 849 dev_err(dev, "program RC io outbound ATU failed\n"); 850 return err; 851 } 852 } 853 854 /* assign message regions */ 855 rockchip_pcie_prog_ob_atu(rockchip, reg_no + 1 + offset, 856 AXI_WRAPPER_NOR_MSG, 857 20 - 1, 0, 0); 858 859 rockchip->msg_bus_addr += ((reg_no + offset) << 20); 860 return err; 861 } 862 863 static int rockchip_pcie_wait_l2(struct rockchip_pcie *rockchip) 864 { 865 u32 value; 866 int err; 867 868 /* send PME_TURN_OFF message */ 869 writel(0x0, rockchip->msg_region + PCIE_RC_SEND_PME_OFF); 870 871 /* read LTSSM and wait for falling into L2 link state */ 872 err = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_DEBUG_OUT_0, 873 value, PCIE_LINK_IS_L2(value), 20, 874 jiffies_to_usecs(5 * HZ)); 875 if (err) { 876 dev_err(rockchip->dev, "PCIe link enter L2 timeout!\n"); 877 return err; 878 } 879 880 return 0; 881 } 882 883 static int __maybe_unused rockchip_pcie_suspend_noirq(struct device *dev) 884 { 885 struct rockchip_pcie *rockchip = dev_get_drvdata(dev); 886 int ret; 887 888 /* disable core and cli int since we don't need to ack PME_ACK */ 889 rockchip_pcie_write(rockchip, (PCIE_CLIENT_INT_CLI << 16) | 890 PCIE_CLIENT_INT_CLI, PCIE_CLIENT_INT_MASK); 891 rockchip_pcie_write(rockchip, (u32)PCIE_CORE_INT, PCIE_CORE_INT_MASK); 892 893 ret = rockchip_pcie_wait_l2(rockchip); 894 if (ret) { 895 rockchip_pcie_enable_interrupts(rockchip); 896 return ret; 897 } 898 899 rockchip_pcie_deinit_phys(rockchip); 900 901 rockchip_pcie_disable_clocks(rockchip); 902 903 regulator_disable(rockchip->vpcie0v9); 904 905 return ret; 906 } 907 908 static int __maybe_unused rockchip_pcie_resume_noirq(struct device *dev) 909 { 910 struct rockchip_pcie *rockchip = dev_get_drvdata(dev); 911 int err; 912 913 err = regulator_enable(rockchip->vpcie0v9); 914 if (err) { 915 dev_err(dev, "fail to enable vpcie0v9 regulator\n"); 916 return err; 917 } 918 919 err = rockchip_pcie_enable_clocks(rockchip); 920 if (err) 921 goto err_disable_0v9; 922 923 err = rockchip_pcie_host_init_port(rockchip); 924 if (err) 925 goto err_pcie_resume; 926 927 err = rockchip_pcie_cfg_atu(rockchip); 928 if (err) 929 goto err_err_deinit_port; 930 931 /* Need this to enter L1 again */ 932 rockchip_pcie_update_txcredit_mui(rockchip); 933 rockchip_pcie_enable_interrupts(rockchip); 934 935 return 0; 936 937 err_err_deinit_port: 938 rockchip_pcie_deinit_phys(rockchip); 939 err_pcie_resume: 940 rockchip_pcie_disable_clocks(rockchip); 941 err_disable_0v9: 942 regulator_disable(rockchip->vpcie0v9); 943 return err; 944 } 945 946 static int rockchip_pcie_probe(struct platform_device *pdev) 947 { 948 struct rockchip_pcie *rockchip; 949 struct device *dev = &pdev->dev; 950 struct pci_bus *bus, *child; 951 struct pci_host_bridge *bridge; 952 struct resource *bus_res; 953 int err; 954 955 if (!dev->of_node) 956 return -ENODEV; 957 958 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*rockchip)); 959 if (!bridge) 960 return -ENOMEM; 961 962 rockchip = pci_host_bridge_priv(bridge); 963 964 platform_set_drvdata(pdev, rockchip); 965 rockchip->dev = dev; 966 rockchip->is_rc = true; 967 968 err = rockchip_pcie_parse_host_dt(rockchip); 969 if (err) 970 return err; 971 972 err = rockchip_pcie_enable_clocks(rockchip); 973 if (err) 974 return err; 975 976 err = rockchip_pcie_set_vpcie(rockchip); 977 if (err) { 978 dev_err(dev, "failed to set vpcie regulator\n"); 979 goto err_set_vpcie; 980 } 981 982 err = rockchip_pcie_host_init_port(rockchip); 983 if (err) 984 goto err_vpcie; 985 986 rockchip_pcie_enable_interrupts(rockchip); 987 988 err = rockchip_pcie_init_irq_domain(rockchip); 989 if (err < 0) 990 goto err_deinit_port; 991 992 err = pci_parse_request_of_pci_ranges(dev, &bridge->windows, 993 &bridge->dma_ranges, &bus_res); 994 if (err) 995 goto err_remove_irq_domain; 996 997 rockchip->root_bus_nr = bus_res->start; 998 999 err = rockchip_pcie_cfg_atu(rockchip); 1000 if (err) 1001 goto err_remove_irq_domain; 1002 1003 rockchip->msg_region = devm_ioremap(dev, rockchip->msg_bus_addr, SZ_1M); 1004 if (!rockchip->msg_region) { 1005 err = -ENOMEM; 1006 goto err_remove_irq_domain; 1007 } 1008 1009 bridge->dev.parent = dev; 1010 bridge->sysdata = rockchip; 1011 bridge->busnr = 0; 1012 bridge->ops = &rockchip_pcie_ops; 1013 bridge->map_irq = of_irq_parse_and_map_pci; 1014 bridge->swizzle_irq = pci_common_swizzle; 1015 1016 err = pci_scan_root_bus_bridge(bridge); 1017 if (err < 0) 1018 goto err_remove_irq_domain; 1019 1020 bus = bridge->bus; 1021 1022 rockchip->root_bus = bus; 1023 1024 pci_bus_size_bridges(bus); 1025 pci_bus_assign_resources(bus); 1026 list_for_each_entry(child, &bus->children, node) 1027 pcie_bus_configure_settings(child); 1028 1029 pci_bus_add_devices(bus); 1030 return 0; 1031 1032 err_remove_irq_domain: 1033 irq_domain_remove(rockchip->irq_domain); 1034 err_deinit_port: 1035 rockchip_pcie_deinit_phys(rockchip); 1036 err_vpcie: 1037 if (!IS_ERR(rockchip->vpcie12v)) 1038 regulator_disable(rockchip->vpcie12v); 1039 if (!IS_ERR(rockchip->vpcie3v3)) 1040 regulator_disable(rockchip->vpcie3v3); 1041 regulator_disable(rockchip->vpcie1v8); 1042 regulator_disable(rockchip->vpcie0v9); 1043 err_set_vpcie: 1044 rockchip_pcie_disable_clocks(rockchip); 1045 return err; 1046 } 1047 1048 static int rockchip_pcie_remove(struct platform_device *pdev) 1049 { 1050 struct device *dev = &pdev->dev; 1051 struct rockchip_pcie *rockchip = dev_get_drvdata(dev); 1052 1053 pci_stop_root_bus(rockchip->root_bus); 1054 pci_remove_root_bus(rockchip->root_bus); 1055 irq_domain_remove(rockchip->irq_domain); 1056 1057 rockchip_pcie_deinit_phys(rockchip); 1058 1059 rockchip_pcie_disable_clocks(rockchip); 1060 1061 if (!IS_ERR(rockchip->vpcie12v)) 1062 regulator_disable(rockchip->vpcie12v); 1063 if (!IS_ERR(rockchip->vpcie3v3)) 1064 regulator_disable(rockchip->vpcie3v3); 1065 regulator_disable(rockchip->vpcie1v8); 1066 regulator_disable(rockchip->vpcie0v9); 1067 1068 return 0; 1069 } 1070 1071 static const struct dev_pm_ops rockchip_pcie_pm_ops = { 1072 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(rockchip_pcie_suspend_noirq, 1073 rockchip_pcie_resume_noirq) 1074 }; 1075 1076 static const struct of_device_id rockchip_pcie_of_match[] = { 1077 { .compatible = "rockchip,rk3399-pcie", }, 1078 {} 1079 }; 1080 MODULE_DEVICE_TABLE(of, rockchip_pcie_of_match); 1081 1082 static struct platform_driver rockchip_pcie_driver = { 1083 .driver = { 1084 .name = "rockchip-pcie", 1085 .of_match_table = rockchip_pcie_of_match, 1086 .pm = &rockchip_pcie_pm_ops, 1087 }, 1088 .probe = rockchip_pcie_probe, 1089 .remove = rockchip_pcie_remove, 1090 }; 1091 module_platform_driver(rockchip_pcie_driver); 1092 1093 MODULE_AUTHOR("Rockchip Inc"); 1094 MODULE_DESCRIPTION("Rockchip AXI PCIe driver"); 1095 MODULE_LICENSE("GPL v2"); 1096