1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * PCIe driver for Renesas R-Car SoCs 4 * Copyright (C) 2014-2020 Renesas Electronics Europe Ltd 5 * 6 * Based on: 7 * arch/sh/drivers/pci/pcie-sh7786.c 8 * arch/sh/drivers/pci/ops-sh7786.c 9 * Copyright (C) 2009 - 2011 Paul Mundt 10 * 11 * Author: Phil Edworthy <phil.edworthy@renesas.com> 12 */ 13 14 #include <linux/bitops.h> 15 #include <linux/clk.h> 16 #include <linux/clk-provider.h> 17 #include <linux/delay.h> 18 #include <linux/interrupt.h> 19 #include <linux/irq.h> 20 #include <linux/irqdomain.h> 21 #include <linux/kernel.h> 22 #include <linux/init.h> 23 #include <linux/iopoll.h> 24 #include <linux/msi.h> 25 #include <linux/of_address.h> 26 #include <linux/of_irq.h> 27 #include <linux/of_platform.h> 28 #include <linux/pci.h> 29 #include <linux/phy/phy.h> 30 #include <linux/platform_device.h> 31 #include <linux/pm_runtime.h> 32 #include <linux/regulator/consumer.h> 33 34 #include "pcie-rcar.h" 35 36 struct rcar_msi { 37 DECLARE_BITMAP(used, INT_PCI_MSI_NR); 38 struct irq_domain *domain; 39 struct mutex map_lock; 40 spinlock_t mask_lock; 41 int irq1; 42 int irq2; 43 }; 44 45 /* Structure representing the PCIe interface */ 46 struct rcar_pcie_host { 47 struct rcar_pcie pcie; 48 struct phy *phy; 49 struct clk *bus_clk; 50 struct rcar_msi msi; 51 int (*phy_init_fn)(struct rcar_pcie_host *host); 52 }; 53 54 static DEFINE_SPINLOCK(pmsr_lock); 55 56 static int rcar_pcie_wakeup(struct device *pcie_dev, void __iomem *pcie_base) 57 { 58 unsigned long flags; 59 u32 pmsr, val; 60 int ret = 0; 61 62 spin_lock_irqsave(&pmsr_lock, flags); 63 64 if (!pcie_base || pm_runtime_suspended(pcie_dev)) { 65 ret = -EINVAL; 66 goto unlock_exit; 67 } 68 69 pmsr = readl(pcie_base + PMSR); 70 71 /* 72 * Test if the PCIe controller received PM_ENTER_L1 DLLP and 73 * the PCIe controller is not in L1 link state. If true, apply 74 * fix, which will put the controller into L1 link state, from 75 * which it can return to L0s/L0 on its own. 76 */ 77 if ((pmsr & PMEL1RX) && ((pmsr & PMSTATE) != PMSTATE_L1)) { 78 writel(L1IATN, pcie_base + PMCTLR); 79 ret = readl_poll_timeout_atomic(pcie_base + PMSR, val, 80 val & L1FAEG, 10, 1000); 81 WARN(ret, "Timeout waiting for L1 link state, ret=%d\n", ret); 82 writel(L1FAEG | PMEL1RX, pcie_base + PMSR); 83 } 84 85 unlock_exit: 86 spin_unlock_irqrestore(&pmsr_lock, flags); 87 return ret; 88 } 89 90 static struct rcar_pcie_host *msi_to_host(struct rcar_msi *msi) 91 { 92 return container_of(msi, struct rcar_pcie_host, msi); 93 } 94 95 static u32 rcar_read_conf(struct rcar_pcie *pcie, int where) 96 { 97 unsigned int shift = BITS_PER_BYTE * (where & 3); 98 u32 val = rcar_pci_read_reg(pcie, where & ~3); 99 100 return val >> shift; 101 } 102 103 #ifdef CONFIG_ARM 104 #define __rcar_pci_rw_reg_workaround(instr) \ 105 " .arch armv7-a\n" \ 106 "1: " instr " %1, [%2]\n" \ 107 "2: isb\n" \ 108 "3: .pushsection .text.fixup,\"ax\"\n" \ 109 " .align 2\n" \ 110 "4: mov %0, #" __stringify(PCIBIOS_SET_FAILED) "\n" \ 111 " b 3b\n" \ 112 " .popsection\n" \ 113 " .pushsection __ex_table,\"a\"\n" \ 114 " .align 3\n" \ 115 " .long 1b, 4b\n" \ 116 " .long 2b, 4b\n" \ 117 " .popsection\n" 118 #endif 119 120 static int rcar_pci_write_reg_workaround(struct rcar_pcie *pcie, u32 val, 121 unsigned int reg) 122 { 123 int error = PCIBIOS_SUCCESSFUL; 124 #ifdef CONFIG_ARM 125 asm volatile( 126 __rcar_pci_rw_reg_workaround("str") 127 : "+r"(error):"r"(val), "r"(pcie->base + reg) : "memory"); 128 #else 129 rcar_pci_write_reg(pcie, val, reg); 130 #endif 131 return error; 132 } 133 134 static int rcar_pci_read_reg_workaround(struct rcar_pcie *pcie, u32 *val, 135 unsigned int reg) 136 { 137 int error = PCIBIOS_SUCCESSFUL; 138 #ifdef CONFIG_ARM 139 asm volatile( 140 __rcar_pci_rw_reg_workaround("ldr") 141 : "+r"(error), "=r"(*val) : "r"(pcie->base + reg) : "memory"); 142 143 if (error != PCIBIOS_SUCCESSFUL) 144 PCI_SET_ERROR_RESPONSE(val); 145 #else 146 *val = rcar_pci_read_reg(pcie, reg); 147 #endif 148 return error; 149 } 150 151 /* Serialization is provided by 'pci_lock' in drivers/pci/access.c */ 152 static int rcar_pcie_config_access(struct rcar_pcie_host *host, 153 unsigned char access_type, struct pci_bus *bus, 154 unsigned int devfn, int where, u32 *data) 155 { 156 struct rcar_pcie *pcie = &host->pcie; 157 unsigned int dev, func, reg, index; 158 int ret; 159 160 /* Wake the bus up in case it is in L1 state. */ 161 ret = rcar_pcie_wakeup(pcie->dev, pcie->base); 162 if (ret) { 163 PCI_SET_ERROR_RESPONSE(data); 164 return PCIBIOS_SET_FAILED; 165 } 166 167 dev = PCI_SLOT(devfn); 168 func = PCI_FUNC(devfn); 169 reg = where & ~3; 170 index = reg / 4; 171 172 /* 173 * While each channel has its own memory-mapped extended config 174 * space, it's generally only accessible when in endpoint mode. 175 * When in root complex mode, the controller is unable to target 176 * itself with either type 0 or type 1 accesses, and indeed, any 177 * controller initiated target transfer to its own config space 178 * result in a completer abort. 179 * 180 * Each channel effectively only supports a single device, but as 181 * the same channel <-> device access works for any PCI_SLOT() 182 * value, we cheat a bit here and bind the controller's config 183 * space to devfn 0 in order to enable self-enumeration. In this 184 * case the regular ECAR/ECDR path is sidelined and the mangled 185 * config access itself is initiated as an internal bus transaction. 186 */ 187 if (pci_is_root_bus(bus)) { 188 if (dev != 0) 189 return PCIBIOS_DEVICE_NOT_FOUND; 190 191 if (access_type == RCAR_PCI_ACCESS_READ) 192 *data = rcar_pci_read_reg(pcie, PCICONF(index)); 193 else 194 rcar_pci_write_reg(pcie, *data, PCICONF(index)); 195 196 return PCIBIOS_SUCCESSFUL; 197 } 198 199 /* Clear errors */ 200 rcar_pci_write_reg(pcie, rcar_pci_read_reg(pcie, PCIEERRFR), PCIEERRFR); 201 202 /* Set the PIO address */ 203 rcar_pci_write_reg(pcie, PCIE_CONF_BUS(bus->number) | 204 PCIE_CONF_DEV(dev) | PCIE_CONF_FUNC(func) | reg, PCIECAR); 205 206 /* Enable the configuration access */ 207 if (pci_is_root_bus(bus->parent)) 208 rcar_pci_write_reg(pcie, PCIECCTLR_CCIE | TYPE0, PCIECCTLR); 209 else 210 rcar_pci_write_reg(pcie, PCIECCTLR_CCIE | TYPE1, PCIECCTLR); 211 212 /* Check for errors */ 213 if (rcar_pci_read_reg(pcie, PCIEERRFR) & UNSUPPORTED_REQUEST) 214 return PCIBIOS_DEVICE_NOT_FOUND; 215 216 /* Check for master and target aborts */ 217 if (rcar_read_conf(pcie, RCONF(PCI_STATUS)) & 218 (PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT)) 219 return PCIBIOS_DEVICE_NOT_FOUND; 220 221 if (access_type == RCAR_PCI_ACCESS_READ) 222 ret = rcar_pci_read_reg_workaround(pcie, data, PCIECDR); 223 else 224 ret = rcar_pci_write_reg_workaround(pcie, *data, PCIECDR); 225 226 /* Disable the configuration access */ 227 rcar_pci_write_reg(pcie, 0, PCIECCTLR); 228 229 return ret; 230 } 231 232 static int rcar_pcie_read_conf(struct pci_bus *bus, unsigned int devfn, 233 int where, int size, u32 *val) 234 { 235 struct rcar_pcie_host *host = bus->sysdata; 236 int ret; 237 238 ret = rcar_pcie_config_access(host, RCAR_PCI_ACCESS_READ, 239 bus, devfn, where, val); 240 if (ret != PCIBIOS_SUCCESSFUL) 241 return ret; 242 243 if (size == 1) 244 *val = (*val >> (BITS_PER_BYTE * (where & 3))) & 0xff; 245 else if (size == 2) 246 *val = (*val >> (BITS_PER_BYTE * (where & 2))) & 0xffff; 247 248 dev_dbg(&bus->dev, "pcie-config-read: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08x\n", 249 bus->number, devfn, where, size, *val); 250 251 return ret; 252 } 253 254 /* Serialization is provided by 'pci_lock' in drivers/pci/access.c */ 255 static int rcar_pcie_write_conf(struct pci_bus *bus, unsigned int devfn, 256 int where, int size, u32 val) 257 { 258 struct rcar_pcie_host *host = bus->sysdata; 259 unsigned int shift; 260 u32 data; 261 int ret; 262 263 ret = rcar_pcie_config_access(host, RCAR_PCI_ACCESS_READ, 264 bus, devfn, where, &data); 265 if (ret != PCIBIOS_SUCCESSFUL) 266 return ret; 267 268 dev_dbg(&bus->dev, "pcie-config-write: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08x\n", 269 bus->number, devfn, where, size, val); 270 271 if (size == 1) { 272 shift = BITS_PER_BYTE * (where & 3); 273 data &= ~(0xff << shift); 274 data |= ((val & 0xff) << shift); 275 } else if (size == 2) { 276 shift = BITS_PER_BYTE * (where & 2); 277 data &= ~(0xffff << shift); 278 data |= ((val & 0xffff) << shift); 279 } else 280 data = val; 281 282 ret = rcar_pcie_config_access(host, RCAR_PCI_ACCESS_WRITE, 283 bus, devfn, where, &data); 284 285 return ret; 286 } 287 288 static struct pci_ops rcar_pcie_ops = { 289 .read = rcar_pcie_read_conf, 290 .write = rcar_pcie_write_conf, 291 }; 292 293 static void rcar_pcie_force_speedup(struct rcar_pcie *pcie) 294 { 295 struct device *dev = pcie->dev; 296 unsigned int timeout = 1000; 297 u32 macsr; 298 299 if ((rcar_pci_read_reg(pcie, MACS2R) & LINK_SPEED) != LINK_SPEED_5_0GTS) 300 return; 301 302 if (rcar_pci_read_reg(pcie, MACCTLR) & SPEED_CHANGE) { 303 dev_err(dev, "Speed change already in progress\n"); 304 return; 305 } 306 307 macsr = rcar_pci_read_reg(pcie, MACSR); 308 if ((macsr & LINK_SPEED) == LINK_SPEED_5_0GTS) 309 goto done; 310 311 /* Set target link speed to 5.0 GT/s */ 312 rcar_rmw32(pcie, EXPCAP(12), PCI_EXP_LNKSTA_CLS, 313 PCI_EXP_LNKSTA_CLS_5_0GB); 314 315 /* Set speed change reason as intentional factor */ 316 rcar_rmw32(pcie, MACCGSPSETR, SPCNGRSN, 0); 317 318 /* Clear SPCHGFIN, SPCHGSUC, and SPCHGFAIL */ 319 if (macsr & (SPCHGFIN | SPCHGSUC | SPCHGFAIL)) 320 rcar_pci_write_reg(pcie, macsr, MACSR); 321 322 /* Start link speed change */ 323 rcar_rmw32(pcie, MACCTLR, SPEED_CHANGE, SPEED_CHANGE); 324 325 while (timeout--) { 326 macsr = rcar_pci_read_reg(pcie, MACSR); 327 if (macsr & SPCHGFIN) { 328 /* Clear the interrupt bits */ 329 rcar_pci_write_reg(pcie, macsr, MACSR); 330 331 if (macsr & SPCHGFAIL) 332 dev_err(dev, "Speed change failed\n"); 333 334 goto done; 335 } 336 337 msleep(1); 338 } 339 340 dev_err(dev, "Speed change timed out\n"); 341 342 done: 343 dev_info(dev, "Current link speed is %s GT/s\n", 344 (macsr & LINK_SPEED) == LINK_SPEED_5_0GTS ? "5" : "2.5"); 345 } 346 347 static void rcar_pcie_hw_enable(struct rcar_pcie_host *host) 348 { 349 struct rcar_pcie *pcie = &host->pcie; 350 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(host); 351 struct resource_entry *win; 352 LIST_HEAD(res); 353 int i = 0; 354 355 /* Try setting 5 GT/s link speed */ 356 rcar_pcie_force_speedup(pcie); 357 358 /* Setup PCI resources */ 359 resource_list_for_each_entry(win, &bridge->windows) { 360 struct resource *res = win->res; 361 362 if (!res->flags) 363 continue; 364 365 switch (resource_type(res)) { 366 case IORESOURCE_IO: 367 case IORESOURCE_MEM: 368 rcar_pcie_set_outbound(pcie, i, win); 369 i++; 370 break; 371 } 372 } 373 } 374 375 static int rcar_pcie_enable(struct rcar_pcie_host *host) 376 { 377 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(host); 378 379 rcar_pcie_hw_enable(host); 380 381 pci_add_flags(PCI_REASSIGN_ALL_BUS); 382 383 bridge->sysdata = host; 384 bridge->ops = &rcar_pcie_ops; 385 386 return pci_host_probe(bridge); 387 } 388 389 static int phy_wait_for_ack(struct rcar_pcie *pcie) 390 { 391 struct device *dev = pcie->dev; 392 unsigned int timeout = 100; 393 394 while (timeout--) { 395 if (rcar_pci_read_reg(pcie, H1_PCIEPHYADRR) & PHY_ACK) 396 return 0; 397 398 udelay(100); 399 } 400 401 dev_err(dev, "Access to PCIe phy timed out\n"); 402 403 return -ETIMEDOUT; 404 } 405 406 static void phy_write_reg(struct rcar_pcie *pcie, 407 unsigned int rate, u32 addr, 408 unsigned int lane, u32 data) 409 { 410 u32 phyaddr; 411 412 phyaddr = WRITE_CMD | 413 ((rate & 1) << RATE_POS) | 414 ((lane & 0xf) << LANE_POS) | 415 ((addr & 0xff) << ADR_POS); 416 417 /* Set write data */ 418 rcar_pci_write_reg(pcie, data, H1_PCIEPHYDOUTR); 419 rcar_pci_write_reg(pcie, phyaddr, H1_PCIEPHYADRR); 420 421 /* Ignore errors as they will be dealt with if the data link is down */ 422 phy_wait_for_ack(pcie); 423 424 /* Clear command */ 425 rcar_pci_write_reg(pcie, 0, H1_PCIEPHYDOUTR); 426 rcar_pci_write_reg(pcie, 0, H1_PCIEPHYADRR); 427 428 /* Ignore errors as they will be dealt with if the data link is down */ 429 phy_wait_for_ack(pcie); 430 } 431 432 static int rcar_pcie_hw_init(struct rcar_pcie *pcie) 433 { 434 int err; 435 436 /* Begin initialization */ 437 rcar_pci_write_reg(pcie, 0, PCIETCTLR); 438 439 /* Set mode */ 440 rcar_pci_write_reg(pcie, 1, PCIEMSR); 441 442 err = rcar_pcie_wait_for_phyrdy(pcie); 443 if (err) 444 return err; 445 446 /* 447 * Initial header for port config space is type 1, set the device 448 * class to match. Hardware takes care of propagating the IDSETR 449 * settings, so there is no need to bother with a quirk. 450 */ 451 rcar_pci_write_reg(pcie, PCI_CLASS_BRIDGE_PCI_NORMAL << 8, IDSETR1); 452 453 /* 454 * Setup Secondary Bus Number & Subordinate Bus Number, even though 455 * they aren't used, to avoid bridge being detected as broken. 456 */ 457 rcar_rmw32(pcie, RCONF(PCI_SECONDARY_BUS), 0xff, 1); 458 rcar_rmw32(pcie, RCONF(PCI_SUBORDINATE_BUS), 0xff, 1); 459 460 /* Initialize default capabilities. */ 461 rcar_rmw32(pcie, REXPCAP(0), 0xff, PCI_CAP_ID_EXP); 462 rcar_rmw32(pcie, REXPCAP(PCI_EXP_FLAGS), 463 PCI_EXP_FLAGS_TYPE, PCI_EXP_TYPE_ROOT_PORT << 4); 464 rcar_rmw32(pcie, RCONF(PCI_HEADER_TYPE), PCI_HEADER_TYPE_MASK, 465 PCI_HEADER_TYPE_BRIDGE); 466 467 /* Enable data link layer active state reporting */ 468 rcar_rmw32(pcie, REXPCAP(PCI_EXP_LNKCAP), PCI_EXP_LNKCAP_DLLLARC, 469 PCI_EXP_LNKCAP_DLLLARC); 470 471 /* Write out the physical slot number = 0 */ 472 rcar_rmw32(pcie, REXPCAP(PCI_EXP_SLTCAP), PCI_EXP_SLTCAP_PSN, 0); 473 474 /* Set the completion timer timeout to the maximum 50ms. */ 475 rcar_rmw32(pcie, TLCTLR + 1, 0x3f, 50); 476 477 /* Terminate list of capabilities (Next Capability Offset=0) */ 478 rcar_rmw32(pcie, RVCCAP(0), 0xfff00000, 0); 479 480 /* Enable MSI */ 481 if (IS_ENABLED(CONFIG_PCI_MSI)) 482 rcar_pci_write_reg(pcie, 0x801f0000, PCIEMSITXR); 483 484 rcar_pci_write_reg(pcie, MACCTLR_INIT_VAL, MACCTLR); 485 486 /* Finish initialization - establish a PCI Express link */ 487 rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR); 488 489 /* This will timeout if we don't have a link. */ 490 err = rcar_pcie_wait_for_dl(pcie); 491 if (err) 492 return err; 493 494 /* Enable INTx interrupts */ 495 rcar_rmw32(pcie, PCIEINTXR, 0, 0xF << 8); 496 497 wmb(); 498 499 return 0; 500 } 501 502 static int rcar_pcie_phy_init_h1(struct rcar_pcie_host *host) 503 { 504 struct rcar_pcie *pcie = &host->pcie; 505 506 /* Initialize the phy */ 507 phy_write_reg(pcie, 0, 0x42, 0x1, 0x0EC34191); 508 phy_write_reg(pcie, 1, 0x42, 0x1, 0x0EC34180); 509 phy_write_reg(pcie, 0, 0x43, 0x1, 0x00210188); 510 phy_write_reg(pcie, 1, 0x43, 0x1, 0x00210188); 511 phy_write_reg(pcie, 0, 0x44, 0x1, 0x015C0014); 512 phy_write_reg(pcie, 1, 0x44, 0x1, 0x015C0014); 513 phy_write_reg(pcie, 1, 0x4C, 0x1, 0x786174A0); 514 phy_write_reg(pcie, 1, 0x4D, 0x1, 0x048000BB); 515 phy_write_reg(pcie, 0, 0x51, 0x1, 0x079EC062); 516 phy_write_reg(pcie, 0, 0x52, 0x1, 0x20000000); 517 phy_write_reg(pcie, 1, 0x52, 0x1, 0x20000000); 518 phy_write_reg(pcie, 1, 0x56, 0x1, 0x00003806); 519 520 phy_write_reg(pcie, 0, 0x60, 0x1, 0x004B03A5); 521 phy_write_reg(pcie, 0, 0x64, 0x1, 0x3F0F1F0F); 522 phy_write_reg(pcie, 0, 0x66, 0x1, 0x00008000); 523 524 return 0; 525 } 526 527 static int rcar_pcie_phy_init_gen2(struct rcar_pcie_host *host) 528 { 529 struct rcar_pcie *pcie = &host->pcie; 530 531 /* 532 * These settings come from the R-Car Series, 2nd Generation User's 533 * Manual, section 50.3.1 (2) Initialization of the physical layer. 534 */ 535 rcar_pci_write_reg(pcie, 0x000f0030, GEN2_PCIEPHYADDR); 536 rcar_pci_write_reg(pcie, 0x00381203, GEN2_PCIEPHYDATA); 537 rcar_pci_write_reg(pcie, 0x00000001, GEN2_PCIEPHYCTRL); 538 rcar_pci_write_reg(pcie, 0x00000006, GEN2_PCIEPHYCTRL); 539 540 rcar_pci_write_reg(pcie, 0x000f0054, GEN2_PCIEPHYADDR); 541 /* The following value is for DC connection, no termination resistor */ 542 rcar_pci_write_reg(pcie, 0x13802007, GEN2_PCIEPHYDATA); 543 rcar_pci_write_reg(pcie, 0x00000001, GEN2_PCIEPHYCTRL); 544 rcar_pci_write_reg(pcie, 0x00000006, GEN2_PCIEPHYCTRL); 545 546 return 0; 547 } 548 549 static int rcar_pcie_phy_init_gen3(struct rcar_pcie_host *host) 550 { 551 int err; 552 553 err = phy_init(host->phy); 554 if (err) 555 return err; 556 557 err = phy_power_on(host->phy); 558 if (err) 559 phy_exit(host->phy); 560 561 return err; 562 } 563 564 static irqreturn_t rcar_pcie_msi_irq(int irq, void *data) 565 { 566 struct rcar_pcie_host *host = data; 567 struct rcar_pcie *pcie = &host->pcie; 568 struct rcar_msi *msi = &host->msi; 569 struct device *dev = pcie->dev; 570 unsigned long reg; 571 572 reg = rcar_pci_read_reg(pcie, PCIEMSIFR); 573 574 /* MSI & INTx share an interrupt - we only handle MSI here */ 575 if (!reg) 576 return IRQ_NONE; 577 578 while (reg) { 579 unsigned int index = find_first_bit(®, 32); 580 int ret; 581 582 ret = generic_handle_domain_irq(msi->domain->parent, index); 583 if (ret) { 584 /* Unknown MSI, just clear it */ 585 dev_dbg(dev, "unexpected MSI\n"); 586 rcar_pci_write_reg(pcie, BIT(index), PCIEMSIFR); 587 } 588 589 /* see if there's any more pending in this vector */ 590 reg = rcar_pci_read_reg(pcie, PCIEMSIFR); 591 } 592 593 return IRQ_HANDLED; 594 } 595 596 static void rcar_msi_top_irq_ack(struct irq_data *d) 597 { 598 irq_chip_ack_parent(d); 599 } 600 601 static void rcar_msi_top_irq_mask(struct irq_data *d) 602 { 603 pci_msi_mask_irq(d); 604 irq_chip_mask_parent(d); 605 } 606 607 static void rcar_msi_top_irq_unmask(struct irq_data *d) 608 { 609 pci_msi_unmask_irq(d); 610 irq_chip_unmask_parent(d); 611 } 612 613 static struct irq_chip rcar_msi_top_chip = { 614 .name = "PCIe MSI", 615 .irq_ack = rcar_msi_top_irq_ack, 616 .irq_mask = rcar_msi_top_irq_mask, 617 .irq_unmask = rcar_msi_top_irq_unmask, 618 }; 619 620 static void rcar_msi_irq_ack(struct irq_data *d) 621 { 622 struct rcar_msi *msi = irq_data_get_irq_chip_data(d); 623 struct rcar_pcie *pcie = &msi_to_host(msi)->pcie; 624 625 /* clear the interrupt */ 626 rcar_pci_write_reg(pcie, BIT(d->hwirq), PCIEMSIFR); 627 } 628 629 static void rcar_msi_irq_mask(struct irq_data *d) 630 { 631 struct rcar_msi *msi = irq_data_get_irq_chip_data(d); 632 struct rcar_pcie *pcie = &msi_to_host(msi)->pcie; 633 unsigned long flags; 634 u32 value; 635 636 spin_lock_irqsave(&msi->mask_lock, flags); 637 value = rcar_pci_read_reg(pcie, PCIEMSIIER); 638 value &= ~BIT(d->hwirq); 639 rcar_pci_write_reg(pcie, value, PCIEMSIIER); 640 spin_unlock_irqrestore(&msi->mask_lock, flags); 641 } 642 643 static void rcar_msi_irq_unmask(struct irq_data *d) 644 { 645 struct rcar_msi *msi = irq_data_get_irq_chip_data(d); 646 struct rcar_pcie *pcie = &msi_to_host(msi)->pcie; 647 unsigned long flags; 648 u32 value; 649 650 spin_lock_irqsave(&msi->mask_lock, flags); 651 value = rcar_pci_read_reg(pcie, PCIEMSIIER); 652 value |= BIT(d->hwirq); 653 rcar_pci_write_reg(pcie, value, PCIEMSIIER); 654 spin_unlock_irqrestore(&msi->mask_lock, flags); 655 } 656 657 static int rcar_msi_set_affinity(struct irq_data *d, const struct cpumask *mask, bool force) 658 { 659 return -EINVAL; 660 } 661 662 static void rcar_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) 663 { 664 struct rcar_msi *msi = irq_data_get_irq_chip_data(data); 665 struct rcar_pcie *pcie = &msi_to_host(msi)->pcie; 666 667 msg->address_lo = rcar_pci_read_reg(pcie, PCIEMSIALR) & ~MSIFE; 668 msg->address_hi = rcar_pci_read_reg(pcie, PCIEMSIAUR); 669 msg->data = data->hwirq; 670 } 671 672 static struct irq_chip rcar_msi_bottom_chip = { 673 .name = "R-Car MSI", 674 .irq_ack = rcar_msi_irq_ack, 675 .irq_mask = rcar_msi_irq_mask, 676 .irq_unmask = rcar_msi_irq_unmask, 677 .irq_set_affinity = rcar_msi_set_affinity, 678 .irq_compose_msi_msg = rcar_compose_msi_msg, 679 }; 680 681 static int rcar_msi_domain_alloc(struct irq_domain *domain, unsigned int virq, 682 unsigned int nr_irqs, void *args) 683 { 684 struct rcar_msi *msi = domain->host_data; 685 unsigned int i; 686 int hwirq; 687 688 mutex_lock(&msi->map_lock); 689 690 hwirq = bitmap_find_free_region(msi->used, INT_PCI_MSI_NR, order_base_2(nr_irqs)); 691 692 mutex_unlock(&msi->map_lock); 693 694 if (hwirq < 0) 695 return -ENOSPC; 696 697 for (i = 0; i < nr_irqs; i++) 698 irq_domain_set_info(domain, virq + i, hwirq + i, 699 &rcar_msi_bottom_chip, domain->host_data, 700 handle_edge_irq, NULL, NULL); 701 702 return 0; 703 } 704 705 static void rcar_msi_domain_free(struct irq_domain *domain, unsigned int virq, 706 unsigned int nr_irqs) 707 { 708 struct irq_data *d = irq_domain_get_irq_data(domain, virq); 709 struct rcar_msi *msi = domain->host_data; 710 711 mutex_lock(&msi->map_lock); 712 713 bitmap_release_region(msi->used, d->hwirq, order_base_2(nr_irqs)); 714 715 mutex_unlock(&msi->map_lock); 716 } 717 718 static const struct irq_domain_ops rcar_msi_domain_ops = { 719 .alloc = rcar_msi_domain_alloc, 720 .free = rcar_msi_domain_free, 721 }; 722 723 static struct msi_domain_info rcar_msi_info = { 724 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | 725 MSI_FLAG_MULTI_PCI_MSI), 726 .chip = &rcar_msi_top_chip, 727 }; 728 729 static int rcar_allocate_domains(struct rcar_msi *msi) 730 { 731 struct rcar_pcie *pcie = &msi_to_host(msi)->pcie; 732 struct fwnode_handle *fwnode = dev_fwnode(pcie->dev); 733 struct irq_domain *parent; 734 735 parent = irq_domain_create_linear(fwnode, INT_PCI_MSI_NR, 736 &rcar_msi_domain_ops, msi); 737 if (!parent) { 738 dev_err(pcie->dev, "failed to create IRQ domain\n"); 739 return -ENOMEM; 740 } 741 irq_domain_update_bus_token(parent, DOMAIN_BUS_NEXUS); 742 743 msi->domain = pci_msi_create_irq_domain(fwnode, &rcar_msi_info, parent); 744 if (!msi->domain) { 745 dev_err(pcie->dev, "failed to create MSI domain\n"); 746 irq_domain_remove(parent); 747 return -ENOMEM; 748 } 749 750 return 0; 751 } 752 753 static void rcar_free_domains(struct rcar_msi *msi) 754 { 755 struct irq_domain *parent = msi->domain->parent; 756 757 irq_domain_remove(msi->domain); 758 irq_domain_remove(parent); 759 } 760 761 static int rcar_pcie_enable_msi(struct rcar_pcie_host *host) 762 { 763 struct rcar_pcie *pcie = &host->pcie; 764 struct device *dev = pcie->dev; 765 struct rcar_msi *msi = &host->msi; 766 struct resource res; 767 int err; 768 769 mutex_init(&msi->map_lock); 770 spin_lock_init(&msi->mask_lock); 771 772 err = of_address_to_resource(dev->of_node, 0, &res); 773 if (err) 774 return err; 775 776 err = rcar_allocate_domains(msi); 777 if (err) 778 return err; 779 780 /* Two irqs are for MSI, but they are also used for non-MSI irqs */ 781 err = devm_request_irq(dev, msi->irq1, rcar_pcie_msi_irq, 782 IRQF_SHARED | IRQF_NO_THREAD, 783 rcar_msi_bottom_chip.name, host); 784 if (err < 0) { 785 dev_err(dev, "failed to request IRQ: %d\n", err); 786 goto err; 787 } 788 789 err = devm_request_irq(dev, msi->irq2, rcar_pcie_msi_irq, 790 IRQF_SHARED | IRQF_NO_THREAD, 791 rcar_msi_bottom_chip.name, host); 792 if (err < 0) { 793 dev_err(dev, "failed to request IRQ: %d\n", err); 794 goto err; 795 } 796 797 /* disable all MSIs */ 798 rcar_pci_write_reg(pcie, 0, PCIEMSIIER); 799 800 /* 801 * Setup MSI data target using RC base address address, which 802 * is guaranteed to be in the low 32bit range on any R-Car HW. 803 */ 804 rcar_pci_write_reg(pcie, lower_32_bits(res.start) | MSIFE, PCIEMSIALR); 805 rcar_pci_write_reg(pcie, upper_32_bits(res.start), PCIEMSIAUR); 806 807 return 0; 808 809 err: 810 rcar_free_domains(msi); 811 return err; 812 } 813 814 static void rcar_pcie_teardown_msi(struct rcar_pcie_host *host) 815 { 816 struct rcar_pcie *pcie = &host->pcie; 817 818 /* Disable all MSI interrupts */ 819 rcar_pci_write_reg(pcie, 0, PCIEMSIIER); 820 821 /* Disable address decoding of the MSI interrupt, MSIFE */ 822 rcar_pci_write_reg(pcie, 0, PCIEMSIALR); 823 824 rcar_free_domains(&host->msi); 825 } 826 827 static int rcar_pcie_get_resources(struct rcar_pcie_host *host) 828 { 829 struct rcar_pcie *pcie = &host->pcie; 830 struct device *dev = pcie->dev; 831 struct resource res; 832 int err, i; 833 834 host->phy = devm_phy_optional_get(dev, "pcie"); 835 if (IS_ERR(host->phy)) 836 return PTR_ERR(host->phy); 837 838 err = of_address_to_resource(dev->of_node, 0, &res); 839 if (err) 840 return err; 841 842 pcie->base = devm_ioremap_resource(dev, &res); 843 if (IS_ERR(pcie->base)) 844 return PTR_ERR(pcie->base); 845 846 host->bus_clk = devm_clk_get(dev, "pcie_bus"); 847 if (IS_ERR(host->bus_clk)) { 848 dev_err(dev, "cannot get pcie bus clock\n"); 849 return PTR_ERR(host->bus_clk); 850 } 851 852 i = irq_of_parse_and_map(dev->of_node, 0); 853 if (!i) { 854 dev_err(dev, "cannot get platform resources for msi interrupt\n"); 855 err = -ENOENT; 856 goto err_irq1; 857 } 858 host->msi.irq1 = i; 859 860 i = irq_of_parse_and_map(dev->of_node, 1); 861 if (!i) { 862 dev_err(dev, "cannot get platform resources for msi interrupt\n"); 863 err = -ENOENT; 864 goto err_irq2; 865 } 866 host->msi.irq2 = i; 867 868 return 0; 869 870 err_irq2: 871 irq_dispose_mapping(host->msi.irq1); 872 err_irq1: 873 return err; 874 } 875 876 static int rcar_pcie_inbound_ranges(struct rcar_pcie *pcie, 877 struct resource_entry *entry, 878 int *index) 879 { 880 u64 restype = entry->res->flags; 881 u64 cpu_addr = entry->res->start; 882 u64 cpu_end = entry->res->end; 883 u64 pci_addr = entry->res->start - entry->offset; 884 u32 flags = LAM_64BIT | LAR_ENABLE; 885 u64 mask; 886 u64 size = resource_size(entry->res); 887 int idx = *index; 888 889 if (restype & IORESOURCE_PREFETCH) 890 flags |= LAM_PREFETCH; 891 892 while (cpu_addr < cpu_end) { 893 if (idx >= MAX_NR_INBOUND_MAPS - 1) { 894 dev_err(pcie->dev, "Failed to map inbound regions!\n"); 895 return -EINVAL; 896 } 897 /* 898 * If the size of the range is larger than the alignment of 899 * the start address, we have to use multiple entries to 900 * perform the mapping. 901 */ 902 if (cpu_addr > 0) { 903 unsigned long nr_zeros = __ffs64(cpu_addr); 904 u64 alignment = 1ULL << nr_zeros; 905 906 size = min(size, alignment); 907 } 908 /* Hardware supports max 4GiB inbound region */ 909 size = min(size, 1ULL << 32); 910 911 mask = roundup_pow_of_two(size) - 1; 912 mask &= ~0xf; 913 914 rcar_pcie_set_inbound(pcie, cpu_addr, pci_addr, 915 lower_32_bits(mask) | flags, idx, true); 916 917 pci_addr += size; 918 cpu_addr += size; 919 idx += 2; 920 } 921 *index = idx; 922 923 return 0; 924 } 925 926 static int rcar_pcie_parse_map_dma_ranges(struct rcar_pcie_host *host) 927 { 928 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(host); 929 struct resource_entry *entry; 930 int index = 0, err = 0; 931 932 resource_list_for_each_entry(entry, &bridge->dma_ranges) { 933 err = rcar_pcie_inbound_ranges(&host->pcie, entry, &index); 934 if (err) 935 break; 936 } 937 938 return err; 939 } 940 941 static const struct of_device_id rcar_pcie_of_match[] = { 942 { .compatible = "renesas,pcie-r8a7779", 943 .data = rcar_pcie_phy_init_h1 }, 944 { .compatible = "renesas,pcie-r8a7790", 945 .data = rcar_pcie_phy_init_gen2 }, 946 { .compatible = "renesas,pcie-r8a7791", 947 .data = rcar_pcie_phy_init_gen2 }, 948 { .compatible = "renesas,pcie-rcar-gen2", 949 .data = rcar_pcie_phy_init_gen2 }, 950 { .compatible = "renesas,pcie-r8a7795", 951 .data = rcar_pcie_phy_init_gen3 }, 952 { .compatible = "renesas,pcie-rcar-gen3", 953 .data = rcar_pcie_phy_init_gen3 }, 954 {}, 955 }; 956 957 /* Design note 346 from Linear Technology says order is not important. */ 958 static const char * const rcar_pcie_supplies[] = { 959 "vpcie1v5", 960 "vpcie3v3", 961 "vpcie12v", 962 }; 963 964 static int rcar_pcie_probe(struct platform_device *pdev) 965 { 966 struct device *dev = &pdev->dev; 967 struct pci_host_bridge *bridge; 968 struct rcar_pcie_host *host; 969 struct rcar_pcie *pcie; 970 unsigned int i; 971 u32 data; 972 int err; 973 974 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*host)); 975 if (!bridge) 976 return -ENOMEM; 977 978 host = pci_host_bridge_priv(bridge); 979 pcie = &host->pcie; 980 pcie->dev = dev; 981 platform_set_drvdata(pdev, host); 982 983 for (i = 0; i < ARRAY_SIZE(rcar_pcie_supplies); i++) { 984 err = devm_regulator_get_enable_optional(dev, rcar_pcie_supplies[i]); 985 if (err < 0 && err != -ENODEV) 986 return dev_err_probe(dev, err, "failed to enable regulator: %s\n", 987 rcar_pcie_supplies[i]); 988 } 989 990 pm_runtime_enable(pcie->dev); 991 err = pm_runtime_get_sync(pcie->dev); 992 if (err < 0) { 993 dev_err(pcie->dev, "pm_runtime_get_sync failed\n"); 994 goto err_pm_put; 995 } 996 997 err = rcar_pcie_get_resources(host); 998 if (err < 0) { 999 dev_err(dev, "failed to request resources: %d\n", err); 1000 goto err_pm_put; 1001 } 1002 1003 err = clk_prepare_enable(host->bus_clk); 1004 if (err) { 1005 dev_err(dev, "failed to enable bus clock: %d\n", err); 1006 goto err_unmap_msi_irqs; 1007 } 1008 1009 err = rcar_pcie_parse_map_dma_ranges(host); 1010 if (err) 1011 goto err_clk_disable; 1012 1013 host->phy_init_fn = of_device_get_match_data(dev); 1014 err = host->phy_init_fn(host); 1015 if (err) { 1016 dev_err(dev, "failed to init PCIe PHY\n"); 1017 goto err_clk_disable; 1018 } 1019 1020 /* Failure to get a link might just be that no cards are inserted */ 1021 if (rcar_pcie_hw_init(pcie)) { 1022 dev_info(dev, "PCIe link down\n"); 1023 err = -ENODEV; 1024 goto err_phy_shutdown; 1025 } 1026 1027 data = rcar_pci_read_reg(pcie, MACSR); 1028 dev_info(dev, "PCIe x%d: link up\n", (data >> 20) & 0x3f); 1029 1030 if (IS_ENABLED(CONFIG_PCI_MSI)) { 1031 err = rcar_pcie_enable_msi(host); 1032 if (err < 0) { 1033 dev_err(dev, 1034 "failed to enable MSI support: %d\n", 1035 err); 1036 goto err_phy_shutdown; 1037 } 1038 } 1039 1040 err = rcar_pcie_enable(host); 1041 if (err) 1042 goto err_msi_teardown; 1043 1044 return 0; 1045 1046 err_msi_teardown: 1047 if (IS_ENABLED(CONFIG_PCI_MSI)) 1048 rcar_pcie_teardown_msi(host); 1049 1050 err_phy_shutdown: 1051 if (host->phy) { 1052 phy_power_off(host->phy); 1053 phy_exit(host->phy); 1054 } 1055 1056 err_clk_disable: 1057 clk_disable_unprepare(host->bus_clk); 1058 1059 err_unmap_msi_irqs: 1060 irq_dispose_mapping(host->msi.irq2); 1061 irq_dispose_mapping(host->msi.irq1); 1062 1063 err_pm_put: 1064 pm_runtime_put(dev); 1065 pm_runtime_disable(dev); 1066 1067 return err; 1068 } 1069 1070 static int rcar_pcie_resume(struct device *dev) 1071 { 1072 struct rcar_pcie_host *host = dev_get_drvdata(dev); 1073 struct rcar_pcie *pcie = &host->pcie; 1074 unsigned int data; 1075 int err; 1076 1077 err = rcar_pcie_parse_map_dma_ranges(host); 1078 if (err) 1079 return 0; 1080 1081 /* Failure to get a link might just be that no cards are inserted */ 1082 err = host->phy_init_fn(host); 1083 if (err) { 1084 dev_info(dev, "PCIe link down\n"); 1085 return 0; 1086 } 1087 1088 data = rcar_pci_read_reg(pcie, MACSR); 1089 dev_info(dev, "PCIe x%d: link up\n", (data >> 20) & 0x3f); 1090 1091 /* Enable MSI */ 1092 if (IS_ENABLED(CONFIG_PCI_MSI)) { 1093 struct resource res; 1094 u32 val; 1095 1096 of_address_to_resource(dev->of_node, 0, &res); 1097 rcar_pci_write_reg(pcie, upper_32_bits(res.start), PCIEMSIAUR); 1098 rcar_pci_write_reg(pcie, lower_32_bits(res.start) | MSIFE, PCIEMSIALR); 1099 1100 bitmap_to_arr32(&val, host->msi.used, INT_PCI_MSI_NR); 1101 rcar_pci_write_reg(pcie, val, PCIEMSIIER); 1102 } 1103 1104 rcar_pcie_hw_enable(host); 1105 1106 return 0; 1107 } 1108 1109 static int rcar_pcie_resume_noirq(struct device *dev) 1110 { 1111 struct rcar_pcie_host *host = dev_get_drvdata(dev); 1112 struct rcar_pcie *pcie = &host->pcie; 1113 1114 if (rcar_pci_read_reg(pcie, PMSR) && 1115 !(rcar_pci_read_reg(pcie, PCIETCTLR) & DL_DOWN)) 1116 return 0; 1117 1118 /* Re-establish the PCIe link */ 1119 rcar_pci_write_reg(pcie, MACCTLR_INIT_VAL, MACCTLR); 1120 rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR); 1121 return rcar_pcie_wait_for_dl(pcie); 1122 } 1123 1124 static const struct dev_pm_ops rcar_pcie_pm_ops = { 1125 SYSTEM_SLEEP_PM_OPS(NULL, rcar_pcie_resume) 1126 .resume_noirq = rcar_pcie_resume_noirq, 1127 }; 1128 1129 static struct platform_driver rcar_pcie_driver = { 1130 .driver = { 1131 .name = "rcar-pcie", 1132 .of_match_table = rcar_pcie_of_match, 1133 .pm = &rcar_pcie_pm_ops, 1134 .suppress_bind_attrs = true, 1135 }, 1136 .probe = rcar_pcie_probe, 1137 }; 1138 1139 #ifdef CONFIG_ARM 1140 static int rcar_pcie_aarch32_abort_handler(unsigned long addr, 1141 unsigned int fsr, struct pt_regs *regs) 1142 { 1143 return !fixup_exception(regs); 1144 } 1145 1146 static const struct of_device_id rcar_pcie_abort_handler_of_match[] __initconst = { 1147 { .compatible = "renesas,pcie-r8a7779" }, 1148 { .compatible = "renesas,pcie-r8a7790" }, 1149 { .compatible = "renesas,pcie-r8a7791" }, 1150 { .compatible = "renesas,pcie-rcar-gen2" }, 1151 {}, 1152 }; 1153 1154 static int __init rcar_pcie_init(void) 1155 { 1156 if (of_find_matching_node(NULL, rcar_pcie_abort_handler_of_match)) { 1157 #ifdef CONFIG_ARM_LPAE 1158 hook_fault_code(17, rcar_pcie_aarch32_abort_handler, SIGBUS, 0, 1159 "asynchronous external abort"); 1160 #else 1161 hook_fault_code(22, rcar_pcie_aarch32_abort_handler, SIGBUS, 0, 1162 "imprecise external abort"); 1163 #endif 1164 } 1165 1166 return platform_driver_register(&rcar_pcie_driver); 1167 } 1168 device_initcall(rcar_pcie_init); 1169 #else 1170 builtin_platform_driver(rcar_pcie_driver); 1171 #endif 1172