1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * PCIe driver for Renesas R-Car SoCs 4 * Copyright (C) 2014-2020 Renesas Electronics Europe Ltd 5 * 6 * Based on: 7 * arch/sh/drivers/pci/pcie-sh7786.c 8 * arch/sh/drivers/pci/ops-sh7786.c 9 * Copyright (C) 2009 - 2011 Paul Mundt 10 * 11 * Author: Phil Edworthy <phil.edworthy@renesas.com> 12 */ 13 14 #include <linux/bitops.h> 15 #include <linux/clk.h> 16 #include <linux/clk-provider.h> 17 #include <linux/delay.h> 18 #include <linux/interrupt.h> 19 #include <linux/irq.h> 20 #include <linux/irqdomain.h> 21 #include <linux/kernel.h> 22 #include <linux/init.h> 23 #include <linux/iopoll.h> 24 #include <linux/msi.h> 25 #include <linux/of_address.h> 26 #include <linux/of_irq.h> 27 #include <linux/of_platform.h> 28 #include <linux/pci.h> 29 #include <linux/phy/phy.h> 30 #include <linux/platform_device.h> 31 #include <linux/pm_runtime.h> 32 33 #include "pcie-rcar.h" 34 35 struct rcar_msi { 36 DECLARE_BITMAP(used, INT_PCI_MSI_NR); 37 struct irq_domain *domain; 38 struct mutex map_lock; 39 spinlock_t mask_lock; 40 int irq1; 41 int irq2; 42 }; 43 44 /* Structure representing the PCIe interface */ 45 struct rcar_pcie_host { 46 struct rcar_pcie pcie; 47 struct phy *phy; 48 struct clk *bus_clk; 49 struct rcar_msi msi; 50 int (*phy_init_fn)(struct rcar_pcie_host *host); 51 }; 52 53 static DEFINE_SPINLOCK(pmsr_lock); 54 55 static int rcar_pcie_wakeup(struct device *pcie_dev, void __iomem *pcie_base) 56 { 57 unsigned long flags; 58 u32 pmsr, val; 59 int ret = 0; 60 61 spin_lock_irqsave(&pmsr_lock, flags); 62 63 if (!pcie_base || pm_runtime_suspended(pcie_dev)) { 64 ret = -EINVAL; 65 goto unlock_exit; 66 } 67 68 pmsr = readl(pcie_base + PMSR); 69 70 /* 71 * Test if the PCIe controller received PM_ENTER_L1 DLLP and 72 * the PCIe controller is not in L1 link state. If true, apply 73 * fix, which will put the controller into L1 link state, from 74 * which it can return to L0s/L0 on its own. 75 */ 76 if ((pmsr & PMEL1RX) && ((pmsr & PMSTATE) != PMSTATE_L1)) { 77 writel(L1IATN, pcie_base + PMCTLR); 78 ret = readl_poll_timeout_atomic(pcie_base + PMSR, val, 79 val & L1FAEG, 10, 1000); 80 WARN(ret, "Timeout waiting for L1 link state, ret=%d\n", ret); 81 writel(L1FAEG | PMEL1RX, pcie_base + PMSR); 82 } 83 84 unlock_exit: 85 spin_unlock_irqrestore(&pmsr_lock, flags); 86 return ret; 87 } 88 89 static struct rcar_pcie_host *msi_to_host(struct rcar_msi *msi) 90 { 91 return container_of(msi, struct rcar_pcie_host, msi); 92 } 93 94 static u32 rcar_read_conf(struct rcar_pcie *pcie, int where) 95 { 96 unsigned int shift = BITS_PER_BYTE * (where & 3); 97 u32 val = rcar_pci_read_reg(pcie, where & ~3); 98 99 return val >> shift; 100 } 101 102 #ifdef CONFIG_ARM 103 #define __rcar_pci_rw_reg_workaround(instr) \ 104 " .arch armv7-a\n" \ 105 "1: " instr " %1, [%2]\n" \ 106 "2: isb\n" \ 107 "3: .pushsection .text.fixup,\"ax\"\n" \ 108 " .align 2\n" \ 109 "4: mov %0, #" __stringify(PCIBIOS_SET_FAILED) "\n" \ 110 " b 3b\n" \ 111 " .popsection\n" \ 112 " .pushsection __ex_table,\"a\"\n" \ 113 " .align 3\n" \ 114 " .long 1b, 4b\n" \ 115 " .long 2b, 4b\n" \ 116 " .popsection\n" 117 #endif 118 119 static int rcar_pci_write_reg_workaround(struct rcar_pcie *pcie, u32 val, 120 unsigned int reg) 121 { 122 int error = PCIBIOS_SUCCESSFUL; 123 #ifdef CONFIG_ARM 124 asm volatile( 125 __rcar_pci_rw_reg_workaround("str") 126 : "+r"(error):"r"(val), "r"(pcie->base + reg) : "memory"); 127 #else 128 rcar_pci_write_reg(pcie, val, reg); 129 #endif 130 return error; 131 } 132 133 static int rcar_pci_read_reg_workaround(struct rcar_pcie *pcie, u32 *val, 134 unsigned int reg) 135 { 136 int error = PCIBIOS_SUCCESSFUL; 137 #ifdef CONFIG_ARM 138 asm volatile( 139 __rcar_pci_rw_reg_workaround("ldr") 140 : "+r"(error), "=r"(*val) : "r"(pcie->base + reg) : "memory"); 141 142 if (error != PCIBIOS_SUCCESSFUL) 143 PCI_SET_ERROR_RESPONSE(val); 144 #else 145 *val = rcar_pci_read_reg(pcie, reg); 146 #endif 147 return error; 148 } 149 150 /* Serialization is provided by 'pci_lock' in drivers/pci/access.c */ 151 static int rcar_pcie_config_access(struct rcar_pcie_host *host, 152 unsigned char access_type, struct pci_bus *bus, 153 unsigned int devfn, int where, u32 *data) 154 { 155 struct rcar_pcie *pcie = &host->pcie; 156 unsigned int dev, func, reg, index; 157 int ret; 158 159 /* Wake the bus up in case it is in L1 state. */ 160 ret = rcar_pcie_wakeup(pcie->dev, pcie->base); 161 if (ret) { 162 PCI_SET_ERROR_RESPONSE(data); 163 return PCIBIOS_SET_FAILED; 164 } 165 166 dev = PCI_SLOT(devfn); 167 func = PCI_FUNC(devfn); 168 reg = where & ~3; 169 index = reg / 4; 170 171 /* 172 * While each channel has its own memory-mapped extended config 173 * space, it's generally only accessible when in endpoint mode. 174 * When in root complex mode, the controller is unable to target 175 * itself with either type 0 or type 1 accesses, and indeed, any 176 * controller initiated target transfer to its own config space 177 * result in a completer abort. 178 * 179 * Each channel effectively only supports a single device, but as 180 * the same channel <-> device access works for any PCI_SLOT() 181 * value, we cheat a bit here and bind the controller's config 182 * space to devfn 0 in order to enable self-enumeration. In this 183 * case the regular ECAR/ECDR path is sidelined and the mangled 184 * config access itself is initiated as an internal bus transaction. 185 */ 186 if (pci_is_root_bus(bus)) { 187 if (dev != 0) 188 return PCIBIOS_DEVICE_NOT_FOUND; 189 190 if (access_type == RCAR_PCI_ACCESS_READ) 191 *data = rcar_pci_read_reg(pcie, PCICONF(index)); 192 else 193 rcar_pci_write_reg(pcie, *data, PCICONF(index)); 194 195 return PCIBIOS_SUCCESSFUL; 196 } 197 198 /* Clear errors */ 199 rcar_pci_write_reg(pcie, rcar_pci_read_reg(pcie, PCIEERRFR), PCIEERRFR); 200 201 /* Set the PIO address */ 202 rcar_pci_write_reg(pcie, PCIE_CONF_BUS(bus->number) | 203 PCIE_CONF_DEV(dev) | PCIE_CONF_FUNC(func) | reg, PCIECAR); 204 205 /* Enable the configuration access */ 206 if (pci_is_root_bus(bus->parent)) 207 rcar_pci_write_reg(pcie, PCIECCTLR_CCIE | TYPE0, PCIECCTLR); 208 else 209 rcar_pci_write_reg(pcie, PCIECCTLR_CCIE | TYPE1, PCIECCTLR); 210 211 /* Check for errors */ 212 if (rcar_pci_read_reg(pcie, PCIEERRFR) & UNSUPPORTED_REQUEST) 213 return PCIBIOS_DEVICE_NOT_FOUND; 214 215 /* Check for master and target aborts */ 216 if (rcar_read_conf(pcie, RCONF(PCI_STATUS)) & 217 (PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT)) 218 return PCIBIOS_DEVICE_NOT_FOUND; 219 220 if (access_type == RCAR_PCI_ACCESS_READ) 221 ret = rcar_pci_read_reg_workaround(pcie, data, PCIECDR); 222 else 223 ret = rcar_pci_write_reg_workaround(pcie, *data, PCIECDR); 224 225 /* Disable the configuration access */ 226 rcar_pci_write_reg(pcie, 0, PCIECCTLR); 227 228 return ret; 229 } 230 231 static int rcar_pcie_read_conf(struct pci_bus *bus, unsigned int devfn, 232 int where, int size, u32 *val) 233 { 234 struct rcar_pcie_host *host = bus->sysdata; 235 int ret; 236 237 ret = rcar_pcie_config_access(host, RCAR_PCI_ACCESS_READ, 238 bus, devfn, where, val); 239 if (ret != PCIBIOS_SUCCESSFUL) 240 return ret; 241 242 if (size == 1) 243 *val = (*val >> (BITS_PER_BYTE * (where & 3))) & 0xff; 244 else if (size == 2) 245 *val = (*val >> (BITS_PER_BYTE * (where & 2))) & 0xffff; 246 247 dev_dbg(&bus->dev, "pcie-config-read: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08x\n", 248 bus->number, devfn, where, size, *val); 249 250 return ret; 251 } 252 253 /* Serialization is provided by 'pci_lock' in drivers/pci/access.c */ 254 static int rcar_pcie_write_conf(struct pci_bus *bus, unsigned int devfn, 255 int where, int size, u32 val) 256 { 257 struct rcar_pcie_host *host = bus->sysdata; 258 unsigned int shift; 259 u32 data; 260 int ret; 261 262 ret = rcar_pcie_config_access(host, RCAR_PCI_ACCESS_READ, 263 bus, devfn, where, &data); 264 if (ret != PCIBIOS_SUCCESSFUL) 265 return ret; 266 267 dev_dbg(&bus->dev, "pcie-config-write: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08x\n", 268 bus->number, devfn, where, size, val); 269 270 if (size == 1) { 271 shift = BITS_PER_BYTE * (where & 3); 272 data &= ~(0xff << shift); 273 data |= ((val & 0xff) << shift); 274 } else if (size == 2) { 275 shift = BITS_PER_BYTE * (where & 2); 276 data &= ~(0xffff << shift); 277 data |= ((val & 0xffff) << shift); 278 } else 279 data = val; 280 281 ret = rcar_pcie_config_access(host, RCAR_PCI_ACCESS_WRITE, 282 bus, devfn, where, &data); 283 284 return ret; 285 } 286 287 static struct pci_ops rcar_pcie_ops = { 288 .read = rcar_pcie_read_conf, 289 .write = rcar_pcie_write_conf, 290 }; 291 292 static void rcar_pcie_force_speedup(struct rcar_pcie *pcie) 293 { 294 struct device *dev = pcie->dev; 295 unsigned int timeout = 1000; 296 u32 macsr; 297 298 if ((rcar_pci_read_reg(pcie, MACS2R) & LINK_SPEED) != LINK_SPEED_5_0GTS) 299 return; 300 301 if (rcar_pci_read_reg(pcie, MACCTLR) & SPEED_CHANGE) { 302 dev_err(dev, "Speed change already in progress\n"); 303 return; 304 } 305 306 macsr = rcar_pci_read_reg(pcie, MACSR); 307 if ((macsr & LINK_SPEED) == LINK_SPEED_5_0GTS) 308 goto done; 309 310 /* Set target link speed to 5.0 GT/s */ 311 rcar_rmw32(pcie, EXPCAP(12), PCI_EXP_LNKSTA_CLS, 312 PCI_EXP_LNKSTA_CLS_5_0GB); 313 314 /* Set speed change reason as intentional factor */ 315 rcar_rmw32(pcie, MACCGSPSETR, SPCNGRSN, 0); 316 317 /* Clear SPCHGFIN, SPCHGSUC, and SPCHGFAIL */ 318 if (macsr & (SPCHGFIN | SPCHGSUC | SPCHGFAIL)) 319 rcar_pci_write_reg(pcie, macsr, MACSR); 320 321 /* Start link speed change */ 322 rcar_rmw32(pcie, MACCTLR, SPEED_CHANGE, SPEED_CHANGE); 323 324 while (timeout--) { 325 macsr = rcar_pci_read_reg(pcie, MACSR); 326 if (macsr & SPCHGFIN) { 327 /* Clear the interrupt bits */ 328 rcar_pci_write_reg(pcie, macsr, MACSR); 329 330 if (macsr & SPCHGFAIL) 331 dev_err(dev, "Speed change failed\n"); 332 333 goto done; 334 } 335 336 msleep(1); 337 } 338 339 dev_err(dev, "Speed change timed out\n"); 340 341 done: 342 dev_info(dev, "Current link speed is %s GT/s\n", 343 (macsr & LINK_SPEED) == LINK_SPEED_5_0GTS ? "5" : "2.5"); 344 } 345 346 static void rcar_pcie_hw_enable(struct rcar_pcie_host *host) 347 { 348 struct rcar_pcie *pcie = &host->pcie; 349 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(host); 350 struct resource_entry *win; 351 LIST_HEAD(res); 352 int i = 0; 353 354 /* Try setting 5 GT/s link speed */ 355 rcar_pcie_force_speedup(pcie); 356 357 /* Setup PCI resources */ 358 resource_list_for_each_entry(win, &bridge->windows) { 359 struct resource *res = win->res; 360 361 if (!res->flags) 362 continue; 363 364 switch (resource_type(res)) { 365 case IORESOURCE_IO: 366 case IORESOURCE_MEM: 367 rcar_pcie_set_outbound(pcie, i, win); 368 i++; 369 break; 370 } 371 } 372 } 373 374 static int rcar_pcie_enable(struct rcar_pcie_host *host) 375 { 376 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(host); 377 378 rcar_pcie_hw_enable(host); 379 380 pci_add_flags(PCI_REASSIGN_ALL_BUS); 381 382 bridge->sysdata = host; 383 bridge->ops = &rcar_pcie_ops; 384 385 return pci_host_probe(bridge); 386 } 387 388 static int phy_wait_for_ack(struct rcar_pcie *pcie) 389 { 390 struct device *dev = pcie->dev; 391 unsigned int timeout = 100; 392 393 while (timeout--) { 394 if (rcar_pci_read_reg(pcie, H1_PCIEPHYADRR) & PHY_ACK) 395 return 0; 396 397 udelay(100); 398 } 399 400 dev_err(dev, "Access to PCIe phy timed out\n"); 401 402 return -ETIMEDOUT; 403 } 404 405 static void phy_write_reg(struct rcar_pcie *pcie, 406 unsigned int rate, u32 addr, 407 unsigned int lane, u32 data) 408 { 409 u32 phyaddr; 410 411 phyaddr = WRITE_CMD | 412 ((rate & 1) << RATE_POS) | 413 ((lane & 0xf) << LANE_POS) | 414 ((addr & 0xff) << ADR_POS); 415 416 /* Set write data */ 417 rcar_pci_write_reg(pcie, data, H1_PCIEPHYDOUTR); 418 rcar_pci_write_reg(pcie, phyaddr, H1_PCIEPHYADRR); 419 420 /* Ignore errors as they will be dealt with if the data link is down */ 421 phy_wait_for_ack(pcie); 422 423 /* Clear command */ 424 rcar_pci_write_reg(pcie, 0, H1_PCIEPHYDOUTR); 425 rcar_pci_write_reg(pcie, 0, H1_PCIEPHYADRR); 426 427 /* Ignore errors as they will be dealt with if the data link is down */ 428 phy_wait_for_ack(pcie); 429 } 430 431 static int rcar_pcie_hw_init(struct rcar_pcie *pcie) 432 { 433 int err; 434 435 /* Begin initialization */ 436 rcar_pci_write_reg(pcie, 0, PCIETCTLR); 437 438 /* Set mode */ 439 rcar_pci_write_reg(pcie, 1, PCIEMSR); 440 441 err = rcar_pcie_wait_for_phyrdy(pcie); 442 if (err) 443 return err; 444 445 /* 446 * Initial header for port config space is type 1, set the device 447 * class to match. Hardware takes care of propagating the IDSETR 448 * settings, so there is no need to bother with a quirk. 449 */ 450 rcar_pci_write_reg(pcie, PCI_CLASS_BRIDGE_PCI_NORMAL << 8, IDSETR1); 451 452 /* 453 * Setup Secondary Bus Number & Subordinate Bus Number, even though 454 * they aren't used, to avoid bridge being detected as broken. 455 */ 456 rcar_rmw32(pcie, RCONF(PCI_SECONDARY_BUS), 0xff, 1); 457 rcar_rmw32(pcie, RCONF(PCI_SUBORDINATE_BUS), 0xff, 1); 458 459 /* Initialize default capabilities. */ 460 rcar_rmw32(pcie, REXPCAP(0), 0xff, PCI_CAP_ID_EXP); 461 rcar_rmw32(pcie, REXPCAP(PCI_EXP_FLAGS), 462 PCI_EXP_FLAGS_TYPE, PCI_EXP_TYPE_ROOT_PORT << 4); 463 rcar_rmw32(pcie, RCONF(PCI_HEADER_TYPE), 0x7f, 464 PCI_HEADER_TYPE_BRIDGE); 465 466 /* Enable data link layer active state reporting */ 467 rcar_rmw32(pcie, REXPCAP(PCI_EXP_LNKCAP), PCI_EXP_LNKCAP_DLLLARC, 468 PCI_EXP_LNKCAP_DLLLARC); 469 470 /* Write out the physical slot number = 0 */ 471 rcar_rmw32(pcie, REXPCAP(PCI_EXP_SLTCAP), PCI_EXP_SLTCAP_PSN, 0); 472 473 /* Set the completion timer timeout to the maximum 50ms. */ 474 rcar_rmw32(pcie, TLCTLR + 1, 0x3f, 50); 475 476 /* Terminate list of capabilities (Next Capability Offset=0) */ 477 rcar_rmw32(pcie, RVCCAP(0), 0xfff00000, 0); 478 479 /* Enable MSI */ 480 if (IS_ENABLED(CONFIG_PCI_MSI)) 481 rcar_pci_write_reg(pcie, 0x801f0000, PCIEMSITXR); 482 483 rcar_pci_write_reg(pcie, MACCTLR_INIT_VAL, MACCTLR); 484 485 /* Finish initialization - establish a PCI Express link */ 486 rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR); 487 488 /* This will timeout if we don't have a link. */ 489 err = rcar_pcie_wait_for_dl(pcie); 490 if (err) 491 return err; 492 493 /* Enable INTx interrupts */ 494 rcar_rmw32(pcie, PCIEINTXR, 0, 0xF << 8); 495 496 wmb(); 497 498 return 0; 499 } 500 501 static int rcar_pcie_phy_init_h1(struct rcar_pcie_host *host) 502 { 503 struct rcar_pcie *pcie = &host->pcie; 504 505 /* Initialize the phy */ 506 phy_write_reg(pcie, 0, 0x42, 0x1, 0x0EC34191); 507 phy_write_reg(pcie, 1, 0x42, 0x1, 0x0EC34180); 508 phy_write_reg(pcie, 0, 0x43, 0x1, 0x00210188); 509 phy_write_reg(pcie, 1, 0x43, 0x1, 0x00210188); 510 phy_write_reg(pcie, 0, 0x44, 0x1, 0x015C0014); 511 phy_write_reg(pcie, 1, 0x44, 0x1, 0x015C0014); 512 phy_write_reg(pcie, 1, 0x4C, 0x1, 0x786174A0); 513 phy_write_reg(pcie, 1, 0x4D, 0x1, 0x048000BB); 514 phy_write_reg(pcie, 0, 0x51, 0x1, 0x079EC062); 515 phy_write_reg(pcie, 0, 0x52, 0x1, 0x20000000); 516 phy_write_reg(pcie, 1, 0x52, 0x1, 0x20000000); 517 phy_write_reg(pcie, 1, 0x56, 0x1, 0x00003806); 518 519 phy_write_reg(pcie, 0, 0x60, 0x1, 0x004B03A5); 520 phy_write_reg(pcie, 0, 0x64, 0x1, 0x3F0F1F0F); 521 phy_write_reg(pcie, 0, 0x66, 0x1, 0x00008000); 522 523 return 0; 524 } 525 526 static int rcar_pcie_phy_init_gen2(struct rcar_pcie_host *host) 527 { 528 struct rcar_pcie *pcie = &host->pcie; 529 530 /* 531 * These settings come from the R-Car Series, 2nd Generation User's 532 * Manual, section 50.3.1 (2) Initialization of the physical layer. 533 */ 534 rcar_pci_write_reg(pcie, 0x000f0030, GEN2_PCIEPHYADDR); 535 rcar_pci_write_reg(pcie, 0x00381203, GEN2_PCIEPHYDATA); 536 rcar_pci_write_reg(pcie, 0x00000001, GEN2_PCIEPHYCTRL); 537 rcar_pci_write_reg(pcie, 0x00000006, GEN2_PCIEPHYCTRL); 538 539 rcar_pci_write_reg(pcie, 0x000f0054, GEN2_PCIEPHYADDR); 540 /* The following value is for DC connection, no termination resistor */ 541 rcar_pci_write_reg(pcie, 0x13802007, GEN2_PCIEPHYDATA); 542 rcar_pci_write_reg(pcie, 0x00000001, GEN2_PCIEPHYCTRL); 543 rcar_pci_write_reg(pcie, 0x00000006, GEN2_PCIEPHYCTRL); 544 545 return 0; 546 } 547 548 static int rcar_pcie_phy_init_gen3(struct rcar_pcie_host *host) 549 { 550 int err; 551 552 err = phy_init(host->phy); 553 if (err) 554 return err; 555 556 err = phy_power_on(host->phy); 557 if (err) 558 phy_exit(host->phy); 559 560 return err; 561 } 562 563 static irqreturn_t rcar_pcie_msi_irq(int irq, void *data) 564 { 565 struct rcar_pcie_host *host = data; 566 struct rcar_pcie *pcie = &host->pcie; 567 struct rcar_msi *msi = &host->msi; 568 struct device *dev = pcie->dev; 569 unsigned long reg; 570 571 reg = rcar_pci_read_reg(pcie, PCIEMSIFR); 572 573 /* MSI & INTx share an interrupt - we only handle MSI here */ 574 if (!reg) 575 return IRQ_NONE; 576 577 while (reg) { 578 unsigned int index = find_first_bit(®, 32); 579 int ret; 580 581 ret = generic_handle_domain_irq(msi->domain->parent, index); 582 if (ret) { 583 /* Unknown MSI, just clear it */ 584 dev_dbg(dev, "unexpected MSI\n"); 585 rcar_pci_write_reg(pcie, BIT(index), PCIEMSIFR); 586 } 587 588 /* see if there's any more pending in this vector */ 589 reg = rcar_pci_read_reg(pcie, PCIEMSIFR); 590 } 591 592 return IRQ_HANDLED; 593 } 594 595 static void rcar_msi_top_irq_ack(struct irq_data *d) 596 { 597 irq_chip_ack_parent(d); 598 } 599 600 static void rcar_msi_top_irq_mask(struct irq_data *d) 601 { 602 pci_msi_mask_irq(d); 603 irq_chip_mask_parent(d); 604 } 605 606 static void rcar_msi_top_irq_unmask(struct irq_data *d) 607 { 608 pci_msi_unmask_irq(d); 609 irq_chip_unmask_parent(d); 610 } 611 612 static struct irq_chip rcar_msi_top_chip = { 613 .name = "PCIe MSI", 614 .irq_ack = rcar_msi_top_irq_ack, 615 .irq_mask = rcar_msi_top_irq_mask, 616 .irq_unmask = rcar_msi_top_irq_unmask, 617 }; 618 619 static void rcar_msi_irq_ack(struct irq_data *d) 620 { 621 struct rcar_msi *msi = irq_data_get_irq_chip_data(d); 622 struct rcar_pcie *pcie = &msi_to_host(msi)->pcie; 623 624 /* clear the interrupt */ 625 rcar_pci_write_reg(pcie, BIT(d->hwirq), PCIEMSIFR); 626 } 627 628 static void rcar_msi_irq_mask(struct irq_data *d) 629 { 630 struct rcar_msi *msi = irq_data_get_irq_chip_data(d); 631 struct rcar_pcie *pcie = &msi_to_host(msi)->pcie; 632 unsigned long flags; 633 u32 value; 634 635 spin_lock_irqsave(&msi->mask_lock, flags); 636 value = rcar_pci_read_reg(pcie, PCIEMSIIER); 637 value &= ~BIT(d->hwirq); 638 rcar_pci_write_reg(pcie, value, PCIEMSIIER); 639 spin_unlock_irqrestore(&msi->mask_lock, flags); 640 } 641 642 static void rcar_msi_irq_unmask(struct irq_data *d) 643 { 644 struct rcar_msi *msi = irq_data_get_irq_chip_data(d); 645 struct rcar_pcie *pcie = &msi_to_host(msi)->pcie; 646 unsigned long flags; 647 u32 value; 648 649 spin_lock_irqsave(&msi->mask_lock, flags); 650 value = rcar_pci_read_reg(pcie, PCIEMSIIER); 651 value |= BIT(d->hwirq); 652 rcar_pci_write_reg(pcie, value, PCIEMSIIER); 653 spin_unlock_irqrestore(&msi->mask_lock, flags); 654 } 655 656 static int rcar_msi_set_affinity(struct irq_data *d, const struct cpumask *mask, bool force) 657 { 658 return -EINVAL; 659 } 660 661 static void rcar_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) 662 { 663 struct rcar_msi *msi = irq_data_get_irq_chip_data(data); 664 struct rcar_pcie *pcie = &msi_to_host(msi)->pcie; 665 666 msg->address_lo = rcar_pci_read_reg(pcie, PCIEMSIALR) & ~MSIFE; 667 msg->address_hi = rcar_pci_read_reg(pcie, PCIEMSIAUR); 668 msg->data = data->hwirq; 669 } 670 671 static struct irq_chip rcar_msi_bottom_chip = { 672 .name = "R-Car MSI", 673 .irq_ack = rcar_msi_irq_ack, 674 .irq_mask = rcar_msi_irq_mask, 675 .irq_unmask = rcar_msi_irq_unmask, 676 .irq_set_affinity = rcar_msi_set_affinity, 677 .irq_compose_msi_msg = rcar_compose_msi_msg, 678 }; 679 680 static int rcar_msi_domain_alloc(struct irq_domain *domain, unsigned int virq, 681 unsigned int nr_irqs, void *args) 682 { 683 struct rcar_msi *msi = domain->host_data; 684 unsigned int i; 685 int hwirq; 686 687 mutex_lock(&msi->map_lock); 688 689 hwirq = bitmap_find_free_region(msi->used, INT_PCI_MSI_NR, order_base_2(nr_irqs)); 690 691 mutex_unlock(&msi->map_lock); 692 693 if (hwirq < 0) 694 return -ENOSPC; 695 696 for (i = 0; i < nr_irqs; i++) 697 irq_domain_set_info(domain, virq + i, hwirq + i, 698 &rcar_msi_bottom_chip, domain->host_data, 699 handle_edge_irq, NULL, NULL); 700 701 return 0; 702 } 703 704 static void rcar_msi_domain_free(struct irq_domain *domain, unsigned int virq, 705 unsigned int nr_irqs) 706 { 707 struct irq_data *d = irq_domain_get_irq_data(domain, virq); 708 struct rcar_msi *msi = domain->host_data; 709 710 mutex_lock(&msi->map_lock); 711 712 bitmap_release_region(msi->used, d->hwirq, order_base_2(nr_irqs)); 713 714 mutex_unlock(&msi->map_lock); 715 } 716 717 static const struct irq_domain_ops rcar_msi_domain_ops = { 718 .alloc = rcar_msi_domain_alloc, 719 .free = rcar_msi_domain_free, 720 }; 721 722 static struct msi_domain_info rcar_msi_info = { 723 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | 724 MSI_FLAG_MULTI_PCI_MSI), 725 .chip = &rcar_msi_top_chip, 726 }; 727 728 static int rcar_allocate_domains(struct rcar_msi *msi) 729 { 730 struct rcar_pcie *pcie = &msi_to_host(msi)->pcie; 731 struct fwnode_handle *fwnode = dev_fwnode(pcie->dev); 732 struct irq_domain *parent; 733 734 parent = irq_domain_create_linear(fwnode, INT_PCI_MSI_NR, 735 &rcar_msi_domain_ops, msi); 736 if (!parent) { 737 dev_err(pcie->dev, "failed to create IRQ domain\n"); 738 return -ENOMEM; 739 } 740 irq_domain_update_bus_token(parent, DOMAIN_BUS_NEXUS); 741 742 msi->domain = pci_msi_create_irq_domain(fwnode, &rcar_msi_info, parent); 743 if (!msi->domain) { 744 dev_err(pcie->dev, "failed to create MSI domain\n"); 745 irq_domain_remove(parent); 746 return -ENOMEM; 747 } 748 749 return 0; 750 } 751 752 static void rcar_free_domains(struct rcar_msi *msi) 753 { 754 struct irq_domain *parent = msi->domain->parent; 755 756 irq_domain_remove(msi->domain); 757 irq_domain_remove(parent); 758 } 759 760 static int rcar_pcie_enable_msi(struct rcar_pcie_host *host) 761 { 762 struct rcar_pcie *pcie = &host->pcie; 763 struct device *dev = pcie->dev; 764 struct rcar_msi *msi = &host->msi; 765 struct resource res; 766 int err; 767 768 mutex_init(&msi->map_lock); 769 spin_lock_init(&msi->mask_lock); 770 771 err = of_address_to_resource(dev->of_node, 0, &res); 772 if (err) 773 return err; 774 775 err = rcar_allocate_domains(msi); 776 if (err) 777 return err; 778 779 /* Two irqs are for MSI, but they are also used for non-MSI irqs */ 780 err = devm_request_irq(dev, msi->irq1, rcar_pcie_msi_irq, 781 IRQF_SHARED | IRQF_NO_THREAD, 782 rcar_msi_bottom_chip.name, host); 783 if (err < 0) { 784 dev_err(dev, "failed to request IRQ: %d\n", err); 785 goto err; 786 } 787 788 err = devm_request_irq(dev, msi->irq2, rcar_pcie_msi_irq, 789 IRQF_SHARED | IRQF_NO_THREAD, 790 rcar_msi_bottom_chip.name, host); 791 if (err < 0) { 792 dev_err(dev, "failed to request IRQ: %d\n", err); 793 goto err; 794 } 795 796 /* disable all MSIs */ 797 rcar_pci_write_reg(pcie, 0, PCIEMSIIER); 798 799 /* 800 * Setup MSI data target using RC base address address, which 801 * is guaranteed to be in the low 32bit range on any R-Car HW. 802 */ 803 rcar_pci_write_reg(pcie, lower_32_bits(res.start) | MSIFE, PCIEMSIALR); 804 rcar_pci_write_reg(pcie, upper_32_bits(res.start), PCIEMSIAUR); 805 806 return 0; 807 808 err: 809 rcar_free_domains(msi); 810 return err; 811 } 812 813 static void rcar_pcie_teardown_msi(struct rcar_pcie_host *host) 814 { 815 struct rcar_pcie *pcie = &host->pcie; 816 817 /* Disable all MSI interrupts */ 818 rcar_pci_write_reg(pcie, 0, PCIEMSIIER); 819 820 /* Disable address decoding of the MSI interrupt, MSIFE */ 821 rcar_pci_write_reg(pcie, 0, PCIEMSIALR); 822 823 rcar_free_domains(&host->msi); 824 } 825 826 static int rcar_pcie_get_resources(struct rcar_pcie_host *host) 827 { 828 struct rcar_pcie *pcie = &host->pcie; 829 struct device *dev = pcie->dev; 830 struct resource res; 831 int err, i; 832 833 host->phy = devm_phy_optional_get(dev, "pcie"); 834 if (IS_ERR(host->phy)) 835 return PTR_ERR(host->phy); 836 837 err = of_address_to_resource(dev->of_node, 0, &res); 838 if (err) 839 return err; 840 841 pcie->base = devm_ioremap_resource(dev, &res); 842 if (IS_ERR(pcie->base)) 843 return PTR_ERR(pcie->base); 844 845 host->bus_clk = devm_clk_get(dev, "pcie_bus"); 846 if (IS_ERR(host->bus_clk)) { 847 dev_err(dev, "cannot get pcie bus clock\n"); 848 return PTR_ERR(host->bus_clk); 849 } 850 851 i = irq_of_parse_and_map(dev->of_node, 0); 852 if (!i) { 853 dev_err(dev, "cannot get platform resources for msi interrupt\n"); 854 err = -ENOENT; 855 goto err_irq1; 856 } 857 host->msi.irq1 = i; 858 859 i = irq_of_parse_and_map(dev->of_node, 1); 860 if (!i) { 861 dev_err(dev, "cannot get platform resources for msi interrupt\n"); 862 err = -ENOENT; 863 goto err_irq2; 864 } 865 host->msi.irq2 = i; 866 867 return 0; 868 869 err_irq2: 870 irq_dispose_mapping(host->msi.irq1); 871 err_irq1: 872 return err; 873 } 874 875 static int rcar_pcie_inbound_ranges(struct rcar_pcie *pcie, 876 struct resource_entry *entry, 877 int *index) 878 { 879 u64 restype = entry->res->flags; 880 u64 cpu_addr = entry->res->start; 881 u64 cpu_end = entry->res->end; 882 u64 pci_addr = entry->res->start - entry->offset; 883 u32 flags = LAM_64BIT | LAR_ENABLE; 884 u64 mask; 885 u64 size = resource_size(entry->res); 886 int idx = *index; 887 888 if (restype & IORESOURCE_PREFETCH) 889 flags |= LAM_PREFETCH; 890 891 while (cpu_addr < cpu_end) { 892 if (idx >= MAX_NR_INBOUND_MAPS - 1) { 893 dev_err(pcie->dev, "Failed to map inbound regions!\n"); 894 return -EINVAL; 895 } 896 /* 897 * If the size of the range is larger than the alignment of 898 * the start address, we have to use multiple entries to 899 * perform the mapping. 900 */ 901 if (cpu_addr > 0) { 902 unsigned long nr_zeros = __ffs64(cpu_addr); 903 u64 alignment = 1ULL << nr_zeros; 904 905 size = min(size, alignment); 906 } 907 /* Hardware supports max 4GiB inbound region */ 908 size = min(size, 1ULL << 32); 909 910 mask = roundup_pow_of_two(size) - 1; 911 mask &= ~0xf; 912 913 rcar_pcie_set_inbound(pcie, cpu_addr, pci_addr, 914 lower_32_bits(mask) | flags, idx, true); 915 916 pci_addr += size; 917 cpu_addr += size; 918 idx += 2; 919 } 920 *index = idx; 921 922 return 0; 923 } 924 925 static int rcar_pcie_parse_map_dma_ranges(struct rcar_pcie_host *host) 926 { 927 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(host); 928 struct resource_entry *entry; 929 int index = 0, err = 0; 930 931 resource_list_for_each_entry(entry, &bridge->dma_ranges) { 932 err = rcar_pcie_inbound_ranges(&host->pcie, entry, &index); 933 if (err) 934 break; 935 } 936 937 return err; 938 } 939 940 static const struct of_device_id rcar_pcie_of_match[] = { 941 { .compatible = "renesas,pcie-r8a7779", 942 .data = rcar_pcie_phy_init_h1 }, 943 { .compatible = "renesas,pcie-r8a7790", 944 .data = rcar_pcie_phy_init_gen2 }, 945 { .compatible = "renesas,pcie-r8a7791", 946 .data = rcar_pcie_phy_init_gen2 }, 947 { .compatible = "renesas,pcie-rcar-gen2", 948 .data = rcar_pcie_phy_init_gen2 }, 949 { .compatible = "renesas,pcie-r8a7795", 950 .data = rcar_pcie_phy_init_gen3 }, 951 { .compatible = "renesas,pcie-rcar-gen3", 952 .data = rcar_pcie_phy_init_gen3 }, 953 {}, 954 }; 955 956 static int rcar_pcie_probe(struct platform_device *pdev) 957 { 958 struct device *dev = &pdev->dev; 959 struct rcar_pcie_host *host; 960 struct rcar_pcie *pcie; 961 u32 data; 962 int err; 963 struct pci_host_bridge *bridge; 964 965 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*host)); 966 if (!bridge) 967 return -ENOMEM; 968 969 host = pci_host_bridge_priv(bridge); 970 pcie = &host->pcie; 971 pcie->dev = dev; 972 platform_set_drvdata(pdev, host); 973 974 pm_runtime_enable(pcie->dev); 975 err = pm_runtime_get_sync(pcie->dev); 976 if (err < 0) { 977 dev_err(pcie->dev, "pm_runtime_get_sync failed\n"); 978 goto err_pm_put; 979 } 980 981 err = rcar_pcie_get_resources(host); 982 if (err < 0) { 983 dev_err(dev, "failed to request resources: %d\n", err); 984 goto err_pm_put; 985 } 986 987 err = clk_prepare_enable(host->bus_clk); 988 if (err) { 989 dev_err(dev, "failed to enable bus clock: %d\n", err); 990 goto err_unmap_msi_irqs; 991 } 992 993 err = rcar_pcie_parse_map_dma_ranges(host); 994 if (err) 995 goto err_clk_disable; 996 997 host->phy_init_fn = of_device_get_match_data(dev); 998 err = host->phy_init_fn(host); 999 if (err) { 1000 dev_err(dev, "failed to init PCIe PHY\n"); 1001 goto err_clk_disable; 1002 } 1003 1004 /* Failure to get a link might just be that no cards are inserted */ 1005 if (rcar_pcie_hw_init(pcie)) { 1006 dev_info(dev, "PCIe link down\n"); 1007 err = -ENODEV; 1008 goto err_phy_shutdown; 1009 } 1010 1011 data = rcar_pci_read_reg(pcie, MACSR); 1012 dev_info(dev, "PCIe x%d: link up\n", (data >> 20) & 0x3f); 1013 1014 if (IS_ENABLED(CONFIG_PCI_MSI)) { 1015 err = rcar_pcie_enable_msi(host); 1016 if (err < 0) { 1017 dev_err(dev, 1018 "failed to enable MSI support: %d\n", 1019 err); 1020 goto err_phy_shutdown; 1021 } 1022 } 1023 1024 err = rcar_pcie_enable(host); 1025 if (err) 1026 goto err_msi_teardown; 1027 1028 return 0; 1029 1030 err_msi_teardown: 1031 if (IS_ENABLED(CONFIG_PCI_MSI)) 1032 rcar_pcie_teardown_msi(host); 1033 1034 err_phy_shutdown: 1035 if (host->phy) { 1036 phy_power_off(host->phy); 1037 phy_exit(host->phy); 1038 } 1039 1040 err_clk_disable: 1041 clk_disable_unprepare(host->bus_clk); 1042 1043 err_unmap_msi_irqs: 1044 irq_dispose_mapping(host->msi.irq2); 1045 irq_dispose_mapping(host->msi.irq1); 1046 1047 err_pm_put: 1048 pm_runtime_put(dev); 1049 pm_runtime_disable(dev); 1050 1051 return err; 1052 } 1053 1054 static int rcar_pcie_resume(struct device *dev) 1055 { 1056 struct rcar_pcie_host *host = dev_get_drvdata(dev); 1057 struct rcar_pcie *pcie = &host->pcie; 1058 unsigned int data; 1059 int err; 1060 1061 err = rcar_pcie_parse_map_dma_ranges(host); 1062 if (err) 1063 return 0; 1064 1065 /* Failure to get a link might just be that no cards are inserted */ 1066 err = host->phy_init_fn(host); 1067 if (err) { 1068 dev_info(dev, "PCIe link down\n"); 1069 return 0; 1070 } 1071 1072 data = rcar_pci_read_reg(pcie, MACSR); 1073 dev_info(dev, "PCIe x%d: link up\n", (data >> 20) & 0x3f); 1074 1075 /* Enable MSI */ 1076 if (IS_ENABLED(CONFIG_PCI_MSI)) { 1077 struct resource res; 1078 u32 val; 1079 1080 of_address_to_resource(dev->of_node, 0, &res); 1081 rcar_pci_write_reg(pcie, upper_32_bits(res.start), PCIEMSIAUR); 1082 rcar_pci_write_reg(pcie, lower_32_bits(res.start) | MSIFE, PCIEMSIALR); 1083 1084 bitmap_to_arr32(&val, host->msi.used, INT_PCI_MSI_NR); 1085 rcar_pci_write_reg(pcie, val, PCIEMSIIER); 1086 } 1087 1088 rcar_pcie_hw_enable(host); 1089 1090 return 0; 1091 } 1092 1093 static int rcar_pcie_resume_noirq(struct device *dev) 1094 { 1095 struct rcar_pcie_host *host = dev_get_drvdata(dev); 1096 struct rcar_pcie *pcie = &host->pcie; 1097 1098 if (rcar_pci_read_reg(pcie, PMSR) && 1099 !(rcar_pci_read_reg(pcie, PCIETCTLR) & DL_DOWN)) 1100 return 0; 1101 1102 /* Re-establish the PCIe link */ 1103 rcar_pci_write_reg(pcie, MACCTLR_INIT_VAL, MACCTLR); 1104 rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR); 1105 return rcar_pcie_wait_for_dl(pcie); 1106 } 1107 1108 static const struct dev_pm_ops rcar_pcie_pm_ops = { 1109 SYSTEM_SLEEP_PM_OPS(NULL, rcar_pcie_resume) 1110 .resume_noirq = rcar_pcie_resume_noirq, 1111 }; 1112 1113 static struct platform_driver rcar_pcie_driver = { 1114 .driver = { 1115 .name = "rcar-pcie", 1116 .of_match_table = rcar_pcie_of_match, 1117 .pm = &rcar_pcie_pm_ops, 1118 .suppress_bind_attrs = true, 1119 }, 1120 .probe = rcar_pcie_probe, 1121 }; 1122 1123 #ifdef CONFIG_ARM 1124 static int rcar_pcie_aarch32_abort_handler(unsigned long addr, 1125 unsigned int fsr, struct pt_regs *regs) 1126 { 1127 return !fixup_exception(regs); 1128 } 1129 1130 static const struct of_device_id rcar_pcie_abort_handler_of_match[] __initconst = { 1131 { .compatible = "renesas,pcie-r8a7779" }, 1132 { .compatible = "renesas,pcie-r8a7790" }, 1133 { .compatible = "renesas,pcie-r8a7791" }, 1134 { .compatible = "renesas,pcie-rcar-gen2" }, 1135 {}, 1136 }; 1137 1138 static int __init rcar_pcie_init(void) 1139 { 1140 if (of_find_matching_node(NULL, rcar_pcie_abort_handler_of_match)) { 1141 #ifdef CONFIG_ARM_LPAE 1142 hook_fault_code(17, rcar_pcie_aarch32_abort_handler, SIGBUS, 0, 1143 "asynchronous external abort"); 1144 #else 1145 hook_fault_code(22, rcar_pcie_aarch32_abort_handler, SIGBUS, 0, 1146 "imprecise external abort"); 1147 #endif 1148 } 1149 1150 return platform_driver_register(&rcar_pcie_driver); 1151 } 1152 device_initcall(rcar_pcie_init); 1153 #else 1154 builtin_platform_driver(rcar_pcie_driver); 1155 #endif 1156