1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * PCIe driver for Renesas R-Car SoCs 4 * Copyright (C) 2014-2020 Renesas Electronics Europe Ltd 5 * 6 * Based on: 7 * arch/sh/drivers/pci/pcie-sh7786.c 8 * arch/sh/drivers/pci/ops-sh7786.c 9 * Copyright (C) 2009 - 2011 Paul Mundt 10 * 11 * Author: Phil Edworthy <phil.edworthy@renesas.com> 12 */ 13 14 #include <linux/bitops.h> 15 #include <linux/cleanup.h> 16 #include <linux/clk.h> 17 #include <linux/clk-provider.h> 18 #include <linux/delay.h> 19 #include <linux/interrupt.h> 20 #include <linux/irq.h> 21 #include <linux/irqchip/irq-msi-lib.h> 22 #include <linux/irqdomain.h> 23 #include <linux/kernel.h> 24 #include <linux/init.h> 25 #include <linux/iopoll.h> 26 #include <linux/msi.h> 27 #include <linux/of_address.h> 28 #include <linux/of_irq.h> 29 #include <linux/of_platform.h> 30 #include <linux/pci.h> 31 #include <linux/phy/phy.h> 32 #include <linux/platform_device.h> 33 #include <linux/pm_runtime.h> 34 #include <linux/regulator/consumer.h> 35 36 #include "pcie-rcar.h" 37 38 struct rcar_msi { 39 DECLARE_BITMAP(used, INT_PCI_MSI_NR); 40 struct irq_domain *domain; 41 struct mutex map_lock; 42 raw_spinlock_t mask_lock; 43 int irq1; 44 int irq2; 45 }; 46 47 /* Structure representing the PCIe interface */ 48 struct rcar_pcie_host { 49 struct rcar_pcie pcie; 50 struct phy *phy; 51 struct clk *bus_clk; 52 struct rcar_msi msi; 53 int (*phy_init_fn)(struct rcar_pcie_host *host); 54 }; 55 56 static int rcar_pcie_wakeup(struct device *pcie_dev, void __iomem *pcie_base) 57 { 58 u32 pmsr, val; 59 int ret = 0; 60 61 if (!pcie_base || pm_runtime_suspended(pcie_dev)) 62 return -EINVAL; 63 64 pmsr = readl(pcie_base + PMSR); 65 66 /* 67 * Test if the PCIe controller received PM_ENTER_L1 DLLP and 68 * the PCIe controller is not in L1 link state. If true, apply 69 * fix, which will put the controller into L1 link state, from 70 * which it can return to L0s/L0 on its own. 71 */ 72 if ((pmsr & PMEL1RX) && ((pmsr & PMSTATE) != PMSTATE_L1)) { 73 writel(L1IATN, pcie_base + PMCTLR); 74 ret = readl_poll_timeout_atomic(pcie_base + PMSR, val, 75 val & L1FAEG, 10, 1000); 76 if (ret) { 77 dev_warn_ratelimited(pcie_dev, 78 "Timeout waiting for L1 link state, ret=%d\n", 79 ret); 80 } 81 writel(L1FAEG | PMEL1RX, pcie_base + PMSR); 82 } 83 84 return ret; 85 } 86 87 static struct rcar_pcie_host *msi_to_host(struct rcar_msi *msi) 88 { 89 return container_of(msi, struct rcar_pcie_host, msi); 90 } 91 92 static u32 rcar_read_conf(struct rcar_pcie *pcie, int where) 93 { 94 unsigned int shift = BITS_PER_BYTE * (where & 3); 95 u32 val = rcar_pci_read_reg(pcie, where & ~3); 96 97 return val >> shift; 98 } 99 100 #ifdef CONFIG_ARM 101 #define __rcar_pci_rw_reg_workaround(instr) \ 102 " .arch armv7-a\n" \ 103 "1: " instr " %1, [%2]\n" \ 104 "2: isb\n" \ 105 "3: .pushsection .text.fixup,\"ax\"\n" \ 106 " .align 2\n" \ 107 "4: mov %0, #" __stringify(PCIBIOS_SET_FAILED) "\n" \ 108 " b 3b\n" \ 109 " .popsection\n" \ 110 " .pushsection __ex_table,\"a\"\n" \ 111 " .align 3\n" \ 112 " .long 1b, 4b\n" \ 113 " .long 2b, 4b\n" \ 114 " .popsection\n" 115 #endif 116 117 static int rcar_pci_write_reg_workaround(struct rcar_pcie *pcie, u32 val, 118 unsigned int reg) 119 { 120 int error = PCIBIOS_SUCCESSFUL; 121 #ifdef CONFIG_ARM 122 asm volatile( 123 __rcar_pci_rw_reg_workaround("str") 124 : "+r"(error):"r"(val), "r"(pcie->base + reg) : "memory"); 125 #else 126 rcar_pci_write_reg(pcie, val, reg); 127 #endif 128 return error; 129 } 130 131 static int rcar_pci_read_reg_workaround(struct rcar_pcie *pcie, u32 *val, 132 unsigned int reg) 133 { 134 int error = PCIBIOS_SUCCESSFUL; 135 #ifdef CONFIG_ARM 136 asm volatile( 137 __rcar_pci_rw_reg_workaround("ldr") 138 : "+r"(error), "=r"(*val) : "r"(pcie->base + reg) : "memory"); 139 140 if (error != PCIBIOS_SUCCESSFUL) 141 PCI_SET_ERROR_RESPONSE(val); 142 #else 143 *val = rcar_pci_read_reg(pcie, reg); 144 #endif 145 return error; 146 } 147 148 /* Serialization is provided by 'pci_lock' in drivers/pci/access.c */ 149 static int rcar_pcie_config_access(struct rcar_pcie_host *host, 150 unsigned char access_type, struct pci_bus *bus, 151 unsigned int devfn, int where, u32 *data) 152 { 153 struct rcar_pcie *pcie = &host->pcie; 154 unsigned int dev, func, reg, index; 155 int ret; 156 157 /* Wake the bus up in case it is in L1 state. */ 158 ret = rcar_pcie_wakeup(pcie->dev, pcie->base); 159 if (ret) { 160 PCI_SET_ERROR_RESPONSE(data); 161 return PCIBIOS_SET_FAILED; 162 } 163 164 dev = PCI_SLOT(devfn); 165 func = PCI_FUNC(devfn); 166 reg = where & ~3; 167 index = reg / 4; 168 169 /* 170 * While each channel has its own memory-mapped extended config 171 * space, it's generally only accessible when in endpoint mode. 172 * When in root complex mode, the controller is unable to target 173 * itself with either type 0 or type 1 accesses, and indeed, any 174 * controller-initiated target transfer to its own config space 175 * results in a completer abort. 176 * 177 * Each channel effectively only supports a single device, but as 178 * the same channel <-> device access works for any PCI_SLOT() 179 * value, we cheat a bit here and bind the controller's config 180 * space to devfn 0 in order to enable self-enumeration. In this 181 * case the regular ECAR/ECDR path is sidelined and the mangled 182 * config access itself is initiated as an internal bus transaction. 183 */ 184 if (pci_is_root_bus(bus)) { 185 if (dev != 0) 186 return PCIBIOS_DEVICE_NOT_FOUND; 187 188 if (access_type == RCAR_PCI_ACCESS_READ) 189 *data = rcar_pci_read_reg(pcie, PCICONF(index)); 190 else 191 rcar_pci_write_reg(pcie, *data, PCICONF(index)); 192 193 return PCIBIOS_SUCCESSFUL; 194 } 195 196 /* Clear errors */ 197 rcar_pci_write_reg(pcie, rcar_pci_read_reg(pcie, PCIEERRFR), PCIEERRFR); 198 199 /* Set the PIO address */ 200 rcar_pci_write_reg(pcie, PCIE_CONF_BUS(bus->number) | 201 PCIE_CONF_DEV(dev) | PCIE_CONF_FUNC(func) | reg, PCIECAR); 202 203 /* Enable the configuration access */ 204 if (pci_is_root_bus(bus->parent)) 205 rcar_pci_write_reg(pcie, PCIECCTLR_CCIE | TYPE0, PCIECCTLR); 206 else 207 rcar_pci_write_reg(pcie, PCIECCTLR_CCIE | TYPE1, PCIECCTLR); 208 209 /* Check for errors */ 210 if (rcar_pci_read_reg(pcie, PCIEERRFR) & UNSUPPORTED_REQUEST) 211 return PCIBIOS_DEVICE_NOT_FOUND; 212 213 /* Check for master and target aborts */ 214 if (rcar_read_conf(pcie, RCONF(PCI_STATUS)) & 215 (PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT)) 216 return PCIBIOS_DEVICE_NOT_FOUND; 217 218 if (access_type == RCAR_PCI_ACCESS_READ) 219 ret = rcar_pci_read_reg_workaround(pcie, data, PCIECDR); 220 else 221 ret = rcar_pci_write_reg_workaround(pcie, *data, PCIECDR); 222 223 /* Disable the configuration access */ 224 rcar_pci_write_reg(pcie, 0, PCIECCTLR); 225 226 return ret; 227 } 228 229 static int rcar_pcie_read_conf(struct pci_bus *bus, unsigned int devfn, 230 int where, int size, u32 *val) 231 { 232 struct rcar_pcie_host *host = bus->sysdata; 233 int ret; 234 235 ret = rcar_pcie_config_access(host, RCAR_PCI_ACCESS_READ, 236 bus, devfn, where, val); 237 if (ret != PCIBIOS_SUCCESSFUL) 238 return ret; 239 240 if (size == 1) 241 *val = (*val >> (BITS_PER_BYTE * (where & 3))) & 0xff; 242 else if (size == 2) 243 *val = (*val >> (BITS_PER_BYTE * (where & 2))) & 0xffff; 244 245 dev_dbg(&bus->dev, "pcie-config-read: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08x\n", 246 bus->number, devfn, where, size, *val); 247 248 return ret; 249 } 250 251 /* Serialization is provided by 'pci_lock' in drivers/pci/access.c */ 252 static int rcar_pcie_write_conf(struct pci_bus *bus, unsigned int devfn, 253 int where, int size, u32 val) 254 { 255 struct rcar_pcie_host *host = bus->sysdata; 256 unsigned int shift; 257 u32 data; 258 int ret; 259 260 ret = rcar_pcie_config_access(host, RCAR_PCI_ACCESS_READ, 261 bus, devfn, where, &data); 262 if (ret != PCIBIOS_SUCCESSFUL) 263 return ret; 264 265 dev_dbg(&bus->dev, "pcie-config-write: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08x\n", 266 bus->number, devfn, where, size, val); 267 268 if (size == 1) { 269 shift = BITS_PER_BYTE * (where & 3); 270 data &= ~(0xff << shift); 271 data |= ((val & 0xff) << shift); 272 } else if (size == 2) { 273 shift = BITS_PER_BYTE * (where & 2); 274 data &= ~(0xffff << shift); 275 data |= ((val & 0xffff) << shift); 276 } else 277 data = val; 278 279 ret = rcar_pcie_config_access(host, RCAR_PCI_ACCESS_WRITE, 280 bus, devfn, where, &data); 281 282 return ret; 283 } 284 285 static struct pci_ops rcar_pcie_ops = { 286 .read = rcar_pcie_read_conf, 287 .write = rcar_pcie_write_conf, 288 }; 289 290 static void rcar_pcie_force_speedup(struct rcar_pcie *pcie) 291 { 292 struct device *dev = pcie->dev; 293 unsigned int timeout = 1000; 294 u32 macsr; 295 296 if ((rcar_pci_read_reg(pcie, MACS2R) & LINK_SPEED) != LINK_SPEED_5_0GTS) 297 return; 298 299 if (rcar_pci_read_reg(pcie, MACCTLR) & SPEED_CHANGE) { 300 dev_err(dev, "Speed change already in progress\n"); 301 return; 302 } 303 304 macsr = rcar_pci_read_reg(pcie, MACSR); 305 if ((macsr & LINK_SPEED) == LINK_SPEED_5_0GTS) 306 goto done; 307 308 /* Set target link speed to 5.0 GT/s */ 309 rcar_rmw32(pcie, EXPCAP(12), PCI_EXP_LNKSTA_CLS, 310 PCI_EXP_LNKSTA_CLS_5_0GB); 311 312 /* Set speed change reason as intentional factor */ 313 rcar_rmw32(pcie, MACCGSPSETR, SPCNGRSN, 0); 314 315 /* Clear SPCHGFIN, SPCHGSUC, and SPCHGFAIL */ 316 if (macsr & (SPCHGFIN | SPCHGSUC | SPCHGFAIL)) 317 rcar_pci_write_reg(pcie, macsr, MACSR); 318 319 /* Start link speed change */ 320 rcar_rmw32(pcie, MACCTLR, SPEED_CHANGE, SPEED_CHANGE); 321 322 while (timeout--) { 323 macsr = rcar_pci_read_reg(pcie, MACSR); 324 if (macsr & SPCHGFIN) { 325 /* Clear the interrupt bits */ 326 rcar_pci_write_reg(pcie, macsr, MACSR); 327 328 if (macsr & SPCHGFAIL) 329 dev_err(dev, "Speed change failed\n"); 330 331 goto done; 332 } 333 334 msleep(1); 335 } 336 337 dev_err(dev, "Speed change timed out\n"); 338 339 done: 340 dev_info(dev, "Current link speed is %s GT/s\n", 341 (macsr & LINK_SPEED) == LINK_SPEED_5_0GTS ? "5" : "2.5"); 342 } 343 344 static void rcar_pcie_hw_enable(struct rcar_pcie_host *host) 345 { 346 struct rcar_pcie *pcie = &host->pcie; 347 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(host); 348 struct resource_entry *win; 349 int i = 0; 350 351 /* Try setting 5 GT/s link speed */ 352 rcar_pcie_force_speedup(pcie); 353 354 /* Setup PCI resources */ 355 resource_list_for_each_entry(win, &bridge->windows) { 356 struct resource *res = win->res; 357 358 if (!res->flags) 359 continue; 360 361 switch (resource_type(res)) { 362 case IORESOURCE_IO: 363 case IORESOURCE_MEM: 364 rcar_pcie_set_outbound(pcie, i, win); 365 i++; 366 break; 367 } 368 } 369 } 370 371 static int rcar_pcie_enable(struct rcar_pcie_host *host) 372 { 373 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(host); 374 375 rcar_pcie_hw_enable(host); 376 377 pci_add_flags(PCI_REASSIGN_ALL_BUS); 378 379 bridge->sysdata = host; 380 bridge->ops = &rcar_pcie_ops; 381 382 return pci_host_probe(bridge); 383 } 384 385 static int phy_wait_for_ack(struct rcar_pcie *pcie) 386 { 387 struct device *dev = pcie->dev; 388 unsigned int timeout = 100; 389 390 while (timeout--) { 391 if (rcar_pci_read_reg(pcie, H1_PCIEPHYADRR) & PHY_ACK) 392 return 0; 393 394 udelay(100); 395 } 396 397 dev_err(dev, "Access to PCIe phy timed out\n"); 398 399 return -ETIMEDOUT; 400 } 401 402 static void phy_write_reg(struct rcar_pcie *pcie, 403 unsigned int rate, u32 addr, 404 unsigned int lane, u32 data) 405 { 406 u32 phyaddr; 407 408 phyaddr = WRITE_CMD | 409 ((rate & 1) << RATE_POS) | 410 ((lane & 0xf) << LANE_POS) | 411 ((addr & 0xff) << ADR_POS); 412 413 /* Set write data */ 414 rcar_pci_write_reg(pcie, data, H1_PCIEPHYDOUTR); 415 rcar_pci_write_reg(pcie, phyaddr, H1_PCIEPHYADRR); 416 417 /* Ignore errors as they will be dealt with if the data link is down */ 418 phy_wait_for_ack(pcie); 419 420 /* Clear command */ 421 rcar_pci_write_reg(pcie, 0, H1_PCIEPHYDOUTR); 422 rcar_pci_write_reg(pcie, 0, H1_PCIEPHYADRR); 423 424 /* Ignore errors as they will be dealt with if the data link is down */ 425 phy_wait_for_ack(pcie); 426 } 427 428 static int rcar_pcie_hw_init(struct rcar_pcie *pcie) 429 { 430 int err; 431 432 /* Begin initialization */ 433 rcar_pci_write_reg(pcie, 0, PCIETCTLR); 434 435 /* Set mode */ 436 rcar_pci_write_reg(pcie, 1, PCIEMSR); 437 438 err = rcar_pcie_wait_for_phyrdy(pcie); 439 if (err) 440 return err; 441 442 /* 443 * Initial header for port config space is type 1, set the device 444 * class to match. Hardware takes care of propagating the IDSETR 445 * settings, so there is no need to bother with a quirk. 446 */ 447 rcar_pci_write_reg(pcie, PCI_CLASS_BRIDGE_PCI_NORMAL << 8, IDSETR1); 448 449 /* 450 * Setup Secondary Bus Number & Subordinate Bus Number, even though 451 * they aren't used, to avoid bridge being detected as broken. 452 */ 453 rcar_rmw32(pcie, RCONF(PCI_SECONDARY_BUS), 0xff, 1); 454 rcar_rmw32(pcie, RCONF(PCI_SUBORDINATE_BUS), 0xff, 1); 455 456 /* Initialize default capabilities. */ 457 rcar_rmw32(pcie, REXPCAP(0), 0xff, PCI_CAP_ID_EXP); 458 rcar_rmw32(pcie, REXPCAP(PCI_EXP_FLAGS), 459 PCI_EXP_FLAGS_TYPE, PCI_EXP_TYPE_ROOT_PORT << 4); 460 rcar_rmw32(pcie, RCONF(PCI_HEADER_TYPE), PCI_HEADER_TYPE_MASK, 461 PCI_HEADER_TYPE_BRIDGE); 462 463 /* Enable data link layer active state reporting */ 464 rcar_rmw32(pcie, REXPCAP(PCI_EXP_LNKCAP), PCI_EXP_LNKCAP_DLLLARC, 465 PCI_EXP_LNKCAP_DLLLARC); 466 467 /* Write out the physical slot number = 0 */ 468 rcar_rmw32(pcie, REXPCAP(PCI_EXP_SLTCAP), PCI_EXP_SLTCAP_PSN, 0); 469 470 /* Set the completion timer timeout to the maximum 50ms. */ 471 rcar_rmw32(pcie, TLCTLR + 1, 0x3f, 50); 472 473 /* Terminate list of capabilities (Next Capability Offset=0) */ 474 rcar_rmw32(pcie, RVCCAP(0), 0xfff00000, 0); 475 476 /* Enable MSI */ 477 if (IS_ENABLED(CONFIG_PCI_MSI)) 478 rcar_pci_write_reg(pcie, 0x801f0000, PCIEMSITXR); 479 480 rcar_pci_write_reg(pcie, MACCTLR_INIT_VAL, MACCTLR); 481 482 /* Finish initialization - establish a PCI Express link */ 483 rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR); 484 485 /* This will timeout if we don't have a link. */ 486 err = rcar_pcie_wait_for_dl(pcie); 487 if (err) 488 return err; 489 490 /* Enable INTx interrupts */ 491 rcar_rmw32(pcie, PCIEINTXR, 0, 0xF << 8); 492 493 wmb(); 494 495 return 0; 496 } 497 498 static int rcar_pcie_phy_init_h1(struct rcar_pcie_host *host) 499 { 500 struct rcar_pcie *pcie = &host->pcie; 501 502 /* Initialize the phy */ 503 phy_write_reg(pcie, 0, 0x42, 0x1, 0x0EC34191); 504 phy_write_reg(pcie, 1, 0x42, 0x1, 0x0EC34180); 505 phy_write_reg(pcie, 0, 0x43, 0x1, 0x00210188); 506 phy_write_reg(pcie, 1, 0x43, 0x1, 0x00210188); 507 phy_write_reg(pcie, 0, 0x44, 0x1, 0x015C0014); 508 phy_write_reg(pcie, 1, 0x44, 0x1, 0x015C0014); 509 phy_write_reg(pcie, 1, 0x4C, 0x1, 0x786174A0); 510 phy_write_reg(pcie, 1, 0x4D, 0x1, 0x048000BB); 511 phy_write_reg(pcie, 0, 0x51, 0x1, 0x079EC062); 512 phy_write_reg(pcie, 0, 0x52, 0x1, 0x20000000); 513 phy_write_reg(pcie, 1, 0x52, 0x1, 0x20000000); 514 phy_write_reg(pcie, 1, 0x56, 0x1, 0x00003806); 515 516 phy_write_reg(pcie, 0, 0x60, 0x1, 0x004B03A5); 517 phy_write_reg(pcie, 0, 0x64, 0x1, 0x3F0F1F0F); 518 phy_write_reg(pcie, 0, 0x66, 0x1, 0x00008000); 519 520 return 0; 521 } 522 523 static int rcar_pcie_phy_init_gen2(struct rcar_pcie_host *host) 524 { 525 struct rcar_pcie *pcie = &host->pcie; 526 527 /* 528 * These settings come from the R-Car Series, 2nd Generation User's 529 * Manual, section 50.3.1 (2) Initialization of the physical layer. 530 */ 531 rcar_pci_write_reg(pcie, 0x000f0030, GEN2_PCIEPHYADDR); 532 rcar_pci_write_reg(pcie, 0x00381203, GEN2_PCIEPHYDATA); 533 rcar_pci_write_reg(pcie, 0x00000001, GEN2_PCIEPHYCTRL); 534 rcar_pci_write_reg(pcie, 0x00000006, GEN2_PCIEPHYCTRL); 535 536 rcar_pci_write_reg(pcie, 0x000f0054, GEN2_PCIEPHYADDR); 537 /* The following value is for DC connection, no termination resistor */ 538 rcar_pci_write_reg(pcie, 0x13802007, GEN2_PCIEPHYDATA); 539 rcar_pci_write_reg(pcie, 0x00000001, GEN2_PCIEPHYCTRL); 540 rcar_pci_write_reg(pcie, 0x00000006, GEN2_PCIEPHYCTRL); 541 542 return 0; 543 } 544 545 static int rcar_pcie_phy_init_gen3(struct rcar_pcie_host *host) 546 { 547 int err; 548 549 err = phy_init(host->phy); 550 if (err) 551 return err; 552 553 err = phy_power_on(host->phy); 554 if (err) 555 phy_exit(host->phy); 556 557 return err; 558 } 559 560 static irqreturn_t rcar_pcie_msi_irq(int irq, void *data) 561 { 562 struct rcar_pcie_host *host = data; 563 struct rcar_pcie *pcie = &host->pcie; 564 struct rcar_msi *msi = &host->msi; 565 struct device *dev = pcie->dev; 566 unsigned long reg; 567 568 reg = rcar_pci_read_reg(pcie, PCIEMSIFR); 569 570 /* MSI & INTx share an interrupt - we only handle MSI here */ 571 if (!reg) 572 return IRQ_NONE; 573 574 while (reg) { 575 unsigned int index = find_first_bit(®, 32); 576 int ret; 577 578 ret = generic_handle_domain_irq(msi->domain, index); 579 if (ret) { 580 /* Unknown MSI, just clear it */ 581 dev_dbg(dev, "unexpected MSI\n"); 582 rcar_pci_write_reg(pcie, BIT(index), PCIEMSIFR); 583 } 584 585 /* see if there's any more pending in this vector */ 586 reg = rcar_pci_read_reg(pcie, PCIEMSIFR); 587 } 588 589 return IRQ_HANDLED; 590 } 591 592 static void rcar_msi_irq_ack(struct irq_data *d) 593 { 594 struct rcar_msi *msi = irq_data_get_irq_chip_data(d); 595 struct rcar_pcie *pcie = &msi_to_host(msi)->pcie; 596 597 /* clear the interrupt */ 598 rcar_pci_write_reg(pcie, BIT(d->hwirq), PCIEMSIFR); 599 } 600 601 static void rcar_msi_irq_mask(struct irq_data *d) 602 { 603 struct rcar_msi *msi = irq_data_get_irq_chip_data(d); 604 struct rcar_pcie *pcie = &msi_to_host(msi)->pcie; 605 u32 value; 606 607 scoped_guard(raw_spinlock_irqsave, &msi->mask_lock) { 608 value = rcar_pci_read_reg(pcie, PCIEMSIIER); 609 value &= ~BIT(d->hwirq); 610 rcar_pci_write_reg(pcie, value, PCIEMSIIER); 611 } 612 } 613 614 static void rcar_msi_irq_unmask(struct irq_data *d) 615 { 616 struct rcar_msi *msi = irq_data_get_irq_chip_data(d); 617 struct rcar_pcie *pcie = &msi_to_host(msi)->pcie; 618 u32 value; 619 620 scoped_guard(raw_spinlock_irqsave, &msi->mask_lock) { 621 value = rcar_pci_read_reg(pcie, PCIEMSIIER); 622 value |= BIT(d->hwirq); 623 rcar_pci_write_reg(pcie, value, PCIEMSIIER); 624 } 625 } 626 627 static void rcar_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) 628 { 629 struct rcar_msi *msi = irq_data_get_irq_chip_data(data); 630 struct rcar_pcie *pcie = &msi_to_host(msi)->pcie; 631 632 msg->address_lo = rcar_pci_read_reg(pcie, PCIEMSIALR) & ~MSIFE; 633 msg->address_hi = rcar_pci_read_reg(pcie, PCIEMSIAUR); 634 msg->data = data->hwirq; 635 } 636 637 static struct irq_chip rcar_msi_bottom_chip = { 638 .name = "R-Car MSI", 639 .irq_ack = rcar_msi_irq_ack, 640 .irq_mask = rcar_msi_irq_mask, 641 .irq_unmask = rcar_msi_irq_unmask, 642 .irq_compose_msi_msg = rcar_compose_msi_msg, 643 }; 644 645 static int rcar_msi_domain_alloc(struct irq_domain *domain, unsigned int virq, 646 unsigned int nr_irqs, void *args) 647 { 648 struct rcar_msi *msi = domain->host_data; 649 unsigned int i; 650 int hwirq; 651 652 mutex_lock(&msi->map_lock); 653 654 hwirq = bitmap_find_free_region(msi->used, INT_PCI_MSI_NR, order_base_2(nr_irqs)); 655 656 mutex_unlock(&msi->map_lock); 657 658 if (hwirq < 0) 659 return -ENOSPC; 660 661 for (i = 0; i < nr_irqs; i++) 662 irq_domain_set_info(domain, virq + i, hwirq + i, 663 &rcar_msi_bottom_chip, domain->host_data, 664 handle_edge_irq, NULL, NULL); 665 666 return 0; 667 } 668 669 static void rcar_msi_domain_free(struct irq_domain *domain, unsigned int virq, 670 unsigned int nr_irqs) 671 { 672 struct irq_data *d = irq_domain_get_irq_data(domain, virq); 673 struct rcar_msi *msi = domain->host_data; 674 675 mutex_lock(&msi->map_lock); 676 677 bitmap_release_region(msi->used, d->hwirq, order_base_2(nr_irqs)); 678 679 mutex_unlock(&msi->map_lock); 680 } 681 682 static const struct irq_domain_ops rcar_msi_domain_ops = { 683 .alloc = rcar_msi_domain_alloc, 684 .free = rcar_msi_domain_free, 685 }; 686 687 #define RCAR_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS | \ 688 MSI_FLAG_USE_DEF_CHIP_OPS | \ 689 MSI_FLAG_PCI_MSI_MASK_PARENT | \ 690 MSI_FLAG_NO_AFFINITY) 691 692 #define RCAR_MSI_FLAGS_SUPPORTED (MSI_GENERIC_FLAGS_MASK | \ 693 MSI_FLAG_MULTI_PCI_MSI) 694 695 static const struct msi_parent_ops rcar_msi_parent_ops = { 696 .required_flags = RCAR_MSI_FLAGS_REQUIRED, 697 .supported_flags = RCAR_MSI_FLAGS_SUPPORTED, 698 .bus_select_token = DOMAIN_BUS_PCI_MSI, 699 .chip_flags = MSI_CHIP_FLAG_SET_ACK, 700 .prefix = "RCAR-", 701 .init_dev_msi_info = msi_lib_init_dev_msi_info, 702 }; 703 704 static int rcar_allocate_domains(struct rcar_msi *msi) 705 { 706 struct rcar_pcie *pcie = &msi_to_host(msi)->pcie; 707 struct irq_domain_info info = { 708 .fwnode = dev_fwnode(pcie->dev), 709 .ops = &rcar_msi_domain_ops, 710 .host_data = msi, 711 .size = INT_PCI_MSI_NR, 712 }; 713 714 msi->domain = msi_create_parent_irq_domain(&info, &rcar_msi_parent_ops); 715 if (!msi->domain) { 716 dev_err(pcie->dev, "failed to create IRQ domain\n"); 717 return -ENOMEM; 718 } 719 720 return 0; 721 } 722 723 static void rcar_free_domains(struct rcar_msi *msi) 724 { 725 irq_domain_remove(msi->domain); 726 } 727 728 static int rcar_pcie_enable_msi(struct rcar_pcie_host *host) 729 { 730 struct rcar_pcie *pcie = &host->pcie; 731 struct device *dev = pcie->dev; 732 struct rcar_msi *msi = &host->msi; 733 struct resource res; 734 int err; 735 736 mutex_init(&msi->map_lock); 737 raw_spin_lock_init(&msi->mask_lock); 738 739 err = of_address_to_resource(dev->of_node, 0, &res); 740 if (err) 741 return err; 742 743 err = rcar_allocate_domains(msi); 744 if (err) 745 return err; 746 747 /* Two IRQs are for MSI, but they are also used for non-MSI IRQs */ 748 err = devm_request_irq(dev, msi->irq1, rcar_pcie_msi_irq, 749 IRQF_SHARED | IRQF_NO_THREAD, 750 rcar_msi_bottom_chip.name, host); 751 if (err < 0) { 752 dev_err(dev, "failed to request IRQ: %d\n", err); 753 goto err; 754 } 755 756 err = devm_request_irq(dev, msi->irq2, rcar_pcie_msi_irq, 757 IRQF_SHARED | IRQF_NO_THREAD, 758 rcar_msi_bottom_chip.name, host); 759 if (err < 0) { 760 dev_err(dev, "failed to request IRQ: %d\n", err); 761 goto err; 762 } 763 764 /* Disable all MSIs */ 765 rcar_pci_write_reg(pcie, 0, PCIEMSIIER); 766 767 /* 768 * Setup MSI data target using RC base address, which is guaranteed 769 * to be in the low 32bit range on any R-Car HW. 770 */ 771 rcar_pci_write_reg(pcie, lower_32_bits(res.start) | MSIFE, PCIEMSIALR); 772 rcar_pci_write_reg(pcie, upper_32_bits(res.start), PCIEMSIAUR); 773 774 return 0; 775 776 err: 777 rcar_free_domains(msi); 778 return err; 779 } 780 781 static void rcar_pcie_teardown_msi(struct rcar_pcie_host *host) 782 { 783 struct rcar_pcie *pcie = &host->pcie; 784 785 /* Disable all MSI interrupts */ 786 rcar_pci_write_reg(pcie, 0, PCIEMSIIER); 787 788 /* Disable address decoding of the MSI interrupt, MSIFE */ 789 rcar_pci_write_reg(pcie, 0, PCIEMSIALR); 790 791 rcar_free_domains(&host->msi); 792 } 793 794 static int rcar_pcie_get_resources(struct rcar_pcie_host *host) 795 { 796 struct rcar_pcie *pcie = &host->pcie; 797 struct device *dev = pcie->dev; 798 struct resource res; 799 int err, i; 800 801 host->phy = devm_phy_optional_get(dev, "pcie"); 802 if (IS_ERR(host->phy)) 803 return PTR_ERR(host->phy); 804 805 err = of_address_to_resource(dev->of_node, 0, &res); 806 if (err) 807 return err; 808 809 pcie->base = devm_ioremap_resource(dev, &res); 810 if (IS_ERR(pcie->base)) 811 return PTR_ERR(pcie->base); 812 813 host->bus_clk = devm_clk_get(dev, "pcie_bus"); 814 if (IS_ERR(host->bus_clk)) { 815 dev_err(dev, "cannot get pcie bus clock\n"); 816 return PTR_ERR(host->bus_clk); 817 } 818 819 i = irq_of_parse_and_map(dev->of_node, 0); 820 if (!i) { 821 dev_err(dev, "cannot get platform resources for msi interrupt\n"); 822 err = -ENOENT; 823 goto err_irq1; 824 } 825 host->msi.irq1 = i; 826 827 i = irq_of_parse_and_map(dev->of_node, 1); 828 if (!i) { 829 dev_err(dev, "cannot get platform resources for msi interrupt\n"); 830 err = -ENOENT; 831 goto err_irq2; 832 } 833 host->msi.irq2 = i; 834 835 return 0; 836 837 err_irq2: 838 irq_dispose_mapping(host->msi.irq1); 839 err_irq1: 840 return err; 841 } 842 843 static int rcar_pcie_inbound_ranges(struct rcar_pcie *pcie, 844 struct resource_entry *entry, 845 int *index) 846 { 847 u64 restype = entry->res->flags; 848 u64 cpu_addr = entry->res->start; 849 u64 cpu_end = entry->res->end; 850 u64 pci_addr = entry->res->start - entry->offset; 851 u32 flags = LAM_64BIT | LAR_ENABLE; 852 u64 mask; 853 u64 size = resource_size(entry->res); 854 int idx = *index; 855 856 if (restype & IORESOURCE_PREFETCH) 857 flags |= LAM_PREFETCH; 858 859 while (cpu_addr < cpu_end) { 860 if (idx >= MAX_NR_INBOUND_MAPS - 1) { 861 dev_err(pcie->dev, "Failed to map inbound regions!\n"); 862 return -EINVAL; 863 } 864 865 /* 866 * If the size of the range is larger than the alignment of 867 * the start address, we have to use multiple entries to 868 * perform the mapping. 869 */ 870 if (cpu_addr > 0) { 871 unsigned long nr_zeros = __ffs64(cpu_addr); 872 u64 alignment = 1ULL << nr_zeros; 873 874 size = min(size, alignment); 875 } 876 877 /* Hardware supports max 4GiB inbound region */ 878 size = min(size, 1ULL << 32); 879 880 mask = roundup_pow_of_two(size) - 1; 881 mask &= ~0xf; 882 883 rcar_pcie_set_inbound(pcie, cpu_addr, pci_addr, 884 lower_32_bits(mask) | flags, idx, true); 885 886 pci_addr += size; 887 cpu_addr += size; 888 idx += 2; 889 } 890 *index = idx; 891 892 return 0; 893 } 894 895 static int rcar_pcie_parse_map_dma_ranges(struct rcar_pcie_host *host) 896 { 897 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(host); 898 struct resource_entry *entry; 899 int index = 0, err = 0; 900 901 resource_list_for_each_entry(entry, &bridge->dma_ranges) { 902 err = rcar_pcie_inbound_ranges(&host->pcie, entry, &index); 903 if (err) 904 break; 905 } 906 907 return err; 908 } 909 910 static const struct of_device_id rcar_pcie_of_match[] = { 911 { .compatible = "renesas,pcie-r8a7779", 912 .data = rcar_pcie_phy_init_h1 }, 913 { .compatible = "renesas,pcie-r8a7790", 914 .data = rcar_pcie_phy_init_gen2 }, 915 { .compatible = "renesas,pcie-r8a7791", 916 .data = rcar_pcie_phy_init_gen2 }, 917 { .compatible = "renesas,pcie-rcar-gen2", 918 .data = rcar_pcie_phy_init_gen2 }, 919 { .compatible = "renesas,pcie-r8a7795", 920 .data = rcar_pcie_phy_init_gen3 }, 921 { .compatible = "renesas,pcie-rcar-gen3", 922 .data = rcar_pcie_phy_init_gen3 }, 923 {}, 924 }; 925 926 /* Design note 346 from Linear Technology says order is not important. */ 927 static const char * const rcar_pcie_supplies[] = { 928 "vpcie1v5", 929 "vpcie3v3", 930 "vpcie12v", 931 }; 932 933 static int rcar_pcie_probe(struct platform_device *pdev) 934 { 935 struct device *dev = &pdev->dev; 936 struct pci_host_bridge *bridge; 937 struct rcar_pcie_host *host; 938 struct rcar_pcie *pcie; 939 unsigned int i; 940 u32 data; 941 int err; 942 943 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*host)); 944 if (!bridge) 945 return -ENOMEM; 946 947 host = pci_host_bridge_priv(bridge); 948 pcie = &host->pcie; 949 pcie->dev = dev; 950 platform_set_drvdata(pdev, host); 951 952 for (i = 0; i < ARRAY_SIZE(rcar_pcie_supplies); i++) { 953 err = devm_regulator_get_enable_optional(dev, rcar_pcie_supplies[i]); 954 if (err < 0 && err != -ENODEV) 955 return dev_err_probe(dev, err, "failed to enable regulator: %s\n", 956 rcar_pcie_supplies[i]); 957 } 958 959 pm_runtime_enable(pcie->dev); 960 err = pm_runtime_get_sync(pcie->dev); 961 if (err < 0) { 962 dev_err(pcie->dev, "pm_runtime_get_sync failed\n"); 963 goto err_pm_put; 964 } 965 966 err = rcar_pcie_get_resources(host); 967 if (err < 0) { 968 dev_err(dev, "failed to request resources: %d\n", err); 969 goto err_pm_put; 970 } 971 972 err = clk_prepare_enable(host->bus_clk); 973 if (err) { 974 dev_err(dev, "failed to enable bus clock: %d\n", err); 975 goto err_unmap_msi_irqs; 976 } 977 978 err = rcar_pcie_parse_map_dma_ranges(host); 979 if (err) 980 goto err_clk_disable; 981 982 host->phy_init_fn = of_device_get_match_data(dev); 983 err = host->phy_init_fn(host); 984 if (err) { 985 dev_err(dev, "failed to init PCIe PHY\n"); 986 goto err_clk_disable; 987 } 988 989 /* Failure to get a link might just be that no cards are inserted */ 990 if (rcar_pcie_hw_init(pcie)) { 991 dev_info(dev, "PCIe link down\n"); 992 err = -ENODEV; 993 goto err_phy_shutdown; 994 } 995 996 data = rcar_pci_read_reg(pcie, MACSR); 997 dev_info(dev, "PCIe x%d: link up\n", (data >> 20) & 0x3f); 998 999 if (IS_ENABLED(CONFIG_PCI_MSI)) { 1000 err = rcar_pcie_enable_msi(host); 1001 if (err < 0) { 1002 dev_err(dev, 1003 "failed to enable MSI support: %d\n", 1004 err); 1005 goto err_phy_shutdown; 1006 } 1007 } 1008 1009 err = rcar_pcie_enable(host); 1010 if (err) 1011 goto err_msi_teardown; 1012 1013 return 0; 1014 1015 err_msi_teardown: 1016 if (IS_ENABLED(CONFIG_PCI_MSI)) 1017 rcar_pcie_teardown_msi(host); 1018 1019 err_phy_shutdown: 1020 if (host->phy) { 1021 phy_power_off(host->phy); 1022 phy_exit(host->phy); 1023 } 1024 1025 err_clk_disable: 1026 clk_disable_unprepare(host->bus_clk); 1027 1028 err_unmap_msi_irqs: 1029 irq_dispose_mapping(host->msi.irq2); 1030 irq_dispose_mapping(host->msi.irq1); 1031 1032 err_pm_put: 1033 pm_runtime_put(dev); 1034 pm_runtime_disable(dev); 1035 1036 return err; 1037 } 1038 1039 static int rcar_pcie_resume(struct device *dev) 1040 { 1041 struct rcar_pcie_host *host = dev_get_drvdata(dev); 1042 struct rcar_pcie *pcie = &host->pcie; 1043 unsigned int data; 1044 int err; 1045 1046 err = rcar_pcie_parse_map_dma_ranges(host); 1047 if (err) 1048 return 0; 1049 1050 /* Failure to get a link might just be that no cards are inserted */ 1051 err = host->phy_init_fn(host); 1052 if (err) { 1053 dev_info(dev, "PCIe link down\n"); 1054 return 0; 1055 } 1056 1057 data = rcar_pci_read_reg(pcie, MACSR); 1058 dev_info(dev, "PCIe x%d: link up\n", (data >> 20) & 0x3f); 1059 1060 /* Enable MSI */ 1061 if (IS_ENABLED(CONFIG_PCI_MSI)) { 1062 struct resource res; 1063 u32 val; 1064 1065 of_address_to_resource(dev->of_node, 0, &res); 1066 rcar_pci_write_reg(pcie, upper_32_bits(res.start), PCIEMSIAUR); 1067 rcar_pci_write_reg(pcie, lower_32_bits(res.start) | MSIFE, PCIEMSIALR); 1068 1069 bitmap_to_arr32(&val, host->msi.used, INT_PCI_MSI_NR); 1070 rcar_pci_write_reg(pcie, val, PCIEMSIIER); 1071 } 1072 1073 rcar_pcie_hw_enable(host); 1074 1075 return 0; 1076 } 1077 1078 static int rcar_pcie_resume_noirq(struct device *dev) 1079 { 1080 struct rcar_pcie_host *host = dev_get_drvdata(dev); 1081 struct rcar_pcie *pcie = &host->pcie; 1082 1083 if (rcar_pci_read_reg(pcie, PMSR) && 1084 !(rcar_pci_read_reg(pcie, PCIETCTLR) & DL_DOWN)) 1085 return 0; 1086 1087 /* Re-establish the PCIe link */ 1088 rcar_pci_write_reg(pcie, MACCTLR_INIT_VAL, MACCTLR); 1089 rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR); 1090 return rcar_pcie_wait_for_dl(pcie); 1091 } 1092 1093 static const struct dev_pm_ops rcar_pcie_pm_ops = { 1094 SYSTEM_SLEEP_PM_OPS(NULL, rcar_pcie_resume) 1095 .resume_noirq = rcar_pcie_resume_noirq, 1096 }; 1097 1098 static struct platform_driver rcar_pcie_driver = { 1099 .driver = { 1100 .name = "rcar-pcie", 1101 .of_match_table = rcar_pcie_of_match, 1102 .pm = &rcar_pcie_pm_ops, 1103 .suppress_bind_attrs = true, 1104 }, 1105 .probe = rcar_pcie_probe, 1106 }; 1107 1108 #ifdef CONFIG_ARM 1109 static int rcar_pcie_aarch32_abort_handler(unsigned long addr, 1110 unsigned int fsr, struct pt_regs *regs) 1111 { 1112 return !fixup_exception(regs); 1113 } 1114 1115 static const struct of_device_id rcar_pcie_abort_handler_of_match[] __initconst = { 1116 { .compatible = "renesas,pcie-r8a7779" }, 1117 { .compatible = "renesas,pcie-r8a7790" }, 1118 { .compatible = "renesas,pcie-r8a7791" }, 1119 { .compatible = "renesas,pcie-rcar-gen2" }, 1120 {}, 1121 }; 1122 1123 static int __init rcar_pcie_init(void) 1124 { 1125 if (of_find_matching_node(NULL, rcar_pcie_abort_handler_of_match)) { 1126 #ifdef CONFIG_ARM_LPAE 1127 hook_fault_code(17, rcar_pcie_aarch32_abort_handler, SIGBUS, 0, 1128 "asynchronous external abort"); 1129 #else 1130 hook_fault_code(22, rcar_pcie_aarch32_abort_handler, SIGBUS, 0, 1131 "imprecise external abort"); 1132 #endif 1133 } 1134 1135 return platform_driver_register(&rcar_pcie_driver); 1136 } 1137 device_initcall(rcar_pcie_init); 1138 #else 1139 builtin_platform_driver(rcar_pcie_driver); 1140 #endif 1141