1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * PCIe driver for Renesas R-Car SoCs 4 * Copyright (C) 2014-2020 Renesas Electronics Europe Ltd 5 * 6 * Based on: 7 * arch/sh/drivers/pci/pcie-sh7786.c 8 * arch/sh/drivers/pci/ops-sh7786.c 9 * Copyright (C) 2009 - 2011 Paul Mundt 10 * 11 * Author: Phil Edworthy <phil.edworthy@renesas.com> 12 */ 13 14 #include <linux/bitops.h> 15 #include <linux/clk.h> 16 #include <linux/clk-provider.h> 17 #include <linux/delay.h> 18 #include <linux/interrupt.h> 19 #include <linux/irq.h> 20 #include <linux/irqchip/irq-msi-lib.h> 21 #include <linux/irqdomain.h> 22 #include <linux/kernel.h> 23 #include <linux/init.h> 24 #include <linux/iopoll.h> 25 #include <linux/msi.h> 26 #include <linux/of_address.h> 27 #include <linux/of_irq.h> 28 #include <linux/of_platform.h> 29 #include <linux/pci.h> 30 #include <linux/phy/phy.h> 31 #include <linux/platform_device.h> 32 #include <linux/pm_runtime.h> 33 #include <linux/regulator/consumer.h> 34 35 #include "pcie-rcar.h" 36 37 struct rcar_msi { 38 DECLARE_BITMAP(used, INT_PCI_MSI_NR); 39 struct irq_domain *domain; 40 struct mutex map_lock; 41 spinlock_t mask_lock; 42 int irq1; 43 int irq2; 44 }; 45 46 /* Structure representing the PCIe interface */ 47 struct rcar_pcie_host { 48 struct rcar_pcie pcie; 49 struct phy *phy; 50 struct clk *bus_clk; 51 struct rcar_msi msi; 52 int (*phy_init_fn)(struct rcar_pcie_host *host); 53 }; 54 55 static DEFINE_SPINLOCK(pmsr_lock); 56 57 static int rcar_pcie_wakeup(struct device *pcie_dev, void __iomem *pcie_base) 58 { 59 unsigned long flags; 60 u32 pmsr, val; 61 int ret = 0; 62 63 spin_lock_irqsave(&pmsr_lock, flags); 64 65 if (!pcie_base || pm_runtime_suspended(pcie_dev)) { 66 ret = -EINVAL; 67 goto unlock_exit; 68 } 69 70 pmsr = readl(pcie_base + PMSR); 71 72 /* 73 * Test if the PCIe controller received PM_ENTER_L1 DLLP and 74 * the PCIe controller is not in L1 link state. If true, apply 75 * fix, which will put the controller into L1 link state, from 76 * which it can return to L0s/L0 on its own. 77 */ 78 if ((pmsr & PMEL1RX) && ((pmsr & PMSTATE) != PMSTATE_L1)) { 79 writel(L1IATN, pcie_base + PMCTLR); 80 ret = readl_poll_timeout_atomic(pcie_base + PMSR, val, 81 val & L1FAEG, 10, 1000); 82 if (ret) { 83 dev_warn_ratelimited(pcie_dev, 84 "Timeout waiting for L1 link state, ret=%d\n", 85 ret); 86 } 87 writel(L1FAEG | PMEL1RX, pcie_base + PMSR); 88 } 89 90 unlock_exit: 91 spin_unlock_irqrestore(&pmsr_lock, flags); 92 return ret; 93 } 94 95 static struct rcar_pcie_host *msi_to_host(struct rcar_msi *msi) 96 { 97 return container_of(msi, struct rcar_pcie_host, msi); 98 } 99 100 static u32 rcar_read_conf(struct rcar_pcie *pcie, int where) 101 { 102 unsigned int shift = BITS_PER_BYTE * (where & 3); 103 u32 val = rcar_pci_read_reg(pcie, where & ~3); 104 105 return val >> shift; 106 } 107 108 #ifdef CONFIG_ARM 109 #define __rcar_pci_rw_reg_workaround(instr) \ 110 " .arch armv7-a\n" \ 111 "1: " instr " %1, [%2]\n" \ 112 "2: isb\n" \ 113 "3: .pushsection .text.fixup,\"ax\"\n" \ 114 " .align 2\n" \ 115 "4: mov %0, #" __stringify(PCIBIOS_SET_FAILED) "\n" \ 116 " b 3b\n" \ 117 " .popsection\n" \ 118 " .pushsection __ex_table,\"a\"\n" \ 119 " .align 3\n" \ 120 " .long 1b, 4b\n" \ 121 " .long 2b, 4b\n" \ 122 " .popsection\n" 123 #endif 124 125 static int rcar_pci_write_reg_workaround(struct rcar_pcie *pcie, u32 val, 126 unsigned int reg) 127 { 128 int error = PCIBIOS_SUCCESSFUL; 129 #ifdef CONFIG_ARM 130 asm volatile( 131 __rcar_pci_rw_reg_workaround("str") 132 : "+r"(error):"r"(val), "r"(pcie->base + reg) : "memory"); 133 #else 134 rcar_pci_write_reg(pcie, val, reg); 135 #endif 136 return error; 137 } 138 139 static int rcar_pci_read_reg_workaround(struct rcar_pcie *pcie, u32 *val, 140 unsigned int reg) 141 { 142 int error = PCIBIOS_SUCCESSFUL; 143 #ifdef CONFIG_ARM 144 asm volatile( 145 __rcar_pci_rw_reg_workaround("ldr") 146 : "+r"(error), "=r"(*val) : "r"(pcie->base + reg) : "memory"); 147 148 if (error != PCIBIOS_SUCCESSFUL) 149 PCI_SET_ERROR_RESPONSE(val); 150 #else 151 *val = rcar_pci_read_reg(pcie, reg); 152 #endif 153 return error; 154 } 155 156 /* Serialization is provided by 'pci_lock' in drivers/pci/access.c */ 157 static int rcar_pcie_config_access(struct rcar_pcie_host *host, 158 unsigned char access_type, struct pci_bus *bus, 159 unsigned int devfn, int where, u32 *data) 160 { 161 struct rcar_pcie *pcie = &host->pcie; 162 unsigned int dev, func, reg, index; 163 int ret; 164 165 /* Wake the bus up in case it is in L1 state. */ 166 ret = rcar_pcie_wakeup(pcie->dev, pcie->base); 167 if (ret) { 168 PCI_SET_ERROR_RESPONSE(data); 169 return PCIBIOS_SET_FAILED; 170 } 171 172 dev = PCI_SLOT(devfn); 173 func = PCI_FUNC(devfn); 174 reg = where & ~3; 175 index = reg / 4; 176 177 /* 178 * While each channel has its own memory-mapped extended config 179 * space, it's generally only accessible when in endpoint mode. 180 * When in root complex mode, the controller is unable to target 181 * itself with either type 0 or type 1 accesses, and indeed, any 182 * controller-initiated target transfer to its own config space 183 * results in a completer abort. 184 * 185 * Each channel effectively only supports a single device, but as 186 * the same channel <-> device access works for any PCI_SLOT() 187 * value, we cheat a bit here and bind the controller's config 188 * space to devfn 0 in order to enable self-enumeration. In this 189 * case the regular ECAR/ECDR path is sidelined and the mangled 190 * config access itself is initiated as an internal bus transaction. 191 */ 192 if (pci_is_root_bus(bus)) { 193 if (dev != 0) 194 return PCIBIOS_DEVICE_NOT_FOUND; 195 196 if (access_type == RCAR_PCI_ACCESS_READ) 197 *data = rcar_pci_read_reg(pcie, PCICONF(index)); 198 else 199 rcar_pci_write_reg(pcie, *data, PCICONF(index)); 200 201 return PCIBIOS_SUCCESSFUL; 202 } 203 204 /* Clear errors */ 205 rcar_pci_write_reg(pcie, rcar_pci_read_reg(pcie, PCIEERRFR), PCIEERRFR); 206 207 /* Set the PIO address */ 208 rcar_pci_write_reg(pcie, PCIE_CONF_BUS(bus->number) | 209 PCIE_CONF_DEV(dev) | PCIE_CONF_FUNC(func) | reg, PCIECAR); 210 211 /* Enable the configuration access */ 212 if (pci_is_root_bus(bus->parent)) 213 rcar_pci_write_reg(pcie, PCIECCTLR_CCIE | TYPE0, PCIECCTLR); 214 else 215 rcar_pci_write_reg(pcie, PCIECCTLR_CCIE | TYPE1, PCIECCTLR); 216 217 /* Check for errors */ 218 if (rcar_pci_read_reg(pcie, PCIEERRFR) & UNSUPPORTED_REQUEST) 219 return PCIBIOS_DEVICE_NOT_FOUND; 220 221 /* Check for master and target aborts */ 222 if (rcar_read_conf(pcie, RCONF(PCI_STATUS)) & 223 (PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT)) 224 return PCIBIOS_DEVICE_NOT_FOUND; 225 226 if (access_type == RCAR_PCI_ACCESS_READ) 227 ret = rcar_pci_read_reg_workaround(pcie, data, PCIECDR); 228 else 229 ret = rcar_pci_write_reg_workaround(pcie, *data, PCIECDR); 230 231 /* Disable the configuration access */ 232 rcar_pci_write_reg(pcie, 0, PCIECCTLR); 233 234 return ret; 235 } 236 237 static int rcar_pcie_read_conf(struct pci_bus *bus, unsigned int devfn, 238 int where, int size, u32 *val) 239 { 240 struct rcar_pcie_host *host = bus->sysdata; 241 int ret; 242 243 ret = rcar_pcie_config_access(host, RCAR_PCI_ACCESS_READ, 244 bus, devfn, where, val); 245 if (ret != PCIBIOS_SUCCESSFUL) 246 return ret; 247 248 if (size == 1) 249 *val = (*val >> (BITS_PER_BYTE * (where & 3))) & 0xff; 250 else if (size == 2) 251 *val = (*val >> (BITS_PER_BYTE * (where & 2))) & 0xffff; 252 253 dev_dbg(&bus->dev, "pcie-config-read: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08x\n", 254 bus->number, devfn, where, size, *val); 255 256 return ret; 257 } 258 259 /* Serialization is provided by 'pci_lock' in drivers/pci/access.c */ 260 static int rcar_pcie_write_conf(struct pci_bus *bus, unsigned int devfn, 261 int where, int size, u32 val) 262 { 263 struct rcar_pcie_host *host = bus->sysdata; 264 unsigned int shift; 265 u32 data; 266 int ret; 267 268 ret = rcar_pcie_config_access(host, RCAR_PCI_ACCESS_READ, 269 bus, devfn, where, &data); 270 if (ret != PCIBIOS_SUCCESSFUL) 271 return ret; 272 273 dev_dbg(&bus->dev, "pcie-config-write: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08x\n", 274 bus->number, devfn, where, size, val); 275 276 if (size == 1) { 277 shift = BITS_PER_BYTE * (where & 3); 278 data &= ~(0xff << shift); 279 data |= ((val & 0xff) << shift); 280 } else if (size == 2) { 281 shift = BITS_PER_BYTE * (where & 2); 282 data &= ~(0xffff << shift); 283 data |= ((val & 0xffff) << shift); 284 } else 285 data = val; 286 287 ret = rcar_pcie_config_access(host, RCAR_PCI_ACCESS_WRITE, 288 bus, devfn, where, &data); 289 290 return ret; 291 } 292 293 static struct pci_ops rcar_pcie_ops = { 294 .read = rcar_pcie_read_conf, 295 .write = rcar_pcie_write_conf, 296 }; 297 298 static void rcar_pcie_force_speedup(struct rcar_pcie *pcie) 299 { 300 struct device *dev = pcie->dev; 301 unsigned int timeout = 1000; 302 u32 macsr; 303 304 if ((rcar_pci_read_reg(pcie, MACS2R) & LINK_SPEED) != LINK_SPEED_5_0GTS) 305 return; 306 307 if (rcar_pci_read_reg(pcie, MACCTLR) & SPEED_CHANGE) { 308 dev_err(dev, "Speed change already in progress\n"); 309 return; 310 } 311 312 macsr = rcar_pci_read_reg(pcie, MACSR); 313 if ((macsr & LINK_SPEED) == LINK_SPEED_5_0GTS) 314 goto done; 315 316 /* Set target link speed to 5.0 GT/s */ 317 rcar_rmw32(pcie, EXPCAP(12), PCI_EXP_LNKSTA_CLS, 318 PCI_EXP_LNKSTA_CLS_5_0GB); 319 320 /* Set speed change reason as intentional factor */ 321 rcar_rmw32(pcie, MACCGSPSETR, SPCNGRSN, 0); 322 323 /* Clear SPCHGFIN, SPCHGSUC, and SPCHGFAIL */ 324 if (macsr & (SPCHGFIN | SPCHGSUC | SPCHGFAIL)) 325 rcar_pci_write_reg(pcie, macsr, MACSR); 326 327 /* Start link speed change */ 328 rcar_rmw32(pcie, MACCTLR, SPEED_CHANGE, SPEED_CHANGE); 329 330 while (timeout--) { 331 macsr = rcar_pci_read_reg(pcie, MACSR); 332 if (macsr & SPCHGFIN) { 333 /* Clear the interrupt bits */ 334 rcar_pci_write_reg(pcie, macsr, MACSR); 335 336 if (macsr & SPCHGFAIL) 337 dev_err(dev, "Speed change failed\n"); 338 339 goto done; 340 } 341 342 msleep(1); 343 } 344 345 dev_err(dev, "Speed change timed out\n"); 346 347 done: 348 dev_info(dev, "Current link speed is %s GT/s\n", 349 (macsr & LINK_SPEED) == LINK_SPEED_5_0GTS ? "5" : "2.5"); 350 } 351 352 static void rcar_pcie_hw_enable(struct rcar_pcie_host *host) 353 { 354 struct rcar_pcie *pcie = &host->pcie; 355 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(host); 356 struct resource_entry *win; 357 LIST_HEAD(res); 358 int i = 0; 359 360 /* Try setting 5 GT/s link speed */ 361 rcar_pcie_force_speedup(pcie); 362 363 /* Setup PCI resources */ 364 resource_list_for_each_entry(win, &bridge->windows) { 365 struct resource *res = win->res; 366 367 if (!res->flags) 368 continue; 369 370 switch (resource_type(res)) { 371 case IORESOURCE_IO: 372 case IORESOURCE_MEM: 373 rcar_pcie_set_outbound(pcie, i, win); 374 i++; 375 break; 376 } 377 } 378 } 379 380 static int rcar_pcie_enable(struct rcar_pcie_host *host) 381 { 382 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(host); 383 384 rcar_pcie_hw_enable(host); 385 386 pci_add_flags(PCI_REASSIGN_ALL_BUS); 387 388 bridge->sysdata = host; 389 bridge->ops = &rcar_pcie_ops; 390 391 return pci_host_probe(bridge); 392 } 393 394 static int phy_wait_for_ack(struct rcar_pcie *pcie) 395 { 396 struct device *dev = pcie->dev; 397 unsigned int timeout = 100; 398 399 while (timeout--) { 400 if (rcar_pci_read_reg(pcie, H1_PCIEPHYADRR) & PHY_ACK) 401 return 0; 402 403 udelay(100); 404 } 405 406 dev_err(dev, "Access to PCIe phy timed out\n"); 407 408 return -ETIMEDOUT; 409 } 410 411 static void phy_write_reg(struct rcar_pcie *pcie, 412 unsigned int rate, u32 addr, 413 unsigned int lane, u32 data) 414 { 415 u32 phyaddr; 416 417 phyaddr = WRITE_CMD | 418 ((rate & 1) << RATE_POS) | 419 ((lane & 0xf) << LANE_POS) | 420 ((addr & 0xff) << ADR_POS); 421 422 /* Set write data */ 423 rcar_pci_write_reg(pcie, data, H1_PCIEPHYDOUTR); 424 rcar_pci_write_reg(pcie, phyaddr, H1_PCIEPHYADRR); 425 426 /* Ignore errors as they will be dealt with if the data link is down */ 427 phy_wait_for_ack(pcie); 428 429 /* Clear command */ 430 rcar_pci_write_reg(pcie, 0, H1_PCIEPHYDOUTR); 431 rcar_pci_write_reg(pcie, 0, H1_PCIEPHYADRR); 432 433 /* Ignore errors as they will be dealt with if the data link is down */ 434 phy_wait_for_ack(pcie); 435 } 436 437 static int rcar_pcie_hw_init(struct rcar_pcie *pcie) 438 { 439 int err; 440 441 /* Begin initialization */ 442 rcar_pci_write_reg(pcie, 0, PCIETCTLR); 443 444 /* Set mode */ 445 rcar_pci_write_reg(pcie, 1, PCIEMSR); 446 447 err = rcar_pcie_wait_for_phyrdy(pcie); 448 if (err) 449 return err; 450 451 /* 452 * Initial header for port config space is type 1, set the device 453 * class to match. Hardware takes care of propagating the IDSETR 454 * settings, so there is no need to bother with a quirk. 455 */ 456 rcar_pci_write_reg(pcie, PCI_CLASS_BRIDGE_PCI_NORMAL << 8, IDSETR1); 457 458 /* 459 * Setup Secondary Bus Number & Subordinate Bus Number, even though 460 * they aren't used, to avoid bridge being detected as broken. 461 */ 462 rcar_rmw32(pcie, RCONF(PCI_SECONDARY_BUS), 0xff, 1); 463 rcar_rmw32(pcie, RCONF(PCI_SUBORDINATE_BUS), 0xff, 1); 464 465 /* Initialize default capabilities. */ 466 rcar_rmw32(pcie, REXPCAP(0), 0xff, PCI_CAP_ID_EXP); 467 rcar_rmw32(pcie, REXPCAP(PCI_EXP_FLAGS), 468 PCI_EXP_FLAGS_TYPE, PCI_EXP_TYPE_ROOT_PORT << 4); 469 rcar_rmw32(pcie, RCONF(PCI_HEADER_TYPE), PCI_HEADER_TYPE_MASK, 470 PCI_HEADER_TYPE_BRIDGE); 471 472 /* Enable data link layer active state reporting */ 473 rcar_rmw32(pcie, REXPCAP(PCI_EXP_LNKCAP), PCI_EXP_LNKCAP_DLLLARC, 474 PCI_EXP_LNKCAP_DLLLARC); 475 476 /* Write out the physical slot number = 0 */ 477 rcar_rmw32(pcie, REXPCAP(PCI_EXP_SLTCAP), PCI_EXP_SLTCAP_PSN, 0); 478 479 /* Set the completion timer timeout to the maximum 50ms. */ 480 rcar_rmw32(pcie, TLCTLR + 1, 0x3f, 50); 481 482 /* Terminate list of capabilities (Next Capability Offset=0) */ 483 rcar_rmw32(pcie, RVCCAP(0), 0xfff00000, 0); 484 485 /* Enable MSI */ 486 if (IS_ENABLED(CONFIG_PCI_MSI)) 487 rcar_pci_write_reg(pcie, 0x801f0000, PCIEMSITXR); 488 489 rcar_pci_write_reg(pcie, MACCTLR_INIT_VAL, MACCTLR); 490 491 /* Finish initialization - establish a PCI Express link */ 492 rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR); 493 494 /* This will timeout if we don't have a link. */ 495 err = rcar_pcie_wait_for_dl(pcie); 496 if (err) 497 return err; 498 499 /* Enable INTx interrupts */ 500 rcar_rmw32(pcie, PCIEINTXR, 0, 0xF << 8); 501 502 wmb(); 503 504 return 0; 505 } 506 507 static int rcar_pcie_phy_init_h1(struct rcar_pcie_host *host) 508 { 509 struct rcar_pcie *pcie = &host->pcie; 510 511 /* Initialize the phy */ 512 phy_write_reg(pcie, 0, 0x42, 0x1, 0x0EC34191); 513 phy_write_reg(pcie, 1, 0x42, 0x1, 0x0EC34180); 514 phy_write_reg(pcie, 0, 0x43, 0x1, 0x00210188); 515 phy_write_reg(pcie, 1, 0x43, 0x1, 0x00210188); 516 phy_write_reg(pcie, 0, 0x44, 0x1, 0x015C0014); 517 phy_write_reg(pcie, 1, 0x44, 0x1, 0x015C0014); 518 phy_write_reg(pcie, 1, 0x4C, 0x1, 0x786174A0); 519 phy_write_reg(pcie, 1, 0x4D, 0x1, 0x048000BB); 520 phy_write_reg(pcie, 0, 0x51, 0x1, 0x079EC062); 521 phy_write_reg(pcie, 0, 0x52, 0x1, 0x20000000); 522 phy_write_reg(pcie, 1, 0x52, 0x1, 0x20000000); 523 phy_write_reg(pcie, 1, 0x56, 0x1, 0x00003806); 524 525 phy_write_reg(pcie, 0, 0x60, 0x1, 0x004B03A5); 526 phy_write_reg(pcie, 0, 0x64, 0x1, 0x3F0F1F0F); 527 phy_write_reg(pcie, 0, 0x66, 0x1, 0x00008000); 528 529 return 0; 530 } 531 532 static int rcar_pcie_phy_init_gen2(struct rcar_pcie_host *host) 533 { 534 struct rcar_pcie *pcie = &host->pcie; 535 536 /* 537 * These settings come from the R-Car Series, 2nd Generation User's 538 * Manual, section 50.3.1 (2) Initialization of the physical layer. 539 */ 540 rcar_pci_write_reg(pcie, 0x000f0030, GEN2_PCIEPHYADDR); 541 rcar_pci_write_reg(pcie, 0x00381203, GEN2_PCIEPHYDATA); 542 rcar_pci_write_reg(pcie, 0x00000001, GEN2_PCIEPHYCTRL); 543 rcar_pci_write_reg(pcie, 0x00000006, GEN2_PCIEPHYCTRL); 544 545 rcar_pci_write_reg(pcie, 0x000f0054, GEN2_PCIEPHYADDR); 546 /* The following value is for DC connection, no termination resistor */ 547 rcar_pci_write_reg(pcie, 0x13802007, GEN2_PCIEPHYDATA); 548 rcar_pci_write_reg(pcie, 0x00000001, GEN2_PCIEPHYCTRL); 549 rcar_pci_write_reg(pcie, 0x00000006, GEN2_PCIEPHYCTRL); 550 551 return 0; 552 } 553 554 static int rcar_pcie_phy_init_gen3(struct rcar_pcie_host *host) 555 { 556 int err; 557 558 err = phy_init(host->phy); 559 if (err) 560 return err; 561 562 err = phy_power_on(host->phy); 563 if (err) 564 phy_exit(host->phy); 565 566 return err; 567 } 568 569 static irqreturn_t rcar_pcie_msi_irq(int irq, void *data) 570 { 571 struct rcar_pcie_host *host = data; 572 struct rcar_pcie *pcie = &host->pcie; 573 struct rcar_msi *msi = &host->msi; 574 struct device *dev = pcie->dev; 575 unsigned long reg; 576 577 reg = rcar_pci_read_reg(pcie, PCIEMSIFR); 578 579 /* MSI & INTx share an interrupt - we only handle MSI here */ 580 if (!reg) 581 return IRQ_NONE; 582 583 while (reg) { 584 unsigned int index = find_first_bit(®, 32); 585 int ret; 586 587 ret = generic_handle_domain_irq(msi->domain->parent, index); 588 if (ret) { 589 /* Unknown MSI, just clear it */ 590 dev_dbg(dev, "unexpected MSI\n"); 591 rcar_pci_write_reg(pcie, BIT(index), PCIEMSIFR); 592 } 593 594 /* see if there's any more pending in this vector */ 595 reg = rcar_pci_read_reg(pcie, PCIEMSIFR); 596 } 597 598 return IRQ_HANDLED; 599 } 600 601 static void rcar_msi_irq_ack(struct irq_data *d) 602 { 603 struct rcar_msi *msi = irq_data_get_irq_chip_data(d); 604 struct rcar_pcie *pcie = &msi_to_host(msi)->pcie; 605 606 /* clear the interrupt */ 607 rcar_pci_write_reg(pcie, BIT(d->hwirq), PCIEMSIFR); 608 } 609 610 static void rcar_msi_irq_mask(struct irq_data *d) 611 { 612 struct rcar_msi *msi = irq_data_get_irq_chip_data(d); 613 struct rcar_pcie *pcie = &msi_to_host(msi)->pcie; 614 unsigned long flags; 615 u32 value; 616 617 spin_lock_irqsave(&msi->mask_lock, flags); 618 value = rcar_pci_read_reg(pcie, PCIEMSIIER); 619 value &= ~BIT(d->hwirq); 620 rcar_pci_write_reg(pcie, value, PCIEMSIIER); 621 spin_unlock_irqrestore(&msi->mask_lock, flags); 622 } 623 624 static void rcar_msi_irq_unmask(struct irq_data *d) 625 { 626 struct rcar_msi *msi = irq_data_get_irq_chip_data(d); 627 struct rcar_pcie *pcie = &msi_to_host(msi)->pcie; 628 unsigned long flags; 629 u32 value; 630 631 spin_lock_irqsave(&msi->mask_lock, flags); 632 value = rcar_pci_read_reg(pcie, PCIEMSIIER); 633 value |= BIT(d->hwirq); 634 rcar_pci_write_reg(pcie, value, PCIEMSIIER); 635 spin_unlock_irqrestore(&msi->mask_lock, flags); 636 } 637 638 static void rcar_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) 639 { 640 struct rcar_msi *msi = irq_data_get_irq_chip_data(data); 641 struct rcar_pcie *pcie = &msi_to_host(msi)->pcie; 642 643 msg->address_lo = rcar_pci_read_reg(pcie, PCIEMSIALR) & ~MSIFE; 644 msg->address_hi = rcar_pci_read_reg(pcie, PCIEMSIAUR); 645 msg->data = data->hwirq; 646 } 647 648 static struct irq_chip rcar_msi_bottom_chip = { 649 .name = "R-Car MSI", 650 .irq_ack = rcar_msi_irq_ack, 651 .irq_mask = rcar_msi_irq_mask, 652 .irq_unmask = rcar_msi_irq_unmask, 653 .irq_compose_msi_msg = rcar_compose_msi_msg, 654 }; 655 656 static int rcar_msi_domain_alloc(struct irq_domain *domain, unsigned int virq, 657 unsigned int nr_irqs, void *args) 658 { 659 struct rcar_msi *msi = domain->host_data; 660 unsigned int i; 661 int hwirq; 662 663 mutex_lock(&msi->map_lock); 664 665 hwirq = bitmap_find_free_region(msi->used, INT_PCI_MSI_NR, order_base_2(nr_irqs)); 666 667 mutex_unlock(&msi->map_lock); 668 669 if (hwirq < 0) 670 return -ENOSPC; 671 672 for (i = 0; i < nr_irqs; i++) 673 irq_domain_set_info(domain, virq + i, hwirq + i, 674 &rcar_msi_bottom_chip, domain->host_data, 675 handle_edge_irq, NULL, NULL); 676 677 return 0; 678 } 679 680 static void rcar_msi_domain_free(struct irq_domain *domain, unsigned int virq, 681 unsigned int nr_irqs) 682 { 683 struct irq_data *d = irq_domain_get_irq_data(domain, virq); 684 struct rcar_msi *msi = domain->host_data; 685 686 mutex_lock(&msi->map_lock); 687 688 bitmap_release_region(msi->used, d->hwirq, order_base_2(nr_irqs)); 689 690 mutex_unlock(&msi->map_lock); 691 } 692 693 static const struct irq_domain_ops rcar_msi_domain_ops = { 694 .alloc = rcar_msi_domain_alloc, 695 .free = rcar_msi_domain_free, 696 }; 697 698 #define RCAR_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS | \ 699 MSI_FLAG_USE_DEF_CHIP_OPS | \ 700 MSI_FLAG_PCI_MSI_MASK_PARENT | \ 701 MSI_FLAG_NO_AFFINITY) 702 703 #define RCAR_MSI_FLAGS_SUPPORTED (MSI_GENERIC_FLAGS_MASK | \ 704 MSI_FLAG_MULTI_PCI_MSI) 705 706 static const struct msi_parent_ops rcar_msi_parent_ops = { 707 .required_flags = RCAR_MSI_FLAGS_REQUIRED, 708 .supported_flags = RCAR_MSI_FLAGS_SUPPORTED, 709 .bus_select_token = DOMAIN_BUS_PCI_MSI, 710 .chip_flags = MSI_CHIP_FLAG_SET_ACK, 711 .prefix = "RCAR-", 712 .init_dev_msi_info = msi_lib_init_dev_msi_info, 713 }; 714 715 static int rcar_allocate_domains(struct rcar_msi *msi) 716 { 717 struct rcar_pcie *pcie = &msi_to_host(msi)->pcie; 718 struct irq_domain_info info = { 719 .fwnode = dev_fwnode(pcie->dev), 720 .ops = &rcar_msi_domain_ops, 721 .host_data = msi, 722 .size = INT_PCI_MSI_NR, 723 }; 724 725 msi->domain = msi_create_parent_irq_domain(&info, &rcar_msi_parent_ops); 726 if (!msi->domain) { 727 dev_err(pcie->dev, "failed to create IRQ domain\n"); 728 return -ENOMEM; 729 } 730 731 return 0; 732 } 733 734 static void rcar_free_domains(struct rcar_msi *msi) 735 { 736 irq_domain_remove(msi->domain); 737 } 738 739 static int rcar_pcie_enable_msi(struct rcar_pcie_host *host) 740 { 741 struct rcar_pcie *pcie = &host->pcie; 742 struct device *dev = pcie->dev; 743 struct rcar_msi *msi = &host->msi; 744 struct resource res; 745 int err; 746 747 mutex_init(&msi->map_lock); 748 spin_lock_init(&msi->mask_lock); 749 750 err = of_address_to_resource(dev->of_node, 0, &res); 751 if (err) 752 return err; 753 754 err = rcar_allocate_domains(msi); 755 if (err) 756 return err; 757 758 /* Two IRQs are for MSI, but they are also used for non-MSI IRQs */ 759 err = devm_request_irq(dev, msi->irq1, rcar_pcie_msi_irq, 760 IRQF_SHARED | IRQF_NO_THREAD, 761 rcar_msi_bottom_chip.name, host); 762 if (err < 0) { 763 dev_err(dev, "failed to request IRQ: %d\n", err); 764 goto err; 765 } 766 767 err = devm_request_irq(dev, msi->irq2, rcar_pcie_msi_irq, 768 IRQF_SHARED | IRQF_NO_THREAD, 769 rcar_msi_bottom_chip.name, host); 770 if (err < 0) { 771 dev_err(dev, "failed to request IRQ: %d\n", err); 772 goto err; 773 } 774 775 /* Disable all MSIs */ 776 rcar_pci_write_reg(pcie, 0, PCIEMSIIER); 777 778 /* 779 * Setup MSI data target using RC base address, which is guaranteed 780 * to be in the low 32bit range on any R-Car HW. 781 */ 782 rcar_pci_write_reg(pcie, lower_32_bits(res.start) | MSIFE, PCIEMSIALR); 783 rcar_pci_write_reg(pcie, upper_32_bits(res.start), PCIEMSIAUR); 784 785 return 0; 786 787 err: 788 rcar_free_domains(msi); 789 return err; 790 } 791 792 static void rcar_pcie_teardown_msi(struct rcar_pcie_host *host) 793 { 794 struct rcar_pcie *pcie = &host->pcie; 795 796 /* Disable all MSI interrupts */ 797 rcar_pci_write_reg(pcie, 0, PCIEMSIIER); 798 799 /* Disable address decoding of the MSI interrupt, MSIFE */ 800 rcar_pci_write_reg(pcie, 0, PCIEMSIALR); 801 802 rcar_free_domains(&host->msi); 803 } 804 805 static int rcar_pcie_get_resources(struct rcar_pcie_host *host) 806 { 807 struct rcar_pcie *pcie = &host->pcie; 808 struct device *dev = pcie->dev; 809 struct resource res; 810 int err, i; 811 812 host->phy = devm_phy_optional_get(dev, "pcie"); 813 if (IS_ERR(host->phy)) 814 return PTR_ERR(host->phy); 815 816 err = of_address_to_resource(dev->of_node, 0, &res); 817 if (err) 818 return err; 819 820 pcie->base = devm_ioremap_resource(dev, &res); 821 if (IS_ERR(pcie->base)) 822 return PTR_ERR(pcie->base); 823 824 host->bus_clk = devm_clk_get(dev, "pcie_bus"); 825 if (IS_ERR(host->bus_clk)) { 826 dev_err(dev, "cannot get pcie bus clock\n"); 827 return PTR_ERR(host->bus_clk); 828 } 829 830 i = irq_of_parse_and_map(dev->of_node, 0); 831 if (!i) { 832 dev_err(dev, "cannot get platform resources for msi interrupt\n"); 833 err = -ENOENT; 834 goto err_irq1; 835 } 836 host->msi.irq1 = i; 837 838 i = irq_of_parse_and_map(dev->of_node, 1); 839 if (!i) { 840 dev_err(dev, "cannot get platform resources for msi interrupt\n"); 841 err = -ENOENT; 842 goto err_irq2; 843 } 844 host->msi.irq2 = i; 845 846 return 0; 847 848 err_irq2: 849 irq_dispose_mapping(host->msi.irq1); 850 err_irq1: 851 return err; 852 } 853 854 static int rcar_pcie_inbound_ranges(struct rcar_pcie *pcie, 855 struct resource_entry *entry, 856 int *index) 857 { 858 u64 restype = entry->res->flags; 859 u64 cpu_addr = entry->res->start; 860 u64 cpu_end = entry->res->end; 861 u64 pci_addr = entry->res->start - entry->offset; 862 u32 flags = LAM_64BIT | LAR_ENABLE; 863 u64 mask; 864 u64 size = resource_size(entry->res); 865 int idx = *index; 866 867 if (restype & IORESOURCE_PREFETCH) 868 flags |= LAM_PREFETCH; 869 870 while (cpu_addr < cpu_end) { 871 if (idx >= MAX_NR_INBOUND_MAPS - 1) { 872 dev_err(pcie->dev, "Failed to map inbound regions!\n"); 873 return -EINVAL; 874 } 875 876 /* 877 * If the size of the range is larger than the alignment of 878 * the start address, we have to use multiple entries to 879 * perform the mapping. 880 */ 881 if (cpu_addr > 0) { 882 unsigned long nr_zeros = __ffs64(cpu_addr); 883 u64 alignment = 1ULL << nr_zeros; 884 885 size = min(size, alignment); 886 } 887 888 /* Hardware supports max 4GiB inbound region */ 889 size = min(size, 1ULL << 32); 890 891 mask = roundup_pow_of_two(size) - 1; 892 mask &= ~0xf; 893 894 rcar_pcie_set_inbound(pcie, cpu_addr, pci_addr, 895 lower_32_bits(mask) | flags, idx, true); 896 897 pci_addr += size; 898 cpu_addr += size; 899 idx += 2; 900 } 901 *index = idx; 902 903 return 0; 904 } 905 906 static int rcar_pcie_parse_map_dma_ranges(struct rcar_pcie_host *host) 907 { 908 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(host); 909 struct resource_entry *entry; 910 int index = 0, err = 0; 911 912 resource_list_for_each_entry(entry, &bridge->dma_ranges) { 913 err = rcar_pcie_inbound_ranges(&host->pcie, entry, &index); 914 if (err) 915 break; 916 } 917 918 return err; 919 } 920 921 static const struct of_device_id rcar_pcie_of_match[] = { 922 { .compatible = "renesas,pcie-r8a7779", 923 .data = rcar_pcie_phy_init_h1 }, 924 { .compatible = "renesas,pcie-r8a7790", 925 .data = rcar_pcie_phy_init_gen2 }, 926 { .compatible = "renesas,pcie-r8a7791", 927 .data = rcar_pcie_phy_init_gen2 }, 928 { .compatible = "renesas,pcie-rcar-gen2", 929 .data = rcar_pcie_phy_init_gen2 }, 930 { .compatible = "renesas,pcie-r8a7795", 931 .data = rcar_pcie_phy_init_gen3 }, 932 { .compatible = "renesas,pcie-rcar-gen3", 933 .data = rcar_pcie_phy_init_gen3 }, 934 {}, 935 }; 936 937 /* Design note 346 from Linear Technology says order is not important. */ 938 static const char * const rcar_pcie_supplies[] = { 939 "vpcie1v5", 940 "vpcie3v3", 941 "vpcie12v", 942 }; 943 944 static int rcar_pcie_probe(struct platform_device *pdev) 945 { 946 struct device *dev = &pdev->dev; 947 struct pci_host_bridge *bridge; 948 struct rcar_pcie_host *host; 949 struct rcar_pcie *pcie; 950 unsigned int i; 951 u32 data; 952 int err; 953 954 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*host)); 955 if (!bridge) 956 return -ENOMEM; 957 958 host = pci_host_bridge_priv(bridge); 959 pcie = &host->pcie; 960 pcie->dev = dev; 961 platform_set_drvdata(pdev, host); 962 963 for (i = 0; i < ARRAY_SIZE(rcar_pcie_supplies); i++) { 964 err = devm_regulator_get_enable_optional(dev, rcar_pcie_supplies[i]); 965 if (err < 0 && err != -ENODEV) 966 return dev_err_probe(dev, err, "failed to enable regulator: %s\n", 967 rcar_pcie_supplies[i]); 968 } 969 970 pm_runtime_enable(pcie->dev); 971 err = pm_runtime_get_sync(pcie->dev); 972 if (err < 0) { 973 dev_err(pcie->dev, "pm_runtime_get_sync failed\n"); 974 goto err_pm_put; 975 } 976 977 err = rcar_pcie_get_resources(host); 978 if (err < 0) { 979 dev_err(dev, "failed to request resources: %d\n", err); 980 goto err_pm_put; 981 } 982 983 err = clk_prepare_enable(host->bus_clk); 984 if (err) { 985 dev_err(dev, "failed to enable bus clock: %d\n", err); 986 goto err_unmap_msi_irqs; 987 } 988 989 err = rcar_pcie_parse_map_dma_ranges(host); 990 if (err) 991 goto err_clk_disable; 992 993 host->phy_init_fn = of_device_get_match_data(dev); 994 err = host->phy_init_fn(host); 995 if (err) { 996 dev_err(dev, "failed to init PCIe PHY\n"); 997 goto err_clk_disable; 998 } 999 1000 /* Failure to get a link might just be that no cards are inserted */ 1001 if (rcar_pcie_hw_init(pcie)) { 1002 dev_info(dev, "PCIe link down\n"); 1003 err = -ENODEV; 1004 goto err_phy_shutdown; 1005 } 1006 1007 data = rcar_pci_read_reg(pcie, MACSR); 1008 dev_info(dev, "PCIe x%d: link up\n", (data >> 20) & 0x3f); 1009 1010 if (IS_ENABLED(CONFIG_PCI_MSI)) { 1011 err = rcar_pcie_enable_msi(host); 1012 if (err < 0) { 1013 dev_err(dev, 1014 "failed to enable MSI support: %d\n", 1015 err); 1016 goto err_phy_shutdown; 1017 } 1018 } 1019 1020 err = rcar_pcie_enable(host); 1021 if (err) 1022 goto err_msi_teardown; 1023 1024 return 0; 1025 1026 err_msi_teardown: 1027 if (IS_ENABLED(CONFIG_PCI_MSI)) 1028 rcar_pcie_teardown_msi(host); 1029 1030 err_phy_shutdown: 1031 if (host->phy) { 1032 phy_power_off(host->phy); 1033 phy_exit(host->phy); 1034 } 1035 1036 err_clk_disable: 1037 clk_disable_unprepare(host->bus_clk); 1038 1039 err_unmap_msi_irqs: 1040 irq_dispose_mapping(host->msi.irq2); 1041 irq_dispose_mapping(host->msi.irq1); 1042 1043 err_pm_put: 1044 pm_runtime_put(dev); 1045 pm_runtime_disable(dev); 1046 1047 return err; 1048 } 1049 1050 static int rcar_pcie_resume(struct device *dev) 1051 { 1052 struct rcar_pcie_host *host = dev_get_drvdata(dev); 1053 struct rcar_pcie *pcie = &host->pcie; 1054 unsigned int data; 1055 int err; 1056 1057 err = rcar_pcie_parse_map_dma_ranges(host); 1058 if (err) 1059 return 0; 1060 1061 /* Failure to get a link might just be that no cards are inserted */ 1062 err = host->phy_init_fn(host); 1063 if (err) { 1064 dev_info(dev, "PCIe link down\n"); 1065 return 0; 1066 } 1067 1068 data = rcar_pci_read_reg(pcie, MACSR); 1069 dev_info(dev, "PCIe x%d: link up\n", (data >> 20) & 0x3f); 1070 1071 /* Enable MSI */ 1072 if (IS_ENABLED(CONFIG_PCI_MSI)) { 1073 struct resource res; 1074 u32 val; 1075 1076 of_address_to_resource(dev->of_node, 0, &res); 1077 rcar_pci_write_reg(pcie, upper_32_bits(res.start), PCIEMSIAUR); 1078 rcar_pci_write_reg(pcie, lower_32_bits(res.start) | MSIFE, PCIEMSIALR); 1079 1080 bitmap_to_arr32(&val, host->msi.used, INT_PCI_MSI_NR); 1081 rcar_pci_write_reg(pcie, val, PCIEMSIIER); 1082 } 1083 1084 rcar_pcie_hw_enable(host); 1085 1086 return 0; 1087 } 1088 1089 static int rcar_pcie_resume_noirq(struct device *dev) 1090 { 1091 struct rcar_pcie_host *host = dev_get_drvdata(dev); 1092 struct rcar_pcie *pcie = &host->pcie; 1093 1094 if (rcar_pci_read_reg(pcie, PMSR) && 1095 !(rcar_pci_read_reg(pcie, PCIETCTLR) & DL_DOWN)) 1096 return 0; 1097 1098 /* Re-establish the PCIe link */ 1099 rcar_pci_write_reg(pcie, MACCTLR_INIT_VAL, MACCTLR); 1100 rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR); 1101 return rcar_pcie_wait_for_dl(pcie); 1102 } 1103 1104 static const struct dev_pm_ops rcar_pcie_pm_ops = { 1105 SYSTEM_SLEEP_PM_OPS(NULL, rcar_pcie_resume) 1106 .resume_noirq = rcar_pcie_resume_noirq, 1107 }; 1108 1109 static struct platform_driver rcar_pcie_driver = { 1110 .driver = { 1111 .name = "rcar-pcie", 1112 .of_match_table = rcar_pcie_of_match, 1113 .pm = &rcar_pcie_pm_ops, 1114 .suppress_bind_attrs = true, 1115 }, 1116 .probe = rcar_pcie_probe, 1117 }; 1118 1119 #ifdef CONFIG_ARM 1120 static int rcar_pcie_aarch32_abort_handler(unsigned long addr, 1121 unsigned int fsr, struct pt_regs *regs) 1122 { 1123 return !fixup_exception(regs); 1124 } 1125 1126 static const struct of_device_id rcar_pcie_abort_handler_of_match[] __initconst = { 1127 { .compatible = "renesas,pcie-r8a7779" }, 1128 { .compatible = "renesas,pcie-r8a7790" }, 1129 { .compatible = "renesas,pcie-r8a7791" }, 1130 { .compatible = "renesas,pcie-rcar-gen2" }, 1131 {}, 1132 }; 1133 1134 static int __init rcar_pcie_init(void) 1135 { 1136 if (of_find_matching_node(NULL, rcar_pcie_abort_handler_of_match)) { 1137 #ifdef CONFIG_ARM_LPAE 1138 hook_fault_code(17, rcar_pcie_aarch32_abort_handler, SIGBUS, 0, 1139 "asynchronous external abort"); 1140 #else 1141 hook_fault_code(22, rcar_pcie_aarch32_abort_handler, SIGBUS, 0, 1142 "imprecise external abort"); 1143 #endif 1144 } 1145 1146 return platform_driver_register(&rcar_pcie_driver); 1147 } 1148 device_initcall(rcar_pcie_init); 1149 #else 1150 builtin_platform_driver(rcar_pcie_driver); 1151 #endif 1152