1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * MediaTek PCIe host controller driver. 4 * 5 * Copyright (c) 2017 MediaTek Inc. 6 * Author: Ryder Lee <ryder.lee@mediatek.com> 7 * Honghui Zhang <honghui.zhang@mediatek.com> 8 */ 9 10 #include <linux/bitfield.h> 11 #include <linux/clk.h> 12 #include <linux/delay.h> 13 #include <linux/iopoll.h> 14 #include <linux/irq.h> 15 #include <linux/irqchip/chained_irq.h> 16 #include <linux/irqchip/irq-msi-lib.h> 17 #include <linux/irqdomain.h> 18 #include <linux/kernel.h> 19 #include <linux/mfd/syscon.h> 20 #include <linux/msi.h> 21 #include <linux/module.h> 22 #include <linux/of_address.h> 23 #include <linux/of_pci.h> 24 #include <linux/of_platform.h> 25 #include <linux/pci.h> 26 #include <linux/phy/phy.h> 27 #include <linux/platform_device.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/regmap.h> 30 #include <linux/reset.h> 31 32 #include "../pci.h" 33 34 /* PCIe shared registers */ 35 #define PCIE_SYS_CFG 0x00 36 #define PCIE_INT_ENABLE 0x0c 37 #define PCIE_CFG_ADDR 0x20 38 #define PCIE_CFG_DATA 0x24 39 40 /* PCIe per port registers */ 41 #define PCIE_BAR0_SETUP 0x10 42 #define PCIE_CLASS 0x34 43 #define PCIE_LINK_STATUS 0x50 44 45 #define PCIE_PORT_INT_EN(x) BIT(20 + (x)) 46 #define PCIE_PORT_PERST(x) BIT(1 + (x)) 47 #define PCIE_PORT_LINKUP BIT(0) 48 #define PCIE_BAR_MAP_MAX GENMASK(31, 16) 49 50 #define PCIE_BAR_ENABLE BIT(0) 51 #define PCIE_REVISION_ID BIT(0) 52 #define PCIE_CLASS_CODE (0x60400 << 8) 53 #define PCIE_CONF_REG(regn) (((regn) & GENMASK(7, 2)) | \ 54 ((((regn) >> 8) & GENMASK(3, 0)) << 24)) 55 #define PCIE_CONF_FUN(fun) (((fun) << 8) & GENMASK(10, 8)) 56 #define PCIE_CONF_DEV(dev) (((dev) << 11) & GENMASK(15, 11)) 57 #define PCIE_CONF_BUS(bus) (((bus) << 16) & GENMASK(23, 16)) 58 #define PCIE_CONF_ADDR(regn, fun, dev, bus) \ 59 (PCIE_CONF_REG(regn) | PCIE_CONF_FUN(fun) | \ 60 PCIE_CONF_DEV(dev) | PCIE_CONF_BUS(bus)) 61 62 /* MediaTek specific configuration registers */ 63 #define PCIE_FTS_NUM 0x70c 64 #define PCIE_FTS_NUM_MASK GENMASK(15, 8) 65 #define PCIE_FTS_NUM_L0(x) FIELD_PREP(PCIE_FTS_NUM_MASK, x) 66 67 #define PCIE_FC_CREDIT 0x73c 68 #define PCIE_FC_CREDIT_MASK (GENMASK(31, 31) | GENMASK(28, 16)) 69 #define PCIE_FC_CREDIT_VAL(x) ((x) << 16) 70 71 /* PCIe V2 share registers */ 72 #define PCIE_SYS_CFG_V2 0x0 73 #define PCIE_CSR_LTSSM_EN(x) BIT(0 + (x) * 8) 74 #define PCIE_CSR_ASPM_L1_EN(x) BIT(1 + (x) * 8) 75 76 /* PCIe V2 per-port registers */ 77 #define PCIE_MSI_VECTOR 0x0c0 78 79 #define PCIE_CONF_VEND_ID 0x100 80 #define PCIE_CONF_DEVICE_ID 0x102 81 #define PCIE_CONF_CLASS_ID 0x106 82 83 #define PCIE_INT_MASK 0x420 84 #define INTX_MASK GENMASK(19, 16) 85 #define INTX_SHIFT 16 86 #define PCIE_INT_STATUS 0x424 87 #define MSI_STATUS BIT(23) 88 #define PCIE_IMSI_STATUS 0x42c 89 #define PCIE_IMSI_ADDR 0x430 90 #define MSI_MASK BIT(23) 91 #define MTK_MSI_IRQS_NUM 32 92 93 #define PCIE_AHB_TRANS_BASE0_L 0x438 94 #define PCIE_AHB_TRANS_BASE0_H 0x43c 95 #define AHB2PCIE_SIZE(x) ((x) & GENMASK(4, 0)) 96 #define PCIE_AXI_WINDOW0 0x448 97 #define WIN_ENABLE BIT(7) 98 /* 99 * Define PCIe to AHB window size as 2^33 to support max 8GB address space 100 * translate, support least 4GB DRAM size access from EP DMA(physical DRAM 101 * start from 0x40000000). 102 */ 103 #define PCIE2AHB_SIZE 0x21 104 105 /* PCIe V2 configuration transaction header */ 106 #define PCIE_CFG_HEADER0 0x460 107 #define PCIE_CFG_HEADER1 0x464 108 #define PCIE_CFG_HEADER2 0x468 109 #define PCIE_CFG_WDATA 0x470 110 #define PCIE_APP_TLP_REQ 0x488 111 #define PCIE_CFG_RDATA 0x48c 112 #define APP_CFG_REQ BIT(0) 113 #define APP_CPL_STATUS GENMASK(7, 5) 114 115 #define CFG_DW0_LENGTH(length) ((length) & GENMASK(9, 0)) 116 #define CFG_DW0_TYPE(type) (((type) << 24) & GENMASK(28, 24)) 117 #define CFG_DW0_FMT(fmt) (((fmt) << 29) & GENMASK(31, 29)) 118 #define CFG_DW2_REGN(regn) ((regn) & GENMASK(11, 2)) 119 #define CFG_DW2_FUN(fun) (((fun) << 16) & GENMASK(18, 16)) 120 #define CFG_DW2_DEV(dev) (((dev) << 19) & GENMASK(23, 19)) 121 #define CFG_DW2_BUS(bus) (((bus) << 24) & GENMASK(31, 24)) 122 #define CFG_HEADER_DW0(type, fmt) \ 123 (CFG_DW0_LENGTH(1) | CFG_DW0_TYPE(type) | CFG_DW0_FMT(fmt)) 124 #define CFG_HEADER_DW1(where, size) \ 125 (GENMASK(((size) - 1), 0) << ((where) & 0x3)) 126 #define CFG_HEADER_DW2(regn, fun, dev, bus) \ 127 (CFG_DW2_REGN(regn) | CFG_DW2_FUN(fun) | \ 128 CFG_DW2_DEV(dev) | CFG_DW2_BUS(bus)) 129 130 #define PCIE_RST_CTRL 0x510 131 #define PCIE_PHY_RSTB BIT(0) 132 #define PCIE_PIPE_SRSTB BIT(1) 133 #define PCIE_MAC_SRSTB BIT(2) 134 #define PCIE_CRSTB BIT(3) 135 #define PCIE_PERSTB BIT(8) 136 #define PCIE_LINKDOWN_RST_EN GENMASK(15, 13) 137 #define PCIE_LINK_STATUS_V2 0x804 138 #define PCIE_PORT_LINKUP_V2 BIT(10) 139 140 struct mtk_pcie_port; 141 142 /** 143 * enum mtk_pcie_quirks - MTK PCIe quirks 144 * @MTK_PCIE_FIX_CLASS_ID: host's class ID needed to be fixed 145 * @MTK_PCIE_FIX_DEVICE_ID: host's device ID needed to be fixed 146 * @MTK_PCIE_NO_MSI: Bridge has no MSI support, and relies on an external block 147 * @MTK_PCIE_SKIP_RSTB: Skip calling RSTB bits on PCIe probe 148 */ 149 enum mtk_pcie_quirks { 150 MTK_PCIE_FIX_CLASS_ID = BIT(0), 151 MTK_PCIE_FIX_DEVICE_ID = BIT(1), 152 MTK_PCIE_NO_MSI = BIT(2), 153 MTK_PCIE_SKIP_RSTB = BIT(3), 154 }; 155 156 /** 157 * struct mtk_pcie_soc - differentiate between host generations 158 * @device_id: device ID which this host need to be fixed 159 * @ops: pointer to configuration access functions 160 * @startup: pointer to controller setting functions 161 * @setup_irq: pointer to initialize IRQ functions 162 * @quirks: PCIe device quirks. 163 */ 164 struct mtk_pcie_soc { 165 unsigned int device_id; 166 struct pci_ops *ops; 167 int (*startup)(struct mtk_pcie_port *port); 168 int (*setup_irq)(struct mtk_pcie_port *port, struct device_node *node); 169 enum mtk_pcie_quirks quirks; 170 }; 171 172 /** 173 * struct mtk_pcie_port - PCIe port information 174 * @base: IO mapped register base 175 * @phys_base: Physical address of the I/O register base region 176 * @list: port list 177 * @pcie: pointer to PCIe host info 178 * @reset: pointer to port reset control 179 * @sys_ck: pointer to transaction/data link layer clock 180 * @ahb_ck: pointer to AHB slave interface operating clock for CSR access 181 * and RC initiated MMIO access 182 * @axi_ck: pointer to application layer MMIO channel operating clock 183 * @aux_ck: pointer to pe2_mac_bridge and pe2_mac_core operating clock 184 * when pcie_mac_ck/pcie_pipe_ck is turned off 185 * @obff_ck: pointer to OBFF functional block operating clock 186 * @pipe_ck: pointer to LTSSM and PHY/MAC layer operating clock 187 * @phy: pointer to PHY control block 188 * @slot: port slot 189 * @irq: GIC irq 190 * @irq_domain: legacy INTx IRQ domain 191 * @inner_domain: inner IRQ domain 192 * @lock: protect the msi_irq_in_use bitmap 193 * @msi_irq_in_use: bit map for assigned MSI IRQ 194 */ 195 struct mtk_pcie_port { 196 void __iomem *base; 197 phys_addr_t phys_base; 198 struct list_head list; 199 struct mtk_pcie *pcie; 200 struct reset_control *reset; 201 struct clk *sys_ck; 202 struct clk *ahb_ck; 203 struct clk *axi_ck; 204 struct clk *aux_ck; 205 struct clk *obff_ck; 206 struct clk *pipe_ck; 207 struct phy *phy; 208 u32 slot; 209 int irq; 210 struct irq_domain *irq_domain; 211 struct irq_domain *inner_domain; 212 struct mutex lock; 213 DECLARE_BITMAP(msi_irq_in_use, MTK_MSI_IRQS_NUM); 214 }; 215 216 /** 217 * struct mtk_pcie - PCIe host information 218 * @dev: pointer to PCIe device 219 * @base: IO mapped register base 220 * @cfg: IO mapped register map for PCIe config 221 * @free_ck: free-run reference clock 222 * @ports: pointer to PCIe port information 223 * @soc: pointer to SoC-dependent operations 224 */ 225 struct mtk_pcie { 226 struct device *dev; 227 void __iomem *base; 228 struct regmap *cfg; 229 struct clk *free_ck; 230 231 struct list_head ports; 232 const struct mtk_pcie_soc *soc; 233 }; 234 235 static void mtk_pcie_subsys_powerdown(struct mtk_pcie *pcie) 236 { 237 struct device *dev = pcie->dev; 238 239 clk_disable_unprepare(pcie->free_ck); 240 241 pm_runtime_put_sync(dev); 242 pm_runtime_disable(dev); 243 } 244 245 static void mtk_pcie_port_free(struct mtk_pcie_port *port) 246 { 247 struct mtk_pcie *pcie = port->pcie; 248 struct device *dev = pcie->dev; 249 250 devm_iounmap(dev, port->base); 251 list_del(&port->list); 252 devm_kfree(dev, port); 253 } 254 255 static void mtk_pcie_put_resources(struct mtk_pcie *pcie) 256 { 257 struct mtk_pcie_port *port, *tmp; 258 259 list_for_each_entry_safe(port, tmp, &pcie->ports, list) { 260 phy_power_off(port->phy); 261 phy_exit(port->phy); 262 clk_disable_unprepare(port->pipe_ck); 263 clk_disable_unprepare(port->obff_ck); 264 clk_disable_unprepare(port->axi_ck); 265 clk_disable_unprepare(port->aux_ck); 266 clk_disable_unprepare(port->ahb_ck); 267 clk_disable_unprepare(port->sys_ck); 268 mtk_pcie_port_free(port); 269 } 270 271 mtk_pcie_subsys_powerdown(pcie); 272 } 273 274 static int mtk_pcie_check_cfg_cpld(struct mtk_pcie_port *port) 275 { 276 u32 val; 277 int err; 278 279 err = readl_poll_timeout_atomic(port->base + PCIE_APP_TLP_REQ, val, 280 !(val & APP_CFG_REQ), 10, 281 100 * USEC_PER_MSEC); 282 if (err) 283 return PCIBIOS_SET_FAILED; 284 285 if (readl(port->base + PCIE_APP_TLP_REQ) & APP_CPL_STATUS) 286 return PCIBIOS_SET_FAILED; 287 288 return PCIBIOS_SUCCESSFUL; 289 } 290 291 static int mtk_pcie_hw_rd_cfg(struct mtk_pcie_port *port, u32 bus, u32 devfn, 292 int where, int size, u32 *val) 293 { 294 u32 tmp; 295 296 /* Write PCIe configuration transaction header for Cfgrd */ 297 writel(CFG_HEADER_DW0(PCIE_TLP_TYPE_CFG0_RDWR, PCIE_TLP_FMT_3DW_NO_DATA), 298 port->base + PCIE_CFG_HEADER0); 299 writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1); 300 writel(CFG_HEADER_DW2(where, PCI_FUNC(devfn), PCI_SLOT(devfn), bus), 301 port->base + PCIE_CFG_HEADER2); 302 303 /* Trigger h/w to transmit Cfgrd TLP */ 304 tmp = readl(port->base + PCIE_APP_TLP_REQ); 305 tmp |= APP_CFG_REQ; 306 writel(tmp, port->base + PCIE_APP_TLP_REQ); 307 308 /* Check completion status */ 309 if (mtk_pcie_check_cfg_cpld(port)) 310 return PCIBIOS_SET_FAILED; 311 312 /* Read cpld payload of Cfgrd */ 313 *val = readl(port->base + PCIE_CFG_RDATA); 314 315 if (size == 1) 316 *val = (*val >> (8 * (where & 3))) & 0xff; 317 else if (size == 2) 318 *val = (*val >> (8 * (where & 3))) & 0xffff; 319 320 return PCIBIOS_SUCCESSFUL; 321 } 322 323 static int mtk_pcie_hw_wr_cfg(struct mtk_pcie_port *port, u32 bus, u32 devfn, 324 int where, int size, u32 val) 325 { 326 /* Write PCIe configuration transaction header for Cfgwr */ 327 writel(CFG_HEADER_DW0(PCIE_TLP_TYPE_CFG0_RDWR, PCIE_TLP_FMT_3DW_DATA), 328 port->base + PCIE_CFG_HEADER0); 329 writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1); 330 writel(CFG_HEADER_DW2(where, PCI_FUNC(devfn), PCI_SLOT(devfn), bus), 331 port->base + PCIE_CFG_HEADER2); 332 333 /* Write Cfgwr data */ 334 val = val << 8 * (where & 3); 335 writel(val, port->base + PCIE_CFG_WDATA); 336 337 /* Trigger h/w to transmit Cfgwr TLP */ 338 val = readl(port->base + PCIE_APP_TLP_REQ); 339 val |= APP_CFG_REQ; 340 writel(val, port->base + PCIE_APP_TLP_REQ); 341 342 /* Check completion status */ 343 return mtk_pcie_check_cfg_cpld(port); 344 } 345 346 static struct mtk_pcie_port *mtk_pcie_find_port(struct pci_bus *bus, 347 unsigned int devfn) 348 { 349 struct mtk_pcie *pcie = bus->sysdata; 350 struct mtk_pcie_port *port; 351 struct pci_dev *dev = NULL; 352 353 /* 354 * Walk the bus hierarchy to get the devfn value 355 * of the port in the root bus. 356 */ 357 while (bus && bus->number) { 358 dev = bus->self; 359 bus = dev->bus; 360 devfn = dev->devfn; 361 } 362 363 list_for_each_entry(port, &pcie->ports, list) 364 if (port->slot == PCI_SLOT(devfn)) 365 return port; 366 367 return NULL; 368 } 369 370 static int mtk_pcie_config_read(struct pci_bus *bus, unsigned int devfn, 371 int where, int size, u32 *val) 372 { 373 struct mtk_pcie_port *port; 374 u32 bn = bus->number; 375 376 port = mtk_pcie_find_port(bus, devfn); 377 if (!port) 378 return PCIBIOS_DEVICE_NOT_FOUND; 379 380 return mtk_pcie_hw_rd_cfg(port, bn, devfn, where, size, val); 381 } 382 383 static int mtk_pcie_config_write(struct pci_bus *bus, unsigned int devfn, 384 int where, int size, u32 val) 385 { 386 struct mtk_pcie_port *port; 387 u32 bn = bus->number; 388 389 port = mtk_pcie_find_port(bus, devfn); 390 if (!port) 391 return PCIBIOS_DEVICE_NOT_FOUND; 392 393 return mtk_pcie_hw_wr_cfg(port, bn, devfn, where, size, val); 394 } 395 396 static struct pci_ops mtk_pcie_ops_v2 = { 397 .read = mtk_pcie_config_read, 398 .write = mtk_pcie_config_write, 399 }; 400 401 static void mtk_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) 402 { 403 struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data); 404 phys_addr_t addr; 405 406 /* MT2712/MT7622 only support 32-bit MSI addresses */ 407 addr = port->phys_base + PCIE_MSI_VECTOR; 408 msg->address_hi = 0; 409 msg->address_lo = lower_32_bits(addr); 410 411 msg->data = data->hwirq; 412 413 dev_dbg(port->pcie->dev, "msi#%d address_hi %#x address_lo %#x\n", 414 (int)data->hwirq, msg->address_hi, msg->address_lo); 415 } 416 417 static void mtk_msi_ack_irq(struct irq_data *data) 418 { 419 struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data); 420 u32 hwirq = data->hwirq; 421 422 writel(1 << hwirq, port->base + PCIE_IMSI_STATUS); 423 } 424 425 static struct irq_chip mtk_msi_bottom_irq_chip = { 426 .name = "MTK MSI", 427 .irq_compose_msi_msg = mtk_compose_msi_msg, 428 .irq_ack = mtk_msi_ack_irq, 429 }; 430 431 static int mtk_pcie_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, 432 unsigned int nr_irqs, void *args) 433 { 434 struct mtk_pcie_port *port = domain->host_data; 435 unsigned long bit; 436 437 WARN_ON(nr_irqs != 1); 438 mutex_lock(&port->lock); 439 440 bit = find_first_zero_bit(port->msi_irq_in_use, MTK_MSI_IRQS_NUM); 441 if (bit >= MTK_MSI_IRQS_NUM) { 442 mutex_unlock(&port->lock); 443 return -ENOSPC; 444 } 445 446 __set_bit(bit, port->msi_irq_in_use); 447 448 mutex_unlock(&port->lock); 449 450 irq_domain_set_info(domain, virq, bit, &mtk_msi_bottom_irq_chip, 451 domain->host_data, handle_edge_irq, 452 NULL, NULL); 453 454 return 0; 455 } 456 457 static void mtk_pcie_irq_domain_free(struct irq_domain *domain, 458 unsigned int virq, unsigned int nr_irqs) 459 { 460 struct irq_data *d = irq_domain_get_irq_data(domain, virq); 461 struct mtk_pcie_port *port = irq_data_get_irq_chip_data(d); 462 463 mutex_lock(&port->lock); 464 465 if (!test_bit(d->hwirq, port->msi_irq_in_use)) 466 dev_err(port->pcie->dev, "trying to free unused MSI#%lu\n", 467 d->hwirq); 468 else 469 __clear_bit(d->hwirq, port->msi_irq_in_use); 470 471 mutex_unlock(&port->lock); 472 473 irq_domain_free_irqs_parent(domain, virq, nr_irqs); 474 } 475 476 static const struct irq_domain_ops msi_domain_ops = { 477 .alloc = mtk_pcie_irq_domain_alloc, 478 .free = mtk_pcie_irq_domain_free, 479 }; 480 481 #define MTK_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS | \ 482 MSI_FLAG_USE_DEF_CHIP_OPS | \ 483 MSI_FLAG_NO_AFFINITY) 484 485 #define MTK_MSI_FLAGS_SUPPORTED (MSI_GENERIC_FLAGS_MASK | \ 486 MSI_FLAG_PCI_MSIX) 487 488 static const struct msi_parent_ops mtk_msi_parent_ops = { 489 .required_flags = MTK_MSI_FLAGS_REQUIRED, 490 .supported_flags = MTK_MSI_FLAGS_SUPPORTED, 491 .bus_select_token = DOMAIN_BUS_PCI_MSI, 492 .chip_flags = MSI_CHIP_FLAG_SET_ACK, 493 .prefix = "MTK-", 494 .init_dev_msi_info = msi_lib_init_dev_msi_info, 495 }; 496 497 static int mtk_pcie_allocate_msi_domains(struct mtk_pcie_port *port) 498 { 499 mutex_init(&port->lock); 500 501 struct irq_domain_info info = { 502 .fwnode = dev_fwnode(port->pcie->dev), 503 .ops = &msi_domain_ops, 504 .host_data = port, 505 .size = MTK_MSI_IRQS_NUM, 506 }; 507 508 port->inner_domain = msi_create_parent_irq_domain(&info, &mtk_msi_parent_ops); 509 if (!port->inner_domain) { 510 dev_err(port->pcie->dev, "failed to create IRQ domain\n"); 511 return -ENOMEM; 512 } 513 514 return 0; 515 } 516 517 static void mtk_pcie_enable_msi(struct mtk_pcie_port *port) 518 { 519 u32 val; 520 phys_addr_t msg_addr; 521 522 msg_addr = port->phys_base + PCIE_MSI_VECTOR; 523 val = lower_32_bits(msg_addr); 524 writel(val, port->base + PCIE_IMSI_ADDR); 525 526 val = readl(port->base + PCIE_INT_MASK); 527 val &= ~MSI_MASK; 528 writel(val, port->base + PCIE_INT_MASK); 529 } 530 531 static void mtk_pcie_irq_teardown_port(struct mtk_pcie_port *port) 532 { 533 irq_set_chained_handler_and_data(port->irq, NULL, NULL); 534 535 if (port->irq_domain) 536 irq_domain_remove(port->irq_domain); 537 538 if (IS_ENABLED(CONFIG_PCI_MSI)) { 539 if (port->inner_domain) 540 irq_domain_remove(port->inner_domain); 541 } 542 543 irq_dispose_mapping(port->irq); 544 } 545 546 static void mtk_pcie_irq_teardown(struct mtk_pcie *pcie) 547 { 548 struct mtk_pcie_port *port, *tmp; 549 550 list_for_each_entry_safe(port, tmp, &pcie->ports, list) 551 mtk_pcie_irq_teardown_port(port); 552 } 553 554 static int mtk_pcie_intx_map(struct irq_domain *domain, unsigned int irq, 555 irq_hw_number_t hwirq) 556 { 557 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq); 558 irq_set_chip_data(irq, domain->host_data); 559 560 return 0; 561 } 562 563 static const struct irq_domain_ops intx_domain_ops = { 564 .map = mtk_pcie_intx_map, 565 }; 566 567 static int mtk_pcie_init_irq_domain(struct mtk_pcie_port *port, 568 struct device_node *node) 569 { 570 struct device *dev = port->pcie->dev; 571 struct device_node *pcie_intc_node; 572 int ret; 573 574 /* Setup INTx */ 575 pcie_intc_node = of_get_next_child(node, NULL); 576 if (!pcie_intc_node) { 577 dev_err(dev, "no PCIe Intc node found\n"); 578 return -ENODEV; 579 } 580 581 port->irq_domain = irq_domain_create_linear(of_fwnode_handle(pcie_intc_node), PCI_NUM_INTX, 582 &intx_domain_ops, port); 583 of_node_put(pcie_intc_node); 584 if (!port->irq_domain) { 585 dev_err(dev, "failed to get INTx IRQ domain\n"); 586 return -ENODEV; 587 } 588 589 if (IS_ENABLED(CONFIG_PCI_MSI)) { 590 ret = mtk_pcie_allocate_msi_domains(port); 591 if (ret) { 592 irq_domain_remove(port->irq_domain); 593 return ret; 594 } 595 } 596 597 return 0; 598 } 599 600 static void mtk_pcie_intr_handler(struct irq_desc *desc) 601 { 602 struct mtk_pcie_port *port = irq_desc_get_handler_data(desc); 603 struct irq_chip *irqchip = irq_desc_get_chip(desc); 604 unsigned long status; 605 u32 bit = INTX_SHIFT; 606 607 chained_irq_enter(irqchip, desc); 608 609 status = readl(port->base + PCIE_INT_STATUS); 610 if (status & INTX_MASK) { 611 for_each_set_bit_from(bit, &status, PCI_NUM_INTX + INTX_SHIFT) { 612 /* Clear the INTx */ 613 writel(1 << bit, port->base + PCIE_INT_STATUS); 614 generic_handle_domain_irq(port->irq_domain, 615 bit - INTX_SHIFT); 616 } 617 } 618 619 if (IS_ENABLED(CONFIG_PCI_MSI)) { 620 if (status & MSI_STATUS){ 621 unsigned long imsi_status; 622 623 /* 624 * The interrupt status can be cleared even if the 625 * MSI status remains pending. As such, given the 626 * edge-triggered interrupt type, its status should 627 * be cleared before being dispatched to the 628 * handler of the underlying device. 629 */ 630 writel(MSI_STATUS, port->base + PCIE_INT_STATUS); 631 while ((imsi_status = readl(port->base + PCIE_IMSI_STATUS))) { 632 for_each_set_bit(bit, &imsi_status, MTK_MSI_IRQS_NUM) 633 generic_handle_domain_irq(port->inner_domain, bit); 634 } 635 } 636 } 637 638 chained_irq_exit(irqchip, desc); 639 } 640 641 static int mtk_pcie_setup_irq(struct mtk_pcie_port *port, 642 struct device_node *node) 643 { 644 struct mtk_pcie *pcie = port->pcie; 645 struct device *dev = pcie->dev; 646 struct platform_device *pdev = to_platform_device(dev); 647 int err; 648 649 err = mtk_pcie_init_irq_domain(port, node); 650 if (err) { 651 dev_err(dev, "failed to init PCIe IRQ domain\n"); 652 return err; 653 } 654 655 if (of_property_present(dev->of_node, "interrupt-names")) 656 port->irq = platform_get_irq_byname(pdev, "pcie_irq"); 657 else 658 port->irq = platform_get_irq(pdev, port->slot); 659 660 if (port->irq < 0) 661 return port->irq; 662 663 irq_set_chained_handler_and_data(port->irq, 664 mtk_pcie_intr_handler, port); 665 666 return 0; 667 } 668 669 static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port) 670 { 671 struct mtk_pcie *pcie = port->pcie; 672 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie); 673 struct resource *mem = NULL; 674 struct resource_entry *entry; 675 const struct mtk_pcie_soc *soc = port->pcie->soc; 676 u32 val; 677 int err; 678 679 entry = resource_list_first_type(&host->windows, IORESOURCE_MEM); 680 if (entry) 681 mem = entry->res; 682 if (!mem) 683 return -EINVAL; 684 685 /* MT7622 platforms need to enable LTSSM and ASPM from PCIe subsys */ 686 if (pcie->base) { 687 val = readl(pcie->base + PCIE_SYS_CFG_V2); 688 val |= PCIE_CSR_LTSSM_EN(port->slot) | 689 PCIE_CSR_ASPM_L1_EN(port->slot); 690 writel(val, pcie->base + PCIE_SYS_CFG_V2); 691 } else if (pcie->cfg) { 692 val = PCIE_CSR_LTSSM_EN(port->slot) | 693 PCIE_CSR_ASPM_L1_EN(port->slot); 694 regmap_update_bits(pcie->cfg, PCIE_SYS_CFG_V2, val, val); 695 } 696 697 if (!(soc->quirks & MTK_PCIE_SKIP_RSTB)) { 698 /* Assert all reset signals */ 699 writel(0, port->base + PCIE_RST_CTRL); 700 701 /* 702 * Enable PCIe link down reset, if link status changed from 703 * link up to link down, this will reset MAC control registers 704 * and configuration space. 705 */ 706 writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL); 707 708 msleep(PCIE_T_PVPERL_MS); 709 710 /* De-assert PHY, PE, PIPE, MAC and configuration reset */ 711 val = readl(port->base + PCIE_RST_CTRL); 712 val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB | 713 PCIE_MAC_SRSTB | PCIE_CRSTB; 714 writel(val, port->base + PCIE_RST_CTRL); 715 } 716 717 /* Set up vendor ID and class code */ 718 if (soc->quirks & MTK_PCIE_FIX_CLASS_ID) { 719 val = PCI_VENDOR_ID_MEDIATEK; 720 writew(val, port->base + PCIE_CONF_VEND_ID); 721 722 val = PCI_CLASS_BRIDGE_PCI; 723 writew(val, port->base + PCIE_CONF_CLASS_ID); 724 } 725 726 if (soc->quirks & MTK_PCIE_FIX_DEVICE_ID) 727 writew(soc->device_id, port->base + PCIE_CONF_DEVICE_ID); 728 729 /* 100ms timeout value should be enough for Gen1/2 training */ 730 err = readl_poll_timeout(port->base + PCIE_LINK_STATUS_V2, val, 731 !!(val & PCIE_PORT_LINKUP_V2), 20, 732 100 * USEC_PER_MSEC); 733 if (err) 734 return -ETIMEDOUT; 735 736 /* Set INTx mask */ 737 val = readl(port->base + PCIE_INT_MASK); 738 val &= ~INTX_MASK; 739 writel(val, port->base + PCIE_INT_MASK); 740 741 if (IS_ENABLED(CONFIG_PCI_MSI)) 742 mtk_pcie_enable_msi(port); 743 744 /* Set AHB to PCIe translation windows */ 745 val = lower_32_bits(mem->start) | 746 AHB2PCIE_SIZE(fls(resource_size(mem))); 747 writel(val, port->base + PCIE_AHB_TRANS_BASE0_L); 748 749 val = upper_32_bits(mem->start); 750 writel(val, port->base + PCIE_AHB_TRANS_BASE0_H); 751 752 /* Set PCIe to AXI translation memory space.*/ 753 val = PCIE2AHB_SIZE | WIN_ENABLE; 754 writel(val, port->base + PCIE_AXI_WINDOW0); 755 756 return 0; 757 } 758 759 static void __iomem *mtk_pcie_map_bus(struct pci_bus *bus, 760 unsigned int devfn, int where) 761 { 762 struct mtk_pcie *pcie = bus->sysdata; 763 764 writel(PCIE_CONF_ADDR(where, PCI_FUNC(devfn), PCI_SLOT(devfn), 765 bus->number), pcie->base + PCIE_CFG_ADDR); 766 767 return pcie->base + PCIE_CFG_DATA + (where & 3); 768 } 769 770 static struct pci_ops mtk_pcie_ops = { 771 .map_bus = mtk_pcie_map_bus, 772 .read = pci_generic_config_read, 773 .write = pci_generic_config_write, 774 }; 775 776 static int mtk_pcie_startup_port(struct mtk_pcie_port *port) 777 { 778 struct mtk_pcie *pcie = port->pcie; 779 u32 func = PCI_FUNC(port->slot); 780 u32 slot = PCI_SLOT(port->slot << 3); 781 u32 val; 782 int err; 783 784 /* assert port PERST_N */ 785 val = readl(pcie->base + PCIE_SYS_CFG); 786 val |= PCIE_PORT_PERST(port->slot); 787 writel(val, pcie->base + PCIE_SYS_CFG); 788 789 /* de-assert port PERST_N */ 790 val = readl(pcie->base + PCIE_SYS_CFG); 791 val &= ~PCIE_PORT_PERST(port->slot); 792 writel(val, pcie->base + PCIE_SYS_CFG); 793 794 /* 100ms timeout value should be enough for Gen1/2 training */ 795 err = readl_poll_timeout(port->base + PCIE_LINK_STATUS, val, 796 !!(val & PCIE_PORT_LINKUP), 20, 797 100 * USEC_PER_MSEC); 798 if (err) 799 return -ETIMEDOUT; 800 801 /* enable interrupt */ 802 val = readl(pcie->base + PCIE_INT_ENABLE); 803 val |= PCIE_PORT_INT_EN(port->slot); 804 writel(val, pcie->base + PCIE_INT_ENABLE); 805 806 /* map to all DDR region. We need to set it before cfg operation. */ 807 writel(PCIE_BAR_MAP_MAX | PCIE_BAR_ENABLE, 808 port->base + PCIE_BAR0_SETUP); 809 810 /* configure class code and revision ID */ 811 writel(PCIE_CLASS_CODE | PCIE_REVISION_ID, port->base + PCIE_CLASS); 812 813 /* configure FC credit */ 814 writel(PCIE_CONF_ADDR(PCIE_FC_CREDIT, func, slot, 0), 815 pcie->base + PCIE_CFG_ADDR); 816 val = readl(pcie->base + PCIE_CFG_DATA); 817 val &= ~PCIE_FC_CREDIT_MASK; 818 val |= PCIE_FC_CREDIT_VAL(0x806c); 819 writel(PCIE_CONF_ADDR(PCIE_FC_CREDIT, func, slot, 0), 820 pcie->base + PCIE_CFG_ADDR); 821 writel(val, pcie->base + PCIE_CFG_DATA); 822 823 /* configure RC FTS number to 250 when it leaves L0s */ 824 writel(PCIE_CONF_ADDR(PCIE_FTS_NUM, func, slot, 0), 825 pcie->base + PCIE_CFG_ADDR); 826 val = readl(pcie->base + PCIE_CFG_DATA); 827 val &= ~PCIE_FTS_NUM_MASK; 828 val |= PCIE_FTS_NUM_L0(0x50); 829 writel(PCIE_CONF_ADDR(PCIE_FTS_NUM, func, slot, 0), 830 pcie->base + PCIE_CFG_ADDR); 831 writel(val, pcie->base + PCIE_CFG_DATA); 832 833 return 0; 834 } 835 836 static int mtk_pcie_startup_port_an7583(struct mtk_pcie_port *port) 837 { 838 struct mtk_pcie *pcie = port->pcie; 839 struct device *dev = pcie->dev; 840 struct pci_host_bridge *host; 841 struct resource_entry *entry; 842 struct regmap *pbus_regmap; 843 resource_size_t addr; 844 u32 args[2], size; 845 846 /* 847 * Configure PBus base address and base address mask to allow 848 * the hw to detect if a given address is accessible on PCIe 849 * controller. 850 */ 851 pbus_regmap = syscon_regmap_lookup_by_phandle_args(dev->of_node, 852 "mediatek,pbus-csr", 853 ARRAY_SIZE(args), 854 args); 855 if (IS_ERR(pbus_regmap)) 856 return PTR_ERR(pbus_regmap); 857 858 host = pci_host_bridge_from_priv(pcie); 859 entry = resource_list_first_type(&host->windows, IORESOURCE_MEM); 860 if (!entry) 861 return -ENODEV; 862 863 addr = entry->res->start - entry->offset; 864 regmap_write(pbus_regmap, args[0], lower_32_bits(addr)); 865 size = lower_32_bits(resource_size(entry->res)); 866 regmap_write(pbus_regmap, args[1], GENMASK(31, __fls(size))); 867 868 return mtk_pcie_startup_port_v2(port); 869 } 870 871 static int mtk_pcie_enable_port(struct mtk_pcie_port *port) 872 { 873 struct mtk_pcie *pcie = port->pcie; 874 struct device *dev = pcie->dev; 875 int err; 876 877 err = clk_prepare_enable(port->sys_ck); 878 if (err) { 879 dev_err(dev, "failed to enable sys_ck%d clock\n", port->slot); 880 return err; 881 } 882 883 err = clk_prepare_enable(port->ahb_ck); 884 if (err) { 885 dev_err(dev, "failed to enable ahb_ck%d\n", port->slot); 886 goto err_ahb_clk; 887 } 888 889 err = clk_prepare_enable(port->aux_ck); 890 if (err) { 891 dev_err(dev, "failed to enable aux_ck%d\n", port->slot); 892 goto err_aux_clk; 893 } 894 895 err = clk_prepare_enable(port->axi_ck); 896 if (err) { 897 dev_err(dev, "failed to enable axi_ck%d\n", port->slot); 898 goto err_axi_clk; 899 } 900 901 err = clk_prepare_enable(port->obff_ck); 902 if (err) { 903 dev_err(dev, "failed to enable obff_ck%d\n", port->slot); 904 goto err_obff_clk; 905 } 906 907 err = clk_prepare_enable(port->pipe_ck); 908 if (err) { 909 dev_err(dev, "failed to enable pipe_ck%d\n", port->slot); 910 goto err_pipe_clk; 911 } 912 913 reset_control_assert(port->reset); 914 reset_control_deassert(port->reset); 915 916 err = phy_init(port->phy); 917 if (err) { 918 dev_err(dev, "failed to initialize port%d phy\n", port->slot); 919 goto err_phy_init; 920 } 921 922 err = phy_power_on(port->phy); 923 if (err) { 924 dev_err(dev, "failed to power on port%d phy\n", port->slot); 925 goto err_phy_on; 926 } 927 928 err = pcie->soc->startup(port); 929 if (err) { 930 dev_info(dev, "Port%d link down\n", port->slot); 931 goto err_soc_startup; 932 } 933 934 return 0; 935 936 err_soc_startup: 937 phy_power_off(port->phy); 938 err_phy_on: 939 phy_exit(port->phy); 940 err_phy_init: 941 clk_disable_unprepare(port->pipe_ck); 942 err_pipe_clk: 943 clk_disable_unprepare(port->obff_ck); 944 err_obff_clk: 945 clk_disable_unprepare(port->axi_ck); 946 err_axi_clk: 947 clk_disable_unprepare(port->aux_ck); 948 err_aux_clk: 949 clk_disable_unprepare(port->ahb_ck); 950 err_ahb_clk: 951 clk_disable_unprepare(port->sys_ck); 952 953 return err; 954 } 955 956 static int mtk_pcie_parse_port(struct mtk_pcie *pcie, 957 struct device_node *node, 958 int slot) 959 { 960 struct mtk_pcie_port *port; 961 struct device *dev = pcie->dev; 962 struct platform_device *pdev = to_platform_device(dev); 963 struct resource *res; 964 char name[20]; 965 int err; 966 967 port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL); 968 if (!port) 969 return -ENOMEM; 970 971 snprintf(name, sizeof(name), "port%d", slot); 972 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name); 973 if (!res) { 974 dev_err(dev, "failed to get port%d base\n", slot); 975 return -EINVAL; 976 } 977 978 port->phys_base = res->start; 979 port->base = devm_ioremap_resource(&pdev->dev, res); 980 if (IS_ERR(port->base)) { 981 dev_err(dev, "failed to map port%d base\n", slot); 982 return PTR_ERR(port->base); 983 } 984 985 snprintf(name, sizeof(name), "sys_ck%d", slot); 986 port->sys_ck = devm_clk_get(dev, name); 987 if (IS_ERR(port->sys_ck)) { 988 dev_err(dev, "failed to get sys_ck%d clock\n", slot); 989 return PTR_ERR(port->sys_ck); 990 } 991 992 /* sys_ck might be divided into the following parts in some chips */ 993 snprintf(name, sizeof(name), "ahb_ck%d", slot); 994 port->ahb_ck = devm_clk_get_optional(dev, name); 995 if (IS_ERR(port->ahb_ck)) 996 return PTR_ERR(port->ahb_ck); 997 998 snprintf(name, sizeof(name), "axi_ck%d", slot); 999 port->axi_ck = devm_clk_get_optional(dev, name); 1000 if (IS_ERR(port->axi_ck)) 1001 return PTR_ERR(port->axi_ck); 1002 1003 snprintf(name, sizeof(name), "aux_ck%d", slot); 1004 port->aux_ck = devm_clk_get_optional(dev, name); 1005 if (IS_ERR(port->aux_ck)) 1006 return PTR_ERR(port->aux_ck); 1007 1008 snprintf(name, sizeof(name), "obff_ck%d", slot); 1009 port->obff_ck = devm_clk_get_optional(dev, name); 1010 if (IS_ERR(port->obff_ck)) 1011 return PTR_ERR(port->obff_ck); 1012 1013 snprintf(name, sizeof(name), "pipe_ck%d", slot); 1014 port->pipe_ck = devm_clk_get_optional(dev, name); 1015 if (IS_ERR(port->pipe_ck)) 1016 return PTR_ERR(port->pipe_ck); 1017 1018 snprintf(name, sizeof(name), "pcie-rst%d", slot); 1019 port->reset = devm_reset_control_get_optional_exclusive(dev, name); 1020 if (PTR_ERR(port->reset) == -EPROBE_DEFER) 1021 return PTR_ERR(port->reset); 1022 1023 /* some platforms may use default PHY setting */ 1024 snprintf(name, sizeof(name), "pcie-phy%d", slot); 1025 port->phy = devm_phy_optional_get(dev, name); 1026 if (IS_ERR(port->phy)) 1027 return PTR_ERR(port->phy); 1028 1029 port->slot = slot; 1030 port->pcie = pcie; 1031 1032 if (pcie->soc->setup_irq) { 1033 err = pcie->soc->setup_irq(port, node); 1034 if (err) 1035 return err; 1036 } 1037 1038 INIT_LIST_HEAD(&port->list); 1039 list_add_tail(&port->list, &pcie->ports); 1040 1041 return 0; 1042 } 1043 1044 static int mtk_pcie_subsys_powerup(struct mtk_pcie *pcie) 1045 { 1046 struct device *dev = pcie->dev; 1047 struct platform_device *pdev = to_platform_device(dev); 1048 struct resource *regs; 1049 struct device_node *cfg_node; 1050 int err; 1051 1052 /* get shared registers, which are optional */ 1053 regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "subsys"); 1054 if (regs) { 1055 pcie->base = devm_ioremap_resource(dev, regs); 1056 if (IS_ERR(pcie->base)) 1057 return PTR_ERR(pcie->base); 1058 } 1059 1060 cfg_node = of_find_compatible_node(NULL, NULL, 1061 "mediatek,generic-pciecfg"); 1062 if (cfg_node) { 1063 pcie->cfg = syscon_node_to_regmap(cfg_node); 1064 of_node_put(cfg_node); 1065 if (IS_ERR(pcie->cfg)) 1066 return PTR_ERR(pcie->cfg); 1067 } 1068 1069 pcie->free_ck = devm_clk_get(dev, "free_ck"); 1070 if (IS_ERR(pcie->free_ck)) { 1071 if (PTR_ERR(pcie->free_ck) == -EPROBE_DEFER) 1072 return -EPROBE_DEFER; 1073 1074 pcie->free_ck = NULL; 1075 } 1076 1077 pm_runtime_enable(dev); 1078 pm_runtime_get_sync(dev); 1079 1080 /* enable top level clock */ 1081 err = clk_prepare_enable(pcie->free_ck); 1082 if (err) { 1083 dev_err(dev, "failed to enable free_ck\n"); 1084 goto err_free_ck; 1085 } 1086 1087 return 0; 1088 1089 err_free_ck: 1090 pm_runtime_put_sync(dev); 1091 pm_runtime_disable(dev); 1092 1093 return err; 1094 } 1095 1096 static int mtk_pcie_setup(struct mtk_pcie *pcie) 1097 { 1098 struct device *dev = pcie->dev; 1099 struct device_node *node = dev->of_node; 1100 struct mtk_pcie_port *port, *tmp; 1101 int err, slot; 1102 1103 slot = of_get_pci_domain_nr(dev->of_node); 1104 if (slot < 0) { 1105 for_each_available_child_of_node_scoped(node, child) { 1106 err = of_pci_get_devfn(child); 1107 if (err < 0) 1108 return dev_err_probe(dev, err, "failed to get devfn\n"); 1109 1110 slot = PCI_SLOT(err); 1111 1112 err = mtk_pcie_parse_port(pcie, child, slot); 1113 if (err) 1114 return err; 1115 } 1116 } else { 1117 err = mtk_pcie_parse_port(pcie, node, slot); 1118 if (err) 1119 return err; 1120 } 1121 1122 err = mtk_pcie_subsys_powerup(pcie); 1123 if (err) 1124 return err; 1125 1126 /* enable each port, and then check link status */ 1127 list_for_each_entry_safe(port, tmp, &pcie->ports, list) { 1128 err = mtk_pcie_enable_port(port); 1129 if (err) { 1130 mtk_pcie_irq_teardown_port(port); 1131 mtk_pcie_port_free(port); 1132 } 1133 } 1134 1135 /* power down PCIe subsys if slots are all empty (link down) */ 1136 if (list_empty(&pcie->ports)) 1137 mtk_pcie_subsys_powerdown(pcie); 1138 1139 return 0; 1140 } 1141 1142 static int mtk_pcie_probe(struct platform_device *pdev) 1143 { 1144 struct device *dev = &pdev->dev; 1145 struct mtk_pcie *pcie; 1146 struct pci_host_bridge *host; 1147 int err; 1148 1149 host = devm_pci_alloc_host_bridge(dev, sizeof(*pcie)); 1150 if (!host) 1151 return -ENOMEM; 1152 1153 pcie = pci_host_bridge_priv(host); 1154 1155 pcie->dev = dev; 1156 pcie->soc = of_device_get_match_data(dev); 1157 platform_set_drvdata(pdev, pcie); 1158 INIT_LIST_HEAD(&pcie->ports); 1159 1160 err = mtk_pcie_setup(pcie); 1161 if (err) 1162 return err; 1163 1164 host->ops = pcie->soc->ops; 1165 host->sysdata = pcie; 1166 host->msi_domain = !!(pcie->soc->quirks & MTK_PCIE_NO_MSI); 1167 1168 err = pci_host_probe(host); 1169 if (err) 1170 goto put_resources; 1171 1172 return 0; 1173 1174 put_resources: 1175 if (!list_empty(&pcie->ports)) 1176 mtk_pcie_put_resources(pcie); 1177 1178 return err; 1179 } 1180 1181 1182 static void mtk_pcie_free_resources(struct mtk_pcie *pcie) 1183 { 1184 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie); 1185 struct list_head *windows = &host->windows; 1186 1187 pci_free_resource_list(windows); 1188 } 1189 1190 static void mtk_pcie_remove(struct platform_device *pdev) 1191 { 1192 struct mtk_pcie *pcie = platform_get_drvdata(pdev); 1193 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie); 1194 1195 pci_lock_rescan_remove(); 1196 pci_stop_root_bus(host->bus); 1197 pci_remove_root_bus(host->bus); 1198 pci_unlock_rescan_remove(); 1199 mtk_pcie_free_resources(pcie); 1200 1201 mtk_pcie_irq_teardown(pcie); 1202 1203 mtk_pcie_put_resources(pcie); 1204 } 1205 1206 static int mtk_pcie_suspend_noirq(struct device *dev) 1207 { 1208 struct mtk_pcie *pcie = dev_get_drvdata(dev); 1209 struct mtk_pcie_port *port; 1210 1211 if (list_empty(&pcie->ports)) 1212 return 0; 1213 1214 list_for_each_entry(port, &pcie->ports, list) { 1215 clk_disable_unprepare(port->pipe_ck); 1216 clk_disable_unprepare(port->obff_ck); 1217 clk_disable_unprepare(port->axi_ck); 1218 clk_disable_unprepare(port->aux_ck); 1219 clk_disable_unprepare(port->ahb_ck); 1220 clk_disable_unprepare(port->sys_ck); 1221 phy_power_off(port->phy); 1222 phy_exit(port->phy); 1223 } 1224 1225 clk_disable_unprepare(pcie->free_ck); 1226 1227 return 0; 1228 } 1229 1230 static int mtk_pcie_resume_noirq(struct device *dev) 1231 { 1232 struct mtk_pcie *pcie = dev_get_drvdata(dev); 1233 struct mtk_pcie_port *port, *tmp; 1234 int err; 1235 1236 if (list_empty(&pcie->ports)) 1237 return 0; 1238 1239 clk_prepare_enable(pcie->free_ck); 1240 1241 list_for_each_entry_safe(port, tmp, &pcie->ports, list) { 1242 err = mtk_pcie_enable_port(port); 1243 if (err) 1244 mtk_pcie_port_free(port); 1245 } 1246 1247 /* In case of EP was removed while system suspend. */ 1248 if (list_empty(&pcie->ports)) 1249 clk_disable_unprepare(pcie->free_ck); 1250 1251 return 0; 1252 } 1253 1254 static const struct dev_pm_ops mtk_pcie_pm_ops = { 1255 NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_pcie_suspend_noirq, 1256 mtk_pcie_resume_noirq) 1257 }; 1258 1259 static const struct mtk_pcie_soc mtk_pcie_soc_v1 = { 1260 .ops = &mtk_pcie_ops, 1261 .startup = mtk_pcie_startup_port, 1262 .quirks = MTK_PCIE_NO_MSI, 1263 }; 1264 1265 static const struct mtk_pcie_soc mtk_pcie_soc_mt2712 = { 1266 .ops = &mtk_pcie_ops_v2, 1267 .startup = mtk_pcie_startup_port_v2, 1268 .setup_irq = mtk_pcie_setup_irq, 1269 }; 1270 1271 static const struct mtk_pcie_soc mtk_pcie_soc_mt7622 = { 1272 .ops = &mtk_pcie_ops_v2, 1273 .startup = mtk_pcie_startup_port_v2, 1274 .setup_irq = mtk_pcie_setup_irq, 1275 .quirks = MTK_PCIE_FIX_CLASS_ID, 1276 }; 1277 1278 static const struct mtk_pcie_soc mtk_pcie_soc_an7583 = { 1279 .ops = &mtk_pcie_ops_v2, 1280 .startup = mtk_pcie_startup_port_an7583, 1281 .setup_irq = mtk_pcie_setup_irq, 1282 .quirks = MTK_PCIE_FIX_CLASS_ID | MTK_PCIE_SKIP_RSTB, 1283 }; 1284 1285 static const struct mtk_pcie_soc mtk_pcie_soc_mt7629 = { 1286 .device_id = PCI_DEVICE_ID_MEDIATEK_7629, 1287 .ops = &mtk_pcie_ops_v2, 1288 .startup = mtk_pcie_startup_port_v2, 1289 .setup_irq = mtk_pcie_setup_irq, 1290 .quirks = MTK_PCIE_FIX_CLASS_ID | MTK_PCIE_FIX_DEVICE_ID, 1291 }; 1292 1293 static const struct of_device_id mtk_pcie_ids[] = { 1294 { .compatible = "airoha,an7583-pcie", .data = &mtk_pcie_soc_an7583 }, 1295 { .compatible = "mediatek,mt2701-pcie", .data = &mtk_pcie_soc_v1 }, 1296 { .compatible = "mediatek,mt7623-pcie", .data = &mtk_pcie_soc_v1 }, 1297 { .compatible = "mediatek,mt2712-pcie", .data = &mtk_pcie_soc_mt2712 }, 1298 { .compatible = "mediatek,mt7622-pcie", .data = &mtk_pcie_soc_mt7622 }, 1299 { .compatible = "mediatek,mt7629-pcie", .data = &mtk_pcie_soc_mt7629 }, 1300 {}, 1301 }; 1302 MODULE_DEVICE_TABLE(of, mtk_pcie_ids); 1303 1304 static struct platform_driver mtk_pcie_driver = { 1305 .probe = mtk_pcie_probe, 1306 .remove = mtk_pcie_remove, 1307 .driver = { 1308 .name = "mtk-pcie", 1309 .of_match_table = mtk_pcie_ids, 1310 .suppress_bind_attrs = true, 1311 .pm = &mtk_pcie_pm_ops, 1312 }, 1313 }; 1314 module_platform_driver(mtk_pcie_driver); 1315 MODULE_DESCRIPTION("MediaTek PCIe host controller driver"); 1316 MODULE_LICENSE("GPL v2"); 1317